diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0cbc732a..ba3576c0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,7 +1,11 @@ image: gcc +variables: + GIT_STRATEGY: clone + stages: - build + - WIDEIO - DDR3 cache: @@ -21,3 +25,4 @@ build: include: - '/DRAMSys/tests/DDR3/ci.yml' + - '/DRAMSys/tests/WIDEIO/ci.yml' diff --git a/DRAMSys/tests/DDR3/ci.yml b/DRAMSys/tests/DDR3/ci.yml index 3e782ac6..06cdadfa 100644 --- a/DRAMSys/tests/DDR3/ci.yml +++ b/DRAMSys/tests/DDR3/ci.yml @@ -1,9 +1,11 @@ +# Standard DDR3 Test: example_ddr3: stage: DDR3 script: - cd build/simulator - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.xml ../../DRAMSys/tests/DDR3/ - - ls + - ls -lah + - ls -lah ../../DRAMSys/tests/DDR3/expected/ - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - cd ../traceAnalyzer @@ -13,6 +15,27 @@ example_ddr3: - build/simulator/ddr3-example_ddr3_ch0.tdb expire_in: 2 days +# Testing Reordering with FR_FCFS Scheduling Algorithm: +fr_fcfs: + stage: DDR3 + script: + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml ../../DRAMSys/tests/DDR3/ + - ls -lah + - ls -lah ../../DRAMSys/tests/DDR3/expected/ + - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-fr_fcfs_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + + allow_failure: true # TODO should be removed after first tests + + artifacts: + paths: + - build/simulator/ddr3-fr_fcfs_ddr3_ch0.tdb + expire_in: 2 days + +# Testing with TLM Protocol Cchecker protocol_checker: stage: DDR3 script: diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml new file mode 100644 index 00000000..e5a6579e --- /dev/null +++ b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml b/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml new file mode 100644 index 00000000..a432321b --- /dev/null +++ b/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/tests/WIDEIO/ci.yml b/DRAMSys/tests/WIDEIO/ci.yml new file mode 100644 index 00000000..76ca5555 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/ci.yml @@ -0,0 +1,28 @@ +example_wideio: + stage: WIDEIO + script: + # Generate specific traces for WIDEIO: + - cd DRAMSys/tests/WIDEIO/traces/ + - perl generator.pl + - cd ../../../../ + # Run DRAMSys + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/WIDEIO/simulations/wideio-example.xml ../../DRAMSys/tests/WIDEIO/ + - ls + # Run Traceanalyzer testing scripts: + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch1.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch2.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch3.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + + allow_failure: true # TODO: should be removed once the problems are fixed! + + artifacts: + paths: + - build/simulator/wideio-example_wideio_ch0.tdb + - build/simulator/wideio-example_wideio_ch1.tdb + - build/simulator/wideio-example_wideio_ch2.tdb + - build/simulator/wideio-example_wideio_ch3.tdb + expire_in: 2 days + diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml new file mode 100755 index 00000000..c6a33e71 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml new file mode 100755 index 00000000..511a7f0a --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml new file mode 100644 index 00000000..dee4f5d4 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml b/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml new file mode 100644 index 00000000..fbe252d6 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml b/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml new file mode 100644 index 00000000..acd95599 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml new file mode 100644 index 00000000..4d32315e --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp b/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp b/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml new file mode 100644 index 00000000..192cb4ea --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk b/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql b/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql new file mode 100644 index 00000000..1ba6c3aa --- /dev/null +++ b/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql @@ -0,0 +1,73 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TBank INTEGER, + TBankgroup INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml b/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml new file mode 100644 index 00000000..fea1f568 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + wideio.stl + + diff --git a/DRAMSys/tests/WIDEIO/traces/generator.pl b/DRAMSys/tests/WIDEIO/traces/generator.pl new file mode 100644 index 00000000..173a0248 --- /dev/null +++ b/DRAMSys/tests/WIDEIO/traces/generator.pl @@ -0,0 +1,75 @@ +#!/usr/bin/perl -w +use warnings; +use strict; + +# Width: 128 bit +# +# Mapping: +# 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 +# H | H B B B | R R R R | R R R R | R R R R | R C C C | C C C C | Y Y Y Y + + +open(OUT, "> wideio.stl"); + +my $length = 100000; +my $size = 0x10; +my $channelOffset = 0x8000000; +my $state = 0; +# state 0: reads only linear +# state 1: reads only random +# state 2: read and writes linear + +for(my $i=0; $i < $length; $i += 4) +{ + my $r = 0; + + if($state == 0) + { + print OUT ($i+0).": read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; + print OUT ($i+1).": read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; + print OUT ($i+2).": read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; + print OUT ($i+3).": read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; + } + elsif($state == 1) + { + $r = int(rand($channelOffset)); + print OUT ($i+0).": read ".sprintf("0x%x",($size*$r)+0*$channelOffset)."\n"; + $r = int(rand($channelOffset)); + print OUT ($i+1).": read ".sprintf("0x%x",($size*$r)+1*$channelOffset)."\n"; + $r = int(rand($channelOffset)); + print OUT ($i+2).": read ".sprintf("0x%x",($size*$r)+2*$channelOffset)."\n"; + $r = int(rand($channelOffset)); + print OUT ($i+3).": read ".sprintf("0x%x",($size*$r)+3*$channelOffset)."\n"; + } + elsif($state == 2) + { + my $rw = int(rand(2))%2; + if($rw == 0) + { + print OUT "$i: read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; + print OUT "$i: read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; + print OUT "$i: read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; + print OUT "$i: read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; + } + else + { + print OUT "$i: write ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; + print OUT "$i: write ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; + print OUT "$i: write ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; + print OUT "$i: write ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; + } + } + else + { + print "Error generating traces (".$state.")"; + exit(-1); + } + + if(($i != 0) && (($i % 1000) == 0)) + { + # GOTO next state every 1000st request: + $state = ($state + 1) % 3; + } +} + +close(OUT);