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More updates of configuration.

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This commit is contained in:
Lukas Steiner
2020-03-26 17:38:15 +01:00
parent 51b8614518
commit e306c6c118
17 changed files with 55 additions and 75 deletions
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1
DRAMSys/library/CMakeLists.txt
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@@ -146,6 +146,7 @@ add_library(DRAMSysLibrary
src/simulation/TemperatureController.cpp
src/simulation/TracePlayer.cpp
src/simulation/TraceSetup.cpp
src/simulation/StlPlayer.h
src/simulation/dram/Dram.cpp
src/simulation/dram/DramRecordable.cpp

29
DRAMSys/library/src/configuration/Configuration.cpp
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@@ -47,20 +47,6 @@ using namespace std;
string Configuration::memspecUri = "";
string Configuration::mcconfigUri = "";
StorageMode string2StoreMode(string s)
{
if (s == "NoStorage")
return StorageMode::NoStorage;
else if (s == "Store")
return StorageMode::Store;
else if (s == "ErrorModel")
return StorageMode::ErrorModel;
else {
SC_REPORT_FATAL("Configuration", ("Unknown StorageMode: " + s).c_str());
throw;
}
}
enum sc_time_unit string2TimeUnit(string s)
{
if (s == "s")
@@ -160,7 +146,7 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "ErrorCSVFile")
errorCSVFile = value;
else if (name == "StoreMode")
StoreMode = string2StoreMode(value);
storeMode = value;
// Temperature Simulation related
else if (name == "TemperatureScale")
{
@@ -203,19 +189,6 @@ void Configuration::setPathToResources(std::string path)
temperatureSim.setPathToResources(path);
}
std::string Configuration::getPathToResources()
{
return pathToResources;
}
// TODO: Never used
void Configuration::setParameters(std::map<std::string, std::string>
parameterMap)
{
for (auto item : parameterMap) {
setParameter(item.first, item.second);
}
}
// Returns the total memory size in bytes
std::uint64_t Configuration::getSimMemSizeInBytes()
{

4
DRAMSys/library/src/configuration/Configuration.h
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@@ -92,12 +92,11 @@ struct Configuration
MemSpec *memSpec;
void setParameter(std::string name, std::string value);
void setParameters(std::map<std::string, std::string> parameterMap);
//Configs for Seed, csv file and StorageMode
unsigned int errorChipSeed;
std::string errorCSVFile = "not defined.";
StorageMode StoreMode;
std::string storeMode;
// Temperature Simulation related
TemperatureSimConfig temperatureSim;
@@ -107,7 +106,6 @@ struct Configuration
unsigned int getBytesPerBurst();
unsigned int adjustNumBytesAfterECC(unsigned bytes);
void setPathToResources(std::string path);
std::string getPathToResources();
};
#endif // CONFIGURATION_H

6
DRAMSys/library/src/simulation/StlPlayer.h
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@@ -66,8 +66,6 @@ public:
this->lineCnt = 0;
}
void nextPayload()
{
std::string line;
@@ -136,8 +134,8 @@ public:
unsigned long long addr = std::stoull(address.c_str(), 0, 16);
// Get the data if necessary.
if (Configuration::getInstance().StoreMode != StorageMode::NoStorage
&& cmd != TLM_READ_COMMAND) {
if (storageEnabled && cmd == TLM_WRITE_COMMAND)
{
// The input trace file must provide the data to be stored into the memory.
iss >> dataStr;
if (dataStr.empty())

9
DRAMSys/library/src/simulation/TracePlayer.cpp
View File

@@ -41,13 +41,12 @@
TracePlayer::TracePlayer(sc_module_name name, TracePlayerListener *listener) :
sc_module(name),
payloadEventQueue(this, &TracePlayer::peqCallback),
numberOfTransactions(0),
transactionsSent(0),
transactionsReceived(0),
listener(listener),
finished(false)
listener(listener)
{
iSocket.register_nb_transport_bw(this, &TracePlayer::nb_transport_bw);
if (Configuration::getInstance().storeMode != "NoStorage")
storageEnabled = true;
}
gp *TracePlayer::allocatePayload()

9
DRAMSys/library/src/simulation/TracePlayer.h
View File

@@ -70,7 +70,8 @@ protected:
void finish();
void terminate();
void setNumberOfTransactions(unsigned int n);
unsigned int numberOfTransactions;
unsigned int numberOfTransactions = 0;
bool storageEnabled;
private:
tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase,
@@ -79,10 +80,10 @@ private:
void sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase,
const sc_time &delay);
MemoryManager memoryManager;
unsigned int transactionsSent;
unsigned int transactionsReceived;
unsigned int transactionsSent = 0;
unsigned int transactionsReceived = 0;
TracePlayerListener *listener;
bool finished;
bool finished = false;
};
#endif // TRACEPLAYER_H

29
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -66,12 +66,21 @@ using namespace DRAMPower;
Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
{
Configuration &config = Configuration::getInstance();
// Adjust number of bytes per burst dynamically to the selected ecc controller
// TODO: ECC only used for WideIO?
bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerBurst);
bytesPerBurst = config.adjustNumBytesAfterECC(bytesPerBurst);
if (config.storeMode == "NoStorage")
storeMode = StorageMode::NoStorage;
else if (config.storeMode == "Store")
storeMode = StorageMode::Store;
else if (config.storeMode == "ErrorModel")
storeMode = StorageMode::ErrorModel;
else
SC_REPORT_FATAL(this->name(), "Unsupported storage mode");
uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes();
if (StoreMode == StorageMode::Store)
if (storeMode == StorageMode::Store)
{
if (Configuration::getInstance().useMalloc)
{
@@ -155,7 +164,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::WR, bank, cycle);
// save data:
if (StoreMode == StorageMode::Store) // Use Storage
if (storeMode == StorageMode::Store) // Use Storage
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
@@ -166,7 +175,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::RD, bank, cycle);
// load data:
if (StoreMode == StorageMode::Store) // use StorageMode
if (storeMode == StorageMode::Store) // use StorageMode
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
@@ -177,7 +186,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
// save data:
if (StoreMode == StorageMode::Store) // Use Storage
if (storeMode == StorageMode::Store) // Use Storage
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
@@ -188,7 +197,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
// Load data:
if (StoreMode == StorageMode::Store) // use StorageMode
if (storeMode == StorageMode::Store) // use StorageMode
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
@@ -245,7 +254,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
PRINTDEBUGMESSAGE(name(), "transport_dgb");
// TODO: This part is not tested yet, neither with traceplayers nor with GEM5 coupling
if (StoreMode == StorageMode::NoStorage)
if (storeMode == StorageMode::NoStorage)
{
SC_REPORT_FATAL("DRAM",
"Debug Transport is used in combination with NoStorage");
@@ -262,7 +271,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
if (cmd == TLM_READ_COMMAND)
{
if (StoreMode == StorageMode::Store)
if (storeMode == StorageMode::Store)
{ // Use Storage
unsigned char *phyAddr = memory + trans.get_address();
memcpy(ptr, phyAddr, trans.get_data_length());
@@ -275,7 +284,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
}
else if (cmd == TLM_WRITE_COMMAND)
{
if (StoreMode == StorageMode::Store)
if (storeMode == StorageMode::Store)
{ // Use Storage
unsigned char *phyAddr = memory + trans.get_address();
memcpy(phyAddr, ptr, trans.get_data_length());

3
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -64,7 +64,8 @@ protected:
MemSpec *memSpec = Configuration::getInstance().memSpec;
// Data Storage:
StorageMode StoreMode = Configuration::getInstance().StoreMode;
enum class StorageMode {NoStorage, Store, ErrorModel} storeMode;
unsigned char *memory;
libDRAMPowerDummy *DRAMPower;

2
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
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@@ -42,7 +42,7 @@
DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3");
// Parameters for DRAMPower

2
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
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@@ -42,7 +42,7 @@
DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4");
// Parameters for DRAMPower

2
DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
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@@ -42,7 +42,7 @@
DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5");
// Parameters for DRAMPower

2
DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
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@@ -42,7 +42,7 @@
DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X");
// Parameters for DRAMPower

2
DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
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@@ -42,7 +42,7 @@
DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6");
// Parameters for DRAMPower

2
DRAMSys/library/src/simulation/dram/DramHBM2.cpp
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@@ -42,7 +42,7 @@
DramHBM2::DramHBM2(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2");
// Parameters for DRAMPower

2
DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
View File

@@ -42,7 +42,7 @@
DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4");
// Parameters for DRAMPower

24
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -145,7 +145,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
libDRAMPower *DRAMPower = new libDRAMPower(powerSpec, 0);
// For each bank in a channel a error Model is created:
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
{
for (unsigned i = 0; i < memSpec->NumberOfBanks; i++)
{
@@ -159,7 +159,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
}
else
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramWideIO", "Error modeling without power analysis is not supported");
DRAMPower = new libDRAMPowerDummy();
}
@@ -197,19 +197,19 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
ememory[bank]->activate(row);
}
else if (phase == BEGIN_WR)
{
DRAMPower->doCommand(MemCommand::WR, bank, cycle);
// save data:
if (StoreMode == StorageMode::Store) // Use Storage
if (storeMode == StorageMode::Store) // Use Storage
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
}
else if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model
else if (storeMode == StorageMode::ErrorModel) // Use Storage with Error Model
{
ememory[bank]->store(payload);
}
@@ -219,12 +219,12 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::RD, bank, cycle);
// load data:
if (StoreMode == StorageMode::Store) // use StorageMode
if (storeMode == StorageMode::Store) // use StorageMode
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
}
else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel
else if (storeMode == StorageMode::ErrorModel) // use StorageMode with errormodel
{
ememory[bank]->load(payload);
}
@@ -234,12 +234,12 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::WRA, bank, cycle);
// save data:
if (StoreMode == StorageMode::Store) // Use Storage
if (storeMode == StorageMode::Store) // Use Storage
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
}
else if (StoreMode == StorageMode::ErrorModel) // Use Storage with Error Model
else if (storeMode == StorageMode::ErrorModel) // Use Storage with Error Model
{
ememory[bank]->store(payload);
}
@@ -249,12 +249,12 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
DRAMPower->doCommand(MemCommand::RDA, bank, cycle);
// Load data:
if (StoreMode == StorageMode::Store) // use StorageMode
if (storeMode == StorageMode::Store) // use StorageMode
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
}
else if (StoreMode == StorageMode::ErrorModel) // use StorageMode with errormodel
else if (storeMode == StorageMode::ErrorModel) // use StorageMode with errormodel
{
ememory[bank]->load(payload);
}
@@ -267,7 +267,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
delay + memSpec->getExecutionTime(Command::REFA, payload));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
ememory[bank]->refresh(row);
}
else if (phase == BEGIN_REFB)

2
DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
View File

@@ -42,7 +42,7 @@
DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name)
{
if (StoreMode == StorageMode::ErrorModel)
if (storeMode == StorageMode::ErrorModel)
SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2");
// Parameters for DRAMPower