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Further imporovement of the gem5 integration

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This commit is contained in:
Matthias Jung
2017-03-10 11:26:32 +01:00
parent 1e6d77a9a5
commit e28d2a6506
7 changed files with 67 additions and 21 deletions
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31
DRAMSys/gem5/main.cpp
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@@ -51,6 +51,20 @@
using namespace std;
class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl
{
public:
Gem5SimControlDRAMsys(string configFile) :
Gem5SystemC::Gem5SimControl("gem5",configFile,0,"")
{
}
void afterSimulate()
{
sc_stop();
}
};
string pathOfFile(string file)
{
return file.substr(0, file.find_last_of('/'));
@@ -64,8 +78,6 @@ int sc_main(int argc, char **argv)
string gem5ConfigFile;
string resources;
int runTime = 10000000;
if(argc > 1)
{
// Get path of resources:
@@ -83,8 +95,8 @@ int sc_main(int argc, char **argv)
// Instantiate DRAMSys:
DRAMSys dramSys("DRAMSys", SimulationXML, resources);
//// Instantiate gem5:
Gem5SystemC::Gem5SimControl sim_control("gem5",gem5ConfigFile,0,"");
// Instantiate gem5:
Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
transactor.socket.bind(dramSys.tSocket);
@@ -92,11 +104,16 @@ int sc_main(int argc, char **argv)
SC_REPORT_INFO("sc_main", "Start of Simulation");
sc_core::sc_start(runTime, sc_core::SC_PS);
sc_core::sc_set_stop_mode(SC_STOP_FINISH_DELTA);
sc_core::sc_start();
if (!sc_core::sc_end_of_simulation_invoked())
{
SC_REPORT_INFO("sc_main","Simulation stopped without explicit sc_stop()");
sc_core::sc_stop();
}
SC_REPORT_INFO("sc_main", "End of Simulation");
//CxxConfig::statsDump();
return EXIT_SUCCESS;
}

2
DRAMSys/simulator/resources/configs/simulator/ddr3-single-device.xml
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@@ -10,4 +10,6 @@
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<gem5 value = "0" />
</simconfig>

8
DRAMSys/simulator/resources/configs/simulator/ddr3.xml
View File

@@ -10,4 +10,12 @@
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<gem5 value = "0" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "214748364c8" />
<gem5 value = "1" />
-->
</simconfig>

12
DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp
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@@ -73,6 +73,11 @@ int string2int(string s)
return std::stoi(s);
}
unsigned long long string2ull(string s)
{
return std::stoull(s);
}
StorageMode string2StoreMode(string s)
{
if(s == "NoStorage")
@@ -185,6 +190,13 @@ void Configuration::setParameter(std::string name, std::string value)
SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str());
} else
NumberOfDevicesOnDIMM = string2int(value);
else if(name == "gem5")
gem5 = string2bool(value);
else if(name == "AddressOffset")
{
AddressOffset = string2ull(value);
cout << "Address Offset: " << AddressOffset << endl;
}
else if(name == "CheckTLM2Protocol")
CheckTLM2Protocol = string2bool(value);
// Specification for ErrorChipSeed, ErrorCSVFile path and StoreMode

2
DRAMSys/simulator/src/controller/core/configuration/Configuration.h
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@@ -81,6 +81,8 @@ struct Configuration
bool SimulationProgressBar = false;
unsigned int NumberOfDevicesOnDIMM = 1;
bool CheckTLM2Protocol = false;
bool gem5 = false;
unsigned long long int AddressOffset = 0;
// MemSpec (from DRAM-Power XML)
MemSpec memSpec;

12
DRAMSys/simulator/src/simulation/Arbiter.h
View File

@@ -124,13 +124,19 @@ private:
{
if (phase == BEGIN_REQ)
{
// adjust address offset:
payload.set_address(payload.get_address() - Configuration::getInstance().AddressOffset);
// Map the payload with socket id.
routeMap[&payload] = id;
// In the begin request phase the socket ID is appended to the payload.
// It will extracted from the payload and used later.
appendDramExtension(id, payload);
payload.acquire();
} else if (phase == END_RESP) {
}
else if (phase == END_RESP)
{
// Erase before the payload is released.
routeMap.erase(&payload);
payload.release();
@@ -142,9 +148,11 @@ private:
virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans)
{
// adjust address offset:
trans.set_address(trans.get_address() - Configuration::getInstance().AddressOffset);
DecodedAddress decodedAddress = xmlAddressDecoder::getInstance().decodeAddress(trans.get_address());
return iSocket[decodedAddress.channel]->transport_dbg(trans);
}
void peqCallback(tlm_generic_payload& payload, const tlm_phase& phase)

21
DRAMSys/simulator/src/simulation/Dram.h
View File

@@ -391,9 +391,10 @@ struct Dram : sc_module
else if (phase == BEGIN_WR)
{
#ifndef DRAMSYS_PCT
#ifndef DRAMSYS_GEM5
assert(payload.get_data_length() == bytesPerBurst);
#endif
if(Configuration::getInstance().gem5 == false)
{
assert(payload.get_data_length() == bytesPerBurst);
}
#endif
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WR, bank, cycle);}
@@ -418,9 +419,10 @@ struct Dram : sc_module
else if (phase == BEGIN_RD)
{
#ifndef DRAMSYS_PCT
#ifndef DRAMSYS_GEM5
assert(payload.get_data_length() == bytesPerBurst);
#endif
if(Configuration::getInstance().gem5 == false)
{
assert(payload.get_data_length() == bytesPerBurst);
}
#endif
numberOfTransactionsServed++;
@@ -451,7 +453,6 @@ struct Dram : sc_module
}
else if (StoreMode == StorageMode::Store) // Use Storage
{
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
}
@@ -556,12 +557,8 @@ struct Dram : sc_module
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans)
{
printDebugMessage("transport_dgb");
// FIXME: maybe the initiator wants to write more than burst size at once
assert(trans.get_data_length() == bytesPerBurst);
// TODO: This part is not tested yet, neither with traceplayers neither with GEM5 coupling
if (StoreMode == StorageMode::NoStorage)
{
@@ -575,7 +572,7 @@ struct Dram : sc_module
unsigned int len = trans.get_data_length();
//unsigned int bank = DramExtension::getExtension(trans).getBank().ID();
cout << "cmd " << (cmd ? "write" : "read") << " adr " << hex << adr << " len " << len << endl;
//cout << "cmd " << (cmd ? "write" : "read") << " adr " << hex << adr << " len " << len << endl;
if ( cmd == tlm::TLM_READ_COMMAND )
{