gem5 subproject added to DRAMSys

DRAMSys/DRAMSys.pro

@@ -16,6 +16,20 @@ SUBDIRS += simulator/library.pro
 SUBDIRS += simulator/simulator.pro
 SUBDIRS += analyzer/traceAnalyzer.pro
 
+
+# Check if gem5 is installed:
+gem5 = $$(GEM5)
+isEmpty(gem5)
+{
+    DEFINES += DRAMSYS_GEM5
+}
+
+contains(DEFINES,DRAMSYS_GEM5)
+{
+    message(Gem5 Simulation Feature Enabled)
+    SUBDIRS += gem5/gem5.pro
+}
+
 # Build Sub Projects in the order given above
 CONFIG += ordered
 

DRAMSys/gem5/gem5.pro

@@ -0,0 +1,75 @@
+TARGET = DRAMSys_gem5
+TEMPLATE = app
+CONFIG += console
+CONFIG -= app_bundle
+CONFIG -= qt
+
+# gem5 parameters:
+gem5_arch = 'ARM'
+gem5_variant = 'opt'
+gem5_root = $$(GEM5)
+
+systemc_home = $$(SYSTEMC_HOME)
+isEmpty(systemc_home) {
+    systemc_home = /opt/systemc
+}
+message(SystemC home is $${systemc_home})
+
+systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)
+isEmpty(systemc_target_arch) {
+    systemc_target_arch = linux64
+}
+
+message(SystemC target architecture is $${systemc_target_arch})
+
+unix:!macx {
+        message(Building on a GNU/Linux)
+        QMAKE_RPATHDIR += $${systemc_home}/lib-$${systemc_target_arch}
+        message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR})
+}
+
+DEFINES += TIXML_USE_STL
+DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
+DEFINES += DRAMSYS_GEM5
+
+unix:!macx {
+        QMAKE_CXXFLAGS += -std=c++11 -O0 -g
+}
+
+macx: {
+        CONFIG += c++11
+        QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
+}
+
+INCLUDEPATH += ../simulator/src/simulation/
+INCLUDEPATH += $${systemc_home}/include
+INCLUDEPATH += ../simulator/src/common/third_party/DRAMPower/src
+INCLUDEPATH += ../simulator/src/common/third_party/DRAMPower/src/libdrampower
+INCLUDEPATH += $${gem5_root}/build/$${gem5_arch}/
+INCLUDEPATH += $${gem5_root}/util/tlm/examples/slave_port
+INCLUDEPATH += $${gem5_root}/util/tlm/examples/common
+INCLUDEPATH += $${gem5_root}/util/tlm/
+INCLUDEPATH += $${gem5_root}/util/systemc
+
+LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc
+LIBS += ../simulator/libDRAMSys.a
+LIBS += ../../DRAMSys/simulator/src/common/third_party/DRAMPower/src/libdrampower.a
+LIBS += -lsqlite3
+LIBS += -L$${gem5_root}/build/$${gem5_arch} -lgem5_$${gem5_variant}
+
+SOURCES += $${gem5_root}/util/systemc/sc_gem5_control.cc
+SOURCES += $${gem5_root}/util/systemc/sc_logger.cc
+SOURCES += $${gem5_root}/util/systemc/sc_module.cc
+SOURCES += $${gem5_root}/util/systemc/stats.cc
+SOURCES += $${gem5_root}/util/tlm/examples/common/cli_parser.cc
+SOURCES += $${gem5_root}/util/tlm/examples/common/report_handler.cc
+SOURCES += $${gem5_root}/util/tlm/master_transactor.cc
+SOURCES += $${gem5_root}/util/tlm/sc_master_port.cc
+SOURCES += $${gem5_root}/util/tlm/sc_slave_port.cc
+SOURCES += $${gem5_root}/util/tlm/slave_transactor.cc
+SOURCES += $${gem5_root}/util/tlm/sc_ext.cc
+SOURCES += $${gem5_root}/util/tlm/sc_mm.cc
+SOURCES += $${gem5_root}/util/tlm/sim_control.cc
+
+SOURCES += main.cpp
+

DRAMSys/gem5/main.cpp

@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ *          Christian Menard
+ *          Abdul Mutaal Ahmad
+ */
+
+#include <iostream>
+#include <systemc>
+#include <tlm>
+#include <string>
+
+#include "DRAMSys.h"
+#include "TraceSetup.h"
+
+#include "report_handler.hh"
+#include "sc_target.hh"
+#include "sim_control.hh"
+#include "slave_transactor.hh"
+#include "stats.hh"
+
+using namespace std;
+
+string pathOfFile(string file)
+{
+    return file.substr(0, file.find_last_of('/'));
+}
+
+int sc_main(int argc, char **argv)
+{
+    SC_REPORT_INFO("sc_main", "Simulation Setup");
+
+    string SimulationXML;
+    string gem5ConfigFile;
+    string resources;
+
+    int runTime = 10000000;
+
+    if(argc > 1)
+    {
+        // Get path of resources:
+        resources = pathOfFile(argv[0])
+                + string("/../../DRAMSys/simulator/resources/");
+
+        SimulationXML = argv[1];
+        gem5ConfigFile = argv[2];
+    }
+    else
+    {
+        SC_REPORT_FATAL("sc_main","Please provide configuration files");
+    }
+
+    // Instantiate DRAMSys:
+    DRAMSys dramSys("DRAMSys", SimulationXML, resources);
+
+    //// Instantiate gem5:
+    Gem5SystemC::Gem5SimControl sim_control("gem5",gem5ConfigFile,0,"");
+    Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
+
+    transactor.socket.bind(dramSys.tSocket);
+    transactor.sim_control.bind(sim_control);
+
+    SC_REPORT_INFO("sc_main", "Start of Simulation");
+
+    sc_core::sc_start(runTime, sc_core::SC_PS);
+
+    SC_REPORT_INFO("sc_main", "End of Simulation");
+
+    //CxxConfig::statsDump();
+
+    return EXIT_SUCCESS;
+}

DRAMSys/simulator/src/simulation/Dram.h

@@ -391,7 +391,9 @@ struct Dram : sc_module
         else if (phase == BEGIN_WR)
         {
 #ifndef DRAMSYS_PCT
+#ifndef DRAMSYS_GEM5
             assert(payload.get_data_length() == bytesPerBurst);
+#endif
 #endif
 
             if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WR, bank, cycle);}
@@ -415,7 +417,11 @@ struct Dram : sc_module
         }
         else if (phase == BEGIN_RD)
         {
+#ifndef DRAMSYS_PCT
+#ifndef DRAMSYS_GEM5
             assert(payload.get_data_length() == bytesPerBurst);
+#endif
+#endif
 
             numberOfTransactionsServed++;
             if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RD, bank, cycle);}