Add compile definitions for optional standards.
This commit is contained in:
Lukas Steiner
@@ -77,6 +77,33 @@ if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation)
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)
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endif()
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if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerDDR5.cpp)
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message("== DDR5 included")
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set(DDR5_SOURCES
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src/configuration/memspec/MemSpecDDR5.cpp
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src/controller/checker/CheckerDDR5.cpp
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src/simulation/dram/DramDDR5.cpp
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)
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endif()
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if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerLPDDR5.cpp)
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message("== LPDDR5 included")
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set(LPDDR5_SOURCES
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src/configuration/memspec/MemSpecLPDDR5.cpp
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src/controller/checker/CheckerLPDDR5.cpp
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src/simulation/dram/DramLPDDR5.cpp
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)
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endif()
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if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerHBM3.cpp)
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message("== HBM3 included")
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set(HBM3_SOURCES
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src/configuration/memspec/MemSpecHBM3.cpp
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src/controller/checker/CheckerHBM3.cpp
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src/simulation/dram/DramHBM3.cpp
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)
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endif()
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add_library(DRAMSysLibrary
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src/common/DebugManager.cpp
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src/common/dramExtensions.cpp
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@@ -89,16 +116,13 @@ add_library(DRAMSysLibrary
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src/configuration/memspec/MemSpec.cpp
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src/configuration/memspec/MemSpecDDR3.cpp
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src/configuration/memspec/MemSpecDDR4.cpp
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src/configuration/memspec/MemSpecDDR5.cpp
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src/configuration/memspec/MemSpecLPDDR4.cpp
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src/configuration/memspec/MemSpecLPDDR5.cpp
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src/configuration/memspec/MemSpecWideIO.cpp
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src/configuration/memspec/MemSpecWideIO2.cpp
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src/configuration/memspec/MemSpecGDDR5.cpp
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src/configuration/memspec/MemSpecGDDR5X.cpp
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src/configuration/memspec/MemSpecGDDR6.cpp
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src/configuration/memspec/MemSpecHBM2.cpp
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src/configuration/memspec/MemSpecHBM3.cpp
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src/configuration/memspec/MemSpecSTTMRAM.cpp
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src/controller/BankMachine.cpp
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@@ -109,16 +133,13 @@ add_library(DRAMSysLibrary
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src/controller/checker/CheckerIF.h
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src/controller/checker/CheckerDDR3.cpp
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src/controller/checker/CheckerDDR4.cpp
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src/controller/checker/CheckerDDR5.cpp
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src/controller/checker/CheckerLPDDR4.cpp
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src/controller/checker/CheckerLPDDR5.cpp
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src/controller/checker/CheckerWideIO.cpp
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src/controller/checker/CheckerWideIO2.cpp
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src/controller/checker/CheckerGDDR5.cpp
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src/controller/checker/CheckerGDDR5X.cpp
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src/controller/checker/CheckerGDDR6.cpp
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src/controller/checker/CheckerHBM2.cpp
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src/controller/checker/CheckerHBM3.cpp
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src/controller/checker/CheckerSTTMRAM.cpp
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src/controller/cmdmux/CmdMuxIF.h
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@@ -168,134 +189,34 @@ add_library(DRAMSysLibrary
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src/simulation/dram/Dram.cpp
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src/simulation/dram/DramDDR3.cpp
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src/simulation/dram/DramDDR4.cpp
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src/simulation/dram/DramDDR5.cpp
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src/simulation/dram/DramDDR4.cpp
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src/simulation/dram/DramLPDDR4.cpp
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src/simulation/dram/DramLPDDR5.cpp
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src/simulation/dram/DramWideIO.cpp
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src/simulation/dram/DramWideIO2.cpp
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src/simulation/dram/DramGDDR5.cpp
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src/simulation/dram/DramGDDR5X.cpp
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src/simulation/dram/DramGDDR6.cpp
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src/simulation/dram/DramHBM2.cpp
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src/simulation/dram/DramHBM3.cpp
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src/simulation/dram/DramSTTMRAM.cpp
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${RECORDING_SOURCES}
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# Simulation Config Files
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resources/simulations/ddr3-example.json
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resources/simulations/ddr3-example2.json
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resources/simulations/ddr3-gem5-se.json
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resources/simulations/ddr4-example.json
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resources/simulations/hbm2-example.json
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resources/simulations/hbm3-example.json
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resources/simulations/lpddr4-example.json
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resources/simulations/ranktest.json
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resources/simulations/wideio-example.json
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resources/simulations/wideio-thermal.json
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# Address Mapping Config Files
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resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json
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resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json
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resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json
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resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json
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resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json
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resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json
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resources/configs/amconfigs/am_ddr3_x16_brc.json
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resources/configs/amconfigs/am_ddr3_x16_rbc.json
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resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
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resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
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resources/configs/amconfigs/am_hbm3_8Gb_pc_brc.json
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resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
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resources/configs/amconfigs/am_ranktest.json
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resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json
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resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json
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resources/configs/amconfigs/am_wideio_4x1Gb_brc.json
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resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json
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resources/configs/amconfigs/am_wideio_4x256Mb_brc.json
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resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json
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resources/configs/amconfigs/am_wideio_4x2Gb_brc.json
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resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json
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resources/configs/amconfigs/am_wideio_4x4Gb_brc.json
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resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json
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resources/configs/amconfigs/am_wideio_4x512Mb_brc.json
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resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json
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# Memory Controller Config Files
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resources/configs/mcconfigs/fifo.json
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resources/configs/mcconfigs/fifoStrict.json
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resources/configs/mcconfigs/fr_fcfs_grp.json
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resources/configs/mcconfigs/fr_fcfs.json
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# Memspec Config Files
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resources/configs/memspecs/HBM2.json
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resources/configs/memspecs/HBM3.json
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resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
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resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
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resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
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resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
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resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
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resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
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resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
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resources/configs/memspecs/memspec_ranktest.json
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resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
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resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
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resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
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resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
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resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
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resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
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resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
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resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
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resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
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resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
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resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
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resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
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resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
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resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
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resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
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resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
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resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
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resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
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resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
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# Simulator Config Files
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resources/configs/simulator/ddr3_ecc.json
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resources/configs/simulator/ddr3.json
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resources/configs/simulator/ddr3_gem5_se.json
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resources/configs/simulator/ddr4.json
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resources/configs/simulator/hbm2.json
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resources/configs/simulator/hbm3.json
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resources/configs/simulator/lpddr4.json
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resources/configs/simulator/wideio.json
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resources/configs/simulator/wideio_thermal.json
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# Thermal Simulation Config Files
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resources/configs/thermalsim/config.json
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resources/configs/thermalsim/powerInfo.json
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${DDR5_SOURCES}
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${LPDDR5_SOURCES}
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${HBM3_SOURCES}
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)
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if(DEFINED DDR5_SOURCES)
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target_compile_definitions(DRAMSysLibrary PRIVATE DDR5_SIM)
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endif()
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if(DEFINED LPDDR5_SOURCES)
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target_compile_definitions(DRAMSysLibrary PRIVATE LPDDR5_SIM)
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endif()
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if(DEFINED HBM3_SOURCES)
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target_compile_definitions(DRAMSysLibrary PRIVATE HBM3_SIM)
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endif()
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if(DEFINED ENV{LIBTHREED_ICE_HOME})
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message("== Thermal simulation available")
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target_compile_definitions(DRAMSysLibrary PRIVATE THERMALSIM)
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@@ -42,18 +42,25 @@
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#include "Configuration.h"
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#include "memspec/MemSpecDDR3.h"
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#include "memspec/MemSpecDDR4.h"
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#include "memspec/MemSpecDDR5.h"
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#include "memspec/MemSpecWideIO.h"
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#include "memspec/MemSpecLPDDR4.h"
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#include "memspec/MemSpecLPDDR5.h"
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#include "memspec/MemSpecWideIO2.h"
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#include "memspec/MemSpecHBM2.h"
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#include "memspec/MemSpecHBM3.h"
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#include "memspec/MemSpecGDDR5.h"
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#include "memspec/MemSpecGDDR5X.h"
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#include "memspec/MemSpecGDDR6.h"
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#include "memspec/MemSpecSTTMRAM.h"
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#ifdef DDR5_SIM
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#include "memspec/MemSpecDDR5.h"
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#endif
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#ifdef LPDDR5_SIM
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#include "memspec/MemSpecLPDDR5.h"
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#endif
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#ifdef HBM3_SIM
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#include "memspec/MemSpecHBM3.h"
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#endif
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using namespace sc_core;
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enum sc_time_unit string2TimeUnit(const std::string &s)
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@@ -326,20 +333,14 @@ void Configuration::loadMemSpec(const DRAMSysConfiguration::MemSpec &memSpecConf
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memSpec = std::make_unique<const MemSpecDDR3>(memSpecConfig);
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else if (memoryType == "DDR4")
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memSpec = std::make_unique<const MemSpecDDR4>(memSpecConfig);
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else if (memoryType == "DDR5")
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memSpec = std::make_unique<const MemSpecDDR5>(memSpecConfig);
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else if (memoryType == "LPDDR4")
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memSpec = std::make_unique<const MemSpecLPDDR4>(memSpecConfig);
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else if (memoryType == "LPDDR5")
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memSpec = std::make_unique<const MemSpecLPDDR5>(memSpecConfig);
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else if (memoryType == "WIDEIO_SDR")
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memSpec = std::make_unique<const MemSpecWideIO>(memSpecConfig);
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else if (memoryType == "WIDEIO2")
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memSpec = std::make_unique<const MemSpecWideIO2>(memSpecConfig);
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else if (memoryType == "HBM2")
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memSpec = std::make_unique<const MemSpecHBM2>(memSpecConfig);
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else if (memoryType == "HBM3")
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memSpec = std::make_unique<const MemSpecHBM3>(memSpecConfig);
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else if (memoryType == "GDDR5")
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memSpec = std::make_unique<const MemSpecGDDR5>(memSpecConfig);
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else if (memoryType == "GDDR5X")
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@@ -348,6 +349,18 @@ void Configuration::loadMemSpec(const DRAMSysConfiguration::MemSpec &memSpecConf
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memSpec = std::make_unique<const MemSpecGDDR6>(memSpecConfig);
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else if (memoryType == "STT-MRAM")
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memSpec = std::make_unique<const MemSpecSTTMRAM>(memSpecConfig);
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#ifdef DDR5_SIM
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else if (memoryType == "DDR5")
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memSpec = std::make_unique<const MemSpecDDR5>(memSpecConfig);
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#endif
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#ifdef LPDDR5_SIM
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else if (memoryType == "LPDDR5")
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memSpec = std::make_unique<const MemSpecLPDDR5>(memSpecConfig);
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#endif
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#ifdef HBM3_SIM
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else if (memoryType == "HBM3")
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memSpec = std::make_unique<const MemSpecHBM3>(memSpecConfig);
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#endif
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else
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SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
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}
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@@ -39,13 +39,10 @@
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#include "checker/CheckerDDR3.h"
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#include "checker/CheckerDDR4.h"
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#include "checker/CheckerDDR5.h"
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#include "checker/CheckerWideIO.h"
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#include "checker/CheckerLPDDR4.h"
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#include "checker/CheckerLPDDR5.h"
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#include "checker/CheckerWideIO2.h"
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#include "checker/CheckerHBM2.h"
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#include "checker/CheckerHBM3.h"
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#include "checker/CheckerGDDR5.h"
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#include "checker/CheckerGDDR5X.h"
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#include "checker/CheckerGDDR6.h"
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@@ -67,6 +64,16 @@
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#include "powerdown/PowerDownManagerStaggered.h"
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#include "powerdown/PowerDownManagerDummy.h"
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#ifdef DDR5_SIM
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#include "checker/CheckerDDR5.h"
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#endif
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#ifdef LPDDR5_SIM
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#include "checker/CheckerLPDDR5.h"
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#endif
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#ifdef HBM3_SIM
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#include "checker/CheckerHBM3.h"
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#endif
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using namespace sc_core;
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using namespace tlm;
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@@ -87,20 +94,14 @@ Controller::Controller(const sc_module_name& name, const Configuration& config)
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checker = std::make_unique<CheckerDDR3>(config);
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else if (memSpec.memoryType == MemSpec::MemoryType::DDR4)
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checker = std::make_unique<CheckerDDR4>(config);
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else if (memSpec.memoryType == MemSpec::MemoryType::DDR5)
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checker = std::make_unique<CheckerDDR5>(config);
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else if (memSpec.memoryType == MemSpec::MemoryType::WideIO)
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checker = std::make_unique<CheckerWideIO>(config);
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else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR4)
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checker = std::make_unique<CheckerLPDDR4>(config);
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else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR5)
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checker = std::make_unique<CheckerLPDDR5>(config);
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::WideIO2)
|
||||
checker = std::make_unique<CheckerWideIO2>(config);
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::HBM2)
|
||||
checker = std::make_unique<CheckerHBM2>(config);
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::HBM3)
|
||||
checker = std::make_unique<CheckerHBM3>(config);
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::GDDR5)
|
||||
checker = std::make_unique<CheckerGDDR5>(config);
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::GDDR5X)
|
||||
@@ -109,6 +110,19 @@ Controller::Controller(const sc_module_name& name, const Configuration& config)
|
||||
checker = std::make_unique<CheckerGDDR6>(config);
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::STTMRAM)
|
||||
checker = std::make_unique<CheckerSTTMRAM>(config);
|
||||
#ifdef DDR5_SIM
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::DDR5)
|
||||
checker = std::make_unique<CheckerDDR5>(config);
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR5)
|
||||
checker = std::make_unique<CheckerLPDDR5>(config);
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
else if (memSpec.memoryType == MemSpec::MemoryType::HBM3)
|
||||
checker = std::make_unique<CheckerHBM3>(config);
|
||||
#endif
|
||||
|
||||
|
||||
// instantiate scheduler and command mux
|
||||
if (config.scheduler == Configuration::Scheduler::Fifo)
|
||||
|
||||
@@ -51,19 +51,26 @@
|
||||
#include "../error/ecchamming.h"
|
||||
#include "dram/DramDDR3.h"
|
||||
#include "dram/DramDDR4.h"
|
||||
#include "dram/DramDDR5.h"
|
||||
#include "dram/DramWideIO.h"
|
||||
#include "dram/DramLPDDR4.h"
|
||||
#include "dram/DramLPDDR5.h"
|
||||
#include "dram/DramWideIO2.h"
|
||||
#include "dram/DramHBM2.h"
|
||||
#include "dram/DramHBM3.h"
|
||||
#include "dram/DramGDDR5.h"
|
||||
#include "dram/DramGDDR5X.h"
|
||||
#include "dram/DramGDDR6.h"
|
||||
#include "dram/DramSTTMRAM.h"
|
||||
#include "../controller/Controller.h"
|
||||
|
||||
#ifdef DDR5_SIM
|
||||
#include "dram/DramDDR5.h"
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
#include "dram/DramLPDDR5.h"
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
#include "dram/DramHBM3.h"
|
||||
#endif
|
||||
|
||||
DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
|
||||
const DRAMSysConfiguration::Configuration &configLib)
|
||||
: DRAMSys(name, configLib, true)
|
||||
@@ -174,27 +181,18 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &add
|
||||
else if (memoryType == MemSpec::MemoryType::DDR4)
|
||||
drams.emplace_back(std::make_unique<DramDDR4>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::DDR5)
|
||||
drams.emplace_back(std::make_unique<DramDDR5>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::WideIO)
|
||||
drams.emplace_back(std::make_unique<DramWideIO>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::LPDDR4)
|
||||
drams.emplace_back(std::make_unique<DramLPDDR4>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::LPDDR5)
|
||||
drams.emplace_back(std::make_unique<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::WideIO2)
|
||||
drams.emplace_back(std::make_unique<DramWideIO2>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::HBM2)
|
||||
drams.emplace_back(std::make_unique<DramHBM2>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::HBM3)
|
||||
drams.emplace_back(std::make_unique<DramHBM3>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
else if (memoryType == MemSpec::MemoryType::GDDR5)
|
||||
drams.emplace_back(std::make_unique<DramGDDR5>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
@@ -207,6 +205,21 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &add
|
||||
else if (memoryType == MemSpec::MemoryType::STTMRAM)
|
||||
drams.emplace_back(std::make_unique<DramSTTMRAM>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
#ifdef DDR5_SIM
|
||||
else if (memoryType == MemSpec::MemoryType::DDR5)
|
||||
drams.emplace_back(std::make_unique<DramDDR5>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
else if (memoryType == MemSpec::MemoryType::LPDDR5)
|
||||
drams.emplace_back(std::make_unique<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
else if (memoryType == MemSpec::MemoryType::HBM3)
|
||||
drams.emplace_back(std::make_unique<DramHBM3>(("dram" + std::to_string(i)).c_str(), config,
|
||||
*temperatureController));
|
||||
#endif
|
||||
|
||||
if (config.checkTLM2Protocol)
|
||||
controllersTlmCheckers.push_back(std::make_unique<tlm_utils::tlm2_base_protocol_checker<>>
|
||||
|
||||
@@ -41,13 +41,10 @@
|
||||
#include "dram/DramRecordable.h"
|
||||
#include "dram/DramDDR3.h"
|
||||
#include "dram/DramDDR4.h"
|
||||
#include "dram/DramDDR5.h"
|
||||
#include "dram/DramWideIO.h"
|
||||
#include "dram/DramLPDDR4.h"
|
||||
#include "dram/DramLPDDR5.h"
|
||||
#include "dram/DramWideIO2.h"
|
||||
#include "dram/DramHBM2.h"
|
||||
#include "dram/DramHBM3.h"
|
||||
#include "dram/DramGDDR5.h"
|
||||
#include "dram/DramGDDR5X.h"
|
||||
#include "dram/DramGDDR6.h"
|
||||
@@ -56,6 +53,16 @@
|
||||
#include "../simulation/TemperatureController.h"
|
||||
#include "../error/ecchamming.h"
|
||||
|
||||
#ifdef DDR5_SIM
|
||||
#include "dram/DramDDR5.h"
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
#include "dram/DramLPDDR5.h"
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
#include "dram/DramHBM3.h"
|
||||
#endif
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
DRAMSysRecordable::DRAMSysRecordable(const sc_module_name& name, const DRAMSysConfiguration::Configuration& configLib)
|
||||
@@ -136,27 +143,18 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
|
||||
else if (memoryType == MemSpec::MemoryType::DDR4)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramDDR4>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::DDR5)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramDDR5>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::WideIO)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::LPDDR4)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR4>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::LPDDR5)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR5>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::WideIO2)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO2>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::HBM2)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramHBM2>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::HBM3)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramHBM3>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
else if (memoryType == MemSpec::MemoryType::GDDR5)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR5>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
@@ -169,6 +167,21 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
|
||||
else if (memoryType == MemSpec::MemoryType::STTMRAM)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramSTTMRAM>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
#ifdef DDR5_SIM
|
||||
else if (memoryType == MemSpec::MemoryType::DDR5)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramDDR5>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
else if (memoryType == MemSpec::MemoryType::LPDDR5)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR5>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
else if (memoryType == MemSpec::MemoryType::HBM3)
|
||||
drams.emplace_back(std::make_unique<DramRecordable<DramHBM3>>(("dram" + std::to_string(i)).c_str(),
|
||||
config, *temperatureController, tlmRecorders[i]));
|
||||
#endif
|
||||
|
||||
if (config.checkTLM2Protocol)
|
||||
controllersTlmCheckers.emplace_back(std::make_unique<tlm_utils::tlm2_base_protocol_checker<>>
|
||||
|
||||
@@ -40,18 +40,25 @@
|
||||
#include "../../common/utils.h"
|
||||
#include "DramDDR3.h"
|
||||
#include "DramDDR4.h"
|
||||
#include "DramDDR5.h"
|
||||
#include "DramWideIO.h"
|
||||
#include "DramLPDDR4.h"
|
||||
#include "DramLPDDR5.h"
|
||||
#include "DramWideIO2.h"
|
||||
#include "DramHBM2.h"
|
||||
#include "DramHBM3.h"
|
||||
#include "DramGDDR5.h"
|
||||
#include "DramGDDR5X.h"
|
||||
#include "DramGDDR6.h"
|
||||
#include "DramSTTMRAM.h"
|
||||
|
||||
#ifdef DDR5_SIM
|
||||
#include "DramDDR5.h"
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
#include "DramLPDDR5.h"
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
#include "DramHBM3.h"
|
||||
#endif
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace tlm;
|
||||
|
||||
@@ -154,14 +161,20 @@ void DramRecordable<BaseDram>::powerWindow()
|
||||
|
||||
template class DramRecordable<DramDDR3>;
|
||||
template class DramRecordable<DramDDR4>;
|
||||
template class DramRecordable<DramDDR5>;
|
||||
template class DramRecordable<DramLPDDR4>;
|
||||
template class DramRecordable<DramLPDDR5>;
|
||||
template class DramRecordable<DramWideIO>;
|
||||
template class DramRecordable<DramWideIO2>;
|
||||
template class DramRecordable<DramGDDR5>;
|
||||
template class DramRecordable<DramGDDR5X>;
|
||||
template class DramRecordable<DramGDDR6>;
|
||||
template class DramRecordable<DramHBM2>;
|
||||
template class DramRecordable<DramHBM3>;
|
||||
template class DramRecordable<DramSTTMRAM>;
|
||||
#ifdef DDR5_SIM
|
||||
template class DramRecordable<DramDDR5>;
|
||||
#endif
|
||||
#ifdef LPDDR5_SIM
|
||||
template class DramRecordable<DramLPDDR5>;
|
||||
#endif
|
||||
#ifdef HBM3_SIM
|
||||
template class DramRecordable<DramHBM3>;
|
||||
#endif
|
||||
Reference in New Issue
Block a user