From df145241cf357d76e0e66c1b3ac52b46a957bc19 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 24 May 2022 14:35:35 +0200 Subject: [PATCH] Add compile definitions for optional standards. --- DRAMSys/library/CMakeLists.txt | 165 +++++------------- .../src/configuration/Configuration.cpp | 31 +++- DRAMSys/library/src/controller/Controller.cpp | 32 +++- DRAMSys/library/src/simulation/DRAMSys.cpp | 37 ++-- .../src/simulation/DRAMSysRecordable.cpp | 37 ++-- .../src/simulation/dram/DramRecordable.cpp | 25 ++- 6 files changed, 157 insertions(+), 170 deletions(-) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 1042eff9..ca779298 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -77,6 +77,33 @@ if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation) ) endif() +if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerDDR5.cpp) + message("== DDR5 included") + set(DDR5_SOURCES + src/configuration/memspec/MemSpecDDR5.cpp + src/controller/checker/CheckerDDR5.cpp + src/simulation/dram/DramDDR5.cpp + ) +endif() + +if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerLPDDR5.cpp) + message("== LPDDR5 included") + set(LPDDR5_SOURCES + src/configuration/memspec/MemSpecLPDDR5.cpp + src/controller/checker/CheckerLPDDR5.cpp + src/simulation/dram/DramLPDDR5.cpp + ) +endif() + +if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerHBM3.cpp) + message("== HBM3 included") + set(HBM3_SOURCES + src/configuration/memspec/MemSpecHBM3.cpp + src/controller/checker/CheckerHBM3.cpp + src/simulation/dram/DramHBM3.cpp + ) +endif() + add_library(DRAMSysLibrary src/common/DebugManager.cpp src/common/dramExtensions.cpp @@ -89,16 +116,13 @@ add_library(DRAMSysLibrary src/configuration/memspec/MemSpec.cpp src/configuration/memspec/MemSpecDDR3.cpp src/configuration/memspec/MemSpecDDR4.cpp - src/configuration/memspec/MemSpecDDR5.cpp src/configuration/memspec/MemSpecLPDDR4.cpp - src/configuration/memspec/MemSpecLPDDR5.cpp src/configuration/memspec/MemSpecWideIO.cpp src/configuration/memspec/MemSpecWideIO2.cpp src/configuration/memspec/MemSpecGDDR5.cpp src/configuration/memspec/MemSpecGDDR5X.cpp src/configuration/memspec/MemSpecGDDR6.cpp src/configuration/memspec/MemSpecHBM2.cpp - src/configuration/memspec/MemSpecHBM3.cpp src/configuration/memspec/MemSpecSTTMRAM.cpp src/controller/BankMachine.cpp @@ -109,16 +133,13 @@ add_library(DRAMSysLibrary src/controller/checker/CheckerIF.h src/controller/checker/CheckerDDR3.cpp src/controller/checker/CheckerDDR4.cpp - src/controller/checker/CheckerDDR5.cpp src/controller/checker/CheckerLPDDR4.cpp - src/controller/checker/CheckerLPDDR5.cpp src/controller/checker/CheckerWideIO.cpp src/controller/checker/CheckerWideIO2.cpp src/controller/checker/CheckerGDDR5.cpp src/controller/checker/CheckerGDDR5X.cpp src/controller/checker/CheckerGDDR6.cpp src/controller/checker/CheckerHBM2.cpp - src/controller/checker/CheckerHBM3.cpp src/controller/checker/CheckerSTTMRAM.cpp src/controller/cmdmux/CmdMuxIF.h @@ -168,134 +189,34 @@ add_library(DRAMSysLibrary src/simulation/dram/Dram.cpp src/simulation/dram/DramDDR3.cpp - src/simulation/dram/DramDDR4.cpp - src/simulation/dram/DramDDR5.cpp + src/simulation/dram/DramDDR4.cpp src/simulation/dram/DramLPDDR4.cpp - src/simulation/dram/DramLPDDR5.cpp src/simulation/dram/DramWideIO.cpp src/simulation/dram/DramWideIO2.cpp src/simulation/dram/DramGDDR5.cpp src/simulation/dram/DramGDDR5X.cpp src/simulation/dram/DramGDDR6.cpp src/simulation/dram/DramHBM2.cpp - src/simulation/dram/DramHBM3.cpp src/simulation/dram/DramSTTMRAM.cpp ${RECORDING_SOURCES} - - - # Simulation Config Files - resources/simulations/ddr3-example.json - resources/simulations/ddr3-example2.json - resources/simulations/ddr3-gem5-se.json - resources/simulations/ddr4-example.json - resources/simulations/hbm2-example.json - resources/simulations/hbm3-example.json - resources/simulations/lpddr4-example.json - resources/simulations/ranktest.json - resources/simulations/wideio-example.json - resources/simulations/wideio-thermal.json - - # Address Mapping Config Files - resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json - resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json - resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json - resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json - resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json - resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json - resources/configs/amconfigs/am_ddr3_x16_brc.json - resources/configs/amconfigs/am_ddr3_x16_rbc.json - resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json - resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json - resources/configs/amconfigs/am_hbm3_8Gb_pc_brc.json - resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json - resources/configs/amconfigs/am_ranktest.json - resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json - resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x1Gb_brc.json - resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x256Mb_brc.json - resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json - resources/configs/amconfigs/am_wideio_4x2Gb_brc.json - resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x4Gb_brc.json - resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json - resources/configs/amconfigs/am_wideio_4x512Mb_brc.json - resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json - - # Memory Controller Config Files - resources/configs/mcconfigs/fifo.json - resources/configs/mcconfigs/fifoStrict.json - resources/configs/mcconfigs/fr_fcfs_grp.json - resources/configs/mcconfigs/fr_fcfs.json - - # Memspec Config Files - resources/configs/memspecs/HBM2.json - resources/configs/memspecs/HBM3.json - resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json - resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json - resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json - resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json - resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json - resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json - resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json - resources/configs/memspecs/memspec_ranktest.json - resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json - resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json - resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json - resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json - resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json - resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json - resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json - resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json - resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json - resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json - resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json - resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json - resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json - resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json - resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json - resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json - resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json - resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json - resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json - resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json - - # Simulator Config Files - resources/configs/simulator/ddr3_ecc.json - resources/configs/simulator/ddr3.json - resources/configs/simulator/ddr3_gem5_se.json - resources/configs/simulator/ddr4.json - resources/configs/simulator/hbm2.json - resources/configs/simulator/hbm3.json - resources/configs/simulator/lpddr4.json - resources/configs/simulator/wideio.json - resources/configs/simulator/wideio_thermal.json - - # Thermal Simulation Config Files - resources/configs/thermalsim/config.json - resources/configs/thermalsim/powerInfo.json + ${DDR5_SOURCES} + ${LPDDR5_SOURCES} + ${HBM3_SOURCES} ) +if(DEFINED DDR5_SOURCES) + target_compile_definitions(DRAMSysLibrary PRIVATE DDR5_SIM) +endif() + +if(DEFINED LPDDR5_SOURCES) + target_compile_definitions(DRAMSysLibrary PRIVATE LPDDR5_SIM) +endif() + +if(DEFINED HBM3_SOURCES) + target_compile_definitions(DRAMSysLibrary PRIVATE HBM3_SIM) +endif() + if(DEFINED ENV{LIBTHREED_ICE_HOME}) message("== Thermal simulation available") target_compile_definitions(DRAMSysLibrary PRIVATE THERMALSIM) diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index a4532f6f..3306c479 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -42,18 +42,25 @@ #include "Configuration.h" #include "memspec/MemSpecDDR3.h" #include "memspec/MemSpecDDR4.h" -#include "memspec/MemSpecDDR5.h" #include "memspec/MemSpecWideIO.h" #include "memspec/MemSpecLPDDR4.h" -#include "memspec/MemSpecLPDDR5.h" #include "memspec/MemSpecWideIO2.h" #include "memspec/MemSpecHBM2.h" -#include "memspec/MemSpecHBM3.h" #include "memspec/MemSpecGDDR5.h" #include "memspec/MemSpecGDDR5X.h" #include "memspec/MemSpecGDDR6.h" #include "memspec/MemSpecSTTMRAM.h" +#ifdef DDR5_SIM +#include "memspec/MemSpecDDR5.h" +#endif +#ifdef LPDDR5_SIM +#include "memspec/MemSpecLPDDR5.h" +#endif +#ifdef HBM3_SIM +#include "memspec/MemSpecHBM3.h" +#endif + using namespace sc_core; enum sc_time_unit string2TimeUnit(const std::string &s) @@ -326,20 +333,14 @@ void Configuration::loadMemSpec(const DRAMSysConfiguration::MemSpec &memSpecConf memSpec = std::make_unique(memSpecConfig); else if (memoryType == "DDR4") memSpec = std::make_unique(memSpecConfig); - else if (memoryType == "DDR5") - memSpec = std::make_unique(memSpecConfig); else if (memoryType == "LPDDR4") memSpec = std::make_unique(memSpecConfig); - else if (memoryType == "LPDDR5") - memSpec = std::make_unique(memSpecConfig); else if (memoryType == "WIDEIO_SDR") memSpec = std::make_unique(memSpecConfig); else if (memoryType == "WIDEIO2") memSpec = std::make_unique(memSpecConfig); else if (memoryType == "HBM2") memSpec = std::make_unique(memSpecConfig); - else if (memoryType == "HBM3") - memSpec = std::make_unique(memSpecConfig); else if (memoryType == "GDDR5") memSpec = std::make_unique(memSpecConfig); else if (memoryType == "GDDR5X") @@ -348,6 +349,18 @@ void Configuration::loadMemSpec(const DRAMSysConfiguration::MemSpec &memSpecConf memSpec = std::make_unique(memSpecConfig); else if (memoryType == "STT-MRAM") memSpec = std::make_unique(memSpecConfig); +#ifdef DDR5_SIM + else if (memoryType == "DDR5") + memSpec = std::make_unique(memSpecConfig); +#endif +#ifdef LPDDR5_SIM + else if (memoryType == "LPDDR5") + memSpec = std::make_unique(memSpecConfig); +#endif +#ifdef HBM3_SIM + else if (memoryType == "HBM3") + memSpec = std::make_unique(memSpecConfig); +#endif else SC_REPORT_FATAL("Configuration", "Unsupported DRAM type"); } diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index dc924869..45d9ac69 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -39,13 +39,10 @@ #include "checker/CheckerDDR3.h" #include "checker/CheckerDDR4.h" -#include "checker/CheckerDDR5.h" #include "checker/CheckerWideIO.h" #include "checker/CheckerLPDDR4.h" -#include "checker/CheckerLPDDR5.h" #include "checker/CheckerWideIO2.h" #include "checker/CheckerHBM2.h" -#include "checker/CheckerHBM3.h" #include "checker/CheckerGDDR5.h" #include "checker/CheckerGDDR5X.h" #include "checker/CheckerGDDR6.h" @@ -67,6 +64,16 @@ #include "powerdown/PowerDownManagerStaggered.h" #include "powerdown/PowerDownManagerDummy.h" +#ifdef DDR5_SIM +#include "checker/CheckerDDR5.h" +#endif +#ifdef LPDDR5_SIM +#include "checker/CheckerLPDDR5.h" +#endif +#ifdef HBM3_SIM +#include "checker/CheckerHBM3.h" +#endif + using namespace sc_core; using namespace tlm; @@ -87,20 +94,14 @@ Controller::Controller(const sc_module_name& name, const Configuration& config) checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::DDR4) checker = std::make_unique(config); - else if (memSpec.memoryType == MemSpec::MemoryType::DDR5) - checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::WideIO) checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR4) checker = std::make_unique(config); - else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR5) - checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::WideIO2) checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::HBM2) checker = std::make_unique(config); - else if (memSpec.memoryType == MemSpec::MemoryType::HBM3) - checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::GDDR5) checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::GDDR5X) @@ -109,6 +110,19 @@ Controller::Controller(const sc_module_name& name, const Configuration& config) checker = std::make_unique(config); else if (memSpec.memoryType == MemSpec::MemoryType::STTMRAM) checker = std::make_unique(config); +#ifdef DDR5_SIM + else if (memSpec.memoryType == MemSpec::MemoryType::DDR5) + checker = std::make_unique(config); +#endif +#ifdef LPDDR5_SIM + else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR5) + checker = std::make_unique(config); +#endif +#ifdef HBM3_SIM + else if (memSpec.memoryType == MemSpec::MemoryType::HBM3) + checker = std::make_unique(config); +#endif + // instantiate scheduler and command mux if (config.scheduler == Configuration::Scheduler::Fifo) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index bb02397d..f9074595 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -51,19 +51,26 @@ #include "../error/ecchamming.h" #include "dram/DramDDR3.h" #include "dram/DramDDR4.h" -#include "dram/DramDDR5.h" #include "dram/DramWideIO.h" #include "dram/DramLPDDR4.h" -#include "dram/DramLPDDR5.h" #include "dram/DramWideIO2.h" #include "dram/DramHBM2.h" -#include "dram/DramHBM3.h" #include "dram/DramGDDR5.h" #include "dram/DramGDDR5X.h" #include "dram/DramGDDR6.h" #include "dram/DramSTTMRAM.h" #include "../controller/Controller.h" +#ifdef DDR5_SIM +#include "dram/DramDDR5.h" +#endif +#ifdef LPDDR5_SIM +#include "dram/DramLPDDR5.h" +#endif +#ifdef HBM3_SIM +#include "dram/DramHBM3.h" +#endif + DRAMSys::DRAMSys(const sc_core::sc_module_name &name, const DRAMSysConfiguration::Configuration &configLib) : DRAMSys(name, configLib, true) @@ -174,27 +181,18 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &add else if (memoryType == MemSpec::MemoryType::DDR4) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); - else if (memoryType == MemSpec::MemoryType::DDR5) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); else if (memoryType == MemSpec::MemoryType::WideIO) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); else if (memoryType == MemSpec::MemoryType::LPDDR4) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); - else if (memoryType == MemSpec::MemoryType::LPDDR5) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); else if (memoryType == MemSpec::MemoryType::WideIO2) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); else if (memoryType == MemSpec::MemoryType::HBM2) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); - else if (memoryType == MemSpec::MemoryType::HBM3) - drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, - *temperatureController)); else if (memoryType == MemSpec::MemoryType::GDDR5) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); @@ -207,6 +205,21 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &add else if (memoryType == MemSpec::MemoryType::STTMRAM) drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, *temperatureController)); +#ifdef DDR5_SIM + else if (memoryType == MemSpec::MemoryType::DDR5) + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, + *temperatureController)); +#endif +#ifdef LPDDR5_SIM + else if (memoryType == MemSpec::MemoryType::LPDDR5) + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, + *temperatureController)); +#endif +#ifdef HBM3_SIM + else if (memoryType == MemSpec::MemoryType::HBM3) + drams.emplace_back(std::make_unique(("dram" + std::to_string(i)).c_str(), config, + *temperatureController)); +#endif if (config.checkTLM2Protocol) controllersTlmCheckers.push_back(std::make_unique> diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 3f16c0f6..27e62e5f 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -41,13 +41,10 @@ #include "dram/DramRecordable.h" #include "dram/DramDDR3.h" #include "dram/DramDDR4.h" -#include "dram/DramDDR5.h" #include "dram/DramWideIO.h" #include "dram/DramLPDDR4.h" -#include "dram/DramLPDDR5.h" #include "dram/DramWideIO2.h" #include "dram/DramHBM2.h" -#include "dram/DramHBM3.h" #include "dram/DramGDDR5.h" #include "dram/DramGDDR5X.h" #include "dram/DramGDDR6.h" @@ -56,6 +53,16 @@ #include "../simulation/TemperatureController.h" #include "../error/ecchamming.h" +#ifdef DDR5_SIM +#include "dram/DramDDR5.h" +#endif +#ifdef LPDDR5_SIM +#include "dram/DramLPDDR5.h" +#endif +#ifdef HBM3_SIM +#include "dram/DramHBM3.h" +#endif + using namespace sc_core; DRAMSysRecordable::DRAMSysRecordable(const sc_module_name& name, const DRAMSysConfiguration::Configuration& configLib) @@ -136,27 +143,18 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, else if (memoryType == MemSpec::MemoryType::DDR4) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); - else if (memoryType == MemSpec::MemoryType::DDR5) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::WideIO) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::LPDDR4) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); - else if (memoryType == MemSpec::MemoryType::LPDDR5) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::WideIO2) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::HBM2) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); - else if (memoryType == MemSpec::MemoryType::HBM3) - drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), - config, *temperatureController, tlmRecorders[i])); else if (memoryType == MemSpec::MemoryType::GDDR5) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); @@ -169,6 +167,21 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, else if (memoryType == MemSpec::MemoryType::STTMRAM) drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), config, *temperatureController, tlmRecorders[i])); +#ifdef DDR5_SIM + else if (memoryType == MemSpec::MemoryType::DDR5) + drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), + config, *temperatureController, tlmRecorders[i])); +#endif +#ifdef LPDDR5_SIM + else if (memoryType == MemSpec::MemoryType::LPDDR5) + drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), + config, *temperatureController, tlmRecorders[i])); +#endif +#ifdef HBM3_SIM + else if (memoryType == MemSpec::MemoryType::HBM3) + drams.emplace_back(std::make_unique>(("dram" + std::to_string(i)).c_str(), + config, *temperatureController, tlmRecorders[i])); +#endif if (config.checkTLM2Protocol) controllersTlmCheckers.emplace_back(std::make_unique> diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 9d4cc8d2..5902f745 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -40,18 +40,25 @@ #include "../../common/utils.h" #include "DramDDR3.h" #include "DramDDR4.h" -#include "DramDDR5.h" #include "DramWideIO.h" #include "DramLPDDR4.h" -#include "DramLPDDR5.h" #include "DramWideIO2.h" #include "DramHBM2.h" -#include "DramHBM3.h" #include "DramGDDR5.h" #include "DramGDDR5X.h" #include "DramGDDR6.h" #include "DramSTTMRAM.h" +#ifdef DDR5_SIM +#include "DramDDR5.h" +#endif +#ifdef LPDDR5_SIM +#include "DramLPDDR5.h" +#endif +#ifdef HBM3_SIM +#include "DramHBM3.h" +#endif + using namespace sc_core; using namespace tlm; @@ -154,14 +161,20 @@ void DramRecordable::powerWindow() template class DramRecordable; template class DramRecordable; -template class DramRecordable; template class DramRecordable; -template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; -template class DramRecordable; template class DramRecordable; +#ifdef DDR5_SIM +template class DramRecordable; +#endif +#ifdef LPDDR5_SIM +template class DramRecordable; +#endif +#ifdef HBM3_SIM +template class DramRecordable; +#endif \ No newline at end of file