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Corrected pools time tracking.

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This commit is contained in:
Iron Prando da Silva
2022-03-24 10:21:54 +01:00
parent 828191af5a
commit cf8d58898f
11 changed files with 229 additions and 211 deletions
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30
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp
View File

@@ -36,7 +36,7 @@
#include "poolcontroller.h"
#include <algorithm>
PoolController::PoolController(const uint poolSize, const std::vector<StringMapper>& dependencies)
PoolController::PoolController(const uint poolSize, const std::vector<PoolEntry>& dependencies)
: mDependencies(mAuxSortInput(dependencies))
{
mPoolSize = poolSize;
@@ -65,17 +65,33 @@ void PoolController::merge(std::vector<DBDependencyEntry>& depEntries) {
}
}
bool PoolController::isDependency(const StringMapper& phaseName) {
return std::binary_search(
uint PoolController::getBusyTime(const StringMapper& phaseName) {
PoolEntry v{phaseName, 0};
auto entryIt = std::lower_bound(
mDependencies.begin(),
mDependencies.end(),
phaseName,
StringMapper::compare
v,
[](const PoolEntry& e1, const PoolEntry& e2) {
return e1.first < e2.first;
}
);
if (entryIt->first == phaseName) {
return entryIt->second;
} else {
return 0;
}
}
std::vector<StringMapper> PoolController::mAuxSortInput(std::vector<StringMapper> vec) {
std::sort(vec.begin(), vec.end());
std::vector<PoolEntry> PoolController::mAuxSortInput(std::vector<PoolEntry> vec) {
std::sort(
vec.begin(),
vec.end(),
[](const PoolEntry& e1, const PoolEntry& e2) {
return e1.first < e2.first;
}
);
return vec;
}

10
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h
View File

@@ -37,9 +37,11 @@
#include "businessObjects/dramTimeDependencies/common/common.h"
typedef std::pair<StringMapper, uint> PoolEntry;
class PoolController {
public:
PoolController(const uint poolSize, const std::vector<StringMapper>& dependencies);
PoolController(const uint poolSize, const std::vector<PoolEntry>& dependencies);
~PoolController() = default;
void clear();
@@ -48,14 +50,14 @@ public:
void merge(std::vector<DBDependencyEntry>& depEntries);
size_t count() { return mCount; }
bool isDependency(const StringMapper& phaseName);
uint getBusyTime(const StringMapper& phaseName);
protected:
const std::vector<StringMapper> mDependencies;
const std::vector<PoolEntry> mDependencies;
std::vector<DBDependencyEntry> mPool;
uint mCount = 0;
uint mPoolSize = 0;
protected:
static std::vector<StringMapper> mAuxSortInput(std::vector<StringMapper> vec);
static std::vector<PoolEntry> mAuxSortInput(std::vector<PoolEntry> vec);
};

6
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp
View File

@@ -72,14 +72,14 @@ void PoolControllerMap::merge(std::vector<DBDependencyEntry>& depEntries) {
}
}
bool PoolControllerMap::isDependency(const StringMapper& poolName, const StringMapper& phaseName) {
uint PoolControllerMap::getBusyTime(const StringMapper& poolName, const StringMapper& phaseName) {
auto pool = mPools.find(poolName);
if (pool != mPools.end()) {
return pool->second.isDependency(phaseName);
return pool->second.getBusyTime(phaseName);
} else {
// TODO throw?
return false;
return 0;
}
}

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h
View File

@@ -48,7 +48,7 @@ public:
void merge(std::vector<DBDependencyEntry>& depEntries);
size_t count(const StringMapper& poolName);
bool isDependency(const StringMapper& poolName, const StringMapper& phaseName);
uint getBusyTime(const StringMapper& poolName, const StringMapper& phaseName);
protected:

44
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
View File

@@ -45,28 +45,6 @@ void DDR3TimeDependencies::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"PREPB",
"RDA",
"WRA",
"REFAB",
"PREAB",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
"PDEA",
"PDXA",
}
}
});
mPools.insert({"NAW", {4, {"ACT"}}});
tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
@@ -105,6 +83,28 @@ void DDR3TimeDependencies::mInitializeValues() {
tWRPDEN = tWL + tBURST + tWR;
tWRAPDEN = tWL + tBURST + tWR + tCK;
mPools.insert({
"CMD_BUS", {
1, {
{"ACT", tCK},
{"RD", tCK},
{"WR", tCK},
{"PREPB", tCK},
{"RDA", tCK},
{"WRA", tCK},
{"REFAB", tCK},
{"PREAB", tCK},
{"PDEP", tCK},
{"PDXP", tCK},
{"SREFEN", tCK},
{"SREFEX", tCK},
{"PDEA", tCK},
{"PDXA", tCK},
}
}
});
mPools.insert({"NAW", {4, {{"ACT", tFAW}}}});
}
const vector<QString> DDR3TimeDependencies::getPossiblePhases() {

58
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp
View File

@@ -45,35 +45,6 @@ void TimeDependenciesInfoDDR3::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"PREPB",
"RDA",
"WRA",
"REFAB",
"PREAB",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
"PDEA",
"PDXA",
}
}
});
mPools.insert({
"NAW", {
4, {
"ACT",
}
}
});
tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt();
tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
@@ -112,6 +83,35 @@ void TimeDependenciesInfoDDR3::mInitializeValues() {
tWRPDEN = tWL + tBURST + tWR;
tWRAPDEN = tWL + tBURST + tWR + tCK;
mPools.insert({
"CMD_BUS", {
1, {
{"ACT", tCK},
{"RD", tCK},
{"WR", tCK},
{"PREPB", tCK},
{"RDA", tCK},
{"WRA", tCK},
{"REFAB", tCK},
{"PREAB", tCK},
{"PDEP", tCK},
{"PDXP", tCK},
{"SREFEN", tCK},
{"SREFEX", tCK},
{"PDEA", tCK},
{"PDXA", tCK},
}
}
});
mPools.insert({
"NAW", {
4, {
{"ACT", tFAW},
}
}
});
}
const std::vector<QString> TimeDependenciesInfoDDR3::getPossiblePhases() {

58
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp
View File

@@ -45,35 +45,6 @@ void TimeDependenciesInfoDDR4::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"PREPB",
"RDA",
"WRA",
"REFAB",
"PREAB",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
"PDEA",
"PDXA",
}
}
});
mPools.insert({
"NAW", {
4, {
"ACT",
}
}
});
tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
@@ -128,6 +99,35 @@ void TimeDependenciesInfoDDR4::mInitializeValues() {
tWRPDEN = tWL + tBURST + tWR;
tWRAPDEN = tWL + tBURST + tWR + tCK;
mPools.insert({
"CMD_BUS", {
1, {
{"ACT", tCK},
{"RD", tCK},
{"WR", tCK},
{"PREPB", tCK},
{"RDA", tCK},
{"WRA", tCK},
{"REFAB", tCK},
{"PREAB", tCK},
{"PDEP", tCK},
{"PDXP", tCK},
{"SREFEN", tCK},
{"SREFEX", tCK},
{"PDEA", tCK},
{"PDXA", tCK},
}
}
});
mPools.insert({
"NAW", {
4, {
{"ACT", tFAW},
}
}
});
}
const std::vector<QString> TimeDependenciesInfoDDR4::getPossiblePhases() {

78
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
View File

@@ -69,45 +69,6 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt();
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"RDA",
"WRA",
"PREPB",
"PREAB",
"REFAB",
"PRESB",
"RFMAB",
"REFSB",
"RFMSB",
}
}
});
mPools.insert({
"FAW_LOGICAL", {
4, {
"ACT",
"REFSB",
"RFMSB",
}
}
});
mPools.insert({
"FAW_PHYSICAL", {
4, {
"ACT",
"REFSB",
"RFMSB",
}
}
});
tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
@@ -208,6 +169,45 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
mPools.insert({
"CMD_BUS", {
1, {
{"ACT", 2 * tCK},
{"RD", 2 * tCK},
{"WR", 2 * tCK},
{"RDA", 2 * tCK},
{"WRA", 2 * tCK},
{"PREPB", tCK},
{"PREAB", tCK},
{"REFAB", tCK},
{"PRESB", tCK},
{"RFMAB", tCK},
{"REFSB", tCK},
{"RFMSB", tCK},
}
}
});
mPools.insert({
"FAW_LOGICAL", {
4, {
{"ACT", tFAW_slr - longCmdOffset},
{"REFSB", tFAW_slr - shortCmdOffset},
{"RFMSB", tFAW_slr - shortCmdOffset},
}
}
});
mPools.insert({
"FAW_PHYSICAL", {
4, {
{"ACT", tFAW_dlr - longCmdOffset},
{"REFSB", tFAW_dlr - shortCmdOffset},
{"RFMSB", tFAW_dlr - shortCmdOffset},
}
}
});
}
const std::vector<QString> TimeDependenciesInfoDDR5::getPossiblePhases() {

88
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp
View File

@@ -45,50 +45,6 @@ void TimeDependenciesInfoHBM2::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({
"RAS_BUS", {
1, {
"ACT",
"PREPB",
"PREAB",
"REFPB",
"REFAB",
"PDEA",
"PDXA",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
}
}
});
mPools.insert({
"CAS_BUS", {
1, {
"RD",
"RDA",
"WR",
"WRA",
"PDEA",
"PDXA",
"PDEP",
"PDXP",
"SREFEN",
"SREFEX",
}
}
});
mPools.insert({
"NAW", {
4, {
"ACT",
"REFPB",
}
}
});
tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
@@ -126,6 +82,50 @@ void TimeDependenciesInfoHBM2::mInitializeValues() {
tWRRDS = tWL + tBURST + tWTRS;
tWRRDL = tWL + tBURST + tWTRL;
mPools.insert({
"RAS_BUS", {
1, {
{"ACT", 2*tCK},
{"PREPB", tCK},
{"PREAB", tCK},
{"REFPB", tCK},
{"REFAB", tCK},
{"PDEA", tCK},
{"PDXA", tCK},
{"PDEP", tCK},
{"PDXP", tCK},
{"SREFEN", tCK},
{"SREFEX", tCK},
}
}
});
mPools.insert({
"CAS_BUS", {
1, {
{"RD", tCK},
{"RDA", tCK},
{"WR", tCK},
{"WRA", tCK},
{"PDEA", tCK},
{"PDXA", tCK},
{"PDEP", tCK},
{"PDXP", tCK},
{"SREFEN", tCK},
{"SREFEX", tCK},
}
}
});
mPools.insert({
"NAW", {
4, {
{"ACT", tFAW},
{"REFPB", tFAW},
}
}
});
}
const std::vector<QString> TimeDependenciesInfoHBM2::getPossiblePhases() {

54
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp
View File

@@ -45,33 +45,6 @@ void TimeDependenciesInfoLPDDR4::mInitializeValues() {
burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
mPools.insert({
"CMD_BUS", {
1, {
"ACT",
"RD",
"WR",
"RDA",
"WRA",
"PREPB",
"PREAB",
"REFAB",
"SREFEN",
"SREFEX",
"REFPB",
}
}
});
mPools.insert({
"NAW", {
4, {
"ACT",
"REFPB",
}
}
});
tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
@@ -119,6 +92,33 @@ void TimeDependenciesInfoLPDDR4::mInitializeValues() {
tREFPDEN = tCK + tCMDCKE;
tSREFPDEN = tCK + tESCKE;
mPools.insert({
"CMD_BUS", {
1, {
{"ACT", 4 * tCK},
{"RD", 4 * tCK},
{"WR", 4 * tCK},
{"RDA", 4 * tCK},
{"WRA", 4 * tCK},
{"PREPB", 2 * tCK},
{"PREAB", 2 * tCK},
{"REFAB", 2 * tCK},
{"SREFEN", 2 * tCK},
{"SREFEX", 2 * tCK},
{"REFPB", 2 * tCK},
}
}
});
mPools.insert({
"NAW", {
4, {
{"ACT", tFAW},
{"REFPB", tFAW},
}
}
});
}
const std::vector<QString> TimeDependenciesInfoLPDDR4::getPossiblePhases() {

12
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
View File

@@ -247,10 +247,11 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr<Configura
}
if (isPoolDep) {
// Captures activate window dependencies
// Captures activate window and command bus dependencies
if (poolController.isDependency(dep.phaseDep, otherPhase->phaseName)) {
if (timeDiff == dep.timeValue) {
auto busyTime = poolController.getBusyTime(dep.phaseDep, otherPhase->phaseName);
if (busyTime > 0 && timeDiff <= busyTime) {
if (timeDiff == busyTime) {
// Captures only the first (exactly matching time) phase in
// the pool window as a dependency
poolController.push(dep.phaseDep, DBDependencyEntry{
@@ -263,14 +264,13 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr<Configura
});
}
if (timeDiff < dep.timeValue) {
if (timeDiff < busyTime) {
poolController.increment(dep.phaseDep);
}
}
continue; // TODO should this continue here or should it be removed for potentially more time dependencies to be captured?
continue;
}
if (timeDiff == dep.timeValue) {