From cf8d58898f2d8613b071251292b049acc72b9ac9 Mon Sep 17 00:00:00 2001 From: Iron Prando da Silva Date: Thu, 24 Mar 2022 10:21:54 +0100 Subject: [PATCH] Corrected pools time tracking. --- .../deviceDependencies/poolcontroller.cpp | 30 +++++-- .../deviceDependencies/poolcontroller.h | 10 ++- .../deviceDependencies/poolcontrollermap.cpp | 6 +- .../deviceDependencies/poolcontrollermap.h | 2 +- .../specialized/DDR3TimeDependencies.cpp | 44 +++++----- .../specialized/TimeDependenciesInfoDDR3.cpp | 58 ++++++------ .../specialized/TimeDependenciesInfoDDR4.cpp | 58 ++++++------ .../specialized/TimeDependenciesInfoDDR5.cpp | 78 ++++++++-------- .../specialized/TimeDependenciesInfoHBM2.cpp | 88 +++++++++---------- .../TimeDependenciesInfoLPDDR4.cpp | 54 ++++++------ .../phasedependenciestracker.cpp | 12 +-- 11 files changed, 229 insertions(+), 211 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp index b54fcc84..3aff2149 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp @@ -36,7 +36,7 @@ #include "poolcontroller.h" #include -PoolController::PoolController(const uint poolSize, const std::vector& dependencies) +PoolController::PoolController(const uint poolSize, const std::vector& dependencies) : mDependencies(mAuxSortInput(dependencies)) { mPoolSize = poolSize; @@ -65,17 +65,33 @@ void PoolController::merge(std::vector& depEntries) { } } -bool PoolController::isDependency(const StringMapper& phaseName) { - return std::binary_search( +uint PoolController::getBusyTime(const StringMapper& phaseName) { + PoolEntry v{phaseName, 0}; + + auto entryIt = std::lower_bound( mDependencies.begin(), mDependencies.end(), - phaseName, - StringMapper::compare + v, + [](const PoolEntry& e1, const PoolEntry& e2) { + return e1.first < e2.first; + } ); + + if (entryIt->first == phaseName) { + return entryIt->second; + } else { + return 0; + } } -std::vector PoolController::mAuxSortInput(std::vector vec) { - std::sort(vec.begin(), vec.end()); +std::vector PoolController::mAuxSortInput(std::vector vec) { + std::sort( + vec.begin(), + vec.end(), + [](const PoolEntry& e1, const PoolEntry& e2) { + return e1.first < e2.first; + } + ); return vec; } \ No newline at end of file diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h index ac650bf9..e7eb76fb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h @@ -37,9 +37,11 @@ #include "businessObjects/dramTimeDependencies/common/common.h" +typedef std::pair PoolEntry; + class PoolController { public: - PoolController(const uint poolSize, const std::vector& dependencies); + PoolController(const uint poolSize, const std::vector& dependencies); ~PoolController() = default; void clear(); @@ -48,14 +50,14 @@ public: void merge(std::vector& depEntries); size_t count() { return mCount; } - bool isDependency(const StringMapper& phaseName); + uint getBusyTime(const StringMapper& phaseName); protected: - const std::vector mDependencies; + const std::vector mDependencies; std::vector mPool; uint mCount = 0; uint mPoolSize = 0; protected: - static std::vector mAuxSortInput(std::vector vec); + static std::vector mAuxSortInput(std::vector vec); }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp index c20f7d18..ae00c001 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp @@ -72,14 +72,14 @@ void PoolControllerMap::merge(std::vector& depEntries) { } } -bool PoolControllerMap::isDependency(const StringMapper& poolName, const StringMapper& phaseName) { +uint PoolControllerMap::getBusyTime(const StringMapper& poolName, const StringMapper& phaseName) { auto pool = mPools.find(poolName); if (pool != mPools.end()) { - return pool->second.isDependency(phaseName); + return pool->second.getBusyTime(phaseName); } else { // TODO throw? - return false; + return 0; } } diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h index fa5b7910..1266c852 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h @@ -48,7 +48,7 @@ public: void merge(std::vector& depEntries); size_t count(const StringMapper& poolName); - bool isDependency(const StringMapper& poolName, const StringMapper& phaseName); + uint getBusyTime(const StringMapper& poolName, const StringMapper& phaseName); protected: diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp index 9382eadf..827849df 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp @@ -45,28 +45,6 @@ void DDR3TimeDependencies::mInitializeValues() { burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - mPools.insert({ - "CMD_BUS", { - 1, { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - } - } - }); - mPools.insert({"NAW", {4, {"ACT"}}}); - tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); @@ -105,6 +83,28 @@ void DDR3TimeDependencies::mInitializeValues() { tWRPDEN = tWL + tBURST + tWR; tWRAPDEN = tWL + tBURST + tWR + tCK; + mPools.insert({ + "CMD_BUS", { + 1, { + {"ACT", tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"PREPB", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"REFAB", tCK}, + {"PREAB", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + } + } + }); + mPools.insert({"NAW", {4, {{"ACT", tFAW}}}}); + } const vector DDR3TimeDependencies::getPossiblePhases() { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp index d3cc0756..7b2db32d 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp @@ -45,35 +45,6 @@ void TimeDependenciesInfoDDR3::mInitializeValues() { burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - mPools.insert({ - "CMD_BUS", { - 1, { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - } - } - }); - - mPools.insert({ - "NAW", { - 4, { - "ACT", - } - } - }); - tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt(); tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); @@ -112,6 +83,35 @@ void TimeDependenciesInfoDDR3::mInitializeValues() { tWRPDEN = tWL + tBURST + tWR; tWRAPDEN = tWL + tBURST + tWR + tCK; + mPools.insert({ + "CMD_BUS", { + 1, { + {"ACT", tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"PREPB", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"REFAB", tCK}, + {"PREAB", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + } + } + }); + + mPools.insert({ + "NAW", { + 4, { + {"ACT", tFAW}, + } + } + }); + } const std::vector TimeDependenciesInfoDDR3::getPossiblePhases() { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp index afcd0b62..78c41b64 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp @@ -45,35 +45,6 @@ void TimeDependenciesInfoDDR4::mInitializeValues() { burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - mPools.insert({ - "CMD_BUS", { - 1, { - "ACT", - "RD", - "WR", - "PREPB", - "RDA", - "WRA", - "REFAB", - "PREAB", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - "PDEA", - "PDXA", - } - } - }); - - mPools.insert({ - "NAW", { - 4, { - "ACT", - } - } - }); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); @@ -128,6 +99,35 @@ void TimeDependenciesInfoDDR4::mInitializeValues() { tWRPDEN = tWL + tBURST + tWR; tWRAPDEN = tWL + tBURST + tWR + tCK; + mPools.insert({ + "CMD_BUS", { + 1, { + {"ACT", tCK}, + {"RD", tCK}, + {"WR", tCK}, + {"PREPB", tCK}, + {"RDA", tCK}, + {"WRA", tCK}, + {"REFAB", tCK}, + {"PREAB", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + } + } + }); + + mPools.insert({ + "NAW", { + 4, { + {"ACT", tFAW}, + } + } + }); + } const std::vector TimeDependenciesInfoDDR4::getPossiblePhases() { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp index dc087ca7..c36b40b5 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp @@ -69,45 +69,6 @@ void TimeDependenciesInfoDDR5::mInitializeValues() { cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt(); bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt(); - mPools.insert({ - "CMD_BUS", { - 1, { - "ACT", - "RD", - "WR", - "RDA", - "WRA", - "PREPB", - "PREAB", - "REFAB", - "PRESB", - "RFMAB", - "REFSB", - "RFMSB", - } - } - }); - - mPools.insert({ - "FAW_LOGICAL", { - 4, { - "ACT", - "REFSB", - "RFMSB", - } - } - }); - - mPools.insert({ - "FAW_PHYSICAL", { - 4, { - "ACT", - "REFSB", - "RFMSB", - } - } - }); - tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt(); tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); @@ -208,6 +169,45 @@ void TimeDependenciesInfoDDR5::mInitializeValues() { tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff; tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff; + mPools.insert({ + "CMD_BUS", { + 1, { + {"ACT", 2 * tCK}, + {"RD", 2 * tCK}, + {"WR", 2 * tCK}, + {"RDA", 2 * tCK}, + {"WRA", 2 * tCK}, + {"PREPB", tCK}, + {"PREAB", tCK}, + {"REFAB", tCK}, + {"PRESB", tCK}, + {"RFMAB", tCK}, + {"REFSB", tCK}, + {"RFMSB", tCK}, + } + } + }); + + mPools.insert({ + "FAW_LOGICAL", { + 4, { + {"ACT", tFAW_slr - longCmdOffset}, + {"REFSB", tFAW_slr - shortCmdOffset}, + {"RFMSB", tFAW_slr - shortCmdOffset}, + } + } + }); + + mPools.insert({ + "FAW_PHYSICAL", { + 4, { + {"ACT", tFAW_dlr - longCmdOffset}, + {"REFSB", tFAW_dlr - shortCmdOffset}, + {"RFMSB", tFAW_dlr - shortCmdOffset}, + } + } + }); + } const std::vector TimeDependenciesInfoDDR5::getPossiblePhases() { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp index 6f8c849a..8fceeb97 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp @@ -45,50 +45,6 @@ void TimeDependenciesInfoHBM2::mInitializeValues() { burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - mPools.insert({ - "RAS_BUS", { - 1, { - "ACT", - "PREPB", - "PREAB", - "REFPB", - "REFAB", - "PDEA", - "PDXA", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - } - } - }); - - mPools.insert({ - "CAS_BUS", { - 1, { - "RD", - "RDA", - "WR", - "WRA", - "PDEA", - "PDXA", - "PDEP", - "PDXP", - "SREFEN", - "SREFEX", - } - } - }); - - mPools.insert({ - "NAW", { - 4, { - "ACT", - "REFPB", - } - } - }); - tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt(); tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt(); @@ -126,6 +82,50 @@ void TimeDependenciesInfoHBM2::mInitializeValues() { tWRRDS = tWL + tBURST + tWTRS; tWRRDL = tWL + tBURST + tWTRL; + mPools.insert({ + "RAS_BUS", { + 1, { + {"ACT", 2*tCK}, + {"PREPB", tCK}, + {"PREAB", tCK}, + {"REFPB", tCK}, + {"REFAB", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + } + } + }); + + mPools.insert({ + "CAS_BUS", { + 1, { + {"RD", tCK}, + {"RDA", tCK}, + {"WR", tCK}, + {"WRA", tCK}, + {"PDEA", tCK}, + {"PDXA", tCK}, + {"PDEP", tCK}, + {"PDXP", tCK}, + {"SREFEN", tCK}, + {"SREFEX", tCK}, + } + } + }); + + mPools.insert({ + "NAW", { + 4, { + {"ACT", tFAW}, + {"REFPB", tFAW}, + } + } + }); + } const std::vector TimeDependenciesInfoHBM2::getPossiblePhases() { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp index 3b8fc142..84976422 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp @@ -45,33 +45,6 @@ void TimeDependenciesInfoLPDDR4::mInitializeValues() { burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt(); dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt(); - mPools.insert({ - "CMD_BUS", { - 1, { - "ACT", - "RD", - "WR", - "RDA", - "WRA", - "PREPB", - "PREAB", - "REFAB", - "SREFEN", - "SREFEX", - "REFPB", - } - } - }); - - mPools.insert({ - "NAW", { - 4, { - "ACT", - "REFPB", - } - } - }); - tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt(); tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt(); tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt(); @@ -119,6 +92,33 @@ void TimeDependenciesInfoLPDDR4::mInitializeValues() { tREFPDEN = tCK + tCMDCKE; tSREFPDEN = tCK + tESCKE; + mPools.insert({ + "CMD_BUS", { + 1, { + {"ACT", 4 * tCK}, + {"RD", 4 * tCK}, + {"WR", 4 * tCK}, + {"RDA", 4 * tCK}, + {"WRA", 4 * tCK}, + {"PREPB", 2 * tCK}, + {"PREAB", 2 * tCK}, + {"REFAB", 2 * tCK}, + {"SREFEN", 2 * tCK}, + {"SREFEX", 2 * tCK}, + {"REFPB", 2 * tCK}, + } + } + }); + + mPools.insert({ + "NAW", { + 4, { + {"ACT", tFAW}, + {"REFPB", tFAW}, + } + } + }); + } const std::vector TimeDependenciesInfoLPDDR4::getPossiblePhases() { diff --git a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp index e2ba2d9b..eb935e2d 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp @@ -247,10 +247,11 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptrphaseName)) { - if (timeDiff == dep.timeValue) { + auto busyTime = poolController.getBusyTime(dep.phaseDep, otherPhase->phaseName); + if (busyTime > 0 && timeDiff <= busyTime) { + if (timeDiff == busyTime) { // Captures only the first (exactly matching time) phase in // the pool window as a dependency poolController.push(dep.phaseDep, DBDependencyEntry{ @@ -263,14 +264,13 @@ PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr