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Standard nomenclature for refresh related configs.

Browse Source 
ControllerCoreRef* for refresh general configs.
ControllerCoreRGR* for RGR specific configs.
This commit is contained in:
Éder F. Zulian
2018-07-10 09:44:48 +02:00
parent af0520faae
commit c6e66305c1
33 changed files with 447 additions and 431 deletions
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12
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
View File

@@ -8,10 +8,10 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
View File

@@ -8,10 +8,10 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
View File

@@ -8,10 +8,10 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
View File

@@ -8,11 +8,11 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
View File

@@ -6,11 +6,11 @@
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
View File

@@ -6,10 +6,10 @@
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

2
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
View File

@@ -8,6 +8,6 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
</mcconfig>

76
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
View File

@@ -6,49 +6,49 @@
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRowGranularRefRowInc value="1"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRowGranularRefRASBInClkCycles value="34"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="8"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="8"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="18"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="52"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="37"/>
<ControllerCoreRGRtRASBInClkCycles value="34"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="8"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="8"/>
<ControllerCoreRGRtRPBInClkCycles value="18"/>
<ControllerCoreRGRtRCBInClkCycles value="52"/>
<ControllerCoreRGRtFAWBInClkCycles value="37"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRowGranularRefRASBInClkCycles value="22"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="15"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="37"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="1"/>
<ControllerCoreRowGranularRefB5 value="1"/>
<ControllerCoreRowGranularRefB6 value="1"/>
<ControllerCoreRowGranularRefB7 value="1"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
View File

@@ -6,10 +6,10 @@
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

2
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
View File

@@ -8,6 +8,6 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/grp.xml
View File

@@ -8,10 +8,10 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
View File

@@ -8,10 +8,10 @@
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

62
DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
View File

@@ -8,41 +8,41 @@
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Refresh yes, no -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- RGR -->
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRowGranularRefRowInc value="1"/>
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="1"/>
<ControllerCoreRowGranularRefB5 value="1"/>
<ControllerCoreRowGranularRefB6 value="1"/>
<ControllerCoreRowGranularRefB7 value="1"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRowGranularRefRASBInClkCycles value="22"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="15"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="37"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="1"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreRefEnablePostpone value="1"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>

12
DRAMSys/library/resources/configs/mcconfigs/sms.xml
View File

@@ -12,10 +12,10 @@
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
</mcconfig>

64
DRAMSys/library/resources/configs/simulator/orgr.xml
View File

@@ -10,42 +10,42 @@
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<!-- NEW COMMANDS USING STARNDARD TIMING VALUES -->
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefRASBInClkCycles value="20"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="6"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="6"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="8"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="27"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="27"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
<!-- NEW COMMANDS USING OPTIMAL TIMING VALUES -->
<!--
<ControllerCoreRowGranularRefRASBInClkCycles value="11"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="5"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="16"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
-->
<!-- SELECT THE BANKS YOU WANT TO REFRESH 1 YES 0 NO (max. 16 banks!) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="1"/>
<ControllerCoreRowGranularRefB5 value="1"/>
<ControllerCoreRowGranularRefB6 value="1"/>
<ControllerCoreRowGranularRefB7 value="1"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</simconfig>

64
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml
View File

@@ -10,42 +10,42 @@
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefRASBInClkCycles value="20"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="6"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="6"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="8"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="27"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="27"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRowGranularRefRASBInClkCycles value="11"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="5"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="16"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="0"/>
<ControllerCoreRowGranularRefB5 value="0"/>
<ControllerCoreRowGranularRefB6 value="0"/>
<ControllerCoreRowGranularRefB7 value="0"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="0"/>
<ControllerCoreRGRB5 value="0"/>
<ControllerCoreRGRB6 value="0"/>
<ControllerCoreRGRB7 value="0"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</simconfig>

64
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml
View File

@@ -10,42 +10,42 @@
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefRASBInClkCycles value="20"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="6"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="6"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="8"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="27"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="27"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
<!-- New commands using optimal timing values -->
<!--
<ControllerCoreRowGranularRefRASBInClkCycles value="11"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="5"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="16"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
-->
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="0"/>
<ControllerCoreRowGranularRefB5 value="0"/>
<ControllerCoreRowGranularRefB6 value="0"/>
<ControllerCoreRowGranularRefB7 value="0"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="0"/>
<ControllerCoreRGRB5 value="0"/>
<ControllerCoreRGRB6 value="0"/>
<ControllerCoreRGRB7 value="0"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</simconfig>

64
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml
View File

@@ -10,42 +10,42 @@
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefRASBInClkCycles value="20"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="6"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="6"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="8"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="27"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="27"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRowGranularRefRASBInClkCycles value="11"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="5"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="16"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="1"/>
<ControllerCoreRowGranularRefB5 value="1"/>
<ControllerCoreRowGranularRefB6 value="1"/>
<ControllerCoreRowGranularRefB7 value="1"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</simconfig>

64
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml
View File

@@ -10,42 +10,42 @@
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<ControllerCoreRowGranularRef value="1"/>
<ControllerCoreRowGranularRefRASBInClkCycles value="20"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="6"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="6"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="8"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="27"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="27"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
<!-- New commands using optimal timing values -->
<!--
<ControllerCoreRowGranularRefRASBInClkCycles value="11"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="5"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="16"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
-->
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="1"/>
<ControllerCoreRowGranularRefB5 value="1"/>
<ControllerCoreRowGranularRefB6 value="1"/>
<ControllerCoreRowGranularRefB7 value="1"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
</simconfig>

2
DRAMSys/library/resources/simulations/rgrsim.xml
View File

@@ -19,6 +19,6 @@
<device clkMhz="1000">rgr_bw_postpone_test.stl</device>
<device clkMhz="1000">1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl</device>
-->
<device clkMhz="1000">rgr_pullin_test.stl</device>
<device clkMhz="1000">rgr_postpone_test.stl</device>
</tracesetup>
</simulation>

8
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -339,12 +339,12 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 9,
(Configuration::getInstance().memSpec.clk *
Configuration::getInstance().WindowSize).value());
if (Configuration::getInstance().ControllerCoreEnableRefPostpone
|| Configuration::getInstance().ControllerCoreEnableRefPullIn) {
if (Configuration::getInstance().ControllerCoreRefEnablePostpone
|| Configuration::getInstance().ControllerCoreRefEnablePullIn) {
sqlite3_bind_int(insertGeneralInfoStatement, 10, 1);
sqlite3_bind_int(insertGeneralInfoStatement, 11,
std::max(Configuration::getInstance().ControllerCoreMaxPulledInARCmd,
Configuration::getInstance().ControllerCoreMaxPostponedARCmd));
std::max(Configuration::getInstance().ControllerCoreRefMaxPulledIn,
Configuration::getInstance().ControllerCoreRefMaxPostponed));
} else {
sqlite3_bind_int(insertGeneralInfoStatement, 10, 0);
sqlite3_bind_int(insertGeneralInfoStatement, 11, 0);

4
DRAMSys/library/src/controller/core/ControllerCore.cpp
View File

@@ -141,7 +141,7 @@ ControllerCore::~ControllerCore()
void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload)
{
/* Refresh can be disabled for tests purpose */
if (config.ControllerCoreDisableRefresh == false) {
if (config.ControllerCoreRefDisable == false) {
sc_time time = sc_time_stamp();
Bank bank = DramExtension::getExtension(payload).getBank();
@@ -172,7 +172,7 @@ bool ControllerCore::scheduleRequest(Command command,
sc_time start = clkAlign(sc_time_stamp());
state->cleanUp(start);
ScheduledCommand scheduledCommand = schedule(command, start, payload);
if (config.ControllerCoreDisableRefresh == true) {
if (config.ControllerCoreRefDisable == true) {
state->change(scheduledCommand);
controller.send(scheduledCommand, payload);
return true;

96
DRAMSys/library/src/controller/core/configuration/Configuration.cpp
View File

@@ -32,7 +32,7 @@
* Authors:
* Janik Schlemminger
* Matthias Jung
* Eder F. Zulian
* Éder F. Zulian
* Felipe S. Prado
*/
@@ -196,56 +196,72 @@ void Configuration::setParameter(std::string name, std::string value)
+ "the address mapping configuration file is "
+ std::to_string(maxNumberofMemChannels) + ".").c_str());
}
} else if (name == "ControllerCoreDisableRefresh")
ControllerCoreDisableRefresh = string2bool(value);
else if (name == "ControllerCoreRowGranularRef")
} else if (name == "ControllerCoreRefDisable")
ControllerCoreRefDisable = string2bool(value);
else if (name == "ControllerCoreRGR")
RowGranularRef = string2bool(value);
else if (name == "ControllerCoreRowGranularRefRowInc")RowInc = string2int(
value);
else if (name == "ControllerCoreRGRRowInc")
RowInc = string2int(value);
else if (name == "ControllerCoreRefMode") {
RefMode = string2int(value);
if (RefMode != 1 && RefMode != 2 && RefMode != 4)
SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str());
} else if (name == "ControllerCoreRowGranularRefNumAR")NumAR = string2int(
value);
else if (name == "ControllerCoreRowGranularRefB0")RGRB0 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB1")RGRB1 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB2")RGRB2 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB3")RGRB3 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB4")RGRB4 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB5")RGRB5 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB6")RGRB6 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB7")RGRB7 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB8")RGRB8 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB9")RGRB9 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB10")RGRB10 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB11")RGRB11 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB12")RGRB12 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB13")RGRB13 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB14")RGRB14 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefB15")RGRB15 = string2bool(value);
else if (name == "ControllerCoreRowGranularRefRASBInClkCycles")
} else if (name == "ControllerCoreRGRNumARIntREFI")
NumAR = string2int(value);
else if (name == "ControllerCoreRGRB0")
RGRB0 = string2bool(value);
else if (name == "ControllerCoreRGRB1")
RGRB1 = string2bool(value);
else if (name == "ControllerCoreRGRB2")
RGRB2 = string2bool(value);
else if (name == "ControllerCoreRGRB3")
RGRB3 = string2bool(value);
else if (name == "ControllerCoreRGRB4")
RGRB4 = string2bool(value);
else if (name == "ControllerCoreRGRB5")
RGRB5 = string2bool(value);
else if (name == "ControllerCoreRGRB6")
RGRB6 = string2bool(value);
else if (name == "ControllerCoreRGRB7")
RGRB7 = string2bool(value);
else if (name == "ControllerCoreRGRB8")
RGRB8 = string2bool(value);
else if (name == "ControllerCoreRGRB9")
RGRB9 = string2bool(value);
else if (name == "ControllerCoreRGRB10")
RGRB10 = string2bool(value);
else if (name == "ControllerCoreRGRB11")
RGRB11 = string2bool(value);
else if (name == "ControllerCoreRGRB12")
RGRB12 = string2bool(value);
else if (name == "ControllerCoreRGRB13")
RGRB13 = string2bool(value);
else if (name == "ControllerCoreRGRB14")
RGRB14 = string2bool(value);
else if (name == "ControllerCoreRGRB15")
RGRB15 = string2bool(value);
else if (name == "ControllerCoreRGRtRASBInClkCycles")
trasbclk = string2int(value);
else if (name == "ControllerCoreRowGranularRefRRDB_LInClkCycles")
else if (name == "ControllerCoreRGRtRRDB_LInClkCycles")
trrdblclk = string2int(value);
else if (name == "ControllerCoreRowGranularRefRRDB_SInClkCycles")
else if (name == "ControllerCoreRGRtRRDB_SInClkCycles")
trrdbsclk = string2int(value);
else if (name == "ControllerCoreRowGranularRefRPBInClkCycles")
else if (name == "ControllerCoreRGRtRPBInClkCycles")
trpbclk = string2int(value);
else if (name == "ControllerCoreRowGranularRefRCBInClkCycles")
else if (name == "ControllerCoreRGRtRCBInClkCycles")
trcbclk = string2int(value);
else if (name == "ControllerCoreRowGranularRefFAWBInClkCycles")
else if (name == "ControllerCoreRGRtFAWBInClkCycles")
tfawbclk = string2int(value);
else if (name == "ControllerCoreForceMaxRefBurst")
ControllerCoreForceMaxRefBurst = string2bool(value);
else if (name == "ControllerCoreEnableRefPostpone") {
ControllerCoreEnableRefPostpone = string2bool(value);
} else if (name == "ControllerCoreEnableRefPullIn") {
ControllerCoreEnableRefPullIn = string2bool(value);
} else if (name == "ControllerCoreMaxPostponedARCmd")
ControllerCoreMaxPostponedARCmd = string2int(value);
else if (name == "ControllerCoreMaxPulledInARCmd")
ControllerCoreMaxPulledInARCmd = string2int(value);
else if (name == "ControllerCoreRefForceMaxPostponeBurst")
ControllerCoreRefForceMaxPostponeBurst = string2bool(value);
else if (name == "ControllerCoreRefEnablePostpone") {
ControllerCoreRefEnablePostpone = string2bool(value);
} else if (name == "ControllerCoreRefEnablePullIn") {
ControllerCoreRefEnablePullIn = string2bool(value);
} else if (name == "ControllerCoreRefMaxPostponed")
ControllerCoreRefMaxPostponed = string2int(value);
else if (name == "ControllerCoreRefMaxPulledIn")
ControllerCoreRefMaxPulledIn = string2int(value);
else if (name == "ThermalSimulation")
ThermalSimulation = string2bool(value);
else if (name == "SimulationProgressBar")

12
DRAMSys/library/src/controller/core/configuration/Configuration.h
View File

@@ -85,7 +85,7 @@ struct Configuration {
unsigned int WindowSize = 1000;
bool Debug = false;
unsigned int NumberOfMemChannels = 1;
bool ControllerCoreDisableRefresh = false;
bool ControllerCoreRefDisable = false;
bool RowGranularRef = false;
unsigned int trasbclk = 0;
sc_time getTrasb();
@@ -122,11 +122,11 @@ struct Configuration {
unsigned int getNumAR(void);
unsigned int getRowInc(void);
unsigned int getRefMode(void);
bool ControllerCoreForceMaxRefBurst = false;
bool ControllerCoreEnableRefPostpone = false;
bool ControllerCoreEnableRefPullIn = false;
unsigned int ControllerCoreMaxPostponedARCmd = 8;
unsigned int ControllerCoreMaxPulledInARCmd = 8;
bool ControllerCoreRefForceMaxPostponeBurst = false;
bool ControllerCoreRefEnablePostpone = false;
bool ControllerCoreRefEnablePullIn = false;
unsigned int ControllerCoreRefMaxPostponed = 8;
unsigned int ControllerCoreRefMaxPulledIn = 8;
bool ThermalSimulation = false;
bool SimulationProgressBar = false;
unsigned int NumberOfDevicesOnDIMM = 1;

10
DRAMSys/library/src/controller/core/refresh/RGR.cpp
View File

@@ -48,7 +48,7 @@ using namespace std;
RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
timing(ctrlcore.config.memSpec.refreshTimings[ccore.getBanks()[0]])
{
fmb = ccore.config.ControllerCoreForceMaxRefBurst;
fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst;
bwl = ccore.config.BankwiseLogic;
ri = ccore.config.getRowInc();
auto nr = ccore.config.memSpec.NumberOfRows;
@@ -59,10 +59,10 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore),
tREFIx = timing.tREFI / m;
trp = ccore.config.getTrpb();
trcd = ccore.config.memSpec.tRCD;
postponeEnabled = ccore.config.ControllerCoreEnableRefPostpone;
pullInEnabled = ccore.config.ControllerCoreEnableRefPullIn;
maxpostpone = ccore.config.ControllerCoreMaxPostponedARCmd * m;
maxpullin = ccore.config.ControllerCoreMaxPulledInARCmd * m;
postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone;
pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn;
maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m;
maxpullin = ccore.config.ControllerCoreRefMaxPulledIn * m;
for (Bank b : ccore.getBanks()) {
pulledin[b] = 0;
postponed[b] = 0;

12
DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp
View File

@@ -53,11 +53,11 @@ RefreshManager::RefreshManager(sc_module_name, ControllerCore &controller) :
auto m = controllerCore.config.getRefMode();
tREFIx = timing.tREFI / m;
tRFCx = m == 4 ? timing.tRFC4 : m == 2 ? timing.tRFC2 : timing.tRFC;
if (controllerCore.config.ControllerCoreEnableRefPostpone) {
maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd * m;
if (controllerCore.config.ControllerCoreRefEnablePostpone) {
maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m;
}
if (controllerCore.config.ControllerCoreEnableRefPullIn) {
maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd * m;
if (controllerCore.config.ControllerCoreRefEnablePullIn) {
maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m;
}
for (Bank bank : controller.getBanks()) {
setUpDummy(refreshPayloads[bank], bank);
@@ -76,7 +76,7 @@ bool RefreshManager::hasCollision(const ScheduledCommand &command)
controllerCore.state->getLastCommand(Command::AutoRefresh).getEnd();
bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh;
if (controllerCore.config.ControllerCoreEnableRefPostpone
if (controllerCore.config.ControllerCoreRefEnablePostpone
&& (arCmdCounter < maxpostpone)) {
// Flexible refresh is on and have "credits" to postpone
// Then there will not be a collision with next refresh because
@@ -187,7 +187,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload,
// requests and credits to postpone. Should be followed by a burst
// refresh
if ((arCmdCounter == maxpostpone) || ((!pendingReq)
&& !controllerCore.config.ControllerCoreForceMaxRefBurst)) {
&& !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) {
// Burst conditions met
if (arCmdCounter < maxpostpone) {
// In case the burst was started by inactivity, need to also

12
DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp
View File

@@ -49,10 +49,10 @@ RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name,
auto m = controllerCore.config.getRefMode();
tREFIx = timing.tREFI / m;
tRFCx = m == 4 ? timing.tRFC4 : m == 2 ? timing.tRFC2 : timing.tRFC;
if (controllerCore.config.ControllerCoreEnableRefPostpone)
maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd * m;
if (controllerCore.config.ControllerCoreEnableRefPullIn)
maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd * m;
if (controllerCore.config.ControllerCoreRefEnablePostpone)
maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m;
if (controllerCore.config.ControllerCoreRefEnablePullIn)
maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m;
for (Bank bank : controller.getBanks()) {
nextPlannedRefreshs[bank] = SC_ZERO_TIME;
arCmdCounter[bank] = 0;
@@ -75,7 +75,7 @@ bool RefreshManagerBankwise::hasCollision(const ScheduledCommand &command)
bool collisionWithPreviousRefEnd = command.getStart() <
controllerCore.state->getLastCommand(Command::AutoRefresh, bank).getEnd();
bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefreshs[bank];
if (controllerCore.config.ControllerCoreEnableRefPostpone
if (controllerCore.config.ControllerCoreRefEnablePostpone
&& (arCmdCounter[bank] < maxpostpone)) {
collisionWithNextRefStart = false;
}
@@ -172,7 +172,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload,
// requests and credits to postpone. Should be followed by a burst
// refresh.
if ((arCmdCounter[bank] == maxpostpone) || ((!pendingReq)
&& !controllerCore.config.ControllerCoreForceMaxRefBurst)) {
&& !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) {
// Burst conditions met
if (arCmdCounter[bank] < maxpostpone) {
// In case the burst was started by inactivity, need to also

2
DRAMSys/tests/TLM_compliance/sim-batch.xml
View File

@@ -8,7 +8,7 @@
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />

2
DRAMSys/tests/continuous_testing_py/baseconfig.xml
View File

@@ -8,7 +8,7 @@
<WindowSize value="100" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="1"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "8" />

2
DRAMSys/tests/error/sim-batch.xml
View File

@@ -8,7 +8,7 @@
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />

2
DRAMSys/tests/simple/sim-batch.xml
View File

@@ -8,7 +8,7 @@
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />

2
DRAMSys/tests/timing_compliance/sim-batch.xml
View File

@@ -8,7 +8,7 @@
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />

130
README.md
View File

@@ -478,10 +478,10 @@ Below, the sub-configurations are listed and explained.
- Size of the window in clock cycles used to evaluate average bandwidth and average power consumption
- *NumberOfMemChannels* (unsigned int)
- Number of memory channels
- *ControllerCoreDisableRefresh* (boolean)
- *ControllerCoreRefDisable* (boolean)
- "1": disables refreshes
- "0": normal operation (refreshes enabled)
- *ControllerCoreRowGranularRef* (boolean)
- *ControllerCoreRGR* (boolean)
- "1": enable row granular refresh
- "0": normal operation
- *ThermalSimulation* (boolean)
@@ -711,43 +711,43 @@ Below, the sub-configurations are listed and explained.
<!-- Bankwise -->
<BankwiseLogic value="0"/>
<!-- Disable refresh. 0: no (refresh enabled), 1: yes (refresh disableb) -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreRefDisable value="0"/>
<!-- Refresh Mode. 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<ControllerCoreRefMode value="1"/>
<!-- RGR -->
<ControllerCoreRowGranularRef value="0"/>
<ControllerCoreRowGranularRefNumAR value="8192"/>
<ControllerCoreRowGranularRefRowInc value="1"/>
<ControllerCoreRGR value="0"/>
<ControllerCoreRGRNumARIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- Banks to be refreshed in RGR mode. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRowGranularRefB0 value="1"/>
<ControllerCoreRowGranularRefB1 value="1"/>
<ControllerCoreRowGranularRefB2 value="1"/>
<ControllerCoreRowGranularRefB3 value="1"/>
<ControllerCoreRowGranularRefB4 value="1"/>
<ControllerCoreRowGranularRefB5 value="1"/>
<ControllerCoreRowGranularRefB6 value="1"/>
<ControllerCoreRowGranularRefB7 value="1"/>
<ControllerCoreRowGranularRefB8 value="0"/>
<ControllerCoreRowGranularRefB9 value="0"/>
<ControllerCoreRowGranularRefB10 value="0"/>
<ControllerCoreRowGranularRefB11 value="0"/>
<ControllerCoreRowGranularRefB12 value="0"/>
<ControllerCoreRowGranularRefB13 value="0"/>
<ControllerCoreRowGranularRefB14 value="0"/>
<ControllerCoreRowGranularRefB15 value="0"/>
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRowGranularRefRASBInClkCycles value="22"/>
<ControllerCoreRowGranularRefRRDB_LInClkCycles value="2"/>
<ControllerCoreRowGranularRefRRDB_SInClkCycles value="2"/>
<ControllerCoreRowGranularRefRPBInClkCycles value="15"/>
<ControllerCoreRowGranularRefRCBInClkCycles value="37"/>
<ControllerCoreRowGranularRefFAWBInClkCycles value="0"/>
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>
<ControllerCoreRefMaxPostponed value="8"/>
<ControllerCoreRefMaxPulledIn value="8"/>
<ControllerCoreRefForceMaxPostponeBurst value="0"/>
</mcconfig>
```
@@ -784,7 +784,7 @@ Below, the sub-configurations are listed and explained.
- "NoStorage": no storage
- "Store": store data without error model
- "ErrorModel": store data with error model [6]
- *ControllerCoreDisableRefresh* (boolean)
- *ControllerCoreRefDisable* (boolean)
- "1": disables refreshes
- "0": normal operation (refreshes enabled)
- ControllerCoreRefMode (unsigned int)
@@ -793,85 +793,85 @@ Below, the sub-configurations are listed and explained.
In 2X mode Refresh commands are issued to the DRAM at the double frequency (tREFI/2).
In 4X mode Refresh commands are issued to the DRAM at the quadruple frequency (tREFI/4).
There is a tRFC value for each mode that comes from the memory specification.
- *ControllerCoreForceMaxRefBurst* (boolean)
- "1": always postpone, resulting in a ControllerCoreMaxPostponedARCmd burst
- *ControllerCoreRefForceMaxPostponeBurst* (boolean)
- "1": always postpone, resulting in a ControllerCoreRefMaxPostponed burst
- "0": normal operation
- *ControllerCoreEnableRefPostpone* (boolean)
- *ControllerCoreRefEnablePostpone* (boolean)
- "1": enables the postpone refresh feature
- "0": normal operation
- *ControllerCoreEnableRefPullIn* (boolean)
- *ControllerCoreRefEnablePullIn* (boolean)
- "1": enables the pull-in refresh feature
- "0": normal operation
- *ControllerCoreMaxPostponedARCmd* (unsigned int)
- *ControllerCoreRefMaxPostponed* (unsigned int)
- Max AR commands to be postponed. Refresh mode affects this config (multiplier).
- *ControllerCoreMaxPulledInARCmd* (unsigned int)
- *ControllerCoreRefMaxPulledIn* (unsigned int)
- Max AR commands to be pulled-in. Refresh mode affects this config (multiplier).
- *ControllerCoreRowGranularRef* (boolean)
- *ControllerCoreRGR* (boolean)
- "1": enables row granular refresh feature (RGR)
- "0": normal operation
- *ControllerCoreRowGranularRefNumAR* (unsigned int)
- *ControllerCoreRGRNumARIntREFI* (unsigned int)
- Number of AR commands to to be issued in a refresh period tREFI
- *ControllerCoreRowGranularRefRowInc* (unsigned int)
- *ControllerCoreRGRRowInc* (unsigned int)
- Row increment for each AR command (selective refresh)
- *ControllerCoreRowGranularRefB0* (boolean)
- *ControllerCoreRGRB0* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB1* (boolean)
- *ControllerCoreRGRB1* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB2* (boolean)
- *ControllerCoreRGRB2* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB3* (boolean)
- *ControllerCoreRGRB3* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB4* (boolean)
- *ControllerCoreRGRB4* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB5* (boolean)
- *ControllerCoreRGRB5* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB6* (boolean)
- *ControllerCoreRGRB6* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB7* (boolean)
- *ControllerCoreRGRB7* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB8* (boolean)
- *ControllerCoreRGRB8* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB9* (boolean)
- *ControllerCoreRGRB9* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB10* (boolean)
- *ControllerCoreRGRB10* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB11* (boolean)
- *ControllerCoreRGRB11* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB12* (boolean)
- *ControllerCoreRGRB12* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB13* (boolean)
- *ControllerCoreRGRB13* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB14* (boolean)
- *ControllerCoreRGRB14* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefB15* (boolean)
- *ControllerCoreRGRB15* (boolean)
- "1": RGR this bank
- "0": skip this bank
- *ControllerCoreRowGranularRefRASBInClkCycles* (unsigned int)
- *ControllerCoreRGRtRASBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRowGranularRefRRDB_LInClkCycles* (unsigned int)
- *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRowGranularRefRRDB_SInClkCycles* (unsigned int)
- *ControllerCoreRGRtRRDB_SInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRowGranularRefRPBInClkCycles* (unsigned int)
- *ControllerCoreRGRtRPBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRowGranularRefRCBInClkCycles* (unsigned int)
- *ControllerCoreRGRtRCBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)
- *ControllerCoreRowGranularRefFAWBInClkCycles* (unsigned int)
- *ControllerCoreRGRtFAWBInClkCycles* (unsigned int)
- Timing can be changed to explore optimum row granular refresh (ORGR)