diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml index c8252d2c..964ed8e2 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml @@ -8,10 +8,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml index c49cb635..635a5a82 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml @@ -8,10 +8,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml index c8252d2c..964ed8e2 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml @@ -8,10 +8,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml index c008de01..5a4ca81f 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml @@ -8,11 +8,11 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml index 66a560b4..b6484e89 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml @@ -6,11 +6,11 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml index 936a8503..d57cdc53 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml @@ -6,10 +6,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml index 44d5db18..945ac58f 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml @@ -8,6 +8,6 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml index ba32827b..cf1427fb 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml @@ -6,49 +6,49 @@ - - - - - - + + + + + + - - - - + + + + - - - - - - + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml index 3e3d5aac..575f79b8 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml @@ -6,10 +6,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml index 68b2799c..9068f558 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml @@ -8,6 +8,6 @@ - + diff --git a/DRAMSys/library/resources/configs/mcconfigs/grp.xml b/DRAMSys/library/resources/configs/mcconfigs/grp.xml index d5474610..1d6be156 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/grp.xml @@ -8,10 +8,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml index 0985157f..f2ecfdbe 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml @@ -8,10 +8,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml index 35d14181..34e89dc9 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml @@ -8,41 +8,41 @@ - + - - - + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + - - - - - - + + + + + + - - - - - + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/sms.xml b/DRAMSys/library/resources/configs/mcconfigs/sms.xml index 049b8a45..003f6a2c 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/sms.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/sms.xml @@ -12,10 +12,10 @@ - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr.xml b/DRAMSys/library/resources/configs/simulator/orgr.xml index 5ea7d678..487a44a8 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr.xml +++ b/DRAMSys/library/resources/configs/simulator/orgr.xml @@ -10,42 +10,42 @@ - - - + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml index c1ee0c9b..f69b11c5 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml @@ -10,42 +10,42 @@ - - - + + + - - - - - - + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml index 66460ef1..77c526e1 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml @@ -10,42 +10,42 @@ - - - + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml index 10673780..331f7f9a 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml @@ -10,42 +10,42 @@ - - - + + + - - - - - - + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml index d8846262..d43a9eb0 100644 --- a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml @@ -10,42 +10,42 @@ - - - + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/rgrsim.xml b/DRAMSys/library/resources/simulations/rgrsim.xml index d9546fe3..3dee8806 100644 --- a/DRAMSys/library/resources/simulations/rgrsim.xml +++ b/DRAMSys/library/resources/simulations/rgrsim.xml @@ -19,6 +19,6 @@ rgr_bw_postpone_test.stl 1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl --> - rgr_pullin_test.stl + rgr_postpone_test.stl diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 0fae8cd7..db59e640 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -339,12 +339,12 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 9, (Configuration::getInstance().memSpec.clk * Configuration::getInstance().WindowSize).value()); - if (Configuration::getInstance().ControllerCoreEnableRefPostpone - || Configuration::getInstance().ControllerCoreEnableRefPullIn) { + if (Configuration::getInstance().ControllerCoreRefEnablePostpone + || Configuration::getInstance().ControllerCoreRefEnablePullIn) { sqlite3_bind_int(insertGeneralInfoStatement, 10, 1); sqlite3_bind_int(insertGeneralInfoStatement, 11, - std::max(Configuration::getInstance().ControllerCoreMaxPulledInARCmd, - Configuration::getInstance().ControllerCoreMaxPostponedARCmd)); + std::max(Configuration::getInstance().ControllerCoreRefMaxPulledIn, + Configuration::getInstance().ControllerCoreRefMaxPostponed)); } else { sqlite3_bind_int(insertGeneralInfoStatement, 10, 0); sqlite3_bind_int(insertGeneralInfoStatement, 11, 0); diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index fd278bb6..f28f8e2a 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -141,7 +141,7 @@ ControllerCore::~ControllerCore() void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload) { /* Refresh can be disabled for tests purpose */ - if (config.ControllerCoreDisableRefresh == false) { + if (config.ControllerCoreRefDisable == false) { sc_time time = sc_time_stamp(); Bank bank = DramExtension::getExtension(payload).getBank(); @@ -172,7 +172,7 @@ bool ControllerCore::scheduleRequest(Command command, sc_time start = clkAlign(sc_time_stamp()); state->cleanUp(start); ScheduledCommand scheduledCommand = schedule(command, start, payload); - if (config.ControllerCoreDisableRefresh == true) { + if (config.ControllerCoreRefDisable == true) { state->change(scheduledCommand); controller.send(scheduledCommand, payload); return true; diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index d95652b0..b7a62027 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -32,7 +32,7 @@ * Authors: * Janik Schlemminger * Matthias Jung - * Eder F. Zulian + * Éder F. Zulian * Felipe S. Prado */ @@ -196,56 +196,72 @@ void Configuration::setParameter(std::string name, std::string value) + "the address mapping configuration file is " + std::to_string(maxNumberofMemChannels) + ".").c_str()); } - } else if (name == "ControllerCoreDisableRefresh") - ControllerCoreDisableRefresh = string2bool(value); - else if (name == "ControllerCoreRowGranularRef") + } else if (name == "ControllerCoreRefDisable") + ControllerCoreRefDisable = string2bool(value); + else if (name == "ControllerCoreRGR") RowGranularRef = string2bool(value); - else if (name == "ControllerCoreRowGranularRefRowInc")RowInc = string2int( - value); + else if (name == "ControllerCoreRGRRowInc") + RowInc = string2int(value); else if (name == "ControllerCoreRefMode") { RefMode = string2int(value); if (RefMode != 1 && RefMode != 2 && RefMode != 4) SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str()); - } else if (name == "ControllerCoreRowGranularRefNumAR")NumAR = string2int( - value); - else if (name == "ControllerCoreRowGranularRefB0")RGRB0 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB1")RGRB1 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB2")RGRB2 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB3")RGRB3 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB4")RGRB4 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB5")RGRB5 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB6")RGRB6 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB7")RGRB7 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB8")RGRB8 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB9")RGRB9 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB10")RGRB10 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB11")RGRB11 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB12")RGRB12 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB13")RGRB13 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB14")RGRB14 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefB15")RGRB15 = string2bool(value); - else if (name == "ControllerCoreRowGranularRefRASBInClkCycles") + } else if (name == "ControllerCoreRGRNumARIntREFI") + NumAR = string2int(value); + else if (name == "ControllerCoreRGRB0") + RGRB0 = string2bool(value); + else if (name == "ControllerCoreRGRB1") + RGRB1 = string2bool(value); + else if (name == "ControllerCoreRGRB2") + RGRB2 = string2bool(value); + else if (name == "ControllerCoreRGRB3") + RGRB3 = string2bool(value); + else if (name == "ControllerCoreRGRB4") + RGRB4 = string2bool(value); + else if (name == "ControllerCoreRGRB5") + RGRB5 = string2bool(value); + else if (name == "ControllerCoreRGRB6") + RGRB6 = string2bool(value); + else if (name == "ControllerCoreRGRB7") + RGRB7 = string2bool(value); + else if (name == "ControllerCoreRGRB8") + RGRB8 = string2bool(value); + else if (name == "ControllerCoreRGRB9") + RGRB9 = string2bool(value); + else if (name == "ControllerCoreRGRB10") + RGRB10 = string2bool(value); + else if (name == "ControllerCoreRGRB11") + RGRB11 = string2bool(value); + else if (name == "ControllerCoreRGRB12") + RGRB12 = string2bool(value); + else if (name == "ControllerCoreRGRB13") + RGRB13 = string2bool(value); + else if (name == "ControllerCoreRGRB14") + RGRB14 = string2bool(value); + else if (name == "ControllerCoreRGRB15") + RGRB15 = string2bool(value); + else if (name == "ControllerCoreRGRtRASBInClkCycles") trasbclk = string2int(value); - else if (name == "ControllerCoreRowGranularRefRRDB_LInClkCycles") + else if (name == "ControllerCoreRGRtRRDB_LInClkCycles") trrdblclk = string2int(value); - else if (name == "ControllerCoreRowGranularRefRRDB_SInClkCycles") + else if (name == "ControllerCoreRGRtRRDB_SInClkCycles") trrdbsclk = string2int(value); - else if (name == "ControllerCoreRowGranularRefRPBInClkCycles") + else if (name == "ControllerCoreRGRtRPBInClkCycles") trpbclk = string2int(value); - else if (name == "ControllerCoreRowGranularRefRCBInClkCycles") + else if (name == "ControllerCoreRGRtRCBInClkCycles") trcbclk = string2int(value); - else if (name == "ControllerCoreRowGranularRefFAWBInClkCycles") + else if (name == "ControllerCoreRGRtFAWBInClkCycles") tfawbclk = string2int(value); - else if (name == "ControllerCoreForceMaxRefBurst") - ControllerCoreForceMaxRefBurst = string2bool(value); - else if (name == "ControllerCoreEnableRefPostpone") { - ControllerCoreEnableRefPostpone = string2bool(value); - } else if (name == "ControllerCoreEnableRefPullIn") { - ControllerCoreEnableRefPullIn = string2bool(value); - } else if (name == "ControllerCoreMaxPostponedARCmd") - ControllerCoreMaxPostponedARCmd = string2int(value); - else if (name == "ControllerCoreMaxPulledInARCmd") - ControllerCoreMaxPulledInARCmd = string2int(value); + else if (name == "ControllerCoreRefForceMaxPostponeBurst") + ControllerCoreRefForceMaxPostponeBurst = string2bool(value); + else if (name == "ControllerCoreRefEnablePostpone") { + ControllerCoreRefEnablePostpone = string2bool(value); + } else if (name == "ControllerCoreRefEnablePullIn") { + ControllerCoreRefEnablePullIn = string2bool(value); + } else if (name == "ControllerCoreRefMaxPostponed") + ControllerCoreRefMaxPostponed = string2int(value); + else if (name == "ControllerCoreRefMaxPulledIn") + ControllerCoreRefMaxPulledIn = string2int(value); else if (name == "ThermalSimulation") ThermalSimulation = string2bool(value); else if (name == "SimulationProgressBar") diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index 28de22c7..5a4583b4 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -85,7 +85,7 @@ struct Configuration { unsigned int WindowSize = 1000; bool Debug = false; unsigned int NumberOfMemChannels = 1; - bool ControllerCoreDisableRefresh = false; + bool ControllerCoreRefDisable = false; bool RowGranularRef = false; unsigned int trasbclk = 0; sc_time getTrasb(); @@ -122,11 +122,11 @@ struct Configuration { unsigned int getNumAR(void); unsigned int getRowInc(void); unsigned int getRefMode(void); - bool ControllerCoreForceMaxRefBurst = false; - bool ControllerCoreEnableRefPostpone = false; - bool ControllerCoreEnableRefPullIn = false; - unsigned int ControllerCoreMaxPostponedARCmd = 8; - unsigned int ControllerCoreMaxPulledInARCmd = 8; + bool ControllerCoreRefForceMaxPostponeBurst = false; + bool ControllerCoreRefEnablePostpone = false; + bool ControllerCoreRefEnablePullIn = false; + unsigned int ControllerCoreRefMaxPostponed = 8; + unsigned int ControllerCoreRefMaxPulledIn = 8; bool ThermalSimulation = false; bool SimulationProgressBar = false; unsigned int NumberOfDevicesOnDIMM = 1; diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index c8e0abcc..cd94840a 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -48,7 +48,7 @@ using namespace std; RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), timing(ctrlcore.config.memSpec.refreshTimings[ccore.getBanks()[0]]) { - fmb = ccore.config.ControllerCoreForceMaxRefBurst; + fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst; bwl = ccore.config.BankwiseLogic; ri = ccore.config.getRowInc(); auto nr = ccore.config.memSpec.NumberOfRows; @@ -59,10 +59,10 @@ RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), tREFIx = timing.tREFI / m; trp = ccore.config.getTrpb(); trcd = ccore.config.memSpec.tRCD; - postponeEnabled = ccore.config.ControllerCoreEnableRefPostpone; - pullInEnabled = ccore.config.ControllerCoreEnableRefPullIn; - maxpostpone = ccore.config.ControllerCoreMaxPostponedARCmd * m; - maxpullin = ccore.config.ControllerCoreMaxPulledInARCmd * m; + postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone; + pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn; + maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m; + maxpullin = ccore.config.ControllerCoreRefMaxPulledIn * m; for (Bank b : ccore.getBanks()) { pulledin[b] = 0; postponed[b] = 0; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index 73f944fe..5613e7cd 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -53,11 +53,11 @@ RefreshManager::RefreshManager(sc_module_name, ControllerCore &controller) : auto m = controllerCore.config.getRefMode(); tREFIx = timing.tREFI / m; tRFCx = m == 4 ? timing.tRFC4 : m == 2 ? timing.tRFC2 : timing.tRFC; - if (controllerCore.config.ControllerCoreEnableRefPostpone) { - maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd * m; + if (controllerCore.config.ControllerCoreRefEnablePostpone) { + maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; } - if (controllerCore.config.ControllerCoreEnableRefPullIn) { - maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd * m; + if (controllerCore.config.ControllerCoreRefEnablePullIn) { + maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; } for (Bank bank : controller.getBanks()) { setUpDummy(refreshPayloads[bank], bank); @@ -76,7 +76,7 @@ bool RefreshManager::hasCollision(const ScheduledCommand &command) controllerCore.state->getLastCommand(Command::AutoRefresh).getEnd(); bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh; - if (controllerCore.config.ControllerCoreEnableRefPostpone + if (controllerCore.config.ControllerCoreRefEnablePostpone && (arCmdCounter < maxpostpone)) { // Flexible refresh is on and have "credits" to postpone // Then there will not be a collision with next refresh because @@ -187,7 +187,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, // requests and credits to postpone. Should be followed by a burst // refresh if ((arCmdCounter == maxpostpone) || ((!pendingReq) - && !controllerCore.config.ControllerCoreForceMaxRefBurst)) { + && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { // Burst conditions met if (arCmdCounter < maxpostpone) { // In case the burst was started by inactivity, need to also diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index b9da4023..20239769 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -49,10 +49,10 @@ RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name, auto m = controllerCore.config.getRefMode(); tREFIx = timing.tREFI / m; tRFCx = m == 4 ? timing.tRFC4 : m == 2 ? timing.tRFC2 : timing.tRFC; - if (controllerCore.config.ControllerCoreEnableRefPostpone) - maxpostpone = controllerCore.config.ControllerCoreMaxPostponedARCmd * m; - if (controllerCore.config.ControllerCoreEnableRefPullIn) - maxpullin = controllerCore.config.ControllerCoreMaxPulledInARCmd * m; + if (controllerCore.config.ControllerCoreRefEnablePostpone) + maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; + if (controllerCore.config.ControllerCoreRefEnablePullIn) + maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; for (Bank bank : controller.getBanks()) { nextPlannedRefreshs[bank] = SC_ZERO_TIME; arCmdCounter[bank] = 0; @@ -75,7 +75,7 @@ bool RefreshManagerBankwise::hasCollision(const ScheduledCommand &command) bool collisionWithPreviousRefEnd = command.getStart() < controllerCore.state->getLastCommand(Command::AutoRefresh, bank).getEnd(); bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefreshs[bank]; - if (controllerCore.config.ControllerCoreEnableRefPostpone + if (controllerCore.config.ControllerCoreRefEnablePostpone && (arCmdCounter[bank] < maxpostpone)) { collisionWithNextRefStart = false; } @@ -172,7 +172,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, // requests and credits to postpone. Should be followed by a burst // refresh. if ((arCmdCounter[bank] == maxpostpone) || ((!pendingReq) - && !controllerCore.config.ControllerCoreForceMaxRefBurst)) { + && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { // Burst conditions met if (arCmdCounter[bank] < maxpostpone) { // In case the burst was started by inactivity, need to also diff --git a/DRAMSys/tests/TLM_compliance/sim-batch.xml b/DRAMSys/tests/TLM_compliance/sim-batch.xml index f42c0180..62d47560 100644 --- a/DRAMSys/tests/TLM_compliance/sim-batch.xml +++ b/DRAMSys/tests/TLM_compliance/sim-batch.xml @@ -8,7 +8,7 @@ - + diff --git a/DRAMSys/tests/continuous_testing_py/baseconfig.xml b/DRAMSys/tests/continuous_testing_py/baseconfig.xml index b968b056..b595973e 100644 --- a/DRAMSys/tests/continuous_testing_py/baseconfig.xml +++ b/DRAMSys/tests/continuous_testing_py/baseconfig.xml @@ -8,7 +8,7 @@ - + diff --git a/DRAMSys/tests/error/sim-batch.xml b/DRAMSys/tests/error/sim-batch.xml index 34dc29e3..461929db 100644 --- a/DRAMSys/tests/error/sim-batch.xml +++ b/DRAMSys/tests/error/sim-batch.xml @@ -8,7 +8,7 @@ - + diff --git a/DRAMSys/tests/simple/sim-batch.xml b/DRAMSys/tests/simple/sim-batch.xml index 6ab12347..cd1f4a95 100644 --- a/DRAMSys/tests/simple/sim-batch.xml +++ b/DRAMSys/tests/simple/sim-batch.xml @@ -8,7 +8,7 @@ - + diff --git a/DRAMSys/tests/timing_compliance/sim-batch.xml b/DRAMSys/tests/timing_compliance/sim-batch.xml index 9813a99d..dbd489d3 100644 --- a/DRAMSys/tests/timing_compliance/sim-batch.xml +++ b/DRAMSys/tests/timing_compliance/sim-batch.xml @@ -8,7 +8,7 @@ - + diff --git a/README.md b/README.md index b14bbbd6..f6355d62 100644 --- a/README.md +++ b/README.md @@ -478,10 +478,10 @@ Below, the sub-configurations are listed and explained. - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption - *NumberOfMemChannels* (unsigned int) - Number of memory channels - - *ControllerCoreDisableRefresh* (boolean) + - *ControllerCoreRefDisable* (boolean) - "1": disables refreshes - "0": normal operation (refreshes enabled) - - *ControllerCoreRowGranularRef* (boolean) + - *ControllerCoreRGR* (boolean) - "1": enable row granular refresh - "0": normal operation - *ThermalSimulation* (boolean) @@ -711,43 +711,43 @@ Below, the sub-configurations are listed and explained. - + - - - + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + - - - - - - + + + + + + - - - - - + + + + + ``` @@ -784,7 +784,7 @@ Below, the sub-configurations are listed and explained. - "NoStorage": no storage - "Store": store data without error model - "ErrorModel": store data with error model [6] - - *ControllerCoreDisableRefresh* (boolean) + - *ControllerCoreRefDisable* (boolean) - "1": disables refreshes - "0": normal operation (refreshes enabled) - ControllerCoreRefMode (unsigned int) @@ -793,85 +793,85 @@ Below, the sub-configurations are listed and explained. In 2X mode Refresh commands are issued to the DRAM at the double frequency (tREFI/2). In 4X mode Refresh commands are issued to the DRAM at the quadruple frequency (tREFI/4). There is a tRFC value for each mode that comes from the memory specification. - - *ControllerCoreForceMaxRefBurst* (boolean) - - "1": always postpone, resulting in a ControllerCoreMaxPostponedARCmd burst + - *ControllerCoreRefForceMaxPostponeBurst* (boolean) + - "1": always postpone, resulting in a ControllerCoreRefMaxPostponed burst - "0": normal operation - - *ControllerCoreEnableRefPostpone* (boolean) + - *ControllerCoreRefEnablePostpone* (boolean) - "1": enables the postpone refresh feature - "0": normal operation - - *ControllerCoreEnableRefPullIn* (boolean) + - *ControllerCoreRefEnablePullIn* (boolean) - "1": enables the pull-in refresh feature - "0": normal operation - - *ControllerCoreMaxPostponedARCmd* (unsigned int) + - *ControllerCoreRefMaxPostponed* (unsigned int) - Max AR commands to be postponed. Refresh mode affects this config (multiplier). - - *ControllerCoreMaxPulledInARCmd* (unsigned int) + - *ControllerCoreRefMaxPulledIn* (unsigned int) - Max AR commands to be pulled-in. Refresh mode affects this config (multiplier). - - *ControllerCoreRowGranularRef* (boolean) + - *ControllerCoreRGR* (boolean) - "1": enables row granular refresh feature (RGR) - "0": normal operation - - *ControllerCoreRowGranularRefNumAR* (unsigned int) + - *ControllerCoreRGRNumARIntREFI* (unsigned int) - Number of AR commands to to be issued in a refresh period tREFI - - *ControllerCoreRowGranularRefRowInc* (unsigned int) + - *ControllerCoreRGRRowInc* (unsigned int) - Row increment for each AR command (selective refresh) - - *ControllerCoreRowGranularRefB0* (boolean) + - *ControllerCoreRGRB0* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB1* (boolean) + - *ControllerCoreRGRB1* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB2* (boolean) + - *ControllerCoreRGRB2* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB3* (boolean) + - *ControllerCoreRGRB3* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB4* (boolean) + - *ControllerCoreRGRB4* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB5* (boolean) + - *ControllerCoreRGRB5* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB6* (boolean) + - *ControllerCoreRGRB6* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB7* (boolean) + - *ControllerCoreRGRB7* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB8* (boolean) + - *ControllerCoreRGRB8* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB9* (boolean) + - *ControllerCoreRGRB9* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB10* (boolean) + - *ControllerCoreRGRB10* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB11* (boolean) + - *ControllerCoreRGRB11* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB12* (boolean) + - *ControllerCoreRGRB12* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB13* (boolean) + - *ControllerCoreRGRB13* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB14* (boolean) + - *ControllerCoreRGRB14* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefB15* (boolean) + - *ControllerCoreRGRB15* (boolean) - "1": RGR this bank - "0": skip this bank - - *ControllerCoreRowGranularRefRASBInClkCycles* (unsigned int) + - *ControllerCoreRGRtRASBInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRowGranularRefRRDB_LInClkCycles* (unsigned int) + - *ControllerCoreRGRtRRDB_LInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRowGranularRefRRDB_SInClkCycles* (unsigned int) + - *ControllerCoreRGRtRRDB_SInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRowGranularRefRPBInClkCycles* (unsigned int) + - *ControllerCoreRGRtRPBInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRowGranularRefRCBInClkCycles* (unsigned int) + - *ControllerCoreRGRtRCBInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR) - - *ControllerCoreRowGranularRefFAWBInClkCycles* (unsigned int) + - *ControllerCoreRGRtFAWBInClkCycles* (unsigned int) - Timing can be changed to explore optimum row granular refresh (ORGR)