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Merge branch 'fix/beat_byte_granularity' into 'develop'

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Allow non-byte granularity for bus width

See merge request ems/astdm/modeling.dram/dram.sys.5!119
This commit is contained in:
Lukas Steiner
2025-04-24 14:15:46 +00:00
parent 1863987af3 db6011425a
commit 9b4fb96cce
4 changed files with 13 additions and 15 deletions
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2
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
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@@ -69,14 +69,12 @@ MemSpec::MemSpec(const Config::MemSpec& memSpec,
dataRate(memSpec.memarchitecturespec.entries.at("dataRate")),
bitWidth(memSpec.memarchitecturespec.entries.at("width")),
dataBusWidth(bitWidth * devicesPerRank),
bytesPerBeat(dataBusWidth / 8),
defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8),
maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8),
tCK(sc_time(memSpec.memtimingspec.entries.at("tCK"), SC_PS)),
memoryId(memSpec.memoryId),
memoryType(memSpec.memoryType),
burstDuration(tCK * (static_cast<double>(defaultBurstLength) / dataRate))
{
commandLengthInCycles = std::vector<double>(Command::numberOfCommands(), 1);
}

1
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
View File

@@ -78,7 +78,6 @@ public:
const unsigned dataRate;
const unsigned bitWidth;
const unsigned dataBusWidth;
const unsigned bytesPerBeat;
const unsigned defaultBytesPerBurst;
const unsigned maxBytesPerBurst;

23
src/libdramsys/DRAMSys/controller/Controller.cpp
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@@ -607,16 +607,16 @@ void Controller::manageRequests(const sc_time& delay)
// continuous block of data that can be fetched with a single burst
DecodedAddress decodedAddress =
addressDecoder.decodeAddress(transToAcquire.payload->get_address());
ControllerExtension::setAutoExtension(*transToAcquire.payload,
nextChannelPayloadIDToAppend++,
Rank(decodedAddress.rank),
Stack(decodedAddress.stack),
BankGroup(decodedAddress.bankgroup),
Bank(decodedAddress.bank),
Row(decodedAddress.row),
Column(decodedAddress.column),
transToAcquire.payload->get_data_length() /
memSpec.bytesPerBeat);
ControllerExtension::setAutoExtension(
*transToAcquire.payload,
nextChannelPayloadIDToAppend++,
Rank(decodedAddress.rank),
Stack(decodedAddress.stack),
BankGroup(decodedAddress.bankgroup),
Bank(decodedAddress.bank),
Row(decodedAddress.row),
Column(decodedAddress.column),
(transToAcquire.payload->get_data_length() * 8) / memSpec.dataBusWidth);
Rank rank = Rank(decodedAddress.rank);
if (ranksNumberOfPayloads[rank] == 0)
@@ -814,7 +814,8 @@ void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)
Bank(decodedAddress.bank),
Row(decodedAddress.row),
Column(decodedAddress.column),
childTrans->get_data_length() / memSpec.bytesPerBeat);
(childTrans->get_data_length() * 8) /
memSpec.dataBusWidth);
}
nextChannelPayloadIDToAppend++;
ParentExtension::setExtension(parentTrans, std::move(childTranses));

2
src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
View File

@@ -195,7 +195,7 @@ void AddressDecoder::plausibilityCheck(const MemSpec& memSpec)
if (memSpec.numberOfChannels != channels || memSpec.ranksPerChannel != ranks ||
memSpec.bankGroupsPerChannel != absoluteBankGroups ||
memSpec.banksPerChannel != absoluteBanks || memSpec.rowsPerBank != rows ||
memSpec.columnsPerRow != columns || memSpec.devicesPerRank * memSpec.bitWidth != bytes * 8)
memSpec.columnsPerRow != columns)
SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match");
}