From db6011425a5e8f94fc14ccf7cb428146e13c5a93 Mon Sep 17 00:00:00 2001
From: Derek Christ <derek.christ@uni-wuerzburg.de>
Date: Mon, 14 Apr 2025 10:23:00 +0200
Subject: [PATCH] Allow non-byte granularity for bus width

---
 .../DRAMSys/configuration/memspec/MemSpec.cpp |  2 --
 .../DRAMSys/configuration/memspec/MemSpec.h   |  1 -
 .../DRAMSys/controller/Controller.cpp         | 23 ++++++++++---------
 .../DRAMSys/simulation/AddressDecoder.cpp     |  2 +-
 4 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
index 812ab40b..bae38dc9 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp
@@ -69,14 +69,12 @@ MemSpec::MemSpec(const Config::MemSpec& memSpec,
     dataRate(memSpec.memarchitecturespec.entries.at("dataRate")),
     bitWidth(memSpec.memarchitecturespec.entries.at("width")),
     dataBusWidth(bitWidth * devicesPerRank),
-    bytesPerBeat(dataBusWidth / 8),
     defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8),
     maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8),
     tCK(sc_time(memSpec.memtimingspec.entries.at("tCK"), SC_PS)),
     memoryId(memSpec.memoryId),
     memoryType(memSpec.memoryType),
     burstDuration(tCK * (static_cast<double>(defaultBurstLength) / dataRate))
-
 {
     commandLengthInCycles = std::vector<double>(Command::numberOfCommands(), 1);
 }
diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
index 89357e68..e7be3742 100644
--- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
+++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
@@ -78,7 +78,6 @@ public:
     const unsigned dataRate;
     const unsigned bitWidth;
     const unsigned dataBusWidth;
-    const unsigned bytesPerBeat;
     const unsigned defaultBytesPerBurst;
     const unsigned maxBytesPerBurst;
 
diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp
index 79da9ece..4149b006 100644
--- a/src/libdramsys/DRAMSys/controller/Controller.cpp
+++ b/src/libdramsys/DRAMSys/controller/Controller.cpp
@@ -564,16 +564,16 @@ void Controller::manageRequests(const sc_time& delay)
                 // continuous block of data that can be fetched with a single burst
                 DecodedAddress decodedAddress =
                     addressDecoder.decodeAddress(transToAcquire.payload->get_address());
-                ControllerExtension::setAutoExtension(*transToAcquire.payload,
-                                                      nextChannelPayloadIDToAppend++,
-                                                      Rank(decodedAddress.rank),
-                                                      Stack(decodedAddress.stack),
-                                                      BankGroup(decodedAddress.bankgroup),
-                                                      Bank(decodedAddress.bank),
-                                                      Row(decodedAddress.row),
-                                                      Column(decodedAddress.column),
-                                                      transToAcquire.payload->get_data_length() /
-                                                          memSpec.bytesPerBeat);
+                ControllerExtension::setAutoExtension(
+                    *transToAcquire.payload,
+                    nextChannelPayloadIDToAppend++,
+                    Rank(decodedAddress.rank),
+                    Stack(decodedAddress.stack),
+                    BankGroup(decodedAddress.bankgroup),
+                    Bank(decodedAddress.bank),
+                    Row(decodedAddress.row),
+                    Column(decodedAddress.column),
+                    (transToAcquire.payload->get_data_length() * 8) / memSpec.dataBusWidth);
 
                 Rank rank = Rank(decodedAddress.rank);
                 if (ranksNumberOfPayloads[rank] == 0)
@@ -771,7 +771,8 @@ void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)
                                               Bank(decodedAddress.bank),
                                               Row(decodedAddress.row),
                                               Column(decodedAddress.column),
-                                              childTrans->get_data_length() / memSpec.bytesPerBeat);
+                                              (childTrans->get_data_length() * 8) /
+                                                  memSpec.dataBusWidth);
     }
     nextChannelPayloadIDToAppend++;
     ParentExtension::setExtension(parentTrans, std::move(childTranses));
diff --git a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
index 4836152d..881fb060 100644
--- a/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
+++ b/src/libdramsys/DRAMSys/simulation/AddressDecoder.cpp
@@ -195,7 +195,7 @@ void AddressDecoder::plausibilityCheck(const MemSpec& memSpec)
     if (memSpec.numberOfChannels != channels || memSpec.ranksPerChannel != ranks ||
         memSpec.bankGroupsPerChannel != absoluteBankGroups ||
         memSpec.banksPerChannel != absoluteBanks || memSpec.rowsPerBank != rows ||
-        memSpec.columnsPerRow != columns || memSpec.devicesPerRank * memSpec.bitWidth != bytes * 8)
+        memSpec.columnsPerRow != columns)
         SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match");
 }