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Reimplement calculation of Channel Memory Size to more readable and safer way

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This commit is contained in:
Thanh Tran
2016-11-08 15:54:59 +01:00
parent ac8982aa39
commit 989d00204b
1 changed files with 15 additions and 6 deletions
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21
DRAMSys/simulator/src/simulation/Dram.h
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@@ -68,8 +68,8 @@ struct Dram : sc_module
unsigned int burstLength = Configuration::getInstance().memSpec.BurstLength;
// All DRAM chips on a DIMM operate in lockstep,
// which constituing aggregate data bus width = chip's bus width * # locksteep-operated chips
unsigned int busWidth = Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM;
unsigned int bytesPerBurst = burstLength * (busWidth / 8);
unsigned int dataBusWidth = Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM;
unsigned int bytesPerBurst = burstLength * (dataBusWidth / 8);
// TLM Related:
tlm_utils::simple_target_socket<Dram> tSocket;
@@ -97,11 +97,20 @@ struct Dram : sc_module
SC_CTOR(Dram) : tSocket("socket")
{
// calculate memory size (in Bytes)
// 1. Get number of banks, rows, columns and data width in bits
unsigned int banks = Configuration::getInstance().memSpec.NumberOfBanks;
unsigned int rows = Configuration::getInstance().memSpec.NumberOfRows;
unsigned int columns = Configuration::getInstance().memSpec.NumberOfColumns;
unsigned int size = banks * rows * columns * (busWidth / 8);
memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
unsigned int bitWidth = Configuration::getInstance().memSpec.bitWidth;
// 2. Calculate size of one DRAM chip in bits
unsigned int chipBitSize = banks * rows * columns * bitWidth;
// 3. Calculate size of one DRAM chip in bytes
unsigned int chipSize = chipBitSize / 8;
// 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM)
unsigned int memorySize = chipSize * Configuration::getInstance().NumberOfDevicesOnDIMM;
// allocate and model storage of one DRAM channel using memory map
memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
tSocket.register_transport_dbg(this,&Dram::transport_dbg);
@@ -117,7 +126,7 @@ struct Dram : sc_module
memArchSpec.nbrOfBanks = Configuration::getInstance().memSpec.NumberOfBanks;
memArchSpec.nbrOfColumns = Configuration::getInstance().memSpec.NumberOfColumns;
memArchSpec.nbrOfRanks = Configuration::getInstance().memSpec.NumberOfRanks;
memArchSpec.width = Configuration::getInstance().memSpec.BusWidth;
memArchSpec.width = Configuration::getInstance().memSpec.bitWidth;
memArchSpec.nbrOfBankGroups = Configuration::getInstance().memSpec.NumberOfBankGroups;
memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec.vDD2 == 0 ? false : true);
memArchSpec.dll = Configuration::getInstance().memSpec.DLL;
@@ -239,7 +248,7 @@ struct Dram : sc_module
double bandwidth = (activeTime/(endTime-startTime)*100);
double bandwidth_IDLE = ((activeTime)/(endTime-startTime-idleTime)*100);
// | clk in Mhz e.g. 800 [MHz] | * | DataRate e.g. 2 | * | BusWidth e.g. 8 | * | Number of devices on a DIMM e.g. 8 | / | 1024 |
double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.BusWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.bitWidth * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 );
cout << name() << string("\tTotal Time: \t") <<(endTime-startTime).to_string() << endl;
//cout << name() << string("\tTotal IDLE: \t") <<idleTime.to_string() << endl;
//cout << name() << string("\tTotal Active DataBus: \t") << activeTime.to_string() << endl;