Rename the data bit width of one DRAM chip to more significant one

This commit is contained in:
Thanh Tran
2016-11-08 15:49:45 +01:00
parent 79b624a88b
commit ac8982aa39
2 changed files with 4 additions and 4 deletions

View File

@@ -170,7 +170,7 @@ void ConfigurationLoader::loadDDR3(Configuration& config, XMLElement* memspec)
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
config.memSpec.BusWidth = queryUIntParameter(architecture, "width");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = true;
config.memSpec.termination = true;
@@ -244,7 +244,7 @@ void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec)
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
config.memSpec.BusWidth = queryUIntParameter(architecture, "width");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = true;
config.memSpec.termination = true;
@@ -317,7 +317,7 @@ void ConfigurationLoader::loadWideIO(Configuration& config, XMLElement* memspec)
config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate");
config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
config.memSpec.BusWidth = queryUIntParameter(architecture, "width");
config.memSpec.bitWidth = queryUIntParameter(architecture, "width");
config.memSpec.DLL = false;
config.memSpec.termination = false;

View File

@@ -82,7 +82,7 @@ struct MemSpec
unsigned int DataRate;
unsigned int NumberOfRows;
unsigned int NumberOfColumns;
unsigned int BusWidth;
unsigned int bitWidth;
bool DLL;
bool termination;