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Rename internal memspec parameters.

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This commit is contained in:
Lukas Steiner
2022-03-02 13:45:50 +01:00
parent a3bab077cd
commit 986311a4d0
48 changed files with 253 additions and 253 deletions
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6
DRAMSys/library/src/common/TlmRecorder.cpp
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@@ -345,9 +345,9 @@ void TlmRecorder::insertGeneralInfo()
{
sqlite3_bind_int64(insertGeneralInfoStatement, 1, static_cast<int64_t>(totalNumTransactions));
sqlite3_bind_int64(insertGeneralInfoStatement, 2, static_cast<int64_t>(simulationTimeCoveredByRecording.value()));
sqlite3_bind_int(insertGeneralInfoStatement, 3, static_cast<int>(Configuration::getInstance().memSpec->numberOfRanks));
sqlite3_bind_int(insertGeneralInfoStatement, 4, static_cast<int>(Configuration::getInstance().memSpec->numberOfBankGroups));
sqlite3_bind_int(insertGeneralInfoStatement, 5, static_cast<int>(Configuration::getInstance().memSpec->numberOfBanks));
sqlite3_bind_int(insertGeneralInfoStatement, 3, static_cast<int>(Configuration::getInstance().memSpec->ranksPerChannel));
sqlite3_bind_int(insertGeneralInfoStatement, 4, static_cast<int>(Configuration::getInstance().memSpec->bankGroupsPerChannel));
sqlite3_bind_int(insertGeneralInfoStatement, 5, static_cast<int>(Configuration::getInstance().memSpec->banksPerChannel));
sqlite3_bind_int64(insertGeneralInfoStatement, 6, static_cast<int64_t>(Configuration::getInstance().memSpec->tCK.value()));
sqlite3_bind_text(insertGeneralInfoStatement, 7, "PS", 2, nullptr);

2
DRAMSys/library/src/common/configuration/memspec/MemSpec.h
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@@ -67,4 +67,4 @@ std::string dump(const MemSpec &c, unsigned int indentation = -1);
} // namespace Configuration
#endif // MEMSPEC_H
#endif // DRAMSYSCONFIGURATION_MEMSPEC_H

2
DRAMSys/library/src/common/dramExtensions.cpp
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@@ -435,7 +435,7 @@ bool operator !=(const Row &lhs, const Row &rhs)
Row Row::operator ++()
{
id = (id + 1) % Configuration::getInstance().memSpec->numberOfRows;
id = (id + 1) % Configuration::getInstance().memSpec->rowsPerBank;
return *this;
}

20
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
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@@ -42,20 +42,20 @@ using namespace tlm;
MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
MemoryType memoryType,
unsigned numberOfChannels,
unsigned numberOfRanks, unsigned banksPerRank,
unsigned ranksPerChannel, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups,
unsigned numberOfDevices)
unsigned banksPerChannel, unsigned bankGroupsPerChannel,
unsigned devicesPerRank)
: numberOfChannels(numberOfChannels),
numberOfRanks(numberOfRanks),
ranksPerChannel(ranksPerChannel),
banksPerRank(banksPerRank),
groupsPerRank(groupsPerRank),
banksPerGroup(banksPerGroup),
numberOfBanks(numberOfBanks),
numberOfBankGroups(numberOfBankGroups),
numberOfDevices(numberOfDevices),
numberOfRows(memSpec.memArchitectureSpec.entries.at("nbrOfRows")),
numberOfColumns(memSpec.memArchitectureSpec.entries.at("nbrOfColumns")),
banksPerChannel(banksPerChannel),
bankGroupsPerChannel(bankGroupsPerChannel),
devicesPerRank(devicesPerRank),
rowsPerBank(memSpec.memArchitectureSpec.entries.at("nbrOfRows")),
columnsPerRow(memSpec.memArchitectureSpec.entries.at("nbrOfColumns")),
defaultBurstLength(memSpec.memArchitectureSpec.entries.at("burstLength")),
maxBurstLength(memSpec.memArchitectureSpec.entries.find("maxBurstLength") !=
memSpec.memArchitectureSpec.entries.end()
@@ -63,7 +63,7 @@ MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
: defaultBurstLength),
dataRate(memSpec.memArchitectureSpec.entries.at("dataRate")),
bitWidth(memSpec.memArchitectureSpec.entries.at("width")),
dataBusWidth(bitWidth * numberOfDevices),
dataBusWidth(bitWidth * devicesPerRank),
defaultBytesPerBurst((defaultBurstLength * dataBusWidth) / 8),
maxBytesPerBurst((maxBurstLength * dataBusWidth) / 8),
fCKMHz(memSpec.memTimingSpec.entries.at("clkMhz")),

18
DRAMSys/library/src/configuration/memspec/MemSpec.h
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@@ -51,15 +51,15 @@ class MemSpec
{
public:
const unsigned numberOfChannels;
const unsigned numberOfRanks;
const unsigned ranksPerChannel;
const unsigned banksPerRank;
const unsigned groupsPerRank;
const unsigned banksPerGroup;
const unsigned numberOfBanks;
const unsigned numberOfBankGroups;
const unsigned numberOfDevices;
const unsigned numberOfRows;
const unsigned numberOfColumns;
const unsigned banksPerChannel;
const unsigned bankGroupsPerChannel;
const unsigned devicesPerRank;
const unsigned rowsPerBank;
const unsigned columnsPerRow;
const unsigned defaultBurstLength;
const unsigned maxBurstLength;
const unsigned dataRate;
@@ -101,10 +101,10 @@ protected:
MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
MemoryType memoryType,
unsigned numberOfChannels,
unsigned numberOfRanks, unsigned banksPerRank,
unsigned ranksPerChannel, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned numberOfBanks, unsigned numberOfBankGroups,
unsigned numberOfDevices);
unsigned banksPerChannel, unsigned bankGroupsPerChannel,
unsigned devicesPerRank);
// Command lengths in cycles on bus, usually one clock cycle
std::vector<unsigned> commandLengthInCycles;

26
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
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@@ -93,26 +93,26 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec)
iDD3P0 (memSpec.memPowerSpec.value().entries.at("idd3p0")),
iDD3P1 (memSpec.memPowerSpec.value().entries.at("idd3p1"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
if (!memSpec.memPowerSpec.has_value())
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "DDR3" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Memory type: " << "DDR3" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

28
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
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@@ -111,27 +111,27 @@ MemSpecDDR4::MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
iDD62 (memSpec.memPowerSpec.value().entries.at("idd62")),
vDD2 (memSpec.memPowerSpec.value().entries.at("vdd2"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
if (!memSpec.memPowerSpec.has_value())
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "DDR4" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Memory type: " << "DDR4" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

28
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
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@@ -55,11 +55,11 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
numberOfDIMMRanks(memSpec.memArchitectureSpec.entries.at("nbrOfDIMMRanks")),
physicalRanksPerDIMMRank(memSpec.memArchitectureSpec.entries.at("nbrOfPhysicalRanks")),
numberOfPhysicalRanks(physicalRanksPerDIMMRank * numberOfDIMMRanks),
dimmRanksPerChannel(memSpec.memArchitectureSpec.entries.at("nbrOfDIMMRanks")),
physicalRanksPerDimmRank(memSpec.memArchitectureSpec.entries.at("nbrOfPhysicalRanks")),
physicalRanksPerChannel(physicalRanksPerDimmRank * dimmRanksPerChannel),
logicalRanksPerPhysicalRank(memSpec.memArchitectureSpec.entries.at("nbrOfLogicalRanks")),
numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks),
logicalRanksPerChannel(logicalRanksPerPhysicalRank * physicalRanksPerChannel),
cmdMode(memSpec.memArchitectureSpec.entries.at("cmdMode")),
refMode(memSpec.memArchitectureSpec.entries.at("refMode")),
RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
@@ -155,29 +155,29 @@ MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
SC_REPORT_FATAL("MemSpecDDR5", "Invalid refresh mode! "
"Set 1 for normal or 2 for fine granularity refresh mode.");
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows
* numberOfColumns * bitWidth * numberOfLogicalRanks;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank
* columnsPerRow * bitWidth * logicalRanksPerChannel;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfDevices
* numberOfRanks / numberOfLogicalRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * devicesPerRank
* ranksPerChannel / logicalRanksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration: " << std::endl << std::endl;
std::cout << " Memory type: " << "DDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " DIMMs per channel: " << numberOfDIMMRanks << std::endl;
std::cout << " Physical ranks per DIMM: " << physicalRanksPerDIMMRank << std::endl;
std::cout << " DIMMs per channel: " << dimmRanksPerChannel << std::endl;
std::cout << " Physical ranks per DIMM: " << physicalRanksPerDimmRank << std::endl;
std::cout << " Logical ranks per device: " << logicalRanksPerPhysicalRank << std::endl;
std::cout << " Total ranks: " << numberOfRanks << std::endl;
std::cout << " Total ranks: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

8
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
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@@ -45,11 +45,11 @@ class MemSpecDDR5 final : public MemSpec
public:
explicit MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec);
const unsigned numberOfDIMMRanks;
const unsigned physicalRanksPerDIMMRank;
const unsigned numberOfPhysicalRanks;
const unsigned dimmRanksPerChannel;
const unsigned physicalRanksPerDimmRank;
const unsigned physicalRanksPerChannel;
const unsigned logicalRanksPerPhysicalRank;
const unsigned numberOfLogicalRanks;
const unsigned logicalRanksPerChannel;
const unsigned cmdMode;
const unsigned refMode;
const unsigned RAAIMT;

12
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
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@@ -90,24 +90,24 @@ MemSpecGDDR5::MemSpecGDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
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@@ -89,24 +89,24 @@ MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSysConfiguration::MemSpec &memSpec)
tLK (tCK * memSpec.memTimingSpec.entries.at("LK")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("TRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR5X" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
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@@ -93,24 +93,24 @@ MemSpecGDDR6::MemSpecGDDR6(const DRAMSysConfiguration::MemSpec &memSpec)
tREFPDE (tCK * memSpec.memTimingSpec.entries.at("REFPDE")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "GDDR6" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -87,24 +87,24 @@ MemSpecHBM2::MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec)
{
commandLengthInCycles[Command::ACT] = 2;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "HBM2" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
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@@ -97,23 +97,23 @@ MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
commandLengthInCycles[Command::SREFEN] = 2;
commandLengthInCycles[Command::SREFEX] = 2;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "LPDDR4" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -102,23 +102,23 @@ MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
{
commandLengthInCycles[Command::ACT] = 2;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "LPDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -78,23 +78,23 @@ MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSysConfiguration::MemSpec &memSpec)
tPRPDEN (tCK * memSpec.memTimingSpec.entries.at("PRPDEN")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfDevices * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * devicesPerRank * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "STT-MRAM" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -99,9 +99,9 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec)
iDD62 (memSpec.memPowerSpec.value().entries.at("idd62")),
vDD2 (memSpec.memPowerSpec.value().entries.at("vdd2"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
if (!memSpec.memPowerSpec.has_value())
SC_REPORT_FATAL("MemSpec", "No power spec defined!");
@@ -111,14 +111,14 @@ MemSpecWideIO::MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec)
std::cout << " Memory type: " << "Wide I/O" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

12
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -81,23 +81,23 @@ MemSpecWideIO2::MemSpecWideIO2(const DRAMSysConfiguration::MemSpec &memSpec)
tRFCpb (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRTRS (tCK * memSpec.memTimingSpec.entries.at("RTRS"))
{
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "Wide I/O 2" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << numberOfDevices << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << std::endl;
}

32
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -75,7 +75,7 @@ Controller::Controller(const sc_module_name &name) :
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
ranksNumberOfPayloads = std::vector<unsigned>(memSpec->numberOfRanks);
ranksNumberOfPayloads = std::vector<unsigned>(memSpec->ranksPerChannel);
thinkDelayFw = config.thinkDelayFw;
thinkDelayBw = config.thinkDelayBw;
@@ -83,7 +83,7 @@ Controller::Controller(const sc_module_name &name) :
phyDelayBw = config.phyDelayBw;
// reserve buffer for command tuples
readyCommands.reserve(memSpec->numberOfBanks);
readyCommands.reserve(memSpec->banksPerChannel);
// instantiate timing checker
if (memSpec->memoryType == MemSpec::MemoryType::DDR3)
@@ -142,28 +142,28 @@ Controller::Controller(const sc_module_name &name) :
// instantiate bank machines (one per bank)
if (config.pagePolicy == Configuration::PagePolicy::Open)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
for (unsigned bankID = 0; bankID < memSpec->banksPerChannel; bankID++)
bankMachines.emplace_back(std::make_unique<BankMachineOpen>(*scheduler, *checker, Bank(bankID)));
}
else if (config.pagePolicy == Configuration::PagePolicy::OpenAdaptive)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
for (unsigned bankID = 0; bankID < memSpec->banksPerChannel; bankID++)
bankMachines.emplace_back(std::make_unique<BankMachineOpenAdaptive>(*scheduler, *checker, Bank(bankID)));
}
else if (config.pagePolicy == Configuration::PagePolicy::Closed)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
for (unsigned bankID = 0; bankID < memSpec->banksPerChannel; bankID++)
bankMachines.emplace_back(std::make_unique<BankMachineClosed>(*scheduler, *checker, Bank(bankID)));
}
else if (config.pagePolicy == Configuration::PagePolicy::ClosedAdaptive)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
for (unsigned bankID = 0; bankID < memSpec->banksPerChannel; bankID++)
bankMachines.emplace_back(std::make_unique<BankMachineClosedAdaptive>(*scheduler, *checker, Bank(bankID)));
}
bankMachinesOnRank = std::vector<std::vector<BankMachine*>>(memSpec->numberOfRanks,
bankMachinesOnRank = std::vector<std::vector<BankMachine*>>(memSpec->ranksPerChannel,
std::vector<BankMachine*>(memSpec->banksPerRank));
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
for (unsigned bankID = 0; bankID < memSpec->banksPerRank; bankID++)
bankMachinesOnRank[rankID][bankID] = bankMachines[rankID * memSpec->banksPerRank + bankID].get();
@@ -172,12 +172,12 @@ Controller::Controller(const sc_module_name &name) :
// instantiate power-down managers (one per rank)
if (config.powerDownPolicy == Configuration::PowerDownPolicy::NoPowerDown)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
powerDownManagers.emplace_back(std::make_unique<PowerDownManagerDummy>());
}
else if (config.powerDownPolicy == Configuration::PowerDownPolicy::Staggered)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
powerDownManagers.emplace_back(std::make_unique<PowerDownManagerStaggered>(bankMachinesOnRank[rankID],
Rank(rankID), *checker));
@@ -187,12 +187,12 @@ Controller::Controller(const sc_module_name &name) :
// instantiate refresh managers (one per rank)
if (config.refreshPolicy == Configuration::RefreshPolicy::NoRefresh)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
refreshManagers.emplace_back(std::make_unique<RefreshManagerDummy>());
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::AllBank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
refreshManagers.emplace_back(std::make_unique<RefreshManagerAllBank>
(bankMachinesOnRank[rankID], *powerDownManagers[rankID].get(), Rank(rankID), *checker));
@@ -200,7 +200,7 @@ Controller::Controller(const sc_module_name &name) :
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::SameBank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
refreshManagers.emplace_back(std::make_unique<RefreshManagerSameBank>
(bankMachinesOnRank[rankID], *powerDownManagers[rankID].get(), Rank(rankID), *checker));
@@ -208,7 +208,7 @@ Controller::Controller(const sc_module_name &name) :
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::PerBank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
// TODO: remove bankMachines in constructor
refreshManagers.emplace_back(std::make_unique<RefreshManagerPerBank>
@@ -217,7 +217,7 @@ Controller::Controller(const sc_module_name &name) :
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::Per2Bank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
// TODO: remove bankMachines in constructor
refreshManagers.emplace_back(std::make_unique<RefreshManagerPer2Bank>
@@ -254,7 +254,7 @@ void Controller::controllerMethod()
// clear command buffer
readyCommands.clear();
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
for (unsigned rankID = 0; rankID < memSpec->ranksPerChannel; rankID++)
{
// (4.1) Check for power-down commands (PDEA/PDEP/SREFEN or PDXA/PDXP/SREFEX)
commandTuple = powerDownManagers[rankID]->getNextCommand();

2
DRAMSys/library/src/controller/ControllerIF.h
View File

@@ -72,7 +72,7 @@ public:
// BusWidth e.g. 8 or 64
* Configuration::getInstance().memSpec->bitWidth
// Number of devices on a DIMM e.g. 8
* Configuration::getInstance().memSpec->numberOfDevices );
* Configuration::getInstance().memSpec->devicesPerRank );
std::cout << name() << std::string(" Total Time: ")
<< sc_core::sc_time_stamp().to_string()

6
DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
View File

@@ -47,12 +47,12 @@ CheckerDDR3::CheckerDDR3()
SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL;

8
DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
View File

@@ -47,14 +47,14 @@ CheckerDDR4::CheckerDDR4()
SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDWR = memSpec->tRL + tBURST + memSpec->tCK - memSpec->tWL + memSpec->tWPRE;

32
DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
View File

@@ -47,39 +47,39 @@ CheckerDDR5::CheckerDDR5()
SC_REPORT_FATAL("CheckerDDR5", "Wrong MemSpec chosen");
lastScheduledByCommandAndDimmRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfDIMMRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->dimmRanksPerChannel, sc_max_time()));
lastScheduledByCommandAndPhysicalRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfPhysicalRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->physicalRanksPerChannel, sc_max_time()));
lastScheduledByCommandAndLogicalRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfLogicalRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->logicalRanksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
// Required for Same Bank Refresh
lastScheduledByCommandAndBankInGroup = std::vector<std::vector<sc_time>>(Command::numberOfCommands(),
std::vector<sc_time>(memSpec->numberOfRanks * memSpec->banksPerGroup, sc_max_time()));
std::vector<sc_time>(memSpec->ranksPerChannel * memSpec->banksPerGroup, sc_max_time()));
lastCommandOnBus = sc_max_time();
dummyCommandOnBus.start = sc_max_time();
dummyCommandOnBus.end = sc_max_time();
last4ActivatesLogical = std::vector<std::queue<sc_time>>(memSpec->numberOfLogicalRanks);
last4ActivatesPhysical = std::vector<std::queue<sc_time>>(memSpec->numberOfPhysicalRanks);
last4ActivatesLogical = std::vector<std::queue<sc_time>>(memSpec->logicalRanksPerChannel);
last4ActivatesPhysical = std::vector<std::queue<sc_time>>(memSpec->physicalRanksPerChannel);
lastBurstLengthByCommandAndDimmRank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfDIMMRanks));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->dimmRanksPerChannel));
lastBurstLengthByCommandAndPhysicalRank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfPhysicalRanks));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->physicalRanksPerChannel));
lastBurstLengthByCommandAndLogicalRank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfLogicalRanks));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->logicalRanksPerChannel));
lastBurstLengthByCommandAndBankGroup = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfBankGroups));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->bankGroupsPerChannel));
lastBurstLengthByCommandAndBank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfBanks));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->banksPerChannel));
lastBurstLengthByCommand = std::vector<uint8_t>(Command::WRA + 1);
lastBurstLengthByCommandAndBankInGroup = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfRanks * memSpec->banksPerGroup));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->ranksPerChannel * memSpec->banksPerGroup));
cmdLengthDiff = memSpec->cmdMode * memSpec->tCK;
@@ -120,7 +120,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic
{
Rank logicalRank = DramExtension::getRank(payload);
Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank);
Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDIMMRank);
Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDimmRank);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup);
@@ -882,7 +882,7 @@ void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload)
{
Rank logicalRank = DramExtension::getRank(payload);
Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank);
Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDIMMRank);
Rank dimmRank = Rank(physicalRank.ID() / memSpec->physicalRanksPerDimmRank);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup);

12
DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
View File

@@ -47,17 +47,17 @@ CheckerGDDR5::CheckerGDDR5()
SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last32Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
last32Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->numberOfRanks);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST;

12
DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
View File

@@ -47,17 +47,17 @@ CheckerGDDR5X::CheckerGDDR5X()
SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last32Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
last32Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->numberOfRanks);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST;

10
DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
View File

@@ -47,16 +47,16 @@ CheckerGDDR6::CheckerGDDR6()
SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->numberOfRanks);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + memSpec->tWCK2DQO + tBURST;

18
DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
View File

@@ -47,17 +47,17 @@ CheckerHBM2::CheckerHBM2()
SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnRasBus = sc_max_time();
lastCommandOnCasBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->numberOfRanks);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDPDE = memSpec->tRL + memSpec->tPL + tBURST + memSpec->tCK;
@@ -81,8 +81,8 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic
if (command == Command::RD || command == Command::RDA)
{
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(memSpec->numberOfRanks == 1) || (burstLength == 2)); // Legacy mode
assert(!(memSpec->numberOfRanks == 2) || (burstLength == 4)); // Pseudo-channel mode
assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2)); // Legacy mode
assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
@@ -136,8 +136,8 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic
else if (command == Command::WR || command == Command::WRA)
{
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(memSpec->numberOfRanks == 1) || (burstLength == 2)); // Legacy mode
assert(!(memSpec->numberOfRanks == 2) || (burstLength == 4)); // Pseudo-channel mode
assert(!(memSpec->ranksPerChannel == 1) || (burstLength == 2)); // Legacy mode
assert(!(memSpec->ranksPerChannel == 2) || (burstLength == 4)); // Pseudo-channel mode
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())

6
DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
View File

@@ -47,12 +47,12 @@ CheckerLPDDR4::CheckerLPDDR4()
SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDWR = memSpec->tRL + memSpec->tDQSCK + tBURST - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST;

14
DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp
View File

@@ -48,22 +48,22 @@ CheckerLPDDR5::CheckerLPDDR5()
else
{
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
lastBurstLengthByCommandAndRank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfRanks));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->ranksPerChannel));
lastBurstLengthByCommandAndBankGroup = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfBankGroups));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->bankGroupsPerChannel));
lastBurstLengthByCommandAndBank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfBanks));
(Command::WRA + 1, std::vector<uint8_t>(memSpec->banksPerChannel));
lastBurstLengthByCommand = std::vector<uint8_t>(Command::WRA + 1);
tBURST16 = 16 / memSpec->dataRate * memSpec->tCK;

6
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
View File

@@ -47,12 +47,12 @@ CheckerSTTMRAM::CheckerSTTMRAM()
SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDWR = memSpec->tRL + tBURST + 2 * memSpec->tCK - memSpec->tWL;

6
DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
View File

@@ -47,12 +47,12 @@ CheckerWideIO::CheckerWideIO()
SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last2Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last2Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength * memSpec->tCK;
tRDWR = memSpec->tRL + tBURST + memSpec->tCK;

6
DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
View File

@@ -47,12 +47,12 @@ CheckerWideIO2::CheckerWideIO2()
SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
tBURST = memSpec->defaultBurstLength / memSpec->dataRate * memSpec->tCK;
tRDPRE = tBURST + std::max(2 * memSpec->tCK, memSpec->tRTP) - 2 * memSpec->tCK;

4
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -77,8 +77,8 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand
CmdMuxOldestRasCas::CmdMuxOldestRasCas() : memSpec(Configuration::getInstance().memSpec)
{
readyRasCommands.reserve(memSpec->numberOfBanks);
readyCasCommands.reserve(memSpec->numberOfBanks);
readyRasCommands.reserve(memSpec->banksPerChannel);
readyCasCommands.reserve(memSpec->banksPerChannel);
readyRasCasCommands.reserve(2);
}

4
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -87,8 +87,8 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
CmdMuxStrictRasCas::CmdMuxStrictRasCas() : memSpec(Configuration::getInstance().memSpec)
{
readyRasCommands.reserve(memSpec->numberOfBanks);
readyCasCommands.reserve(memSpec->numberOfBanks);
readyRasCommands.reserve(memSpec->banksPerChannel);
readyCasCommands.reserve(memSpec->banksPerChannel);
readyRasCasCommands.reserve(2);
}

2
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp
View File

@@ -50,7 +50,7 @@ RefreshManagerAllBank::RefreshManagerAllBank(std::vector<BankMachine*>& bankMach
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
timeForNextTrigger = getTimeForFirstTrigger(memSpec->getRefreshIntervalAB(),
rank, memSpec->numberOfRanks);
rank, memSpec->ranksPerChannel);
setUpDummy(refreshPayload, 0, rank);
maxPostponed = static_cast<int>(config.refreshMaxPostponed);

2
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.cpp
View File

@@ -50,7 +50,7 @@ RefreshManagerPer2Bank::RefreshManagerPer2Bank(std::vector<BankMachine*>& bankMa
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
timeForNextTrigger = getTimeForFirstTrigger(memSpec->getRefreshIntervalP2B(),
rank, memSpec->numberOfRanks);
rank, memSpec->ranksPerChannel);
// each bank pair has one payload (e.g. 0-8, 1-9, 2-10, 3-11, ...)
for (unsigned outerID = 0; outerID < memSpec->banksPerRank; outerID += (memSpec->getPer2BankOffset() * 2))

2
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp
View File

@@ -49,7 +49,7 @@ RefreshManagerPerBank::RefreshManagerPerBank(std::vector<BankMachine*>& bankMach
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
timeForNextTrigger = getTimeForFirstTrigger(memSpec->getRefreshIntervalPB(),
rank, memSpec->numberOfRanks);
rank, memSpec->ranksPerChannel);
for (auto it : bankMachinesOnRank)
{
setUpDummy(refreshPayloads[it], 0, rank, it->getBankGroup(), it->getBank());

2
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp
View File

@@ -49,7 +49,7 @@ RefreshManagerSameBank::RefreshManagerSameBank(std::vector<BankMachine*>& bankMa
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
timeForNextTrigger = getTimeForFirstTrigger(memSpec->getRefreshIntervalSB(),
rank, memSpec->numberOfRanks);
rank, memSpec->ranksPerChannel);
// each same-bank group has one payload (e.g. 0-4-8-12-16-20-24-28)
refreshPayloads = std::vector<tlm_generic_payload>(memSpec->banksPerGroup);

4
DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp
View File

@@ -43,10 +43,10 @@ using namespace tlm;
SchedulerFifo::SchedulerFifo()
{
Configuration &config = Configuration::getInstance();
buffer = std::vector<std::deque<tlm_generic_payload *>>(config.memSpec->numberOfBanks);
buffer = std::vector<std::deque<tlm_generic_payload *>>(config.memSpec->banksPerChannel);
if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise)
bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->numberOfBanks);
bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->banksPerChannel);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite)
bufferCounter = new BufferCounterReadWrite(config.requestBufferSize);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared)

4
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
View File

@@ -43,10 +43,10 @@ using namespace tlm;
SchedulerFrFcfs::SchedulerFrFcfs()
{
Configuration &config = Configuration::getInstance();
buffer = std::vector<std::list<tlm_generic_payload *>>(config.memSpec->numberOfBanks);
buffer = std::vector<std::list<tlm_generic_payload *>>(config.memSpec->banksPerChannel);
if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise)
bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->numberOfBanks);
bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->banksPerChannel);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite)
bufferCounter = new BufferCounterReadWrite(config.requestBufferSize);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared)

4
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp
View File

@@ -43,10 +43,10 @@ using namespace tlm;
SchedulerFrFcfsGrp::SchedulerFrFcfsGrp()
{
Configuration &config = Configuration::getInstance();
buffer = std::vector<std::list<tlm_generic_payload *>>(config.memSpec->numberOfBanks);
buffer = std::vector<std::list<tlm_generic_payload *>>(config.memSpec->banksPerChannel);
if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise)
bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->numberOfBanks);
bufferCounter = new BufferCounterBankwise(config.requestBufferSize, config.memSpec->banksPerChannel);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite)
bufferCounter = new BufferCounterReadWrite(config.requestBufferSize);
else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared)

8
DRAMSys/library/src/error/errormodel.cpp
View File

@@ -54,13 +54,13 @@ void errorModel::init()
thermalSim = Configuration::getInstance().thermalSimulation;
// Get Configuration parameters:
burstLenght = Configuration::getInstance().memSpec->defaultBurstLength;
numberOfColumns = Configuration::getInstance().memSpec->numberOfColumns;
numberOfColumns = Configuration::getInstance().memSpec->columnsPerRow;
bytesPerColumn = std::log2(Configuration::getInstance().memSpec->dataBusWidth);
// Adjust number of bytes per column dynamically to the selected ecc controller
//TODO: bytesPerColumn = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerColumn);
numberOfRows = Configuration::getInstance().memSpec->numberOfRows;
numberOfRows = Configuration::getInstance().memSpec->rowsPerBank;
numberOfBitErrorEvents = 0;
@@ -216,7 +216,7 @@ void errorModel::store(tlm::tlm_generic_payload &trans)
// Check that there is no column overfow:
std::stringstream msg;
msg << "key.column is " << key.column << " numberOfColumns is " <<
msg << "key.column is " << key.column << " columnsPerRow is " <<
numberOfColumns;
PRINTDEBUGMESSAGE(name(), msg.str());
assert(key.column <= numberOfColumns);
@@ -262,7 +262,7 @@ void errorModel::markBitFlips()
{
double temp = getTemperature();
for (unsigned int row = 0;
row < Configuration::getInstance().memSpec->numberOfRows; row++) {
row < Configuration::getInstance().memSpec->rowsPerBank; row++) {
// If the row has never been accessed ignore it and go to the next one
if (lastRowAccess[row] != SC_ZERO_TIME) {
// Get the time interval between now and the last acivate/refresh

8
DRAMSys/library/src/simulation/AddressDecoder.cpp
View File

@@ -109,10 +109,10 @@ AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addre
Configuration &config = Configuration::getInstance();
const MemSpec *memSpec = config.memSpec;
if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks
|| memSpec->numberOfBankGroups != bankGroups || memSpec->numberOfBanks != banks
|| memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
|| memSpec->numberOfDevices * memSpec->bitWidth != bytes * 8)
if (memSpec->numberOfChannels != channels || memSpec->ranksPerChannel != ranks
|| memSpec->bankGroupsPerChannel != bankGroups || memSpec->banksPerChannel != banks
|| memSpec->rowsPerBank != rows || memSpec->columnsPerRow != columns
|| memSpec->devicesPerRank * memSpec->bitWidth != bytes * 8)
SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match");
}

4
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -108,14 +108,14 @@ void Dram::reportPower()
std::cout << name() << std::string(" Total Energy: ")
<< std::fixed << std::setprecision( 2 )
<< DRAMPower->getEnergy().total_energy
* Configuration::getInstance().memSpec->numberOfDevices
* Configuration::getInstance().memSpec->devicesPerRank
<< std::string(" pJ")
<< std::endl;
std::cout << name() << std::string(" Average Power: ")
<< std::fixed << std::setprecision( 2 )
<< DRAMPower->getPower().average_power
* Configuration::getInstance().memSpec->numberOfDevices
* Configuration::getInstance().memSpec->devicesPerRank
<< std::string(" mW") << std::endl;
}

10
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
View File

@@ -55,12 +55,12 @@ DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name)
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpec->defaultBurstLength;
memArchSpec.dataRate = memSpec->dataRate;
memArchSpec.nbrOfRows = memSpec->numberOfRows;
memArchSpec.nbrOfBanks = memSpec->numberOfBanks;
memArchSpec.nbrOfColumns = memSpec->numberOfColumns;
memArchSpec.nbrOfRanks = memSpec->numberOfRanks;
memArchSpec.nbrOfRows = memSpec->rowsPerBank;
memArchSpec.nbrOfBanks = memSpec->banksPerChannel;
memArchSpec.nbrOfColumns = memSpec->columnsPerRow;
memArchSpec.nbrOfRanks = memSpec->ranksPerChannel;
memArchSpec.width = memSpec->bitWidth;
memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups;
memArchSpec.nbrOfBankGroups = memSpec->bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = false;
memArchSpec.dll = true;

10
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
View File

@@ -55,12 +55,12 @@ DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name)
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpec->defaultBurstLength;
memArchSpec.dataRate = memSpec->dataRate;
memArchSpec.nbrOfRows = memSpec->numberOfRows;
memArchSpec.nbrOfBanks = memSpec->numberOfBanks;
memArchSpec.nbrOfColumns = memSpec->numberOfColumns;
memArchSpec.nbrOfRanks = memSpec->numberOfRanks;
memArchSpec.nbrOfRows = memSpec->rowsPerBank;
memArchSpec.nbrOfBanks = memSpec->banksPerChannel;
memArchSpec.nbrOfColumns = memSpec->columnsPerRow;
memArchSpec.nbrOfRanks = memSpec->ranksPerChannel;
memArchSpec.width = memSpec->bitWidth;
memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups;
memArchSpec.nbrOfBankGroups = memSpec->bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = true;

8
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -70,7 +70,7 @@ void DramRecordable<BaseDram>::reportPower()
BaseDram::reportPower();
tlmRecorder.recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().memSpec->numberOfDevices);
* Configuration::getInstance().memSpec->devicesPerRank);
}
template<class BaseDram>
@@ -136,15 +136,15 @@ void DramRecordable<BaseDram>::powerWindow()
// Store the time (in seconds) and the current average power (in mW) into the database
tlmRecorder.recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().memSpec->numberOfDevices);
* Configuration::getInstance().memSpec->devicesPerRank);
// Here considering that DRAMPower provides the energy in pJ and the power in mW
PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string(
this->DRAMPower->getEnergy().window_energy *
Configuration::getInstance().memSpec->numberOfDevices) + std::string("\t[pJ]"));
Configuration::getInstance().memSpec->devicesPerRank) + std::string("\t[pJ]"));
PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string(
this->DRAMPower->getPower().window_average_power *
Configuration::getInstance().memSpec->numberOfDevices) + std::string("\t[mW]"));
Configuration::getInstance().memSpec->devicesPerRank) + std::string("\t[mW]"));
}
}

14
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -56,12 +56,12 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpec->defaultBurstLength;
memArchSpec.dataRate = memSpec->dataRate;
memArchSpec.nbrOfRows = memSpec->numberOfRows;
memArchSpec.nbrOfBanks = memSpec->numberOfBanks;
memArchSpec.nbrOfColumns = memSpec->numberOfColumns;
memArchSpec.nbrOfRanks = memSpec->numberOfRanks;
memArchSpec.nbrOfRows = memSpec->rowsPerBank;
memArchSpec.nbrOfBanks = memSpec->banksPerChannel;
memArchSpec.nbrOfColumns = memSpec->columnsPerRow;
memArchSpec.nbrOfRanks = memSpec->ranksPerChannel;
memArchSpec.width = memSpec->bitWidth;
memArchSpec.nbrOfBankGroups = memSpec->numberOfBankGroups;
memArchSpec.nbrOfBankGroups = memSpec->bankGroupsPerChannel;
memArchSpec.twoVoltageDomains = true;
memArchSpec.dll = false;
@@ -144,7 +144,7 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
// For each bank in a channel a error Model is created:
if (storeMode == Configuration::StoreMode::ErrorModel)
{
for (unsigned i = 0; i < memSpec->numberOfBanks; i++)
for (unsigned i = 0; i < memSpec->banksPerChannel; i++)
{
errorModel *em;
std::string errorModelStr = "errorModel_bank" + std::to_string(i);
@@ -157,7 +157,7 @@ DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
{
for (unsigned i = 0; i < memSpec->numberOfBanks; i++)
for (unsigned i = 0; i < memSpec->banksPerChannel; i++)
{
errorModel *em;
std::string errorModelStr = "errorModel_bank" + std::to_string(i);