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Merge branch 'feat/cxx17_adaptions' into 'develop'

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Add C++17 features.

See merge request ems/astdm/modeling.dram/dram.sys!346
This commit is contained in:
Lukas Steiner
2022-03-01 15:27:36 +00:00
parent 050738b1af 17e224229d
commit a3bab077cd
46 changed files with 299 additions and 279 deletions
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30
DRAMSys/library/src/controller/BankMachine.cpp
View File

@@ -40,7 +40,7 @@
using namespace sc_core;
using namespace tlm;
BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
BankMachine::BankMachine(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
: scheduler(scheduler), checker(checker), bank(bank)
{
memSpec = Configuration::getInstance().memSpec;
@@ -155,7 +155,7 @@ bool BankMachine::isPrecharged() const
return state == State::Precharged;
}
BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
BankMachineOpen::BankMachineOpen(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
: BankMachine(scheduler, checker, bank) {}
sc_time BankMachineOpen::start()
@@ -165,7 +165,7 @@ sc_time BankMachineOpen::start()
if (!(sleeping || blocked))
{
currentPayload = scheduler->getNextRequest(this);
currentPayload = scheduler.getNextRequest(this);
if (currentPayload != nullptr)
{
if (state == State::Precharged) // bank precharged
@@ -184,13 +184,13 @@ sc_time BankMachineOpen::start()
else // row miss
nextCommand = Command::PREPB;
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
}
}
return timeToSchedule;
}
BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
BankMachineClosed::BankMachineClosed(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
: BankMachine(scheduler, checker, bank) {}
sc_time BankMachineClosed::start()
@@ -200,7 +200,7 @@ sc_time BankMachineClosed::start()
if (!(sleeping || blocked))
{
currentPayload = scheduler->getNextRequest(this);
currentPayload = scheduler.getNextRequest(this);
if (currentPayload != nullptr)
{
if (state == State::Precharged) // bank precharged
@@ -214,13 +214,13 @@ sc_time BankMachineClosed::start()
else
SC_REPORT_FATAL("BankMachine", "Wrong TLM command");
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
}
}
return timeToSchedule;
}
BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
BankMachineOpenAdaptive::BankMachineOpenAdaptive(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
: BankMachine(scheduler, checker, bank) {}
sc_time BankMachineOpenAdaptive::start()
@@ -230,7 +230,7 @@ sc_time BankMachineOpenAdaptive::start()
if (!(sleeping || blocked))
{
currentPayload = scheduler->getNextRequest(this);
currentPayload = scheduler.getNextRequest(this);
if (currentPayload != nullptr)
{
if (state == State::Precharged) // bank precharged
@@ -239,7 +239,7 @@ sc_time BankMachineOpenAdaptive::start()
{
if (DramExtension::getRow(currentPayload) == openRow) // row hit
{
if (scheduler->hasFurtherRequest(bank) && !scheduler->hasFurtherRowHit(bank, openRow))
if (scheduler.hasFurtherRequest(bank) && !scheduler.hasFurtherRowHit(bank, openRow))
{
if (currentPayload->is_read())
nextCommand = Command::RDA;
@@ -261,13 +261,13 @@ sc_time BankMachineOpenAdaptive::start()
else // row miss
nextCommand = Command::PREPB;
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
}
}
return timeToSchedule;
}
BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
BankMachineClosedAdaptive::BankMachineClosedAdaptive(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
: BankMachine(scheduler, checker, bank) {}
sc_time BankMachineClosedAdaptive::start()
@@ -277,7 +277,7 @@ sc_time BankMachineClosedAdaptive::start()
if (!(sleeping || blocked))
{
currentPayload = scheduler->getNextRequest(this);
currentPayload = scheduler.getNextRequest(this);
if (currentPayload != nullptr)
{
if (state == State::Precharged && !blocked) // bank precharged
@@ -286,7 +286,7 @@ sc_time BankMachineClosedAdaptive::start()
{
if (DramExtension::getRow(currentPayload) == openRow) // row hit
{
if (scheduler->hasFurtherRowHit(bank, openRow))
if (scheduler.hasFurtherRowHit(bank, openRow))
{
if (currentPayload->is_read())
nextCommand = Command::RD;
@@ -308,7 +308,7 @@ sc_time BankMachineClosedAdaptive::start()
else // row miss, should never happen
SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy");
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
}
}
return timeToSchedule;

14
DRAMSys/library/src/controller/BankMachine.h
View File

@@ -63,11 +63,11 @@ public:
protected:
enum class State {Precharged, Activated} state = State::Precharged;
BankMachine(SchedulerIF *, CheckerIF *, Bank);
BankMachine(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank);
const MemSpec* memSpec;
tlm::tlm_generic_payload *currentPayload = nullptr;
SchedulerIF *scheduler;
CheckerIF *checker;
const SchedulerIF& scheduler;
const CheckerIF& checker;
Command nextCommand = Command::NOP;
Row openRow;
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
@@ -83,28 +83,28 @@ protected:
class BankMachineOpen final : public BankMachine
{
public:
BankMachineOpen(SchedulerIF *, CheckerIF *, Bank);
BankMachineOpen(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank);
sc_core::sc_time start() override;
};
class BankMachineClosed final : public BankMachine
{
public:
BankMachineClosed(SchedulerIF *, CheckerIF *, Bank);
BankMachineClosed(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank);
sc_core::sc_time start() override;
};
class BankMachineOpenAdaptive final : public BankMachine
{
public:
BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank);
BankMachineOpenAdaptive(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank);
sc_core::sc_time start() override;
};
class BankMachineClosedAdaptive final : public BankMachine
{
public:
BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank);
BankMachineClosedAdaptive(const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank);
sc_core::sc_time start() override;
};

139
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -87,102 +87,100 @@ Controller::Controller(const sc_module_name &name) :
// instantiate timing checker
if (memSpec->memoryType == MemSpec::MemoryType::DDR3)
checker = new CheckerDDR3();
checker = std::make_unique<CheckerDDR3>();
else if (memSpec->memoryType == MemSpec::MemoryType::DDR4)
checker = new CheckerDDR4();
checker = std::make_unique<CheckerDDR4>();
else if (memSpec->memoryType == MemSpec::MemoryType::DDR5)
checker = new CheckerDDR5();
checker = std::make_unique<CheckerDDR5>();
else if (memSpec->memoryType == MemSpec::MemoryType::WideIO)
checker = new CheckerWideIO();
checker = std::make_unique<CheckerWideIO>();
else if (memSpec->memoryType == MemSpec::MemoryType::LPDDR4)
checker = new CheckerLPDDR4();
checker = std::make_unique<CheckerLPDDR4>();
else if (memSpec->memoryType == MemSpec::MemoryType::LPDDR5)
checker = new CheckerLPDDR5();
checker = std::make_unique<CheckerLPDDR5>();
else if (memSpec->memoryType == MemSpec::MemoryType::WideIO2)
checker = new CheckerWideIO2();
checker = std::make_unique<CheckerWideIO2>();
else if (memSpec->memoryType == MemSpec::MemoryType::HBM2)
checker = new CheckerHBM2();
checker = std::make_unique<CheckerHBM2>();
else if (memSpec->memoryType == MemSpec::MemoryType::GDDR5)
checker = new CheckerGDDR5();
checker = std::make_unique<CheckerGDDR5>();
else if (memSpec->memoryType == MemSpec::MemoryType::GDDR5X)
checker = new CheckerGDDR5X();
checker = std::make_unique<CheckerGDDR5X>();
else if (memSpec->memoryType == MemSpec::MemoryType::GDDR6)
checker = new CheckerGDDR6();
checker = std::make_unique<CheckerGDDR6>();
else if (memSpec->memoryType == MemSpec::MemoryType::STTMRAM)
checker = new CheckerSTTMRAM();
checker = std::make_unique<CheckerSTTMRAM>();
// instantiate scheduler and command mux
if (config.scheduler == Configuration::Scheduler::Fifo)
scheduler = new SchedulerFifo();
scheduler = std::make_unique<SchedulerFifo>();
else if (config.scheduler == Configuration::Scheduler::FrFcfs)
scheduler = new SchedulerFrFcfs();
scheduler = std::make_unique<SchedulerFrFcfs>();
else if (config.scheduler == Configuration::Scheduler::FrFcfsGrp)
scheduler = new SchedulerFrFcfsGrp();
scheduler = std::make_unique<SchedulerFrFcfsGrp>();
if (config.cmdMux == Configuration::CmdMux::Oldest)
{
if (memSpec->hasRasAndCasBus())
cmdMux = new CmdMuxOldestRasCas();
cmdMux = std::make_unique<CmdMuxOldestRasCas>();
else
cmdMux = new CmdMuxOldest();
cmdMux = std::make_unique<CmdMuxOldest>();
}
else if (config.cmdMux == Configuration::CmdMux::Strict)
{
if (memSpec->hasRasAndCasBus())
cmdMux = new CmdMuxStrictRasCas();
cmdMux = std::make_unique<CmdMuxStrictRasCas>();
else
cmdMux = new CmdMuxStrict();
cmdMux = std::make_unique<CmdMuxStrict>();
}
if (config.respQueue == Configuration::RespQueue::Fifo)
respQueue = new RespQueueFifo();
respQueue = std::make_unique<RespQueueFifo>();
else if (config.respQueue == Configuration::RespQueue::Reorder)
respQueue = new RespQueueReorder();
respQueue = std::make_unique<RespQueueReorder>();
// instantiate bank machines (one per bank)
if (config.pagePolicy == Configuration::PagePolicy::Open)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID)));
bankMachines.emplace_back(std::make_unique<BankMachineOpen>(*scheduler, *checker, Bank(bankID)));
}
else if (config.pagePolicy == Configuration::PagePolicy::OpenAdaptive)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID)));
bankMachines.emplace_back(std::make_unique<BankMachineOpenAdaptive>(*scheduler, *checker, Bank(bankID)));
}
else if (config.pagePolicy == Configuration::PagePolicy::Closed)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID)));
bankMachines.emplace_back(std::make_unique<BankMachineClosed>(*scheduler, *checker, Bank(bankID)));
}
else if (config.pagePolicy == Configuration::PagePolicy::ClosedAdaptive)
{
for (unsigned bankID = 0; bankID < memSpec->numberOfBanks; bankID++)
bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID)));
bankMachines.emplace_back(std::make_unique<BankMachineClosedAdaptive>(*scheduler, *checker, Bank(bankID)));
}
bankMachinesOnRank = std::vector<std::vector<BankMachine*>>(memSpec->numberOfRanks,
std::vector<BankMachine*>(memSpec->banksPerRank));
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
bankMachinesOnRank.emplace_back(bankMachines.begin() + rankID * memSpec->banksPerRank,
bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank);
for (unsigned bankID = 0; bankID < memSpec->banksPerRank; bankID++)
bankMachinesOnRank[rankID][bankID] = bankMachines[rankID * memSpec->banksPerRank + bankID].get();
}
// instantiate power-down managers (one per rank)
if (config.powerDownPolicy == Configuration::PowerDownPolicy::NoPowerDown)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
PowerDownManagerIF *manager = new PowerDownManagerDummy();
powerDownManagers.push_back(manager);
}
powerDownManagers.emplace_back(std::make_unique<PowerDownManagerDummy>());
}
else if (config.powerDownPolicy == Configuration::PowerDownPolicy::Staggered)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
PowerDownManagerIF *manager = new PowerDownManagerStaggered(bankMachinesOnRank[rankID],
Rank(rankID), checker);
powerDownManagers.push_back(manager);
powerDownManagers.emplace_back(std::make_unique<PowerDownManagerStaggered>(bankMachinesOnRank[rankID],
Rank(rankID), *checker));
}
}
@@ -190,24 +188,22 @@ Controller::Controller(const sc_module_name &name) :
if (config.refreshPolicy == Configuration::RefreshPolicy::NoRefresh)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
refreshManagers.push_back(new RefreshManagerDummy());
refreshManagers.emplace_back(std::make_unique<RefreshManagerDummy>());
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::AllBank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
RefreshManagerIF *manager = new RefreshManagerAllBank
(bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker);
refreshManagers.push_back(manager);
refreshManagers.emplace_back(std::make_unique<RefreshManagerAllBank>
(bankMachinesOnRank[rankID], *powerDownManagers[rankID].get(), Rank(rankID), *checker));
}
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::SameBank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
RefreshManagerIF *manager = new RefreshManagerSameBank
(bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker);
refreshManagers.push_back(manager);
refreshManagers.emplace_back(std::make_unique<RefreshManagerSameBank>
(bankMachinesOnRank[rankID], *powerDownManagers[rankID].get(), Rank(rankID), *checker));
}
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::PerBank)
@@ -215,9 +211,8 @@ Controller::Controller(const sc_module_name &name) :
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
// TODO: remove bankMachines in constructor
RefreshManagerIF *manager = new RefreshManagerPerBank
(bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker);
refreshManagers.push_back(manager);
refreshManagers.emplace_back(std::make_unique<RefreshManagerPerBank>
(bankMachinesOnRank[rankID], *powerDownManagers[rankID], Rank(rankID), *checker));
}
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::Per2Bank)
@@ -225,9 +220,8 @@ Controller::Controller(const sc_module_name &name) :
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
// TODO: remove bankMachines in constructor
RefreshManagerIF *manager = new RefreshManagerPer2Bank
(bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker);
refreshManagers.push_back(manager);
refreshManagers.emplace_back(std::make_unique<RefreshManagerPer2Bank>
(bankMachinesOnRank[rankID], *powerDownManagers[rankID], Rank(rankID), *checker));
}
}
else
@@ -236,20 +230,9 @@ Controller::Controller(const sc_module_name &name) :
idleTimeCollector.start();
}
Controller::~Controller()
void Controller::end_of_simulation()
{
idleTimeCollector.end();
for (auto it : refreshManagers)
delete it;
for (auto it : powerDownManagers)
delete it;
for (auto it : bankMachines)
delete it;
delete respQueue;
delete cmdMux;
delete scheduler;
delete checker;
}
void Controller::controllerMethod()
@@ -261,9 +244,9 @@ void Controller::controllerMethod()
manageRequests(SC_ZERO_TIME);
// (3) Start refresh and power-down managers to issue requests for the current time
for (auto it : refreshManagers)
for (auto& it : refreshManagers)
it->start();
for (auto it : powerDownManagers)
for (auto& it : powerDownManagers)
it->start();
// (4) Collect all ready commands from BMs, RMs and PDMs
@@ -327,7 +310,7 @@ void Controller::controllerMethod()
refreshManagers[rank.ID()]->updateState(command);
powerDownManagers[rank.ID()]->updateState(command);
checker->insert(command, payload);
checker->insert(command, *payload);
if (command.isCasCommand())
{
@@ -347,7 +330,8 @@ void Controller::controllerMethod()
if (ranksNumberOfPayloads[rank.ID()] == 0)
powerDownManagers[rank.ID()]->triggerEntry();
sendToDram(command, payload, thinkDelayFw + phyDelayFw);
sc_time fwDelay = thinkDelayFw + phyDelayFw;
sendToDram(command, *payload, fwDelay);
}
else
readyCmdBlocked = true;
@@ -356,19 +340,19 @@ void Controller::controllerMethod()
// (6) Restart bank machines, refresh managers and power-down managers to issue new requests for the future
sc_time timeForNextTrigger = sc_max_time();
sc_time localTime;
for (auto it : bankMachines)
for (auto& it : bankMachines)
{
localTime = it->start();
if (!(localTime == sc_time_stamp() && readyCmdBlocked))
timeForNextTrigger = std::min(timeForNextTrigger, localTime);
}
for (auto it : refreshManagers)
for (auto& it : refreshManagers)
{
localTime = it->start();
if (!(localTime == sc_time_stamp() && readyCmdBlocked))
timeForNextTrigger = std::min(timeForNextTrigger, localTime);
}
for (auto it : powerDownManagers)
for (auto& it : powerDownManagers)
{
localTime = it->start();
if (!(localTime == sc_time_stamp() && readyCmdBlocked))
@@ -440,7 +424,9 @@ void Controller::manageRequests(const sc_time &delay)
bankMachines[bank.ID()]->start();
transToAcquire.payload->set_response_status(TLM_OK_RESPONSE);
sendToFrontend(transToAcquire.payload, END_REQ, delay);
tlm_phase bwPhase = END_REQ;
sc_time bwDelay = delay;
sendToFrontend(*transToAcquire.payload, bwPhase, bwDelay);
transToAcquire.payload = nullptr;
}
else
@@ -476,7 +462,9 @@ void Controller::manageResponses()
if (transToRelease.payload != nullptr)
{
// last payload was released in this cycle
sendToFrontend(transToRelease.payload, BEGIN_RESP, memSpec->tCK);
tlm_phase bwPhase = BEGIN_RESP;
sc_time bwDelay = memSpec->tCK;
sendToFrontend(*transToRelease.payload, bwPhase, bwDelay);
transToRelease.time = sc_max_time();
}
else
@@ -494,11 +482,14 @@ void Controller::manageResponses()
if (transToRelease.payload != nullptr)
{
tlm_phase bwPhase = BEGIN_RESP;
sc_time bwDelay;
if (transToRelease.time == sc_time_stamp()) // last payload was released in this cycle
sendToFrontend(transToRelease.payload, BEGIN_RESP, memSpec->tCK);
bwDelay = memSpec->tCK;
else
sendToFrontend(transToRelease.payload, BEGIN_RESP, SC_ZERO_TIME);
bwDelay = SC_ZERO_TIME;
sendToFrontend(*transToRelease.payload, bwPhase, bwDelay);
transToRelease.time = sc_max_time();
}
else
@@ -510,13 +501,13 @@ void Controller::manageResponses()
}
}
void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase, sc_time delay)
void Controller::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay)
{
tSocket->nb_transport_bw(*payload, phase, delay);
tSocket->nb_transport_bw(payload, phase, delay);
}
void Controller::sendToDram(Command command, tlm_generic_payload *payload, sc_time delay)
void Controller::sendToDram(Command command, tlm_generic_payload& payload, sc_time& delay)
{
tlm_phase phase = command.toPhase();
iSocket->nb_transport_fw(*payload, phase, delay);
iSocket->nb_transport_fw(payload, phase, delay);
}

38
DRAMSys/library/src/controller/Controller.h
View File

@@ -42,36 +42,34 @@
#include <tlm>
#include "ControllerIF.h"
#include "Command.h"
#include "BankMachine.h"
#include "cmdmux/CmdMuxIF.h"
#include "checker/CheckerIF.h"
#include "refresh/RefreshManagerIF.h"
#include "powerdown/PowerDownManagerIF.h"
#include "respqueue/RespQueueIF.h"
class BankMachine;
class SchedulerIF;
class PowerDownManagerStaggered;
class Controller : public ControllerIF
{
public:
explicit Controller(const sc_core::sc_module_name &name);
SC_HAS_PROCESS(Controller);
~Controller() override;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
unsigned int transport_dbg(tlm::tlm_generic_payload &trans) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) override;
unsigned int transport_dbg(tlm::tlm_generic_payload& trans) override;
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_core::sc_time);
virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_core::sc_time);
virtual void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay);
virtual void sendToDram(Command, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay);
void end_of_simulation() override;
virtual void controllerMethod();
SchedulerIF *scheduler;
std::unique_ptr<SchedulerIF> scheduler;
const MemSpec *memSpec;
sc_core::sc_time thinkDelayFw;
@@ -84,13 +82,13 @@ private:
std::vector<unsigned> ranksNumberOfPayloads;
ReadyCommands readyCommands;
std::vector<BankMachine *> bankMachines;
std::vector<std::vector<BankMachine *>> bankMachinesOnRank;
CmdMuxIF *cmdMux;
CheckerIF *checker;
RespQueueIF *respQueue;
std::vector<RefreshManagerIF *> refreshManagers;
std::vector<PowerDownManagerIF *> powerDownManagers;
std::vector<std::unique_ptr<BankMachine>> bankMachines;
std::vector<std::vector<BankMachine*>> bankMachinesOnRank;
std::unique_ptr<CmdMuxIF> cmdMux;
std::unique_ptr<CheckerIF> checker;
std::unique_ptr<RespQueueIF> respQueue;
std::vector<std::unique_ptr<RefreshManagerIF>> refreshManagers;
std::vector<std::unique_ptr<PowerDownManagerIF>> powerDownManagers;
struct Transaction
{

10
DRAMSys/library/src/controller/ControllerIF.h
View File

@@ -99,7 +99,7 @@ public:
protected:
// Bind sockets with virtual functions
explicit ControllerIF(const sc_core::sc_module_name &name)
explicit ControllerIF(const sc_core::sc_module_name& name)
: sc_core::sc_module(name), tSocket("tSocket"), iSocket("iSocket")
{
tSocket.register_nb_transport_fw(this, &ControllerIF::nb_transport_fw);
@@ -109,9 +109,11 @@ protected:
SC_HAS_PROCESS(ControllerIF);
// Virtual transport functions
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_core::sc_time &) = 0;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_core::sc_time &) = 0;
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) = 0;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase,
sc_core::sc_time& delay) = 0;
// Bandwidth related
class IdleTimeCollector

14
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -67,23 +67,23 @@ tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &,
return TLM_ACCEPTED;
}
void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase, sc_time delay)
void ControllerRecordable::sendToFrontend(tlm_generic_payload& payload, tlm_phase& phase, sc_time& delay)
{
recordPhase(*payload, phase, delay);
tSocket->nb_transport_bw(*payload, phase, delay);
recordPhase(payload, phase, delay);
tSocket->nb_transport_bw(payload, phase, delay);
}
void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload, sc_time delay)
void ControllerRecordable::sendToDram(Command command, tlm_generic_payload& payload, sc_time& delay)
{
if (command.isCasCommand())
{
TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, *payload);
TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, payload);
tlmRecorder.updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start,
sc_time_stamp() + delay + dataStrobe.end, *payload);
sc_time_stamp() + delay + dataStrobe.end, payload);
}
tlm_phase phase = command.toPhase();
iSocket->nb_transport_fw(*payload, phase, delay);
iSocket->nb_transport_fw(payload, phase, delay);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)

4
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -52,8 +52,8 @@ protected:
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase,
sc_core::sc_time &delay) override;
void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_core::sc_time) override;
void sendToDram(Command, tlm::tlm_generic_payload *, sc_core::sc_time) override;
void sendToFrontend(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) override;
void sendToDram(Command command, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) override;
void controllerMethod() override;

4
DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
View File

@@ -65,7 +65,7 @@ CheckerDDR3::CheckerDDR3()
tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK;
}
sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);
@@ -424,7 +424,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, tlm_generic_paylo
return earliestTimeToStart;
}
void CheckerDDR3::insert(Command command, tlm_generic_payload *payload)
void CheckerDDR3::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);

4
DRAMSys/library/src/controller/checker/CheckerDDR3.h
View File

@@ -46,8 +46,8 @@ class CheckerDDR3 final : public CheckerIF
{
public:
CheckerDDR3();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecDDR3 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
View File

@@ -68,7 +68,7 @@ CheckerDDR4::CheckerDDR4()
tWRAPDEN = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR;
}
sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
@@ -456,7 +456,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, tlm_generic_paylo
return earliestTimeToStart;
}
void CheckerDDR4::insert(Command command, tlm_generic_payload *payload)
void CheckerDDR4::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);

4
DRAMSys/library/src/controller/checker/CheckerDDR4.h
View File

@@ -46,8 +46,8 @@ class CheckerDDR4 final : public CheckerIF
{
public:
CheckerDDR4();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecDDR4 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
View File

@@ -116,7 +116,7 @@ CheckerDDR5::CheckerDDR5()
tWRAPDEN = memSpec->tWL + tBURST16 + memSpec->tWR + cmdLengthDiff;
}
sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank logicalRank = DramExtension::getRank(payload);
Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank);
@@ -878,7 +878,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo
return earliestTimeToStart;
}
void CheckerDDR5::insert(Command command, tlm_generic_payload *payload)
void CheckerDDR5::insert(Command command, const tlm_generic_payload& payload)
{
Rank logicalRank = DramExtension::getRank(payload);
Rank physicalRank = Rank(logicalRank.ID() / memSpec->logicalRanksPerPhysicalRank);

4
DRAMSys/library/src/controller/checker/CheckerDDR5.h
View File

@@ -47,8 +47,8 @@ class CheckerDDR5 final : public CheckerIF
{
public:
CheckerDDR5();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecDDR5 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
View File

@@ -69,7 +69,7 @@ CheckerGDDR5::CheckerGDDR5()
tWRPRE = memSpec->tWL + tBURST + memSpec->tWR;
}
sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
@@ -538,7 +538,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payl
return earliestTimeToStart;
}
void CheckerGDDR5::insert(Command command, tlm_generic_payload *payload)
void CheckerGDDR5::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);

4
DRAMSys/library/src/controller/checker/CheckerGDDR5.h
View File

@@ -46,8 +46,8 @@ class CheckerGDDR5 final : public CheckerIF
{
public:
CheckerGDDR5();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecGDDR5 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
View File

@@ -69,7 +69,7 @@ CheckerGDDR5X::CheckerGDDR5X()
tWRPRE = memSpec->tWL + tBURST + memSpec->tWR;
}
sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
@@ -542,7 +542,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, tlm_generic_pay
return earliestTimeToStart;
}
void CheckerGDDR5X::insert(Command command, tlm_generic_payload *payload)
void CheckerGDDR5X::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);

4
DRAMSys/library/src/controller/checker/CheckerGDDR5X.h
View File

@@ -46,8 +46,8 @@ class CheckerGDDR5X final : public CheckerIF
{
public:
CheckerGDDR5X();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecGDDR5X *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
View File

@@ -68,7 +68,7 @@ CheckerGDDR6::CheckerGDDR6()
tWRPRE = memSpec->tWL + tBURST + memSpec->tWR;
}
sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
@@ -559,7 +559,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, tlm_generic_payl
return earliestTimeToStart;
}
void CheckerGDDR6::insert(Command command, tlm_generic_payload *payload)
void CheckerGDDR6::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);

4
DRAMSys/library/src/controller/checker/CheckerGDDR6.h
View File

@@ -46,8 +46,8 @@ class CheckerGDDR6 final : public CheckerIF
{
public:
CheckerGDDR6();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecGDDR6 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
View File

@@ -69,7 +69,7 @@ CheckerHBM2::CheckerHBM2()
tWRRDL = memSpec->tWL + tBURST + memSpec->tWTRL;
}
sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
@@ -517,7 +517,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_paylo
return earliestTimeToStart;
}
void CheckerHBM2::insert(Command command, tlm_generic_payload *payload)
void CheckerHBM2::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);

4
DRAMSys/library/src/controller/checker/CheckerHBM2.h
View File

@@ -46,8 +46,8 @@ class CheckerHBM2 final : public CheckerIF
{
public:
CheckerHBM2();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecHBM2 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerIF.h
View File

@@ -43,8 +43,8 @@ class CheckerIF
public:
virtual ~CheckerIF() = default;
virtual sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) = 0;
virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0;
};
#endif // CHECKERIF_H

4
DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
View File

@@ -71,7 +71,7 @@ CheckerLPDDR4::CheckerLPDDR4()
tREFPDEN = memSpec->tCK + memSpec->tCMDCKE;
}
sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);
@@ -512,7 +512,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, tlm_generic_pay
return earliestTimeToStart;
}
void CheckerLPDDR4::insert(Command command, tlm_generic_payload *payload)
void CheckerLPDDR4::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);

4
DRAMSys/library/src/controller/checker/CheckerLPDDR4.h
View File

@@ -46,8 +46,8 @@ class CheckerLPDDR4 final : public CheckerIF
{
public:
CheckerLPDDR4();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecLPDDR4 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp
View File

@@ -71,7 +71,7 @@ CheckerLPDDR5::CheckerLPDDR5()
}
}
sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
@@ -637,7 +637,7 @@ sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_pay
return earliestTimeToStart;
}
void CheckerLPDDR5::insert(Command command, tlm_generic_payload *payload)
void CheckerLPDDR5::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);

4
DRAMSys/library/src/controller/checker/CheckerLPDDR5.h
View File

@@ -47,8 +47,8 @@ class CheckerLPDDR5 final : public CheckerIF
{
public:
CheckerLPDDR5();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecLPDDR5 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
View File

@@ -65,7 +65,7 @@ CheckerSTTMRAM::CheckerSTTMRAM()
tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK;
}
sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);
@@ -380,7 +380,7 @@ sc_time CheckerSTTMRAM::timeToSatisfyConstraints(Command command, tlm_generic_pa
return earliestTimeToStart;
}
void CheckerSTTMRAM::insert(Command command, tlm_generic_payload *payload)
void CheckerSTTMRAM::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);

4
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h
View File

@@ -46,8 +46,8 @@ class CheckerSTTMRAM final : public CheckerIF
{
public:
CheckerSTTMRAM();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecSTTMRAM *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
View File

@@ -65,7 +65,7 @@ CheckerWideIO::CheckerWideIO()
tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR; // + memSpec->tCK; ??
}
sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);
@@ -401,7 +401,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, tlm_generic_pay
return earliestTimeToStart;
}
void CheckerWideIO::insert(Command command, tlm_generic_payload *payload)
void CheckerWideIO::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);

4
DRAMSys/library/src/controller/checker/CheckerWideIO.h
View File

@@ -46,8 +46,8 @@ class CheckerWideIO final : public CheckerIF
{
public:
CheckerWideIO();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecWideIO *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
View File

@@ -66,7 +66,7 @@ CheckerWideIO2::CheckerWideIO2()
tWRRD_R = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tRTRS - memSpec->tRL;
}
sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, const tlm_generic_payload& payload) const
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);
@@ -479,7 +479,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, tlm_generic_pa
return earliestTimeToStart;
}
void CheckerWideIO2::insert(Command command, tlm_generic_payload *payload)
void CheckerWideIO2::insert(Command command, const tlm_generic_payload& payload)
{
Rank rank = DramExtension::getRank(payload);
Bank bank = DramExtension::getBank(payload);

4
DRAMSys/library/src/controller/checker/CheckerWideIO2.h
View File

@@ -46,8 +46,8 @@ class CheckerWideIO2 final : public CheckerIF
{
public:
CheckerWideIO2();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
const MemSpecWideIO2 *memSpec;

11
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp
View File

@@ -33,13 +33,14 @@
*/
#include "PowerDownManagerStaggered.h"
#include "../BankMachine.h"
#include "../../common/utils.h"
using namespace sc_core;
using namespace tlm;
PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector<BankMachine *> &bankMachinesOnRank,
Rank rank, CheckerIF *checker)
PowerDownManagerStaggered::PowerDownManagerStaggered(std::vector<BankMachine*>& bankMachinesOnRank,
Rank rank, CheckerIF& checker)
: bankMachinesOnRank(bankMachinesOnRank), checker(checker)
{
setUpDummy(powerDownPayload, UINT64_MAX - 1, rank);
@@ -92,7 +93,7 @@ sc_time PowerDownManagerStaggered::start()
else if (state == State::ExtraRefresh)
nextCommand = Command::REFAB;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, powerDownPayload);
}
else if (entryTriggered)
{
@@ -106,12 +107,12 @@ sc_time PowerDownManagerStaggered::start()
}
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, powerDownPayload);
}
else if (enterSelfRefresh)
{
nextCommand = Command::SREFEN;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &powerDownPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, powerDownPayload);
}
return timeToSchedule;

11
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -37,13 +37,16 @@
#include <systemc>
#include "PowerDownManagerIF.h"
#include "../BankMachine.h"
#include "../../common/dramExtensions.h"
#include "../checker/CheckerIF.h"
class BankMachine;
class PowerDownManagerStaggered final : public PowerDownManagerIF
{
public:
PowerDownManagerStaggered(std::vector<BankMachine *> &, Rank, CheckerIF *);
PowerDownManagerStaggered(std::vector<BankMachine*>& bankMachinesOnRank,
Rank rank, CheckerIF& checker);
void triggerEntry() override;
void triggerExit() override;
@@ -56,8 +59,8 @@ public:
private:
enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle;
tlm::tlm_generic_payload powerDownPayload;
std::vector<BankMachine *> &bankMachinesOnRank;
CheckerIF *checker;
std::vector<BankMachine*>& bankMachinesOnRank;
CheckerIF& checker;
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
Command nextCommand = Command::NOP;

14
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp
View File

@@ -34,6 +34,8 @@
*/
#include "RefreshManagerAllBank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../common/dramExtensions.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
@@ -41,8 +43,8 @@
using namespace sc_core;
using namespace tlm;
RefreshManagerAllBank::RefreshManagerAllBank(std::vector<BankMachine *> &bankMachinesOnRank,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
RefreshManagerAllBank::RefreshManagerAllBank(std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker)
: bankMachinesOnRank(bankMachinesOnRank), powerDownManager(powerDownManager), checker(checker)
{
Configuration &config = Configuration::getInstance();
@@ -69,7 +71,7 @@ sc_time RefreshManagerAllBank::start()
if (sc_time_stamp() >= timeForNextTrigger) // Normal refresh
{
powerDownManager->triggerInterruption();
powerDownManager.triggerInterruption();
if (sleeping)
return timeToSchedule;
@@ -109,7 +111,7 @@ sc_time RefreshManagerAllBank::start()
else
nextCommand = Command::REFAB;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, refreshPayload);
return timeToSchedule;
}
}
@@ -130,7 +132,7 @@ sc_time RefreshManagerAllBank::start()
if (doRefresh)
{
nextCommand = Command::REFAB;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, refreshPayload);
return timeToSchedule;
}
}
@@ -172,7 +174,7 @@ sc_time RefreshManagerAllBank::start()
else
nextCommand = Command::RFMAB;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, refreshPayload);
return timeToSchedule;
}
}

16
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h
View File

@@ -40,15 +40,17 @@
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
class BankMachine;
class PowerDownManagerIF;
class RefreshManagerAllBank final : public RefreshManagerIF
{
public:
RefreshManagerAllBank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
RefreshManagerAllBank(std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker);
CommandTuple::Type getNextCommand() override;
sc_core::sc_time start() override;
@@ -57,12 +59,12 @@ public:
private:
enum class State {Regular, Pulledin} state = State::Regular;
const MemSpec *memSpec;
std::vector<BankMachine *> &bankMachinesOnRank;
PowerDownManagerIF *powerDownManager;
std::vector<BankMachine*>& bankMachinesOnRank;
PowerDownManagerIF& powerDownManager;
tlm::tlm_generic_payload refreshPayload;
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
const CheckerIF& checker;
Command nextCommand = Command::NOP;
unsigned activatedBanks = 0;

13
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.cpp
View File

@@ -33,6 +33,8 @@
*/
#include "RefreshManagerPer2Bank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
@@ -40,8 +42,9 @@
using namespace sc_core;
using namespace tlm;
RefreshManagerPer2Bank::RefreshManagerPer2Bank(std::vector<BankMachine *> &bankMachinesOnRank,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
RefreshManagerPer2Bank::RefreshManagerPer2Bank(std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank,
const CheckerIF& checker)
: powerDownManager(powerDownManager), checker(checker)
{
Configuration &config = Configuration::getInstance();
@@ -83,7 +86,7 @@ sc_time RefreshManagerPer2Bank::start()
if (sc_time_stamp() >= timeForNextTrigger)
{
powerDownManager->triggerInterruption();
powerDownManager.triggerInterruption();
if (sleeping)
return timeToSchedule;
@@ -149,7 +152,7 @@ sc_time RefreshManagerPer2Bank::start()
skipSelection = true;
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentRefreshPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentRefreshPayload);
return timeToSchedule;
}
}
@@ -197,7 +200,7 @@ sc_time RefreshManagerPer2Bank::start()
}
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentRefreshPayload);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentRefreshPayload);
return timeToSchedule;
}
}

21
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.h
View File

@@ -42,14 +42,17 @@
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
class BankMachine;
class PowerDownManagerIF;
class RefreshManagerPer2Bank final : public RefreshManagerIF
{
public:
RefreshManagerPer2Bank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
RefreshManagerPer2Bank(std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker);
CommandTuple::Type getNextCommand() override;
sc_core::sc_time start() override;
@@ -58,17 +61,17 @@ public:
private:
enum class State {Regular, Pulledin} state = State::Regular;
const MemSpec *memSpec;
PowerDownManagerIF *powerDownManager;
std::unordered_map<BankMachine *, tlm::tlm_generic_payload> refreshPayloads;
PowerDownManagerIF& powerDownManager;
std::unordered_map<BankMachine*, tlm::tlm_generic_payload> refreshPayloads;
tlm::tlm_generic_payload *currentRefreshPayload;
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
const CheckerIF& checker;
Command nextCommand = Command::NOP;
std::list<std::vector<BankMachine *>> remainingBankMachines;
std::list<std::vector<BankMachine *>> allBankMachines;
std::list<std::vector<BankMachine *>>::iterator currentIterator;
std::list<std::vector<BankMachine*>> remainingBankMachines;
std::list<std::vector<BankMachine*>> allBankMachines;
std::list<std::vector<BankMachine*>>::iterator currentIterator;
int flexibilityCounter = 0;
int maxPostponed = 0;

12
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.cpp
View File

@@ -33,6 +33,8 @@
*/
#include "RefreshManagerPerBank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
@@ -40,8 +42,8 @@
using namespace sc_core;
using namespace tlm;
RefreshManagerPerBank::RefreshManagerPerBank(std::vector<BankMachine *> &bankMachinesOnRank,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
RefreshManagerPerBank::RefreshManagerPerBank(std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker)
: powerDownManager(powerDownManager), checker(checker)
{
Configuration &config = Configuration::getInstance();
@@ -73,7 +75,7 @@ sc_time RefreshManagerPerBank::start()
if (sc_time_stamp() >= timeForNextTrigger)
{
powerDownManager->triggerInterruption();
powerDownManager.triggerInterruption();
if (sleeping)
return timeToSchedule;
@@ -125,7 +127,7 @@ sc_time RefreshManagerPerBank::start()
}
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayloads[*currentIterator]);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, refreshPayloads[*currentIterator]);
return timeToSchedule;
}
}
@@ -156,7 +158,7 @@ sc_time RefreshManagerPerBank::start()
else
nextCommand = Command::REFPB;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayloads[*currentIterator]);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, refreshPayloads[*currentIterator]);
return timeToSchedule;
}
}

13
DRAMSys/library/src/controller/refresh/RefreshManagerPerBank.h
View File

@@ -42,14 +42,17 @@
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
class BankMachine;
class PowerDownManagerIF;
class RefreshManagerPerBank final : public RefreshManagerIF
{
public:
RefreshManagerPerBank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
RefreshManagerPerBank(std::vector<BankMachine *>& bankMachinesOnRank, PowerDownManagerIF& powerDownManager,
Rank rank, const CheckerIF& checker);
CommandTuple::Type getNextCommand() override;
sc_core::sc_time start() override;
@@ -58,11 +61,11 @@ public:
private:
enum class State {Regular, Pulledin} state = State::Regular;
const MemSpec *memSpec;
PowerDownManagerIF *powerDownManager;
PowerDownManagerIF& powerDownManager;
std::unordered_map<BankMachine*, tlm::tlm_generic_payload> refreshPayloads;
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
const CheckerIF& checker;
Command nextCommand = Command::NOP;
std::list<BankMachine *> remainingBankMachines;

24
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp
View File

@@ -33,6 +33,8 @@
*/
#include "RefreshManagerSameBank.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
@@ -40,8 +42,8 @@
using namespace sc_core;
using namespace tlm;
RefreshManagerSameBank::RefreshManagerSameBank(std::vector<BankMachine *> &bankMachinesOnRank,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
RefreshManagerSameBank::RefreshManagerSameBank(std::vector<BankMachine*>& bankMachinesOnRank,
PowerDownManagerIF& powerDownManager, Rank rank, const CheckerIF& checker)
: powerDownManager(powerDownManager), checker(checker)
{
Configuration &config = Configuration::getInstance();
@@ -91,7 +93,7 @@ sc_time RefreshManagerSameBank::start()
if (sc_time_stamp() >= timeForNextTrigger)
{
powerDownManager->triggerInterruption();
powerDownManager.triggerInterruption();
if (sleeping)
return timeToSchedule;
@@ -155,8 +157,8 @@ sc_time RefreshManagerSameBank::start()
skipSelection = true;
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand,
&refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand,
refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
return timeToSchedule;
}
}
@@ -201,8 +203,8 @@ sc_time RefreshManagerSameBank::start()
}
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand,
&refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand,
refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
return timeToSchedule;
}
}
@@ -239,8 +241,8 @@ sc_time RefreshManagerSameBank::start()
if (groupIt->isActivated())
nextCommand = Command::PRESB;
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand,
&refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand,
refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
return timeToSchedule;
}
else if (!imtCandidates.empty())
@@ -276,8 +278,8 @@ sc_time RefreshManagerSameBank::start()
break;
}
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand,
&refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
timeToSchedule = checker.timeToSatisfyConstraints(nextCommand,
refreshPayloads[currentIterator->front()->getBank().ID() % memSpec->banksPerGroup]);
return timeToSchedule;
}
}

13
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.h
View File

@@ -41,14 +41,17 @@
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../checker/CheckerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
class BankMachine;
class PowerDownManagerIF;
class RefreshManagerSameBank final : public RefreshManagerIF
{
public:
RefreshManagerSameBank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
RefreshManagerSameBank(std::vector<BankMachine *>& bankMachinesOnRank, PowerDownManagerIF& powerDownManager,
Rank rank, const CheckerIF& checker);
CommandTuple::Type getNextCommand() override;
sc_core::sc_time start() override;
@@ -57,11 +60,11 @@ public:
private:
enum class State {Regular, Pulledin} state = State::Regular;
const MemSpec *memSpec;
PowerDownManagerIF *powerDownManager;
PowerDownManagerIF& powerDownManager;
std::vector<tlm::tlm_generic_payload> refreshPayloads;
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
const CheckerIF& checker;
Command nextCommand = Command::NOP;
std::list<std::vector<BankMachine *>> remainingBankMachines;

36
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -40,6 +40,7 @@
#include <cstdlib>
#include <iostream>
#include <memory>
#include <vector>
#include <stdexcept>
@@ -150,45 +151,46 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping &add
// Create arbiter
if (config.arbiter == Configuration::Arbiter::Simple)
arbiter = std::unique_ptr<Arbiter>(new ArbiterSimple("arbiter", addressMapping));
arbiter = std::make_unique<ArbiterSimple>("arbiter", addressMapping);
else if (config.arbiter == Configuration::Arbiter::Fifo)
arbiter = std::unique_ptr<Arbiter>(new ArbiterFifo("arbiter", addressMapping));
arbiter = std::make_unique<ArbiterFifo>("arbiter", addressMapping);
else if (config.arbiter == Configuration::Arbiter::Reorder)
arbiter = std::unique_ptr<Arbiter>(new ArbiterReorder("arbiter", addressMapping));
arbiter = std::make_unique<ArbiterReorder>("arbiter", addressMapping);
// Create controllers and DRAMs
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
controllers.emplace_back(new Controller(("controller" + std::to_string(i)).c_str()));
controllers.emplace_back(std::make_unique<Controller>(("controller" + std::to_string(i)).c_str()));
if (memoryType == MemSpec::MemoryType::DDR3)
drams.emplace_back(new DramDDR3(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramDDR3>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::DDR4)
drams.emplace_back(new DramDDR4(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramDDR4>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(new DramDDR5(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramDDR5>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::WideIO)
drams.emplace_back(new DramWideIO(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramWideIO>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
drams.emplace_back(new DramLPDDR4(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramLPDDR4>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(new DramLPDDR5(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramLPDDR5>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::WideIO2)
drams.emplace_back(new DramWideIO2(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramWideIO2>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::HBM2)
drams.emplace_back(new DramHBM2(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramHBM2>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::GDDR5)
drams.emplace_back(new DramGDDR5(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramGDDR5>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::GDDR5X)
drams.emplace_back(new DramGDDR5X(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramGDDR5X>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::GDDR6)
drams.emplace_back(new DramGDDR6(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramGDDR6>(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::STTMRAM)
drams.emplace_back(new DramSTTMRAM(("dram" + std::to_string(i)).c_str()));
drams.emplace_back(std::make_unique<DramSTTMRAM>(("dram" + std::to_string(i)).c_str()));
if (config.checkTLM2Protocol)
controllersTlmCheckers.push_back(new tlm_utils::tlm2_base_protocol_checker<>(("TlmCheckerController" + std::to_string(i)).c_str()));
controllersTlmCheckers.push_back(std::make_unique<tlm_utils::tlm2_base_protocol_checker<>>
(("TlmCheckerController" + std::to_string(i)).c_str()));
}
}

2
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -73,7 +73,7 @@ protected:
void end_of_simulation() override;
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*> controllersTlmCheckers;
std::vector<std::unique_ptr<tlm_utils::tlm2_base_protocol_checker<>>> controllersTlmCheckers;
// TODO: Each DRAM has a reorder buffer (check this!)
std::unique_ptr<ReorderBuffer> reorder;

36
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
View File

@@ -34,6 +34,8 @@
* Derek Christ
*/
#include <memory>
#include "DRAMSysRecordable.h"
#include "../controller/ControllerRecordable.h"
#include "dram/DramRecordable.h"
@@ -119,45 +121,45 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
// Create arbiter
if (config.arbiter == Configuration::Arbiter::Simple)
arbiter = std::unique_ptr<Arbiter>(new ArbiterSimple("arbiter", configuration.addressMapping));
arbiter = std::make_unique<ArbiterSimple>("arbiter", configuration.addressMapping);
else if (config.arbiter == Configuration::Arbiter::Fifo)
arbiter = std::unique_ptr<Arbiter>(new ArbiterFifo("arbiter", configuration.addressMapping));
arbiter = std::make_unique<ArbiterFifo>("arbiter", configuration.addressMapping);
else if (config.arbiter == Configuration::Arbiter::Reorder)
arbiter = std::unique_ptr<Arbiter>(new ArbiterReorder("arbiter", configuration.addressMapping));
arbiter = std::make_unique<ArbiterReorder>("arbiter", configuration.addressMapping);
// Create controllers and DRAMs
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
controllers.emplace_back(new ControllerRecordable(("controller" + std::to_string(i)).c_str(), tlmRecorders[i]));
controllers.emplace_back(std::make_unique<ControllerRecordable>(("controller" + std::to_string(i)).c_str(), tlmRecorders[i]));
if (memoryType == MemSpec::MemoryType::DDR3)
drams.emplace_back(new DramRecordable<DramDDR3>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramDDR3>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::DDR4)
drams.emplace_back(new DramRecordable<DramDDR4>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramDDR4>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(new DramRecordable<DramDDR5>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramDDR5>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO)
drams.emplace_back(new DramRecordable<DramWideIO>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
drams.emplace_back(new DramRecordable<DramLPDDR4>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR4>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(new DramRecordable<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR5>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO2)
drams.emplace_back(new DramRecordable<DramWideIO2>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO2>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::HBM2)
drams.emplace_back(new DramRecordable<DramHBM2>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramHBM2>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR5)
drams.emplace_back(new DramRecordable<DramGDDR5>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR5>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR5X)
drams.emplace_back(new DramRecordable<DramGDDR5X>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR5X>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR6)
drams.emplace_back(new DramRecordable<DramGDDR6>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramGDDR6>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::STTMRAM)
drams.emplace_back(new DramRecordable<DramSTTMRAM>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
drams.emplace_back(std::make_unique<DramRecordable<DramSTTMRAM>>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
if (config.checkTLM2Protocol)
controllersTlmCheckers.emplace_back(new tlm_utils::tlm2_base_protocol_checker<>(("TLMCheckerController"
controllersTlmCheckers.emplace_back(std::make_unique<tlm_utils::tlm2_base_protocol_checker<>>(("TLMCheckerController"
+ std::to_string(i)).c_str()));
}
}

7
DRAMSys/simulator/main.cpp
View File

@@ -38,6 +38,7 @@
*/
#include <iostream>
#include <memory>
#include <string>
#include <utility>
#include <vector>
@@ -109,10 +110,10 @@ int sc_main(int argc, char **argv)
#ifdef RECORDING
if (conf.simConfig.databaseRecording.value_or(false))
dramSys = std::unique_ptr<DRAMSys>(new DRAMSysRecordable("DRAMSys", conf));
dramSys = std::make_unique<DRAMSysRecordable>("DRAMSys", conf);
else
#endif
dramSys = std::unique_ptr<DRAMSys>(new DRAMSys("DRAMSys", conf));
dramSys = std::make_unique<DRAMSys>("DRAMSys", conf);
if (!conf.traceSetup.has_value())
SC_REPORT_FATAL("sc_main", "No tracesetup section provided.");
@@ -126,7 +127,7 @@ int sc_main(int argc, char **argv)
if (player->addLengthConverter)
{
std::string converterName("Converter_");
lengthConverters.emplace_back(new LengthConverter(converterName.append(player->name()).c_str(),
lengthConverters.emplace_back(std::make_unique<LengthConverter>(converterName.append(player->name()).c_str(),
Configuration::getInstance().memSpec->maxBytesPerBurst,
Configuration::getInstance().storeMode != Configuration::StoreMode::NoStorage));
player->iSocket.bind(lengthConverters.back()->tSocket);