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Merge branch 'DRAMSys4.0_ctrl' into 'master'

Browse Source 
Version 4.0, road to open sourcing

See merge request ems/astdm/dram.sys!243
This commit is contained in:
Matthias Jung
2020-03-24 15:23:27 +01:00
parent f6072e9d4f 89221c53a7
commit 96f05f18de
283 changed files with 12258 additions and 10773 deletions
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2
.gitignore vendored
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@@ -3,7 +3,7 @@
/dram/debug
/dram/release
/dram/build
*pro.user*
*.user
*.tdb
*.tdb-journal
*.out

8
.gitmodules vendored
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@@ -4,7 +4,13 @@
[submodule "DRAMSys/library/src/common/third_party/DRAMPower"]
path = DRAMSys/library/src/common/third_party/DRAMPower
url = https://github.com/tukl-msd/DRAMPower.git
branch = master
branch = rgr
[submodule "DRAMSys/unitTests/googletest"]
path = DRAMSys/unitTests/googletest
url = https://github.com/google/googletest.git
[submodule "DRAMSys/library/src/common/third_party/systemc"]
path = DRAMSys/library/src/common/third_party/systemc
url = https://github.com/accellera-official/systemc.git
[submodule "DRAMSys/library/src/common/third_party/sqlite-amalgamation"]
path = DRAMSys/library/src/common/third_party/sqlite-amalgamation
url = https://github.com/azadkuh/sqlite-amalgamation.git

45
utils/getqwt.sh → DRAMSys/CMakeLists.txt Executable file → Normal file
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@@ -1,6 +1,4 @@
#!/usr/bin/env bash
# Copyright (c) 2017, University of Kaiserslautern
# Copyright (c) 2020, Fraunhofer IESE
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -30,16 +28,33 @@
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Author: Éder F. Zulian
# Author: Matthias Jung
cmake_minimum_required(VERSION 3.10)
# Project Name:
project(DRAMSys)
# Configuration:
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows")
# Add sqlite3 Dependency:
set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature")
set(BUILD_ENABLE_RTREE ON)
add_subdirectory(library/src/common/third_party/sqlite-amalgamation)
# Add DRAMSysLibrary:
add_subdirectory(library)
# Add TraceAnalyzer:
add_subdirectory(traceAnalyzer)
# Build:
add_executable(DRAMSys simulator/main.cpp)
target_include_directories(DRAMSys
PUBLIC library/src/simulation/
PUBLIC library/src/common/third_party/sqlite-amalgamation/
)
target_link_libraries(DRAMSys sqlite3::sqlite3 systemc DRAMSysLibrary)
dest=$HOME/qwt-6.1
svn checkout svn://svn.code.sf.net/p/qwt/code/branches/qwt-6.1 $dest
cd $dest
svn up -r 2481
if [[ $(hostname -s) =~ ^head[0-9]+$ ]] || [[ $(hostname -s) =~ ^node[0-9]+$ ]]; then
# Elwetritsch cluster - heads or nodes
module load qt/5.5
fi
qmake qwt.pro
make
echo "Done."

58
DRAMSys/DRAMSys.pro
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@@ -1,58 +0,0 @@
TEMPLATE = subdirs
thermalsim = $$(THERMALSIM)
isEmpty(thermalsim) {
thermalsim = false
}
$$eval(thermalsim) {
message(Thermal Simulation Feature Enabled)
} else {
message(Thermal Simulation Feature Disabled)
}
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
message(Coverage check ENABLED)
} else {
message(Coverage check DISABLED)
}
systemc_home = $$(SYSTEMC_HOME)
isEmpty(systemc_home) {
systemc_home = /opt/systemc
}
message(SystemC home is $${systemc_home})
SUBDIRS += library
SUBDIRS += unitTests
SUBDIRS += simulator
SUBDIRS += traceAnalyzer
library.subdir = library
unitTests.subdir = unitTests
simulator.subdir = simulator
traceAnalyzer.subdir = traceAnalyzer
# Check if gem5 is installed:
gem5 = $$(GEM5)
isEmpty(gem5) {
message(GEM5 environment variable not found)
message(Gem5 Simulation Disabled)
} else {
message(Gem5 Simulation Feature Enabled)
message(Gem5 home is $${gem5})
DEFINES += DRAMSYS_GEM5
SUBDIRS += gem5
gem5.subdir = gem5
gem5.depends = library simulator
}
# Define Build Order
simulator.depends = library
# Additional Files:
# tests folder (DRAMSys/tests)
include(tests/tests.pri)
DISTFILES += ../README.md

146
DRAMSys/library/CMakeLists.txt Normal file
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@@ -0,0 +1,146 @@
# Copyright (c) 2020, Fraunhofer IESE
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Author: Matthias Jung
cmake_minimum_required(VERSION 3.10)
# Project Name
project(DRAMSysLibrary)
# Add DRAMPower:
add_subdirectory(src/common/third_party/DRAMPower)
# Add SystemC:
set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs")
add_subdirectory(src/common/third_party/systemc)
# Configuration:
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
include_directories(
src/simulation
src/simulation/dram
src/controller
src/controller/checker
src/controller/cmdmux
src/controller/powerdown
src/controller/refresh
src/controller/scheduler
src/common
src/common/third_party/DRAMPower/src
src/configuration
src/configuration/memspec
src/error
src/error/ECC
)
add_library(DRAMSysLibrary
src/common/third_party/tinyxml2/tinyxml2.cpp
src/common/TlmRecorder.cpp
src/common/DebugManager.cpp
src/configuration/Configuration.cpp
src/simulation/MemoryManager.cpp
src/simulation/TemperatureController.cpp
src/configuration/ConfigurationLoader.cpp
src/controller/Command.cpp
src/error/errormodel.cpp
src/simulation/TracePlayer.cpp
src/simulation/TraceSetup.cpp
src/simulation/DRAMSys.cpp
src/simulation/Setup.cpp
src/error/ECC/Bit.cpp
src/error/ECC/ECC.cpp
src/error/ECC/Word.cpp
src/error/eccbaseclass.cpp
src/error/ecchamming.cpp
src/common/AddressDecoder.cpp
src/simulation/dram/Dram.cpp
src/simulation/Arbiter.cpp
src/common/CongenAddressDecoder.cpp
src/common/XmlAddressDecoder.cpp
src/common/timingCalculations.cpp
src/common/dramExtensions.cpp
src/common/utils.cpp
src/simulation/dram/DramDDR3.cpp
src/simulation/dram/DramDDR4.cpp
src/simulation/dram/DramRecordable.cpp
src/simulation/dram/DramWideIO.cpp
src/configuration/memspec/MemSpec.cpp
src/controller/BankMachine.cpp
src/controller/Controller.cpp
src/controller/scheduler/SchedulerFifo.cpp
src/controller/scheduler/SchedulerFrFcfs.cpp
src/controller/cmdmux/CmdMuxStrict.cpp
src/controller/cmdmux/CmdMuxOldest.cpp
src/controller/ControllerRecordable.cpp
src/controller/checker/CheckerDDR3.cpp
src/controller/refresh/RefreshManager.cpp
src/controller/refresh/RefreshManagerDummy.cpp
src/controller/refresh/RefreshManagerBankwise.cpp
src/controller/checker/CheckerWideIO.cpp
src/configuration/memspec/MemSpecDDR3.cpp
src/configuration/memspec/MemSpecDDR4.cpp
src/configuration/memspec/MemSpecWideIO.cpp
src/configuration/memspec/MemSpecLPDDR4.cpp
src/controller/checker/CheckerDDR4.cpp
src/simulation/dram/DramLPDDR4.cpp
src/controller/checker/CheckerLPDDR4.cpp
src/configuration/memspec/MemSpecWideIO2.cpp
src/simulation/dram/DramWideIO2.cpp
src/controller/checker/CheckerWideIO2.cpp
src/configuration/memspec/MemSpecHBM2.cpp
src/simulation/dram/DramHBM2.cpp
src/controller/checker/CheckerHBM2.cpp
src/configuration/memspec/MemSpecGDDR5.cpp
src/configuration/memspec/MemSpecGDDR5X.cpp
src/configuration/memspec/MemSpecGDDR6.cpp
src/controller/checker/CheckerGDDR5.cpp
src/controller/checker/CheckerGDDR5X.cpp
src/controller/checker/CheckerGDDR6.cpp
src/simulation/dram/DramGDDR5.cpp
src/simulation/dram/DramGDDR5X.cpp
src/simulation/dram/DramGDDR6.cpp
src/controller/powerdown/PowerDownManagerStaggered.cpp
src/controller/powerdown/PowerDownManagerDummy.cpp
)
# Build:
target_include_directories(DRAMSysLibrary
PUBLIC src/common/third_party/DRAMPower/src
PUBLIC src/common/third_party/sqlite-amalgamation/
)
target_link_libraries(DRAMSysLibrary
SystemC::systemc
sqlite3::sqlite3
DRAMPower
)

275
DRAMSys/library/library.pro
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@@ -1,275 +0,0 @@
TARGET = DRAMSys
TEMPLATE = lib
CONFIG += staticlib
CONFIG += console
CONFIG -= app_bundle
CONFIG -= qt
system(cd ../../DRAMSys/library/src/common/third_party/DRAMPower; make src/libdrampower.a;)
systemc_home = $$(SYSTEMC_HOME)
isEmpty(systemc_home) {
systemc_home = /opt/systemc
}
# Check if PCT's SystemC should be used?
dramsys_pct = $$(DRAMSYS_PCT)
isEmpty(dramsys_pct) {
dramsys_pct = false
}
$$eval(dramsys_pct) {
# PCT:
message(PCT Simulation Feature Enabled)
systemc_home = /software/Synopsys_CoWare/K-2015.12-SP1/SLS/linux/common
INCLUDEPATH += $${systemc_home}/include/tlm
DEFINES += DRAMSYS_PCT
}
# Check if gem5 should be used
gem5 = $$(GEM5)
isEmpty(gem5) {
message(GEM5 environment variable not found)
message(Gem5 Simulation Disabled)
} else {
message(Gem5 Simulation Feature Enabled)
message(Gem5 home is $${gem5})
DEFINES += DRAMSYS_GEM5
}
message(SystemC home is $${systemc_home})
systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)
isEmpty(systemc_target_arch) {
systemc_target_arch = linux64
}
message(SystemC target architecture is $${systemc_target_arch})
INCLUDEPATH += $${systemc_home}/include
INCLUDEPATH += src/common/third_party/DRAMPower/src
INCLUDEPATH += src/common/third_party/DRAMPower/src/libdrampower
INCLUDEPATH += src/common/third_party/json/include
DEFINES += TIXML_USE_STL
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
coverage_check = true
message(Coverage check ENABLED)
} else {
coverage_check = false
message(Coverage check DISABLED)
}
unix:!macx {
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0
QMAKE_LFLAGS += -lgcov --coverage
}
}
macx: {
CONFIG += c++11
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
QMAKE_MACOSX_DEPLOYMENT_TARGET=10.14
$$eval(coverage_check) {
QMAKE_CXXFLAGS += --coverage
QMAKE_LFLAGS += --coverage
}
}
QMAKE_CXXFLAGS += -isystem $${systemc_home}/include
SOURCES += \
src/common/third_party/tinyxml2/tinyxml2.cpp \
src/common/TlmRecorder.cpp \
src/common/DebugManager.cpp \
src/controller/core/configuration/Configuration.cpp \
src/controller/core/powerdown/PowerDownManagerTimeout.cpp \
src/controller/core/powerdown/PowerDownManagerBankwise.cpp \
src/controller/core/powerdown/PowerDownManager.cpp \
src/controller/scheduler/FrFcfs.cpp \
src/controller/scheduler/Fifo.cpp \
src/controller/scheduler/SMS.cpp \
src/controller/core/refresh/RefreshManagerBankwise.cpp \
src/controller/core/refresh/RefreshManager.cpp \
src/controller/core/refresh/RGR.cpp \
src/controller/core/scheduling/checker/WriteChecker.cpp \
src/controller/core/scheduling/checker/RefreshChecker.cpp \
src/controller/core/scheduling/checker/ReadChecker.cpp \
src/controller/core/scheduling/checker/PrechargeChecker.cpp \
src/controller/core/scheduling/checker/PrechargeAllChecker.cpp \
src/controller/core/scheduling/checker/PowerDownChecker.cpp \
src/controller/core/scheduling/checker/ActivateChecker.cpp \
src/controller/core/scheduling/checker/PreBChecker.cpp \
src/controller/core/scheduling/checker/ActBChecker.cpp \
src/controller/core/scheduling/ScheduledCommand.cpp \
src/controller/core/Slots.cpp \
src/controller/core/ControllerCore.cpp \
src/simulation/MemoryManager.cpp \
src/simulation/TemperatureController.cpp \
src/controller/core/configuration/ConfigurationLoader.cpp \
src/controller/core/powerdown/NoPowerDown.cpp \
src/controller/Command.cpp \
src/controller/ControllerState.cpp \
src/controller/RowBufferStates.cpp \
src/controller/scheduler/IScheduler.cpp \
src/controller/scheduler/FifoStrict.cpp \
src/error/errormodel.cpp \
src/controller/Controller.cpp \
src/simulation/TracePlayer.cpp \
src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp \
src/simulation/TraceSetup.cpp \
src/simulation/DRAMSys.cpp \
src/simulation/Setup.cpp \
src/error/ECC/Bit.cpp \
src/error/ECC/ECC.cpp \
src/error/ECC/Word.cpp \
src/error/eccbaseclass.cpp \
src/error/ecchamming.cpp \
src/controller/scheduler/FrFcfsRp.cpp \
src/controller/scheduler/FrFcfsGrp.cpp \
src/controller/scheduler/Grp.cpp \
src/controller/RecordableController.cpp \
src/common/AddressDecoder.cpp \
src/simulation/Dram.cpp \
src/simulation/RecordableDram.cpp \
src/simulation/Arbiter.cpp \
src/common/CongenAddressDecoder.cpp \
src/common/XmlAddressDecoder.cpp \
src/controller/core/timingCalculations.cpp \
src/common/dramExtensions.cpp \
src/common/utils.cpp \
src/simulation/DramDDR3.cpp \
src/simulation/DramDDR4.cpp \
src/simulation/DramRecordable.cpp \
src/simulation/DramWideIO.cpp
HEADERS += \
src/common/third_party/tinyxml2/tinyxml2.h \
src/common/TlmRecorder.h \
src/common/tlm2_base_protocol_checker.h \
src/common/protocol.h \
src/common/DebugManager.h \
src/controller/core/configuration/Configuration.h \
src/controller/core/powerdown/PowerDownManagerTimeout.h \
src/controller/core/powerdown/PowerDownManagerBankwise.h \
src/controller/core/powerdown/PowerDownManager.h \
src/controller/scheduler/FrFcfs.h \
src/controller/scheduler/Fifo.h \
src/controller/scheduler/SMS.h \
src/controller/Controller.h \
src/controller/core/refresh/RefreshManagerBankwise.h \
src/controller/core/refresh/RefreshManager.h \
src/controller/core/refresh/IRefreshManager.h \
src/controller/core/refresh/RGR.h \
src/controller/core/scheduling/checker/WriteChecker.h \
src/controller/core/scheduling/checker/RefreshChecker.h \
src/controller/core/scheduling/checker/ReadChecker.h \
src/controller/core/scheduling/checker/PrechargeChecker.h \
src/controller/core/scheduling/checker/PrechargeAllChecker.h \
src/controller/core/scheduling/checker/PowerDownChecker.h \
src/controller/core/scheduling/checker/ICommandChecker.h \
src/controller/core/scheduling/checker/ActivateChecker.h \
src/controller/core/scheduling/checker/PreBChecker.h \
src/controller/core/scheduling/checker/ActBChecker.h \
src/controller/core/scheduling/ScheduledCommand.h \
src/controller/core/Slots.h \
src/controller/core/ControllerCore.h \
src/simulation/TracePlayer.h \
src/simulation/MemoryManager.h \
src/simulation/Dram.h \
src/simulation/Arbiter.h \
src/common/libDRAMPower.h \
src/simulation/ReorderBuffer.h \
src/controller/core/configuration/MemSpec.h \
src/simulation/StlPlayer.h \
src/simulation/TracePlayerListener.h \
src/simulation/TraceGenerator.h \
src/simulation/TemperatureController.h \
src/controller/core/powerdown/NoPowerDown.h \
src/controller/Command.h \
src/controller/RowBufferStates.h \
src/controller/ControllerState.h \
src/controller/core/powerdown/IPowerDownManager.h \
src/controller/scheduler/IScheduler.h \
src/controller/scheduler/FifoStrict.h \
src/controller/IController.h \
src/controller/core/configuration/ConfigurationLoader.h \
src/error/errormodel.h \
src/simulation/ExampleInitiator.h \
src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h \
src/simulation/TraceSetup.h \
src/simulation/DRAMSys.h \
src/simulation/Setup.h \
src/error/ECC/Bit.h \
src/error/ECC/ECC.h \
src/error/ECC/Word.h \
src/error/eccbaseclass.h \
src/error/ecchamming.h \
src/controller/scheduler/FrFcfsRp.h \
src/controller/scheduler/FrFcfsGrp.h \
src/controller/scheduler/Grp.h \
src/simulation/IArbiter.h \
src/simulation/SimpleArbiter.h \
src/controller/RecordableController.h \
src/simulation/RecordableDram.h \
src/common/AddressDecoder.h \
src/common/CongenAddressDecoder.h \
src/common/XmlAddressDecoder.h \
src/controller/core/timingCalculations.h \
src/common/dramExtensions.h \
src/common/utils.h \
src/controller/core/configuration/TemperatureSimConfig.h \
src/simulation/DramDDR3.h \
src/simulation/DramDDR4.h \
src/simulation/DramRecordable.h \
src/simulation/DramWideIO.h
#src/common/third_party/json/include/nlohmann/json.hpp \
thermalsim = $$(THERMALSIM)
isEmpty(thermalsim) {
thermalsim = false
}
$$eval(thermalsim) {
message(Thermal Simulation Feature Enabled)
libthreed_ice_home = $$(LIBTHREED_ICE_HOME)
isEmpty(libthreed_ice_home) {
libthreed_ice_home = /opt/3D-ICE/
}
message(LIBTHREED_ICE_HOME path is $${libthreed_ice_home})
libsuperlu_home = $$(LIBSUPERLU_HOME)
isEmpty(libsuperlu_home) {
libsuperlu_home = /opt/SuperLU_4.3/
}
message(LIBSUPERLU_HOME path is $${libthreed_ice_home})
LIBS += -L$${libthreed_ice_home}/lib -lthreed-ice-2.2.4
LIBS += -L$${libsuperlu_home}/lib -lsuperlu_4.3
LIBS += -lblas
message(Libraries: $${LIBS})
INCLUDEPATH += $${libthreed_ice_home}/include
INCLUDEPATH += $${libsuperlu_home}/SRC
INCLUDEPATH += $${systemc_home}/include
message(Include paths: $${INCLUDEPATH})
QMAKE_CXXFLAGS += -DTHERMALSIM
message(Compiler flags: $${QMAKE_CXXFLAGS})
} else {
message(Thermal Simulation Feature Disabled)
}
# Additional Files:
include(resources/resources.pri)
DISTFILES += ../DRAMSys.astylerc

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml
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@@ -1,5 +1,4 @@
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml
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@@ -14,7 +14,6 @@ B B B | R R R R R R R R R R R R R R | C C C C C C C C C C |
-->
<addressmapping>
<channel from="128" to="128" /> <!-- workaround to have only one channel -->
<bank from="24" to="26" />
<row from="10" to="23" />
<column from="0" to="9" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml
View File

@@ -26,7 +26,6 @@
-->
<addressmapping>
<channel from="128" to="128" /> <!-- workaround to have only one channel -->
<bank from="28" to="30" />
<row from="13" to="27" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml
View File

@@ -26,7 +26,6 @@
-->
<addressmapping>
<channel from="128" to="128" /> <!-- workaround to have only one channel -->
<row from="16" to="30" />
<bank from="13" to="15" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
View File

@@ -16,7 +16,6 @@ B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml
View File

@@ -16,7 +16,6 @@ R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<row from="16" to="29" />
<bank from="13" to="15" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml
View File

@@ -16,7 +16,6 @@ B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<bank from="28" to="30" />
<row from="13" to="27" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml
View File

@@ -16,7 +16,6 @@ R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<row from="16" to="30" />
<bank from="13" to="15" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml
View File

@@ -1,5 +1,4 @@
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<bank from="26" to="28" />
<row from="13" to="25" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml
View File

@@ -1,5 +1,4 @@
<addressmapping>
<channel from="128" to="128" /> <!-- only one channel -->
<row from="16" to="28" />
<bank from="13" to="15" />
<column from="3" to="12" />

7
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<bankgroup from="30" to="31" />
<bank from="28" to="29" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

9
DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml Normal file
View File

@@ -0,0 +1,9 @@
<addressmapping>
<!--channel from="30" to="32" /-->
<rank from="29" to="29" /> <!-- 2 pseudo channels -->
<bankgroup from="27" to="28" />
<bank from="25" to="26" />
<row from="10" to="24" />
<column from="3" to="9" />
<bytes from="0" to="2" />
</addressmapping>

6
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml Normal file
View File

@@ -0,0 +1,6 @@
<addressmapping>
<bank from="27" to="29" />
<row from="11" to="26" />
<column from="1" to="10" />
<bytes from="0" to="0" />
</addressmapping>

6
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml Normal file
View File

@@ -0,0 +1,6 @@
<addressmapping>
<row from="14" to="29" />
<bank from="11" to="13" />
<column from="1" to="10" />
<bytes from="0" to="0" />
</addressmapping>

25
DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml Normal file
View File

@@ -0,0 +1,25 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<rank from="30" to="31" />
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml Normal file
View File

@@ -0,0 +1,11 @@
<!-- Bank Row Column -->
<addressmapping>
<channel from="28" to="29" />
<bank from="25" to="27" />
<row from="12" to="24" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml Normal file
View File

@@ -0,0 +1,11 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="28" to="29" />
<row from="15" to="27" />
<bank from="12" to="14" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="27" to="28" />
<bank from="25" to="26" />
<row from="11" to="24" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="27" to="28" />
<row from="13" to="26" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="25" to="26" />
<bank from="23" to="24" />
<row from="11" to="22" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="25" to="26" />
<row from="13" to="24" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="28" to="29" />
<bank from="26" to="27" />
<row from="11" to="25" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="28" to="29" />
<row from="13" to="27" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="29" to="30" />
<bank from="27" to="28" />
<row from="12" to="26" />
<column from="4" to="11" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="29" to="30" />
<row from="14" to="28" />
<bank from="12" to="13" />
<column from="4" to="11" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="26" to="27" />
<bank from="24" to="25" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml Normal file
View File

@@ -0,0 +1,7 @@
<addressmapping>
<channel from="26" to="27" />
<row from="13" to="25" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

1
DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml
View File

@@ -11,7 +11,6 @@
-->
<addressmapping>
<channel from="128" to="128" /> <!-- workaround to have only one channel -->
<bank from="30" to="32" />
<row from="13" to="29" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml
View File

@@ -1,5 +1,4 @@
<addressmapping>
<channel from="128" to="128" />
<row from="16" to="32" />
<bank from="13" to="15" />
<column from="3" to="12" />

1
DRAMSys/library/resources/configs/amconfigs/rgram.xml
View File

@@ -1,5 +1,4 @@
<addressmapping>
<channel from="128" to="128" />
<bank from="30" to="32" />
<row from="13" to="29" />
<column from="3" to="12" />

7
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

8
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml
View File

@@ -1,5 +1,6 @@
<mcconfig>
<OpenPagePolicy value="1" />
<AdaptivePagePolicy value="0" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
@@ -34,13 +35,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

8
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
View File

@@ -1,5 +1,6 @@
<mcconfig>
<OpenPagePolicy value="1" />
<AdaptivePagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
@@ -34,13 +35,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

16
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml
View File

@@ -17,22 +17,6 @@
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<ControllerCoreRGRRowInc value="1"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRGRtRASBInClkCycles value="34"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="8"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="8"/>
<ControllerCoreRGRtRPBInClkCycles value="18"/>
<ControllerCoreRGRtRCBInClkCycles value="52"/>
<ControllerCoreRGRtFAWBInClkCycles value="37"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: yes, 0: no (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/grp.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/par_bs.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml
View File

@@ -33,13 +33,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

7
DRAMSys/library/resources/configs/mcconfigs/sms.xml
View File

@@ -34,13 +34,6 @@
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<!-- Timings for RGR normal or optimal values -->
<ControllerCoreRGRtRASBInClkCycles value="22"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="15"/>
<ControllerCoreRGRtRCBInClkCycles value="37"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Postpone, pull-in -->
<ControllerCoreRefEnablePostpone value="0"/>
<ControllerCoreRefEnablePullIn value="0"/>

49
DRAMSys/library/resources/configs/memspecs/HBM2.xml Normal file
View File

@@ -0,0 +1,49 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--8GiB, 8 channels, 1GiB per channel-->
<memspec>
<parameter id="memoryId" type="string" value="https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder" />
<parameter id="memoryType" type="string" value="HBM2" />
<memarchitecturespec>
<parameter id="width" type="uint" value="64" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="2" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1000" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="RC" type="uint" value="42" />
<parameter id="RAS" type="uint" value="28" />
<parameter id="RCDRD" type="uint" value="12" />
<parameter id="RCDWR" type="uint" value="6" />
<parameter id="RRDL" type="uint" value="6" />
<parameter id="RRDS" type="uint" value="4" />
<parameter id="FAW" type="uint" value="16" />
<parameter id="RTP" type="uint" value="5" />
<parameter id="RP" type="uint" value="14" />
<parameter id="RL" type="uint" value="17" />
<parameter id="WL" type="uint" value="7" />
<parameter id="PL" type="uint" value="0" />
<parameter id="WR" type="uint" value="14" />
<parameter id="CCDL" type="uint" value="3" />
<parameter id="CCDS" type="uint" value="2" />
<parameter id="WTRL" type="uint" value="9" />
<parameter id="WTRS" type="uint" value="4" />
<parameter id="RTW" type="uint" value="18" />
<parameter id="XP" type="uint" value="8" />
<parameter id="CKE" type="uint" value="8" />
<parameter id="XS" type="uint" value="216" />
<parameter id="RFC" type="uint" value="220" />
<parameter id="RFCSB" type="uint" value="96" />
<parameter id="RREFD" type="uint" value="8" />
<parameter id="REFI" type="uint" value="3900" />
<parameter id="REFISB" type="uint" value="244" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml Normal file
View File

@@ -0,0 +1,64 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 2/4, REFM 1/0.5/0.25-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-200_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="4096" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="200" />
<parameter id="RC" type="uint" value="12" />
<parameter id="RCD" type="uint" value="4" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="4" />
<parameter id="RFC" type="uint" value="18" />
<parameter id="RAS" type="uint" value="9" />
<parameter id="WL" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="AC" type="uint" value="1" />
<parameter id="WR" type="uint" value="3" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" />
<parameter id="REFI" type="uint" value="3120" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD_R" type="uint" value="2" />
<parameter id="CCD_W" type="uint" value="1" />
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 2/4, REFM 1/0.5/0.25-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-266_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="4096" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="266" />
<parameter id="RC" type="uint" value="16" />
<parameter id="RCD" type="uint" value="5" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="5" />
<parameter id="RFC" type="uint" value="24" />
<parameter id="RAS" type="uint" value="12" />
<parameter id="WL" type="uint" value="1" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="AC" type="uint" value="1" />
<parameter id="WR" type="uint" value="4" />
<parameter id="XP" type="uint" value="3" />
<parameter id="XS" type="uint" value="27" />
<parameter id="REFI" type="uint" value="4160" />
<parameter id="TAW" type="uint" value="14" />
<parameter id="RRD" type="uint" value="3" />
<parameter id="CCD_R" type="uint" value="2" />
<parameter id="CCD_W" type="uint" value="1" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="4" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="6.06" />
<parameter id="idd02" type="double" value="21.82" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.16" />
<parameter id="idd2n2" type="double" value="4.76" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.58" />
<parameter id="idd3n2" type="double" value="7.24" />
<parameter id="idd4r" type="double" value="1.82" />
<parameter id="idd4r2" type="double" value="111.22" />
<parameter id="idd4w" type="double" value="1.82" />
<parameter id="idd4w2" type="double" value="78.0" />
<parameter id="idd5" type="double" value="14.48" />
<parameter id="idd52" type="double" value="48.34" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-1866_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="933" />
<parameter id="REFI" type="uint" value="7280" />
<parameter id="RFC" type="uint" value="243" />
<parameter id="RFC2" type="uint" value="150" />
<parameter id="RFC4" type="uint" value="103" />
<parameter id="RL" type="uint" value="13" />
<parameter id="WL" type="uint" value="12" />
<parameter id="CL" type="uint" value="13" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="13" />
<parameter id="RAS" type="uint" value="32" />
<parameter id="RCD" type="uint" value="13" />
<parameter id="RC" type="uint" value="45" />
<parameter id="FAW" type="uint" value="22" />
<parameter id="RTP" type="uint" value="8" />
<parameter id="WR" type="uint" value="14" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="5" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="5" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="7" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="255" />
<parameter id="XS" type="uint" value="252" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="56.25" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="33.75" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="39.5" />
<parameter id="idd4r" type="double" value="157.5" />
<parameter id="idd4w" type="double" value="135.0" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

64
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1200" />
<parameter id="REFI" type="uint" value="9360" />
<parameter id="RFC" type="uint" value="312" />
<parameter id="RFC2" type="uint" value="192" />
<parameter id="RFC4" type="uint" value="132" />
<parameter id="RL" type="uint" value="16" />
<parameter id="WL" type="uint" value="16" />
<parameter id="CL" type="uint" value="16" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="16" />
<parameter id="RAS" type="uint" value="39" />
<parameter id="RCD" type="uint" value="16" />
<parameter id="RC" type="uint" value="55" />
<parameter id="FAW" type="uint" value="26" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WR" type="uint" value="18" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="6" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="6" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="9" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="325" />
<parameter id="XS" type="uint" value="324" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.75" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="38.25" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="44.0" />
<parameter id="idd4r" type="double" value="184.5" />
<parameter id="idd4w" type="double" value="168.75" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

43
DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 4/8, DBI disabled/enabled, REFM 0.25/0.5/1/2/4-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_4x64_2Gb_WIDEIO2-400_64bit" />
<parameter id="memoryType" type="string" value="WIDEIO2" />
<memarchitecturespec>
<parameter id="width" type="uint" value="64" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="512" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RCD" type="uint" value="8" />
<parameter id="RPPB" type="uint" value="8" />
<parameter id="RPAB" type="uint" value="9" />
<parameter id="RAS" type="uint" value="17" />
<parameter id="RCPB" type="uint" value="24" />
<parameter id="RCAB" type="uint" value="26" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="RRD" type="uint" value="4" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="1560" />
<parameter id="RFCAB" type="uint" value="72" />
<parameter id="RFCPB" type="uint" value="36" />
<parameter id="CKESR" type="uint" value="6" />
<parameter id="XS" type="uint" value="76" />
<parameter id="XP" type="uint" value="3" />
<parameter id="RL" type="uint" value="7" />
<parameter id="WL" type="uint" value="5" />
<parameter id="WR" type="uint" value="8" />
<parameter id="RTP" type="uint" value="3" />
<parameter id="CCD" type="uint" value="2" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

43
DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--BL 4/8, DBI disabled/enabled, REFM 0.25/0.5/1/2/4-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_4x64_2Gb_WIDEIO2-533_64bit" />
<parameter id="memoryType" type="string" value="WIDEIO2" />
<memarchitecturespec>
<parameter id="width" type="uint" value="64" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="512" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="533" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RPPB" type="uint" value="10" />
<parameter id="RPAB" type="uint" value="12" />
<parameter id="RAS" type="uint" value="23" />
<parameter id="RCPB" type="uint" value="32" />
<parameter id="RCAB" type="uint" value="34" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="RRD" type="uint" value="6" />
<parameter id="FAW" type="uint" value="32" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="REFM" type="uint" value="1" />
<parameter id="REFI" type="uint" value="2078" />
<parameter id="RFCAB" type="uint" value="96" />
<parameter id="RFCPB" type="uint" value="48" />
<parameter id="CKESR" type="uint" value="8" />
<parameter id="XS" type="uint" value="102" />
<parameter id="XP" type="uint" value="4" />
<parameter id="RL" type="uint" value="9" />
<parameter id="WL" type="uint" value="7" />
<parameter id="WR" type="uint" value="11" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="CCD" type="uint" value="2" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

50
DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<!--Single channel device with 8Gb, Set A WL-->
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_8Gb_LPDDR4-3200_16bit" />
<parameter id="memoryType" type="string" value="LPDDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="16" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfRows" type="uint" value="65536" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="16" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1600" />
<parameter id="REFI" type="uint" value="6246" />
<parameter id="REFIPB" type="uint" value="780" />
<parameter id="RFCAB" type="uint" value="448" />
<parameter id="RFCPB" type="uint" value="224" />
<parameter id="RPAB" type="uint" value="34" />
<parameter id="RPPB" type="uint" value="29" />
<parameter id="PPD" type="uint" value="4" />
<parameter id="RAS" type="uint" value="68" />
<parameter id="RCD" type="uint" value="29" />
<parameter id="FAW" type="uint" value="64" />
<parameter id="RRD" type="uint" value="16" />
<parameter id="CCD" type="uint" value="8" />
<parameter id="RL" type="uint" value="28" />
<parameter id="RPST" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="6" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WL" type="uint" value="14" />
<parameter id="DQSS" type="uint" value="1" />
<parameter id="DQS2DQ" type="uint" value="2" />
<!--parameter id="nWR" type="uint" value="30" /-->
<parameter id="WR" type="uint" value="29" />
<parameter id="WPRE" type="uint" value="2" />
<parameter id="WTR" type="uint" value="16" />
<parameter id="XP" type="uint" value="12" />
<parameter id="SR" type="uint" value="24" />
<parameter id="XSR" type="uint" value="460" />
<parameter id="ESCKE" type="uint" value="3" />
<parameter id="CKE" type="uint" value="12" />
<parameter id="CMDCKE" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<!-- to be completed -->
</mempowerspec>
</memspec>

55
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-800_8bit_G" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="16384" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="400" />
<parameter id="RC" type="uint" value="20" /> <!-- 50 ns -->
<parameter id="RCD" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RL" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RP" type="uint" value="5" /> <!-- 12.5 ns -->
<parameter id="RFC" type="uint" value="44" /> <!-- 110 ns for 1Gb -->
<parameter id="RAS" type="uint" value="15" /> <!-- 37.5 ns -->
<parameter id="WL" type="uint" value="5" /> <!-- jedec 5 clk cycles -->
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" /> <!-- 0.4 ns -->
<parameter id="RTP" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="WR" type="uint" value="6" /> <!-- 15 ns -->
<parameter id="XP" type="uint" value="3" /> <!-- 3 clk cycles -->
<parameter id="XPDLL" type="uint" value="10" /> <!-- 10 clk cycles -->
<parameter id="XS" type="uint" value="48" /> <!-- 110ns + 10ns -->
<parameter id="XSDLL" type="uint" value="512" /> <!-- 512 clk cycles ns -->
<parameter id="REFI" type="uint" value="3120" /> <!-- 78 000 ns -->
<parameter id="CL" type="uint" value="5" /> <!-- jedec 5 clk cycles -->
<parameter id="FAW" type="uint" value="16" /> <!-- 40 ns -->
<parameter id="RRD" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="CCD" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="WTR" type="uint" value="4" /> <!-- 4 clk cycles -->
<parameter id="CKE" type="uint" value="3" /> <!-- 3 clk cycles -->
<parameter id="CKESR" type="uint" value="4" /> <!-- 4 clk cycles -->
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.0" />
<parameter id="idd2p0" type="double" value="12.0" />
<parameter id="idd2p1" type="double" value="25.0" />
<parameter id="idd2n" type="double" value="35.0" />
<parameter id="idd3p0" type="double" value="30.0" />
<parameter id="idd3p1" type="double" value="30.0" />
<parameter id="idd3n" type="double" value="40.0" />
<parameter id="idd4w" type="double" value="110.0" />
<parameter id="idd4r" type="double" value="105.0" />
<parameter id="idd5" type="double" value="160.0" />
<parameter id="idd6" type="double" value="8.0" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>

98
DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml Normal file
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_6Gb_LPDDR3-3200_16bit_A" />
<parameter id="memoryType" type="string" value="LPDDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="16" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="49152" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="16" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1600" />
<parameter id="REFIAB" type="uint" value="6246" />
<parameter id="REFIPB" type="uint" value="780" />
<parameter id="RFCAB" type="uint" value="448" />
<parameter id="RFCPB" type="uint" value="224" />
<parameter id="RL" type="uint" value="28" />
<parameter id="WL" type="uint" value="14" />
<parameter id="CL" type="uint" value="12" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RPAB" type="uint" value="34" />
<parameter id="RPPB" type="uint" value="29" />
<parameter id="PPD" type="uint" value="4" />
<parameter id="RAS" type="uint" value="68" />
<parameter id="RCD" type="uint" value="29" />
<parameter id="RC" type="uint" value="97" />
<parameter id="FAW" type="uint" value="64" />
<parameter id="RRD" type="uint" value="16" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WR" type="uint" value="29" />
<parameter id="CCD" type="uint" value="8" />
<parameter id="CCDMW" type="uint" value="32" />
<parameter id="WTR" type="uint" value="16" />
<parameter id="DQSCK" type="uint" value="3" />
<parameter id="XP" type="uint" value="12" />
<parameter id="XS" type="uint" value="458" />
<parameter id="ESCKE" type="uint" value="24" />
<parameter id="CKE" type="uint" value="12" />
<parameter id="CKESR" type="uint" value="24" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="3.5" />
<parameter id="idd02" type="double" value="45.0" />
<parameter id="idd0ql" type="double" value="0.75" />
<parameter id="idd2p" type="double" value="1.2" />
<parameter id="idd2p2" type="double" value="3.0" />
<parameter id="idd2pQ" type="double" value="0.75" />
<parameter id="idd2ps" type="double" value="1.2" />
<parameter id="idd2ps2" type="double" value="3.0" />
<parameter id="idd2psq" type="double" value="0.75" />
<parameter id="idd2n" type="double" value="2.0" />
<parameter id="idd2n2" type="double" value="27.0" />
<parameter id="idd2nQ" type="double" value="0.75" />
<parameter id="idd2ns" type="double" value="2.0" />
<parameter id="idd2ns2" type="double" value="23.0" />
<parameter id="idd2nsq" type="double" value="0.75" />
<parameter id="idd3p" type="double" value="1.2" />
<parameter id="idd3p2" type="double" value="9.0" />
<parameter id="idd3pQ" type="double" value="0.75" />
<parameter id="idd3ps" type="double" value="1.2" />
<parameter id="idd3ps2" type="double" value="9.0" />
<parameter id="idd3psq" type="double" value="0.75" />
<parameter id="idd3n" type="double" value="2.25" />
<parameter id="idd3n2" type="double" value="30.0" />
<parameter id="idd3nQ" type="double" value="0.75" />
<parameter id="idd3ns" type="double" value="2.25" />
<parameter id="idd3ns2" type="double" value="30.0" />
<parameter id="idd3nsq" type="double" value="0.75" />
<parameter id="idd4r" type="double" value="2.25" />
<parameter id="idd4r2" type="double" value="275.0" />
<parameter id="idd4rq" type="double" value="150.0" />
<parameter id="idd4w" type="double" value="2.25.0" />
<parameter id="idd4w2" type="double" value="210.0" />
<parameter id="idd4wq" type="double" value="55.0" />
<!-- refresh after every trfc -->
<parameter id="idd5" type="double" value="10.0" />
<parameter id="idd52" type="double" value="90.0" />
<parameter id="idd5q" type="double" value="0.75" />
<!-- ref once in every trefi -->
<parameter id="idd5ab" type="double" value="2.5" />
<parameter id="idd5ab2" type="double" value="30.0" />
<parameter id="idd5abq" type="double" value="0.75" />
<!-- perbank ref, ref once in every trefi/8 -->
<parameter id="idd5b" type="double" value="2.5" />
<parameter id="idd5b2" type="double" value="30.0" />
<parameter id="idd5bq" type="double" value="0.75" />
<parameter id="idd6" type="double" value="0.3" />
<parameter id="idd62" type="double" value="0.5" />
<parameter id="idd6q" type="double" value="0.1" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.1" />
<parameter id="vddq" type="double" value="1.1" />
</mempowerspec>
</memspec>

55
DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml Normal file
View File

@@ -0,0 +1,55 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-1600_8bit_G" />
<parameter id="memoryType" type="string" value="DDR3" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfRanks" type="uint" value="4" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="16384" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="800" />
<parameter id="RC" type="uint" value="38" />
<parameter id="RCD" type="uint" value="10" />
<parameter id="RL" type="uint" value="10" />
<parameter id="RP" type="uint" value="10" />
<parameter id="RFC" type="uint" value="88" />
<parameter id="RAS" type="uint" value="28" />
<parameter id="WL" type="uint" value="8" />
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="0" />
<parameter id="RTP" type="uint" value="6" />
<parameter id="WR" type="uint" value="12" />
<parameter id="XP" type="uint" value="6" />
<parameter id="XPDLL" type="uint" value="20" />
<parameter id="XS" type="uint" value="96" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="REFI" type="uint" value="6240" />
<parameter id="CL" type="uint" value="10" />
<parameter id="FAW" type="uint" value="24" />
<parameter id="RRD" type="uint" value="5" />
<parameter id="CCD" type="uint" value="4" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="4" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="70.0" />
<parameter id="idd2p0" type="double" value="12.0" />
<parameter id="idd2p1" type="double" value="30.0" />
<parameter id="idd2n" type="double" value="45.0" />
<parameter id="idd3p0" type="double" value="35.0" />
<parameter id="idd3p1" type="double" value="35.0" />
<parameter id="idd3n" type="double" value="45.0" />
<parameter id="idd4w" type="double" value="145.0" />
<parameter id="idd4r" type="double" value="140.0" />
<parameter id="idd5" type="double" value="170.0" />
<parameter id="idd6" type="double" value="8.0" />
<parameter id="vdd" type="double" value="1.5" />
</mempowerspec>
</memspec>

4
DRAMSys/library/resources/configs/simulator/ddr3.xml
View File

@@ -2,8 +2,8 @@
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>

29
DRAMSys/library/resources/configs/simulator/ddr4.xml Normal file
View File

@@ -0,0 +1,29 @@
<simconfig>
<SimulationName value="ddr4" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

29
DRAMSys/library/resources/configs/simulator/hbm2.xml Normal file
View File

@@ -0,0 +1,29 @@
<simconfig>
<SimulationName value="hbm2" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

29
DRAMSys/library/resources/configs/simulator/lpddr4.xml Normal file
View File

@@ -0,0 +1,29 @@
<simconfig>
<SimulationName value="lpddr4" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

23
DRAMSys/library/resources/scripts/createTraceDB.sql
View File

@@ -1,5 +1,6 @@
DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS CommandLengths;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
@@ -17,6 +18,7 @@ CREATE TABLE Phases(
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfRanks INTEGER,
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
@@ -29,6 +31,24 @@ CREATE TABLE GeneralInfo(
ControllerThread INTEGER
);
CREATE TABLE CommandLengths(
ACT INTEGER,
PRE INTEGER,
PREA INTEGER,
RD INTEGER,
RDA INTEGER,
WR INTEGER,
WRA INTEGER,
REFA INTEGER,
REFB INTEGER,
PDEA INTEGER,
PDXA INTEGER,
PDEP INTEGER,
PDXP INTEGER,
SREFEN INTEGER,
SREFEX INTEGER
);
CREATE TABLE Power(
time DOUBLE,
AveragePower DOUBLE
@@ -58,8 +78,9 @@ CREATE TABLE Transactions(
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TBank INTEGER,
TRank INTEGER,
TBankgroup INTEGER,
TBank INTEGER,
TRow INTEGER,
TColumn INTEGER,
DataStrobeBegin INTEGER,

25
DRAMSys/library/resources/simulations/ddr4-example.xml Normal file
View File

@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr4-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr4.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="JEDEC_4Gb_DDR4-1866_8bit_A.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

25
DRAMSys/library/resources/simulations/hbm2-example.xml Normal file
View File

@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="hbm2-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="hbm2.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="HBM2.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_hbm2_8Gb_pc_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="1000">ddr3_example.stl</device>
</tracesetup>
</simulation>

25
DRAMSys/library/resources/simulations/lpddr4-example.xml Normal file
View File

@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="lpddr4-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="lpddr4.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="JEDEC_8Gb_LPDDR4-3200_16bit.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_lpddr4_8Gbx16_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

25
DRAMSys/library/resources/simulations/ranktest.xml Normal file
View File

@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ranktest"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="memspec_ranktest.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ranktest.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ranktest.stl</device>
</tracesetup>
</simulation>

5
DRAMSys/library/src/common/AddressDecoder.cpp
View File

@@ -60,8 +60,3 @@ void AddressDecoder::createInstance(Type t)
break;
}
}
AddressDecoder::AddressDecoder()
{
}

17
DRAMSys/library/src/common/AddressDecoder.h
View File

@@ -71,7 +71,7 @@ public:
};
protected:
AddressDecoder();
AddressDecoder() {}
static AddressDecoder *m_pInstance;
public:
@@ -80,12 +80,21 @@ public:
virtual void setConfiguration(std::string url) = 0;
virtual DecodedAddress decodeAddress(sc_dt::uint64 addr) = 0;
virtual sc_dt::uint64 encodeAddress(DecodedAddress n) = 0;
virtual DecodedAddress decodeAddress(uint64_t addr) = 0;
virtual uint64_t encodeAddress(DecodedAddress n) = 0;
virtual void print() = 0;
std::map<std::string, unsigned int> amount;
struct Amount
{
unsigned channel = 1;
unsigned rank = 1;
unsigned bankgroup = 1;
unsigned bank = 1;
unsigned row = 1;
unsigned column = 1;
unsigned bytes = 1;
} amount;
};
#endif // ADDRESSDECODER_H

16
DRAMSys/library/src/common/CongenAddressDecoder.cpp
View File

@@ -188,14 +188,14 @@ void CongenAddressDecoder::setConfiguration(std::string url)
}
// Fill the amount map. This is copied from xmlAddressDecoder without further investigation
amount["channel"] = 1;
amount["bank"] = pow(2.0, m_vBankBits.size());
amount["row"] = pow(2.0, m_vRowBits.size());
amount["column"] = pow(2.0, m_vColumnBits.size());
amount["bytes"] = pow(2.0, m_nByteBits);
amount.channel = 1;
amount.bank = pow(2.0, m_vBankBits.size());
amount.row = pow(2.0, m_vRowBits.size());
amount.column = pow(2.0, m_vColumnBits.size());
amount.bytes = pow(2.0, m_nByteBits);
}
DecodedAddress CongenAddressDecoder::decodeAddress(sc_dt::uint64 addr)
DecodedAddress CongenAddressDecoder::decodeAddress(uint64_t addr)
{
DecodedAddress result;
@@ -251,9 +251,9 @@ DecodedAddress CongenAddressDecoder::decodeAddress(sc_dt::uint64 addr)
return result;
}
sc_dt::uint64 CongenAddressDecoder::encodeAddress(DecodedAddress n)
uint64_t CongenAddressDecoder::encodeAddress(DecodedAddress n)
{
sc_dt::uint64 address = 0;
uint64_t address = 0;
// Bank
// it->first: position of the target bit in the DecodedAddress struct field

4
DRAMSys/library/src/common/CongenAddressDecoder.h
View File

@@ -101,8 +101,8 @@ public:
virtual void setConfiguration(std::string url);
virtual DecodedAddress decodeAddress(sc_dt::uint64 addr);
virtual sc_dt::uint64 encodeAddress(DecodedAddress n);
virtual DecodedAddress decodeAddress(uint64_t addr);
virtual uint64_t encodeAddress(DecodedAddress n);
static bool testConfigFile(std::string url);

8
DRAMSys/library/src/common/DebugManager.cpp
View File

@@ -35,7 +35,10 @@
*/
#include "DebugManager.h"
#include "../controller/core/configuration/Configuration.h"
#ifdef DEBUGGING
#include "../configuration/Configuration.h"
using namespace std;
void DebugManager::printDebugMessage(string sender, string message)
@@ -65,7 +68,7 @@ void DebugManager::openDebugFile(string filename)
}
DebugManager::DebugManager() :
writeToConsole(true), writeToFile(true)
writeToConsole(false), writeToFile(false)
{
}
@@ -76,3 +79,4 @@ DebugManager::~DebugManager()
debugFile.close();
}
}
#endif

8
DRAMSys/library/src/common/DebugManager.h
View File

@@ -37,6 +37,13 @@
#ifndef DEBUGMANAGER_H
#define DEBUGMANAGER_H
//#define DEBUGGING
#ifndef DEBUGGING
#define PRINTDEBUGMESSAGE(sender, message) {}
#else
#define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message)
#include <systemc.h>
#include <string>
#include <set>
@@ -62,5 +69,6 @@ private:
ofstream debugFile;
};
#endif
#endif // DEBUGMANAGER_H

181
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -43,15 +43,13 @@
#include "protocol.h"
#include "dramExtensions.h"
#include "XmlAddressDecoder.h"
#include "../controller/core/configuration/Configuration.h"
#include "../controller/Controller.h"
#include "../configuration/Configuration.h"
using namespace std;
using namespace tlm;
TlmRecorder::TlmRecorder(sc_module_name /*name*/, string uri,
string dbname) : sqlScriptURI(uri), dbName(dbname), totalNumTransactions(1),
simulationTimeCoveredByRecording(SC_ZERO_TIME)
TlmRecorder::TlmRecorder(std::string name, std::string uri, std::string dbname) :
name(name), sqlScriptURI(uri), dbName(dbname),
totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME)
{
recordedData.reserve(transactionCommitRate);
setUpTransactionTerminatingPhases();
@@ -66,7 +64,7 @@ TlmRecorder::TlmRecorder(sc_module_name /*name*/, string uri,
createTables(TlmRecorder::sqlScriptURI);
prepareSqlStatements();
printDebugMessage("Starting new database transaction");
PRINTDEBUGMESSAGE(name, "Starting new database transaction");
}
TlmRecorder::~TlmRecorder()
@@ -79,6 +77,7 @@ TlmRecorder::~TlmRecorder()
sqlite3_finalize(insertPhaseStatement);
sqlite3_finalize(updatePhaseStatement);
sqlite3_finalize(insertGeneralInfoStatement);
sqlite3_finalize(insertCommandLengthsStatement);
sqlite3_finalize(insertDebugMessageStatement);
sqlite3_finalize(updateDataStrobeStatement);
sqlite3_finalize(insertPowerStatement);
@@ -91,15 +90,15 @@ void TlmRecorder::recordPower(double timeInSeconds, double averagePower)
executeSqlStatement(insertPowerStatement);
}
void TlmRecorder::recordPhase(tlm::tlm_generic_payload &trans,
tlm::tlm_phase phase, sc_time time)
void TlmRecorder::recordPhase(tlm_generic_payload &trans,
tlm_phase phase, sc_time time)
{
if (currentTransactionsInSystem.count(&trans) == 0)
introduceTransactionSystem(trans);
string phaseName = phaseNameToString(phase);
string phaseBeginPrefix = "BEGIN_";
string phaseEndPrefix = "END_";
std::string phaseName = phaseNameToString(phase);
std::string phaseBeginPrefix = "BEGIN_";
std::string phaseEndPrefix = "END_";
if (phaseName.find(phaseBeginPrefix) != string::npos) {
phaseName.erase(0, phaseBeginPrefix.length());
@@ -111,7 +110,7 @@ void TlmRecorder::recordPhase(tlm::tlm_generic_payload &trans,
currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time);
}
bool phaseTerminatesTransaction = count(transactionTerminatingPhases.begin(),
bool phaseTerminatesTransaction = std::count(transactionTerminatingPhases.begin(),
transactionTerminatingPhases.end(), phase) == 1;
if (phaseTerminatesTransaction)
removeTransactionFromSystem(trans);
@@ -121,7 +120,7 @@ void TlmRecorder::recordPhase(tlm::tlm_generic_payload &trans,
void TlmRecorder::updateDataStrobe(const sc_time &begin, const sc_time &end,
tlm::tlm_generic_payload &trans)
tlm_generic_payload &trans)
{
assert(currentTransactionsInSystem.count(&trans) != 0);
currentTransactionsInSystem[&trans].timeOnDataStrobe.start = begin;
@@ -137,7 +136,7 @@ void TlmRecorder::recordDebugMessage(std::string message, sc_time time)
// ------------- internal -----------------------
void TlmRecorder::introduceTransactionSystem(tlm::tlm_generic_payload &trans)
void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans)
{
unsigned int id = totalNumTransactions++;
currentTransactionsInSystem[&trans].id = id;
@@ -148,30 +147,28 @@ void TlmRecorder::introduceTransactionSystem(tlm::tlm_generic_payload &trans)
currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(
trans);
if (DramExtension::getExtension(trans).getThread().ID() ==
Controller::ControllerThreadId())
if (DramExtension::getExtension(trans).getThread().ID() == UINT_MAX)
currentTransactionsInSystem[&trans].timeOfGeneration = SC_ZERO_TIME;
else
currentTransactionsInSystem[&trans].timeOfGeneration =
GenerationExtension::getExtension(&trans).TimeOfGeneration();
printDebugMessage("New transaction #" + to_string(id) + " generation time " +
PRINTDEBUGMESSAGE(name, "New transaction #" + to_string(id) + " generation time " +
currentTransactionsInSystem[&trans].timeOfGeneration.to_string());
if (id % transactionCommitRate == 0) {
printDebugMessage(
"Committing transactions " + to_string(id - transactionCommitRate + 1) + " - "
+ to_string(id));
PRINTDEBUGMESSAGE(name, "Committing transactions " +
to_string(id - transactionCommitRate + 1) + " - " + to_string(id));
commitRecordedDataToDB();
}
}
void TlmRecorder::removeTransactionFromSystem(tlm::tlm_generic_payload &trans)
void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans)
{
assert(currentTransactionsInSystem.count(&trans) != 0);
printDebugMessage("Removing transaction #" + to_string(
currentTransactionsInSystem[&trans].id));
PRINTDEBUGMESSAGE(name, "Removing transaction #" +
to_string(currentTransactionsInSystem[&trans].id));
Transaction &recordingData = currentTransactionsInSystem[&trans];
recordedData.push_back(recordingData);
@@ -199,16 +196,16 @@ void TlmRecorder::commitRecordedDataToDB()
}
void TlmRecorder::Transaction::insertPhase(string name, sc_time begin)
void TlmRecorder::Transaction::insertPhase(std::string name, sc_time begin)
{
recordedPhases.push_back(Phase(name, begin));
}
void TlmRecorder::Transaction::setPhaseEnd(string name, sc_time end)
void TlmRecorder::Transaction::setPhaseEnd(std::string name, sc_time end)
{
// Find the latest recorder phase for that transaction with a matching name and update it
// Note: Transaction have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) only update the latest
// one that has been recorder
// Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD)
// only update the latest one that has been recorded
for (int i = recordedPhases.size() - 1; i >= 0; i--) {
Phase &data = recordedPhases[i];
if (data.name == name) {
@@ -223,7 +220,7 @@ void TlmRecorder::Transaction::setPhaseEnd(string name, sc_time end)
void TlmRecorder::openDB(std::string name)
{
ifstream f(name.c_str());
std::ifstream f(name.c_str());
if (f.good()) {
if (remove(name.c_str()) != 0) {
SC_REPORT_FATAL("TlmRecorder", "Error deleting file" );
@@ -237,49 +234,46 @@ void TlmRecorder::openDB(std::string name)
}
void TlmRecorder::createTables(string pathToURI)
void TlmRecorder::createTables(std::string pathToURI)
{
string initial = loadTextFileContents(pathToURI);
std::string initial = loadTextFileContents(pathToURI);
executeSqlCommand(initial);
}
void TlmRecorder::setUpTransactionTerminatingPhases()
{
transactionTerminatingPhases.push_back(tlm::END_RESP);
transactionTerminatingPhases.push_back(END_RESP);
// Refresh All
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_REFA));
// Refresh Bank
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_REFB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
(END_ACTB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
(END_PREB));
// Phases for Power Down
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_PDNA));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_PDNP));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_SREF));
// Phases for Power Down Bankwise
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_PDNAB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_PDNPB));
transactionTerminatingPhases.push_back(static_cast<const tlm::tlm_phase>
transactionTerminatingPhases.push_back(static_cast<const tlm_phase>
(END_SREFB));
}
void TlmRecorder::prepareSqlStatements()
{
insertTransactionString =
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:bank,:bankgroup,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)";
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank,"
":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)";
insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)";
updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id";
updateDataStrobeString =
@@ -290,8 +284,12 @@ void TlmRecorder::prepareSqlStatements()
updatePhaseString =
"UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name";
insertGeneralInfoString =
"INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,clk,UnitOfTime,MCconfig,Memspec,Traces, WindowSize, FlexibleRefresh, MaxRefBurst, ControllerThread) VALUES"
"(:numberOfTransactions,:end,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,:traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread)";
"INSERT INTO GeneralInfo VALUES"
"(:numberOfTransactions,:end,:numberOfRanks,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,"
":traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread)";
insertCommandLengthsString =
"INSERT INTO CommandLengths VALUES"
"(:ACT, :PRE, :PREA, :RD, :RDA, :WR, :WRA, :REFA, :REFB, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)";
insertDebugMessageString =
"INSERT INTO DebugMessages (Time,Message) Values (:time,:message)";
insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)";
@@ -306,12 +304,14 @@ void TlmRecorder::prepareSqlStatements()
&updateDataStrobeStatement, 0);
sqlite3_prepare_v2(db, insertGeneralInfoString.c_str(), -1,
&insertGeneralInfoStatement, 0);
sqlite3_prepare_v2(db, insertCommandLengthsString.c_str(), -1,
&insertCommandLengthsStatement, 0);
sqlite3_prepare_v2(db, insertDebugMessageString.c_str(), -1,
&insertDebugMessageStatement, 0);
sqlite3_prepare_v2(db, insertPowerString.c_str(), -1, &insertPowerStatement, 0);
}
void TlmRecorder::insertDebugMessageInDB(string message, const sc_time &time)
void TlmRecorder::insertDebugMessageInDB(std::string message, const sc_time &time)
{
sqlite3_bind_int64(insertDebugMessageStatement, 1, time.value());
sqlite3_bind_text(insertDebugMessageStatement, 2, message.c_str(),
@@ -325,37 +325,61 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 2,
simulationTimeCoveredByRecording.value());
sqlite3_bind_int(insertGeneralInfoStatement, 3,
Configuration::getInstance().memSpec->NumberOfBanks);
Configuration::getInstance().memSpec->NumberOfRanks);
sqlite3_bind_int(insertGeneralInfoStatement, 4,
Configuration::getInstance().memSpec->NumberOfBanks);
sqlite3_bind_int(insertGeneralInfoStatement, 5,
Configuration::getInstance().memSpec->clk.value());
sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 6, mcconfig.c_str(),
sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 7, mcconfig.c_str(),
mcconfig.length(), NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 7, memspec.c_str(),
sqlite3_bind_text(insertGeneralInfoStatement, 8, memspec.c_str(),
memspec.length(), NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 8, traces.c_str(),
sqlite3_bind_text(insertGeneralInfoStatement, 9, traces.c_str(),
traces.length(), NULL);
if (!Configuration::getInstance().EnableWindowing)
sqlite3_bind_int64(insertGeneralInfoStatement, 9, 0);
sqlite3_bind_int64(insertGeneralInfoStatement, 10, 0);
else
sqlite3_bind_int64(insertGeneralInfoStatement, 9,
sqlite3_bind_int64(insertGeneralInfoStatement, 10,
(Configuration::getInstance().memSpec->clk *
Configuration::getInstance().WindowSize).value());
if (Configuration::getInstance().ControllerCoreRefEnablePostpone
|| Configuration::getInstance().ControllerCoreRefEnablePullIn) {
sqlite3_bind_int(insertGeneralInfoStatement, 10, 1);
sqlite3_bind_int(insertGeneralInfoStatement, 11,
sqlite3_bind_int(insertGeneralInfoStatement, 11, 1);
sqlite3_bind_int(insertGeneralInfoStatement, 12,
std::max(Configuration::getInstance().ControllerCoreRefMaxPulledIn,
Configuration::getInstance().ControllerCoreRefMaxPostponed));
} else {
sqlite3_bind_int(insertGeneralInfoStatement, 10, 0);
sqlite3_bind_int(insertGeneralInfoStatement, 11, 0);
sqlite3_bind_int(insertGeneralInfoStatement, 12, 0);
}
sqlite3_bind_int(insertGeneralInfoStatement, 12,
Controller::ControllerThreadId()); ;
sqlite3_bind_int(insertGeneralInfoStatement, 13, UINT_MAX);
executeSqlStatement(insertGeneralInfoStatement);
}
void TlmRecorder::insertCommandLengths()
{
MemSpec *memSpec = Configuration::getInstance().memSpec;
sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLength[Command::ACT]);
sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLength[Command::PRE]);
sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLength[Command::PREA]);
sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLength[Command::RD]);
sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLength[Command::RDA]);
sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLength[Command::WR]);
sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLength[Command::WRA]);
sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLength[Command::REFA]);
sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLength[Command::REFB]);
sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLength[Command::PDEA]);
sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLength[Command::PDXA]);
sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLength[Command::PDEP]);
sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLength[Command::PDXP]);
sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLength[Command::SREFEN]);
sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLength[Command::SREFEX]);
executeSqlStatement(insertCommandLengthsStatement);
}
void TlmRecorder::insertTransactionInDB(Transaction &recordingData)
{
sqlite3_bind_int(insertTransactionStatement, 1, recordingData.id);
@@ -367,20 +391,22 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData)
sqlite3_bind_int(insertTransactionStatement, 6,
recordingData.dramExtension.getChannel().ID());
sqlite3_bind_int(insertTransactionStatement, 7,
recordingData.dramExtension.getBank().ID());
recordingData.dramExtension.getRank().ID());
sqlite3_bind_int(insertTransactionStatement, 8,
recordingData.dramExtension.getBankGroup().ID());
sqlite3_bind_int(insertTransactionStatement, 9,
recordingData.dramExtension.getRow().ID());
recordingData.dramExtension.getBank().ID());
sqlite3_bind_int(insertTransactionStatement, 10,
recordingData.dramExtension.getRow().ID());
sqlite3_bind_int(insertTransactionStatement, 11,
recordingData.dramExtension.getColumn().ID());
sqlite3_bind_int64(insertTransactionStatement, 11,
recordingData.timeOnDataStrobe.start.value());
sqlite3_bind_int64(insertTransactionStatement, 12,
recordingData.timeOnDataStrobe.end.value());
recordingData.timeOnDataStrobe.start.value());
sqlite3_bind_int64(insertTransactionStatement, 13,
recordingData.timeOnDataStrobe.end.value());
sqlite3_bind_int64(insertTransactionStatement, 14,
recordingData.timeOfGeneration.value());
sqlite3_bind_text(insertTransactionStatement, 14,
sqlite3_bind_text(insertTransactionStatement, 15,
recordingData.cmd.c_str(), recordingData.cmd.length(), NULL);
executeSqlStatement(insertTransactionStatement);
@@ -395,7 +421,7 @@ void TlmRecorder::insertRangeInDB(unsigned int id, const sc_time &begin,
sqlite3_bind_int64(insertRangeStatement, 3, end.value());
executeSqlStatement(insertRangeStatement);
}
void TlmRecorder::insertPhaseInDB(string phaseName, const sc_time &begin,
void TlmRecorder::insertPhaseInDB(std::string phaseName, const sc_time &begin,
const sc_time &end,
unsigned int transactionID)
{
@@ -418,9 +444,9 @@ void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement)
sqlite3_reset(statement);
}
void TlmRecorder::executeSqlCommand(string command)
void TlmRecorder::executeSqlCommand(std::string command)
{
printDebugMessage("Creating database by running provided sql script");
PRINTDEBUGMESSAGE(name, "Creating database by running provided sql script");
char *errMsg = 0;
int rc = sqlite3_exec(db, command.c_str(), NULL, 0, &errMsg);
@@ -429,22 +455,17 @@ void TlmRecorder::executeSqlCommand(string command)
sqlite3_free(errMsg);
}
printDebugMessage("Database created successfully");
}
void TlmRecorder::printDebugMessage(std::string message)
{
DebugManager::getInstance().printDebugMessage(this->name(), message);
PRINTDEBUGMESSAGE(name, "Database created successfully");
}
void TlmRecorder::closeConnection()
{
commitRecordedDataToDB();
insertGeneralInfo();
printDebugMessage(
"Number of transactions written to DB: " + std::to_string(
totalNumTransactions - 1));
printDebugMessage("tlmPhaseRecorder:\tEnd Recording");
insertCommandLengths();
PRINTDEBUGMESSAGE(name, "Number of transactions written to DB: "
+ std::to_string(totalNumTransactions - 1));
PRINTDEBUGMESSAGE(name, "tlmPhaseRecorder:\tEnd Recording");
sqlite3_close(db);
db = NULL;
}

54
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -53,40 +53,39 @@
#include "DebugManager.h"
#include "utils.h"
using namespace std;
using namespace tlm;
class TlmRecorder : public sc_module
class TlmRecorder
{
public:
std::string sqlScriptURI;
std::string dbName;
TlmRecorder(sc_module_name /*name*/, string uri, string dbname);
TlmRecorder(std::string name, std::string uri, std::string dbname);
~TlmRecorder();
void recordMCconfig(string mcconfig)
void recordMCconfig(std::string mcconfig)
{
this->mcconfig = mcconfig;
}
void recordMemspec(string memspec)
void recordMemspec(std::string memspec)
{
this->memspec = memspec;
}
void recordTracenames(string traces)
void recordTracenames(std::string traces)
{
this->traces = traces;
}
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase,
void recordPhase(tlm_generic_payload &trans, tlm_phase phase,
sc_time time);
void recordPower(double timeInSeconds, double averagePower);
void recordDebugMessage(std::string message, sc_time time);
void updateDataStrobe(const sc_time &begin, const sc_time &end,
tlm::tlm_generic_payload &trans);
tlm_generic_payload &trans);
void closeConnection();
private:
struct Transaction {
Transaction() {}
Transaction(unsigned int id): id(id) {}
@@ -100,16 +99,18 @@ private:
TimeInterval timeOnDataStrobe;
struct Phase {
Phase(string name, sc_time begin): name(name), interval(begin, SC_ZERO_TIME) {}
string name;
Phase(std::string name, sc_time begin): name(name), interval(begin, SC_ZERO_TIME) {}
std::string name;
TimeInterval interval;
};
std::vector<Phase> recordedPhases;
void insertPhase(string name, sc_time begin);
void setPhaseEnd(string name, sc_time end);
void insertPhase(std::string name, sc_time begin);
void setPhaseEnd(std::string name, sc_time end);
};
std::string name;
std::string mcconfig, memspec, traces;
void prepareSqlStatements();
@@ -120,35 +121,34 @@ private:
void createTables(std::string pathToURI);
void setUpTransactionTerminatingPhases();
void introduceTransactionSystem(tlm::tlm_generic_payload &trans);
void removeTransactionFromSystem(tlm::tlm_generic_payload &trans);
void introduceTransactionSystem(tlm_generic_payload &trans);
void removeTransactionFromSystem(tlm_generic_payload &trans);
void commitRecordedDataToDB();
void insertGeneralInfo();
void insertCommandLengths();
void insertTransactionInDB(Transaction &recordingData);
void insertRangeInDB(unsigned int id, const sc_time &begin, const sc_time &end);
void insertPhaseInDB(string phaseName, const sc_time &begin, const sc_time &end,
void insertPhaseInDB(std::string phaseName, const sc_time &begin, const sc_time &end,
unsigned int transactionID);
void insertDebugMessageInDB(string message, const sc_time &time);
void printDebugMessage(std::string message);
void insertDebugMessageInDB(std::string message, const sc_time &time);
static const int transactionCommitRate = 1000;
vector<Transaction> recordedData;
map<tlm::tlm_generic_payload *, Transaction> currentTransactionsInSystem;
std::vector<Transaction> recordedData;
std::map<tlm::tlm_generic_payload *, Transaction> currentTransactionsInSystem;
unsigned int totalNumTransactions;
sc_time simulationTimeCoveredByRecording;
std::vector<tlm::tlm_phase> transactionTerminatingPhases;
std::vector<tlm_phase> transactionTerminatingPhases;
sqlite3 *db = NULL;
sqlite3_stmt *insertTransactionStatement, *insertRangeStatement,
*updateRangeStatement,
*insertPhaseStatement, *updatePhaseStatement, *insertGeneralInfoStatement,
*updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement,
*insertGeneralInfoStatement, *insertCommandLengthsStatement,
*insertDebugMessageStatement, *updateDataStrobeStatement, *insertPowerStatement;
std::string insertTransactionString, insertRangeString, updateRangeString,
insertPhaseString, updatePhaseString, insertGeneralInfoString,
insertDebugMessageString, updateDataStrobeString, insertPowerString;
std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString,
updatePhaseString, insertGeneralInfoString, insertCommandLengthsString,
insertDebugMessageString, updateDataStrobeString, insertPowerString;
};
#endif // TLMRECORDER_H

134
DRAMSys/library/src/common/XmlAddressDecoder.cpp
View File

@@ -39,9 +39,8 @@
#include <systemc.h>
#include "utils.h"
#include "bitset"
#include "../controller/core/configuration/Configuration.h"
#include "../configuration/Configuration.h"
using namespace std;
using namespace tinyxml2;
XmlAddressDecoder::XmlAddressDecoder()
@@ -56,51 +55,110 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI)
tinyxml2::XMLElement *addressMap = doc.RootElement();
string xmlNodeName(addressMap->Name());
if ( xmlNodeName != "addressmapping") {
if (xmlNodeName != "addressmapping")
reportFatal("AddressDecorder", "addressmap node expected");
}
for (XMLElement *child = addressMap->FirstChildElement();
child != NULL;
child = child->NextSiblingElement()) {
int from;
int to;
child != NULL; child = child->NextSiblingElement())
{
unsigned from;
unsigned to;
child->QueryAttribute("from", &from);
child->QueryAttribute("to", &to);
shifts[child->Name()] = from;
masks[child->Name()] = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount[child->Name()] = pow(2.0, to - from + 1.0);
if (std::strcmp(child->Name(), "channel") == 0)
{
shifts.channel = from;
masks.channel = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.channel = pow(2.0, to - from + 1.0);
}
else if (std::strcmp(child->Name(), "rank") == 0)
{
shifts.rank = from;
masks.rank = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.rank = pow(2.0, to - from + 1.0);
}
else if (std::strcmp(child->Name(), "bankgroup") == 0)
{
shifts.bankgroup = from;
masks.bankgroup = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.bankgroup = pow(2.0, to - from + 1.0);
}
else if (std::strcmp(child->Name(), "bank") == 0)
{
shifts.bank = from;
masks.bank = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.bank = pow(2.0, to - from + 1.0);
}
else if (std::strcmp(child->Name(), "row") == 0)
{
shifts.row = from;
masks.row = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.row = pow(2.0, to - from + 1.0);
}
else if (std::strcmp(child->Name(), "column") == 0)
{
shifts.column = from;
masks.column = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.column = pow(2.0, to - from + 1.0);
}
else if (std::strcmp(child->Name(), "bytes") == 0)
{
shifts.bytes = from;
masks.bytes = pow(2.0, to + 1.0) - pow(2.0, from + 0.0);
amount.bytes = pow(2.0, to - from + 1.0);
}
else
SC_REPORT_FATAL("XmlAddressDecoder", ("Unknown field " + std::string(child->Name())).c_str());
}
banksPerGroup = amount.bank;
amount.bank = banksPerGroup * amount.bankgroup * amount.rank;
bankgroupsPerRank = amount.bankgroup;
amount.bankgroup = bankgroupsPerRank * amount.rank;
maximumAddress = amount.bytes * amount.column * amount.row * banksPerGroup * bankgroupsPerRank * amount.rank * amount.channel - 1;
Configuration &config = Configuration::getInstance();
MemSpec *memSpec = config.memSpec;
if (config.NumberOfMemChannels != amount.channel || memSpec->NumberOfRanks != amount.rank
|| memSpec->NumberOfBankGroups != amount.bankgroup || memSpec->NumberOfBanks != amount.bank
|| memSpec->NumberOfRows != amount.row || memSpec->NumberOfColumns != amount.column
|| config.NumberOfDevicesOnDIMM * memSpec->bitWidth != amount.bytes * 8)
SC_REPORT_FATAL("XmlAddressDecoder", "Memspec and addressmapping do not match");
}
DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr)
DecodedAddress XmlAddressDecoder::decodeAddress(uint64_t addr)
{
if (addr > maximumAddress)
SC_REPORT_WARNING("XmlAddressDecoder", ("Address " + std::to_string(addr) + " out of range (maximum address is " + std::to_string(maximumAddress) + ")").c_str());
DecodedAddress result;
result.channel = (addr & masks["channel"]) >> shifts["channel"];
//result.rank = (addr & masks["rank"]) >> shifts["rank"];
//result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"];
result.bank = (addr & masks["bank"]) >> shifts["bank"];
result.bankgroup = result.bank %
Configuration::getInstance().memSpec->NumberOfBankGroups;
result.rank = result.bank % Configuration::getInstance().memSpec->NumberOfRanks;
result.row = (addr & masks["row"]) >> shifts["row"];
result.column = (addr & masks["column"]) >> shifts["column"];
result.bytes = (addr & masks["bytes"]) >> shifts["bytes"];
result.channel = (addr & masks.channel) >> shifts.channel;
result.rank = (addr & masks.rank) >> shifts.rank;
result.bankgroup = ((addr & masks.bankgroup) >> shifts.bankgroup)
+ result.rank * bankgroupsPerRank;
result.bank = ((addr & masks.bank) >> shifts.bank)
+ result.bankgroup * banksPerGroup;
result.row = (addr & masks.row) >> shifts.row;
result.column = (addr & masks.column) >> shifts.column;
result.bytes = (addr & masks.bytes) >> shifts.bytes;
return result;
}
sc_dt::uint64 XmlAddressDecoder::encodeAddress(DecodedAddress n)
uint64_t XmlAddressDecoder::encodeAddress(DecodedAddress n)
{
return n.channel << shifts["channel"] |
n.rank << shifts["rank"] |
n.bankgroup << shifts["bankgroup"] |
n.row << shifts["row"] |
n.bank << shifts["bank"] |
n.column << shifts["column"] |
n.bytes << shifts["bytes"];
return (n.channel << shifts.channel) |
(n.rank << shifts.rank) |
((n.bankgroup % bankgroupsPerRank) << shifts.bankgroup) |
((n.bank % banksPerGroup) << shifts.bank) |
(n.row << shifts.row) |
(n.column << shifts.column) |
(n.bytes << shifts.bytes);
}
bool XmlAddressDecoder::testConfigFile(std::string url)
@@ -117,10 +175,14 @@ bool XmlAddressDecoder::testConfigFile(std::string url)
void XmlAddressDecoder::print()
{
cout << headline << endl;
cout << "Address Mapping:" << endl << endl;
for (auto &pair : masks) {
cout << std::setw(16) << pair.first << ": " << bitset<48>(pair.second) << endl;
}
cout << endl;
std::cout << headline << std::endl;
std::cout << "Address Mapping:" << std::endl << std::endl;
std::cout << " channel: " << std::bitset<64>(masks.channel) << std::endl;
std::cout << " rank: " << std::bitset<64>(masks.rank) << std::endl;
std::cout << " bankgroup: " << std::bitset<64>(masks.bankgroup) << std::endl;
std::cout << " bank: " << std::bitset<64>(masks.bank) << std::endl;
std::cout << " row: " << std::bitset<64>(masks.row) << std::endl;
std::cout << " column: " << std::bitset<64>(masks.column) << std::endl;
std::cout << " bytes: " << std::bitset<64>(masks.bytes) << std::endl;
std::cout << std::endl;
}

32
DRAMSys/library/src/common/XmlAddressDecoder.h
View File

@@ -51,16 +51,40 @@ class XmlAddressDecoder : private AddressDecoder
friend class AddressDecoder;
private:
std::map<std::string, sc_dt::uint64> masks;
std::map<std::string, unsigned int> shifts;
struct Masks
{
uint64_t channel = 0;
uint64_t rank = 0;
uint64_t bankgroup = 0;
uint64_t bank = 0;
uint64_t row = 0;
uint64_t column = 0;
uint64_t bytes = 0;
} masks;
struct Shifts
{
unsigned channel = 0;
unsigned rank = 0;
unsigned bankgroup = 0;
unsigned bank = 0;
unsigned row = 0;
unsigned column = 0;
unsigned bytes = 0;
} shifts;
unsigned banksPerGroup;
unsigned banksPerRank;
unsigned bankgroupsPerRank;
tinyxml2::XMLElement *addressmapping;
uint64_t maximumAddress;
public:
XmlAddressDecoder();
virtual DecodedAddress decodeAddress(sc_dt::uint64 addr);
virtual sc_dt::uint64 encodeAddress(DecodedAddress n);
virtual DecodedAddress decodeAddress(uint64_t addr);
virtual uint64_t encodeAddress(DecodedAddress n);
void setConfiguration(std::string url);

129
DRAMSys/library/src/common/dramExtensions.cpp
View File

@@ -36,33 +36,27 @@
*/
#include "dramExtensions.h"
#include "../controller/core/configuration/Configuration.h"
#include "../configuration/Configuration.h"
#include "map"
#include "utils.h"
using namespace tlm;
DramExtension::DramExtension() :
thread(0), channel(0), bank(0), bankgroup(0), row(0), column(0), burstlength(0)
{
}
thread(0), channel(0), rank(0), bankgroup(0), bank(0),
row(0), column(0), burstlength(0), payloadID(0) {}
DramExtension::DramExtension(const Thread &thread, const Bank &bank,
const BankGroup &bankgroup, const Row &row, const Column &column,
unsigned int burstlength) :
thread(thread), channel(0), bank(bank), bankgroup(bankgroup), row(row),
column(column), burstlength(burstlength)
{
}
DramExtension::DramExtension(const Thread &thread, const Rank &rank, const BankGroup &bankgroup,
const Bank &bank, const Row &row, const Column &column,
unsigned int burstlength, uint64_t payloadID) :
thread(thread), channel(0), rank(rank), bankgroup(bankgroup), bank(bank),
row(row), column(column), burstlength(burstlength), payloadID(payloadID) {}
DramExtension::DramExtension(const Thread &thread, const Channel &channel,
const Bank &bank, const BankGroup &bankgroup, const Row &row,
const Column &column, unsigned int burstlength) :
thread(thread), channel(channel), bank(bank), bankgroup(bankgroup), row(row),
column(column), burstlength(burstlength)
{
}
DramExtension::DramExtension(const Thread &thread, const Channel &channel, const Rank &rank,
const BankGroup &bankgroup, const Bank &bank, const Row &row,
const Column &column, unsigned int burstlength, uint64_t payloadID) :
thread(thread), channel(channel), rank(rank), bankgroup(bankgroup), bank(bank),
row(row), column(column), burstlength(burstlength), payloadID(payloadID) {}
DramExtension &DramExtension::getExtension(const tlm_generic_payload *payload)
{
@@ -78,14 +72,14 @@ DramExtension &DramExtension::getExtension(const tlm_generic_payload &payload)
return DramExtension::getExtension(&payload);
}
Bank DramExtension::getBank(const tlm_generic_payload *payload)
Thread DramExtension::getThread(const tlm_generic_payload *payload)
{
return DramExtension::getExtension(payload).getBank();
return DramExtension::getExtension(payload).getThread();
}
Bank DramExtension::getBank(const tlm_generic_payload &payload)
Thread DramExtension::getThread(const tlm_generic_payload &payload)
{
return DramExtension::getBank(&payload);
return DramExtension::getThread(&payload);
}
Channel DramExtension::getChannel(const tlm_generic_payload *payload)
@@ -98,14 +92,34 @@ Channel DramExtension::getChannel(const tlm_generic_payload &payload)
return DramExtension::getChannel(&payload);
}
Thread DramExtension::getThread(const tlm_generic_payload *payload)
Rank DramExtension::getRank(const tlm_generic_payload *payload)
{
return DramExtension::getExtension(payload).getThread();
return DramExtension::getExtension(payload).getRank();
}
Thread DramExtension::getThread(const tlm_generic_payload &payload)
Rank DramExtension::getRank(const tlm_generic_payload &payload)
{
return DramExtension::getThread(&payload);
return DramExtension::getRank(&payload);
}
BankGroup DramExtension::getBankGroup(const tlm_generic_payload *payload)
{
return DramExtension::getExtension(payload).getBankGroup();
}
BankGroup DramExtension::getBankGroup(const tlm_generic_payload &payload)
{
return DramExtension::getBankGroup(&payload);
}
Bank DramExtension::getBank(const tlm_generic_payload *payload)
{
return DramExtension::getExtension(payload).getBank();
}
Bank DramExtension::getBank(const tlm_generic_payload &payload)
{
return DramExtension::getBank(&payload);
}
Row DramExtension::getRow(const tlm_generic_payload *payload)
@@ -118,18 +132,39 @@ Row DramExtension::getRow(const tlm_generic_payload &payload)
return DramExtension::getRow(&payload);
}
Column DramExtension::getColumn(const tlm_generic_payload *payload)
{
return DramExtension::getExtension(payload).getColumn();
}
Column DramExtension::getColumn(const tlm_generic_payload &payload)
{
return DramExtension::getColumn(&payload);
}
uint64_t DramExtension::getPayloadID(const tlm_generic_payload *payload)
{
return DramExtension::getExtension(payload).getPayloadID();
}
uint64_t DramExtension::getPayloadID(const tlm_generic_payload &payload)
{
return DramExtension::getPayloadID(&payload);
}
tlm_extension_base *DramExtension::clone() const
{
return new DramExtension(thread, bank, bankgroup, row, column, burstlength);
return new DramExtension(thread, channel, rank, bankgroup, bank, row, column, burstlength, payloadID);
}
void DramExtension::copy_from(const tlm_extension_base &ext)
{
const DramExtension &cpyFrom = static_cast<const DramExtension &>(ext);
thread = cpyFrom.thread;
bank = cpyFrom.bank;
channel = cpyFrom.channel;
rank = cpyFrom.rank;
bankgroup = cpyFrom.bankgroup;
bank = cpyFrom.bank;
row = cpyFrom.row;
column = cpyFrom.column;
burstlength = cpyFrom.burstlength;
@@ -145,9 +180,9 @@ Channel DramExtension::getChannel() const
return channel;
}
Bank DramExtension::getBank() const
Rank DramExtension::getRank() const
{
return bank;
return rank;
}
BankGroup DramExtension::getBankGroup() const
@@ -155,6 +190,11 @@ BankGroup DramExtension::getBankGroup() const
return bankgroup;
}
Bank DramExtension::getBank() const
{
return bank;
}
Row DramExtension::getRow() const
{
return row;
@@ -170,6 +210,11 @@ unsigned int DramExtension::getBurstlength() const
return burstlength;
}
uint64_t DramExtension::getPayloadID() const
{
return payloadID;
}
void DramExtension::incrementRow()
{
++row;
@@ -182,14 +227,12 @@ tlm_extension_base *GenerationExtension::clone() const
void GenerationExtension::copy_from(const tlm_extension_base &ext)
{
const GenerationExtension &cpyFrom = static_cast<const GenerationExtension &>
(ext);
const GenerationExtension &cpyFrom = static_cast<const GenerationExtension &>(ext);
timeOfGeneration = cpyFrom.timeOfGeneration;
}
GenerationExtension &GenerationExtension::getExtension(const
tlm::tlm_generic_payload *payload)
GenerationExtension &GenerationExtension::getExtension(const tlm_generic_payload *payload)
{
GenerationExtension *result = NULL;
payload->get_extension(result);
@@ -197,14 +240,12 @@ GenerationExtension &GenerationExtension::getExtension(const
return *result;
}
sc_time GenerationExtension::getTimeOfGeneration(const tlm::tlm_generic_payload
*payload)
sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload *payload)
{
return GenerationExtension::getExtension(payload).TimeOfGeneration();
}
sc_time GenerationExtension::getTimeOfGeneration(const tlm::tlm_generic_payload
&payload)
sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload &payload)
{
return GenerationExtension::getTimeOfGeneration(&payload);
}
@@ -236,6 +277,16 @@ bool operator !=(const Channel &lhs, const Channel &rhs)
return !(lhs == rhs);
}
//RANK
bool operator ==(const Rank &lhs, const Rank &rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Rank &lhs, const Rank &rhs)
{
return !(lhs == rhs);
}
//BANKGROUP
bool operator ==(const BankGroup &lhs, const BankGroup &rhs)

83
DRAMSys/library/src/common/dramExtensions.h
View File

@@ -41,6 +41,8 @@
#include <iostream>
#include <systemc.h>
using namespace tlm;
class Thread
{
public:
@@ -69,6 +71,20 @@ private:
unsigned int id;
};
class Rank
{
public:
explicit Rank(unsigned int id) : id(id) {}
unsigned int ID() const
{
return id;
}
private:
unsigned int id;
};
class BankGroup
{
public:
@@ -145,72 +161,84 @@ private:
};
class DramExtension : public tlm::tlm_extension<DramExtension>
class DramExtension : public tlm_extension<DramExtension>
{
public:
DramExtension();
DramExtension(const Thread &thread, const Bank &bank,
const BankGroup &bankgroup, const Row &row, const Column &column,
unsigned int burstlength = 0);
DramExtension(const Thread &thread, const Channel &channel, const Bank &bank,
const BankGroup &bankgroup, const Row &row,
const Column &column, unsigned int burstlength = 0);
DramExtension(const Thread &thread, const Rank &rank, const BankGroup &bankgroup,
const Bank &bank, const Row &row, const Column &column,
unsigned int burstlength, uint64_t payloadID);
DramExtension(const Thread &thread, const Channel &channel, const Rank &rank,
const BankGroup &bankgroup, const Bank &bank, const Row &row,
const Column &column, unsigned int burstlength, uint64_t payloadID);
virtual tlm_extension_base *clone() const;
virtual void copy_from(const tlm_extension_base &ext);
static DramExtension &getExtension(const tlm::tlm_generic_payload *payload);
static DramExtension &getExtension(const tlm::tlm_generic_payload &payload);
static DramExtension &getExtension(const tlm_generic_payload *payload);
static DramExtension &getExtension(const tlm_generic_payload &payload);
// Used for convience, caller could also use getExtension(..) to access these field
static Bank getBank(const tlm::tlm_generic_payload *payload);
static Bank getBank(const tlm::tlm_generic_payload &payload);
static Channel getChannel(const tlm::tlm_generic_payload *payload);
static Channel getChannel(const tlm::tlm_generic_payload &payload);
static Thread getThread(const tlm::tlm_generic_payload *payload);
static Thread getThread(const tlm::tlm_generic_payload &payload);
static Row getRow(const tlm::tlm_generic_payload *payload);
static Row getRow(const tlm::tlm_generic_payload &payload);
static Thread getThread(const tlm_generic_payload *payload);
static Thread getThread(const tlm_generic_payload &payload);
static Channel getChannel(const tlm_generic_payload *payload);
static Channel getChannel(const tlm_generic_payload &payload);
static Rank getRank(const tlm_generic_payload *payload);
static Rank getRank(const tlm_generic_payload &payload);
static BankGroup getBankGroup(const tlm_generic_payload *payload);
static BankGroup getBankGroup(const tlm_generic_payload &payload);
static Bank getBank(const tlm_generic_payload *payload);
static Bank getBank(const tlm_generic_payload &payload);
static Row getRow(const tlm_generic_payload *payload);
static Row getRow(const tlm_generic_payload &payload);
static Column getColumn(const tlm_generic_payload *payload);
static Column getColumn(const tlm_generic_payload &payload);
static uint64_t getPayloadID(const tlm_generic_payload *payload);
static uint64_t getPayloadID(const tlm_generic_payload &payload);
Thread getThread() const;
Channel getChannel() const;
Bank getBank() const;
Rank getRank() const;
BankGroup getBankGroup() const;
Bank getBank() const;
Row getRow() const;
Column getColumn() const;
unsigned int getBurstlength() const;
uint64_t getPayloadID() const;
void incrementRow();
private:
Thread thread;
Channel channel;
Bank bank;
Rank rank;
BankGroup bankgroup;
Bank bank;
Row row;
Column column;
unsigned int burstlength;
uint64_t payloadID;
};
// Used to indicate the time when a payload is created (in a traceplayer or in a core)
// Note that this time can be different from the time the payload enters the DRAM system
//(at that time the phase BEGIN_REQ is recorded), so timeOfGeneration =< time(BEGIN_REQ)
class GenerationExtension : public tlm::tlm_extension<GenerationExtension>
class GenerationExtension : public tlm_extension<GenerationExtension>
{
public:
GenerationExtension(sc_time timeOfGeneration) : timeOfGeneration(
timeOfGeneration) {}
GenerationExtension(sc_time timeOfGeneration)
: timeOfGeneration(timeOfGeneration) {}
virtual tlm_extension_base *clone() const;
virtual void copy_from(const tlm_extension_base &ext);
static GenerationExtension &getExtension(const tlm::tlm_generic_payload
*payload);
static GenerationExtension
&getExtension(const tlm_generic_payload *payload);
sc_time TimeOfGeneration() const
{
return timeOfGeneration;
}
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload);
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload);
static sc_time getTimeOfGeneration(const tlm_generic_payload *payload);
static sc_time getTimeOfGeneration(const tlm_generic_payload &payload);
private:
sc_time timeOfGeneration;
@@ -224,6 +252,9 @@ bool operator<(const Thread &lhs, const Thread &rhs);
bool operator==(const Channel &lhs, const Channel &rhs);
bool operator!=(const Channel &lhs, const Channel &rhs);
bool operator==(const Rank &lhs, const Rank &rhs);
bool operator!=(const Rank &lhs, const Rank &rhs);
bool operator==(const BankGroup &lhs, const BankGroup &rhs);
bool operator!=(const BankGroup &lhs, const BankGroup &rhs);

17
DRAMSys/library/src/common/protocol.h
View File

@@ -39,17 +39,11 @@
#define PROTOCOL_H
// DRAM Control Phases
DECLARE_EXTENDED_PHASE(BEGIN_PREB);
DECLARE_EXTENDED_PHASE(END_PREB);
DECLARE_EXTENDED_PHASE(BEGIN_PRE);
DECLARE_EXTENDED_PHASE(END_PRE);
DECLARE_EXTENDED_PHASE(BEGIN_PRE_ALL);
DECLARE_EXTENDED_PHASE(END_PRE_ALL);
DECLARE_EXTENDED_PHASE(BEGIN_ACTB);
DECLARE_EXTENDED_PHASE(END_ACTB);
DECLARE_EXTENDED_PHASE(BEGIN_PREA);
DECLARE_EXTENDED_PHASE(END_PREA);
DECLARE_EXTENDED_PHASE(BEGIN_ACT);
DECLARE_EXTENDED_PHASE(END_ACT);
@@ -60,7 +54,6 @@ DECLARE_EXTENDED_PHASE(END_REFA);
DECLARE_EXTENDED_PHASE(BEGIN_REFB);
DECLARE_EXTENDED_PHASE(END_REFB);
// Phases for Read and Write
DECLARE_EXTENDED_PHASE(BEGIN_WR);
DECLARE_EXTENDED_PHASE(END_WR);
@@ -94,11 +87,5 @@ DECLARE_EXTENDED_PHASE(END_PDNAB);
DECLARE_EXTENDED_PHASE(BEGIN_SREFB);
DECLARE_EXTENDED_PHASE(END_SREFB);
//Triggers
DECLARE_EXTENDED_PHASE(REF_TRIGGER);
DECLARE_EXTENDED_PHASE(PDN_TRIGGER);
#endif // PROTOCOL_H

2
DRAMSys/library/src/common/third_party/DRAMPower vendored

Submodule DRAMSys/library/src/common/third_party/DRAMPower updated: 746d56ea53...1ddc48a387

1
DRAMSys/library/src/common/third_party/sqlite-amalgamation vendored Submodule

Submodule DRAMSys/library/src/common/third_party/sqlite-amalgamation added at 9be05e1340

1
DRAMSys/library/src/common/third_party/systemc vendored Submodule

Submodule DRAMSys/library/src/common/third_party/systemc added at 6041825095

36
DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp → DRAMSys/library/src/common/timingCalculations.cpp
View File

@@ -31,33 +31,41 @@
*
* Authors:
* Janik Schlemminger
* Robert Gernhardt
* Matthias Jung
*/
#include "NoPowerDown.h"
#include "timingCalculations.h"
#include "../configuration/memspec/MemSpec.h"
#include "DebugManager.h"
#include "../configuration/Configuration.h"
#include "utils.h"
void NoPowerDown::triggerSleep(Bank /*bank*/, sc_time /*time*/)
sc_time getDelayToMeetConstraint(sc_time previous, sc_time start,
sc_time constraint)
{
return;
if (previous + constraint > start)
return previous + constraint - start;
else
return SC_ZERO_TIME;
}
void NoPowerDown::sleep(Bank /*bank*/, sc_time /*time*/)
const sc_time FrequencyToClk(double frequencyMhz)
{
return;
return sc_time(1 / frequencyMhz, SC_US);
}
void NoPowerDown::wakeUp(Bank /*bank*/, sc_time /*time*/)
const sc_time clkAlign(sc_time time, Alignment alignment)
{
return;
sc_time clk = Configuration::getInstance().memSpec->clk;
if (alignment == UP)
return ceil(time / clk) * clk;
else
return floor(time / clk) * clk;
}
void NoPowerDown::wakeUpForRefresh(Bank /*bank*/, sc_time /*time*/)
bool isClkAligned(sc_time time, sc_time clk)
{
return;
return !((time / clk) - ceil(time / clk));
}
bool NoPowerDown::isInSelfRefresh(Bank /*bank*/)
{
return false;
}

8
DRAMSys/library/src/controller/core/timingCalculations.h → DRAMSys/library/src/common/timingCalculations.h
View File

@@ -39,14 +39,8 @@
#include <systemc.h>
#include <tlm.h>
#include "../../common/dramExtensions.h"
#include "../Command.h"
#include "dramExtensions.h"
sc_time getMinExecutionTimeForPowerDownCmd(Command command);
sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload);
sc_time getReadAccessTime();
sc_time getWriteAccessTime();
sc_time getDelayToMeetConstraint(sc_time previous, sc_time start,
sc_time constraint);

19
DRAMSys/library/src/common/utils.cpp
View File

@@ -40,10 +40,11 @@
#include <tlm.h>
#include <fstream>
#include "dramExtensions.h"
#include "../controller/Controller.h"
#include <sstream>
using namespace std;
using namespace tinyxml2;
using namespace tlm;
bool TimeInterval::timeIsInInterval(sc_time time)
{
@@ -69,7 +70,7 @@ void reportFatal(std::string sender, std::string message)
SC_REPORT_FATAL(sender.c_str(), message.c_str());
}
std::string phaseNameToString(tlm::tlm_phase phase)
std::string phaseNameToString(tlm_phase phase)
{
std::ostringstream oss;
oss << phase;
@@ -236,19 +237,19 @@ string loadTextFileContents(string filename)
}
}
void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank)
void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank)
{
payload.set_address(bank.getStartAddress());
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_command(TLM_READ_COMMAND);
payload.set_data_length(0);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
payload.set_response_status(TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(
Controller::ControllerThreadId()), bank, BankGroup(0), Row(0),
Column(0))); //payload takes ownership
//TODO .. Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!!
payload.set_extension(new DramExtension(Thread(UINT_MAX), rank, BankGroup(0),
bank, Row(0), Column(0), 0, 0));
// payload takes ownership
// TODO: Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!!
}
std::string getFileName(std::string uri)

4
DRAMSys/library/src/common/utils.h
View File

@@ -92,7 +92,7 @@ bool isIn(const T &value, const std::vector<T> &collection)
}
constexpr const char headline[] =
"=========================================================";
"===========================================================================";
static inline void loadbar(unsigned int x,
unsigned int n,
@@ -146,7 +146,7 @@ std::string queryStringParameter(tinyxml2::XMLElement *node, std::string name);
bool queryBoolParameter(tinyxml2::XMLElement *node, std::string name);
double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name);
void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank);
void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0));
#endif // UTILS_H

143
DRAMSys/library/src/controller/core/configuration/Configuration.cpp → DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -40,17 +40,13 @@
#include "Configuration.h"
#include "ConfigurationLoader.h"
#include "../../../common/XmlAddressDecoder.h"
#include "../common/XmlAddressDecoder.h"
using namespace std;
string Configuration::memspecUri = "";
string Configuration::mcconfigUri = "";
Configuration::Configuration()
{
}
bool string2bool(string s)
{
if (s.compare("0") == 0) {
@@ -142,18 +138,21 @@ void Configuration::setParameter(std::string name, std::string value)
BankwiseLogic = string2bool(value);
else if (name == "OpenPagePolicy")
OpenPagePolicy = string2bool(value);
else if (name == "AdaptivePagePolicy")
AdaptivePagePolicy = string2bool(value);
else if (name == "MaxNrOfTransactions")
MaxNrOfTransactions = string2int(value);
else if (name == "Scheduler")
Scheduler = value;
else if (name == "SJFProbability")
if (string2int(value) > 100 || string2int(value) < 0) {
{
if (string2int(value) > 100 || string2int(value) < 0)
SC_REPORT_FATAL("Configuration",
("Invalid value for parameter " + name +
". This parameter must be between 0 and 100.").c_str());
} else {
else
SJFProbability = string2int(value);
}
}
else if (name == "RequestBufferSize")
RequestBufferSize = string2int(value);
else if (name == "Capsize")
@@ -177,36 +176,31 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "EnableWindowing")
EnableWindowing = string2bool(value);
else if (name == "WindowSize")
if (string2int(value) < 1) {
{
if (string2int(value) < 1)
SC_REPORT_FATAL("Configuration",
("Invalid value for parameter " + name +
". This parameter must be at least one.").c_str());
} else
else
WindowSize = string2int(value);
}
else if (name == "Debug")
Debug = string2bool(value);
else if (name == "NumberOfMemChannels") {
else if (name == "NumberOfMemChannels")
NumberOfMemChannels = string2int(value);
unsigned int maxNumberofMemChannels =
AddressDecoder::getInstance().amount["channel"];
if (NumberOfMemChannels > maxNumberofMemChannels) {
SC_REPORT_FATAL("Configuration", ("Invalid value for parameter "
+ name
+ ". Value is out of range. The maximum value according to "
+ "the address mapping configuration file is "
+ std::to_string(maxNumberofMemChannels) + ".").c_str());
}
} else if (name == "ControllerCoreRefDisable")
else if (name == "ControllerCoreRefDisable")
ControllerCoreRefDisable = string2bool(value);
else if (name == "ControllerCoreRGR")
RowGranularRef = string2bool(value);
else if (name == "ControllerCoreRGRRowInc")
RowInc = string2int(value);
else if (name == "ControllerCoreRefMode") {
else if (name == "ControllerCoreRefMode")
{
RefMode = string2int(value);
if (RefMode != 1 && RefMode != 2 && RefMode != 4)
SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str());
} else if (name == "ControllerCoreRefNumARCmdsIntREFI")
}
else if (name == "ControllerCoreRefNumARCmdsIntREFI")
NumAR = string2int(value);
else if (name == "ControllerCoreRGRB0")
RGRB0 = string2bool(value);
@@ -240,25 +234,13 @@ void Configuration::setParameter(std::string name, std::string value)
RGRB14 = string2bool(value);
else if (name == "ControllerCoreRGRB15")
RGRB15 = string2bool(value);
else if (name == "ControllerCoreRGRtRASBInClkCycles")
trasbclk = string2int(value);
else if (name == "ControllerCoreRGRtRRDB_LInClkCycles")
trrdblclk = string2int(value);
else if (name == "ControllerCoreRGRtRRDB_SInClkCycles")
trrdbsclk = string2int(value);
else if (name == "ControllerCoreRGRtRPBInClkCycles")
trpbclk = string2int(value);
else if (name == "ControllerCoreRGRtRCBInClkCycles")
trcbclk = string2int(value);
else if (name == "ControllerCoreRGRtFAWBInClkCycles")
tfawbclk = string2int(value);
else if (name == "ControllerCoreRefForceMaxPostponeBurst")
ControllerCoreRefForceMaxPostponeBurst = string2bool(value);
else if (name == "ControllerCoreRefEnablePostpone") {
else if (name == "ControllerCoreRefEnablePostpone")
ControllerCoreRefEnablePostpone = string2bool(value);
} else if (name == "ControllerCoreRefEnablePullIn") {
else if (name == "ControllerCoreRefEnablePullIn")
ControllerCoreRefEnablePullIn = string2bool(value);
} else if (name == "ControllerCoreRefMaxPostponed")
else if (name == "ControllerCoreRefMaxPostponed")
ControllerCoreRefMaxPostponed = string2int(value);
else if (name == "ControllerCoreRefMaxPulledIn")
ControllerCoreRefMaxPulledIn = string2int(value);
@@ -267,21 +249,25 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "SimulationProgressBar")
SimulationProgressBar = string2bool(value);
else if (name == "NumberOfDevicesOnDIMM")
if (string2int(value) < 1) {
{
if (string2int(value) < 1)
SC_REPORT_FATAL("Configuration",
("Invalid value for parameter " + name +
". This parameter must be at least one.").c_str());
} else
else
NumberOfDevicesOnDIMM = string2int(value);
else if (name == "AddressOffset") {
}
else if (name == "AddressOffset")
{
#ifdef DRAMSYS_GEM5
AddressOffset = string2ull(value);
#else
AddressOffset = 0;
#endif
} else if (name == "UseMalloc") {
}
else if (name == "UseMalloc")
UseMalloc = string2bool(value);
} else if (name == "CheckTLM2Protocol")
else if (name == "CheckTLM2Protocol")
CheckTLM2Protocol = string2bool(value);
else if (name == "ECCControllerMode")
ECCMode = string2ECCControllerMode(value);
@@ -293,22 +279,25 @@ void Configuration::setParameter(std::string name, std::string value)
else if (name == "StoreMode")
StoreMode = string2StoreMode(value);
// Temperature Simulation related
else if (name == "TemperatureScale") {
if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") {
else if (name == "TemperatureScale")
{
if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin")
SC_REPORT_FATAL("Configuration",
("Invalid value for parameter " + name + ".").c_str());
}
temperatureSim.TemperatureScale = value;
} else if (name == "StaticTemperatureDefaultValue")
}
else if (name == "StaticTemperatureDefaultValue")
temperatureSim.StaticTemperatureDefaultValue = string2int(value);
else if (name == "ThermalSimPeriod")
temperatureSim.ThermalSimPeriod = std::stod(value.c_str());
else if (name == "ThermalSimUnit")
temperatureSim.ThermalSimUnit = string2TimeUnit(value);
else if (name == "PowerInfoFile") {
else if (name == "PowerInfoFile")
{
temperatureSim.powerInfoFile = value;
temperatureSim.parsePowerInfoFile();
} else if (name == "IceServerIp")
}
else if (name == "IceServerIp")
temperatureSim.IceServerIp = value;
else if (name == "IceServerPort")
temperatureSim.IceServerPort = string2int(value);
@@ -320,10 +309,9 @@ void Configuration::setParameter(std::string name, std::string value)
temperatureSim.GenerateTemperatureMap = string2bool(value);
else if (name == "GeneratePowerMap")
temperatureSim.GeneratePowerMap = string2bool(value);
else {
else
SC_REPORT_FATAL("Configuration",
("Parameter " + name + " not defined in Configuration").c_str());
}
}
void Configuration::setPathToResources(std::string path)
@@ -336,7 +324,7 @@ std::string Configuration::getPathToResources()
{
return pathToResources;
}
// TODO: Never used
void Configuration::setParameters(std::map<std::string, std::string>
parameterMap)
{
@@ -349,6 +337,9 @@ void Configuration::setParameters(std::map<std::string, std::string>
std::uint64_t Configuration::getSimMemSizeInBytes()
{
// 1. Get number of banks, rows, columns and data width in bits for one die (or chip)
std::string type = memSpec->MemoryType;
std::uint64_t ranks = memSpec->NumberOfRanks;
std::uint64_t bankgroups = memSpec->NumberOfBankGroups;
std::uint64_t banks = memSpec->NumberOfBanks;
std::uint64_t rows = memSpec->NumberOfRows;
std::uint64_t columns = memSpec->NumberOfColumns;
@@ -360,15 +351,19 @@ std::uint64_t Configuration::getSimMemSizeInBytes()
// 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM)
std::uint64_t memorySize = chipSize * NumberOfDevicesOnDIMM;
std::cout << headline << std::endl << std::endl;
std::cout << std::setw(24) << "Memory size in bytes : " << memorySize << std::endl;
std::cout << std::setw(24) << "Number of banks : " << banks << std::endl;
std::cout << std::setw(24) << "Number of rows : " << rows << std::endl;
std::cout << std::setw(24) << "Number of columns : " << columns << std::endl;
std::cout << std::setw(24) << "Chip data bus width : " << bitWidth << std::endl;
std::cout << std::setw(24) << "Chip size in bits : " << chipBitSize << std::endl;
std::cout << std::setw(24) << "Chip Size in bytes : " << chipSize << std::endl;
std::cout << std::setw(24) << "Devices/Chips on DIMM: " << NumberOfDevicesOnDIMM << std::endl;
std::cout << headline << std::endl;
std::cout << "Per Channel Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << type << std::endl;
std::cout << " Memory size in bytes: " << memorySize << std::endl;
std::cout << " Number of ranks: " << ranks << std::endl;
std::cout << " Number of bankgroups: " << bankgroups << std::endl;
std::cout << " Number of banks: " << banks << std::endl;
std::cout << " Number of rows: " << rows << std::endl;
std::cout << " Number of columns: " << columns << std::endl;
std::cout << " Chip data bus width: " << bitWidth << std::endl;
std::cout << " Chip size in bits: " << chipBitSize << std::endl;
std::cout << " Chip Size in bytes: " << chipSize << std::endl;
std::cout << " Devices/Chips on DIMM: " << NumberOfDevicesOnDIMM << std::endl;
std::cout << std::endl;
assert(memorySize > 0);
@@ -398,37 +393,13 @@ unsigned int Configuration::getBytesPerBurst()
// offset of the N-byte-wide memory module (DIMM) (a single data word
// or burst element has N bytes. N = 2^(# bits for byte offset)).
unsigned int burstElementSizeInBytes =
AddressDecoder::getInstance().amount["bytes"];
AddressDecoder::getInstance().amount.bytes;
assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->BurstLength));
}
return bytesPerBurst;
}
sc_time Configuration::getTrasb()
{
return trasbclk * memSpec->clk;
}
sc_time Configuration::getTrrdb_L()
{
return trrdblclk * memSpec->clk;
}
sc_time Configuration::getTrrdb_S()
{
return trrdbsclk * memSpec->clk;
}
sc_time Configuration::getTrpb()
{
return trpbclk * memSpec->clk;
}
sc_time Configuration::getTrcb()
{
return trcbclk * memSpec->clk;
}
sc_time Configuration::getTfawb()
{
return tfawbclk * memSpec->clk;
}
bool Configuration::getRGRBank(unsigned int w)
{
bool flg = w == 0 ? RGRB0 : w == 1 ? RGRB1 : w == 2 ? RGRB2 : w == 3 ? RGRB3 : w

21
DRAMSys/library/src/controller/core/configuration/Configuration.h → DRAMSys/library/src/configuration/Configuration.h
View File

@@ -42,11 +42,11 @@
#include <systemc.h>
#include <string>
#include <cstdint>
#include "MemSpec.h"
#include "memspec/MemSpec.h"
#include "TemperatureSimConfig.h"
#include "../../../common/utils.h"
#include "../common/utils.h"
#include "../../../error/eccbaseclass.h"
#include "../error/eccbaseclass.h"
enum class StorageMode {NoStorage, Store, ErrorModel};
@@ -65,6 +65,7 @@ struct Configuration
// MCConfig:
bool BankwiseLogic = false;
bool OpenPagePolicy = true;
bool AdaptivePagePolicy = false;
unsigned int MaxNrOfTransactions = 8;
std::string Scheduler;
unsigned int SJFProbability;
@@ -88,18 +89,6 @@ struct Configuration
unsigned int NumberOfMemChannels = 1;
bool ControllerCoreRefDisable = false;
bool RowGranularRef = false;
unsigned int trasbclk = 0;
sc_time getTrasb();
unsigned int trrdblclk = 0;
sc_time getTrrdb_L();
unsigned int trrdbsclk = 0;
sc_time getTrrdb_S();
unsigned int trpbclk = 0;
sc_time getTrpb();
unsigned int trcbclk = 0;
sc_time getTrcb();
unsigned int tfawbclk = 0;
sc_time getTfawb();
bool RGRB0 = true;
bool RGRB1 = true;
bool RGRB2 = true;
@@ -160,7 +149,7 @@ struct Configuration
std::string getPathToResources();
private:
Configuration();
Configuration() {}
unsigned int powerDownTimeoutInClk = 3;
};

775
DRAMSys/library/src/configuration/ConfigurationLoader.cpp Normal file
View File

@@ -0,0 +1,775 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Matthias Jung
* Lukas Steiner
*/
#include "ConfigurationLoader.h"
#include "memspec/MemSpec.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
#include "memspec/MemSpecGDDR5X.h"
#include "memspec/MemSpecGDDR6.h"
#include "../common/timingCalculations.h"
using namespace tinyxml2;
using namespace std;
void ConfigurationLoader::loadSimConfig(Configuration &config,
string simconfigUri)
{
tinyxml2::XMLDocument doc;
loadXML(simconfigUri, doc);
XMLElement *simconfig = doc.FirstChildElement("simconfig");
loadConfig(config, simconfig);
}
void ConfigurationLoader::loadSimConfig(Configuration &config,
XMLElement *simconfig)
{
if (simconfig->Attribute("src")) {
XMLDocument doc;
string src(simconfig->Attribute("src"));
loadXML(src, doc);
loadSimConfig(config, doc.FirstChildElement("simconfig"));
}
loadConfig(config, simconfig);
}
void ConfigurationLoader::loadTemperatureSimConfig(Configuration &config,
std::string thermalsimconfigUri)
{
loadConfigFromUri(config, thermalsimconfigUri, "thermalsimconfig");
}
void ConfigurationLoader::loadTemperatureSimConfig(Configuration &config,
XMLElement *thermalsimconfig)
{
if (thermalsimconfig->Attribute("src")) {
// Configuration is inside another a file
std::string uri(thermalsimconfig->Attribute("src"));
loadConfigFromUri(config, uri, "thermalsimconfig");
} else {
loadConfig(config, thermalsimconfig);
}
}
void ConfigurationLoader::loadConfig(Configuration &config,
XMLElement *configNode)
{
XMLElement *element;
for (element = configNode->FirstChildElement(); element != NULL;
element = element->NextSiblingElement()) {
config.setParameter(element->Name(), element->Attribute("value"));
}
}
void ConfigurationLoader::loadConfigFromUri(Configuration &config,
std::string uri, std::string first_element)
{
tinyxml2::XMLDocument doc;
loadXML(uri, doc);
XMLElement *e = doc.FirstChildElement(first_element.c_str());
loadConfig(config, e);
}
void ConfigurationLoader::loadMCConfig(Configuration &config,
string mcconfigUri)
{
tinyxml2::XMLDocument doc;
config.mcconfigUri = mcconfigUri;
loadXML(mcconfigUri, doc);
XMLElement *mcconfig = doc.FirstChildElement("mcconfig");
loadConfig(config, mcconfig);
}
void ConfigurationLoader::loadMCConfig(Configuration &config,
XMLElement *mcconfig)
{
if (mcconfig->Attribute("src"))
{
XMLDocument doc;
string src(mcconfig->Attribute("src"));
config.mcconfigUri = src;
loadXML(src, doc);
loadMCConfig(config, doc.FirstChildElement("mcconfig"));
}
else
loadConfig(config, mcconfig);
}
void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri)
{
tinyxml2::XMLDocument doc;
config.memspecUri = memspecUri;
loadXML(memspecUri, doc);
XMLElement *memspec = doc.FirstChildElement("memspec");
loadMemSpec(config, memspec);
}
void ConfigurationLoader::loadMemSpec(Configuration &config,
XMLElement *memspec)
{
string memoryType = queryStringParameter(memspec, "memoryType");
if (memoryType == "DDR4")
{
Configuration::getInstance().memSpec = new MemSpecDDR4();
loadCommons(config, memspec);
loadDDR4(config, memspec);
}
else if (memoryType == "DDR3")
{
Configuration::getInstance().memSpec = new MemSpecDDR3();
loadCommons(config, memspec);
loadDDR3(config, memspec);
}
else if (memoryType == "LPDDR4")
{
Configuration::getInstance().memSpec = new MemSpecLPDDR4();
loadCommons(config, memspec);
loadLPDDR4(config, memspec);
}
else if (memoryType == "WIDEIO_SDR")
{
Configuration::getInstance().memSpec = new MemSpecWideIO();
loadCommons(config, memspec);
loadWideIO(config, memspec);
}
else if (memoryType == "WIDEIO2")
{
Configuration::getInstance().memSpec = new MemSpecWideIO2();
loadCommons(config, memspec);
loadWideIO2(config, memspec);
}
else if (memoryType == "HBM2")
{
Configuration::getInstance().memSpec = new MemSpecHBM2();
loadCommons(config, memspec);
loadHBM2(config, memspec);
}
else if (memoryType == "GDDR5")
{
Configuration::getInstance().memSpec = new MemSpecGDDR5();
loadCommons(config, memspec);
loadGDDR5(config, memspec);
}
else if (memoryType == "GDDR5X")
{
Configuration::getInstance().memSpec = new MemSpecGDDR5X();
loadCommons(config, memspec);
loadGDDR5X(config, memspec);
}
else if (memoryType == "GDDR6")
{
Configuration::getInstance().memSpec = new MemSpecGDDR6();
loadCommons(config, memspec);
loadGDDR6(config, memspec);
}
else
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec)
{
MemSpec *memSpec = config.memSpec;
memSpec->MemoryId = queryStringParameter(xmlSpec, "memoryId");
memSpec->MemoryType = queryStringParameter(xmlSpec, "memoryType");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->BurstLength = queryUIntParameter(architecture, "burstLength");
memSpec->DataRate = queryUIntParameter(architecture, "dataRate");
memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
memSpec->bitWidth = queryUIntParameter(architecture, "width");
// Clock
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
memSpec->clk = FrequencyToClk(memSpec->clkMHz);
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
{
MemSpecDDR3 *memSpec = dynamic_cast<MemSpecDDR3 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = 1;
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for DDR3
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
}
void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
{
MemSpecDDR4 *memSpec = dynamic_cast<MemSpecDDR4 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for DDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
unsigned refMode = Configuration::getInstance().getRefMode();
if (refMode == 1)
{
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
}
else if (refMode == 2)
{
memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2");
}
else if (refMode == 4)
{
memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4");
}
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
{
MemSpecLPDDR4 *memSpec = dynamic_cast<MemSpecLPDDR4 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture:
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = 1;
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for LPDDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB");
memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB");
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRPST = clk * queryUIntParameter(timings, "RPST");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS");
memSpec->tDQS2DQ = clk * queryUIntParameter(timings, "DQS2DQ");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWPRE = clk * queryUIntParameter(timings, "WPRE");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tSR = clk * queryUIntParameter(timings, "SR");
memSpec->tXSR = clk * queryUIntParameter(timings, "XSR");
memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
{
MemSpecWideIO *memSpec = dynamic_cast<MemSpecWideIO *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = 1;
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tAC = clk * queryUIntParameter(timings, "AC");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tCCD_R = clk * queryUIntParameter(timings, "CCD_R");
memSpec->tCCD_W = clk * queryUIntParameter(timings, "CCD_W");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tTAW = clk * queryUIntParameter(timings, "TAW");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12");
memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12");
memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2");
memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2");
memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2");
memSpec->iDD52 = queryDoubleParameter(powers, "idd52");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
}
void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec)
{
MemSpecWideIO2 *memSpec = dynamic_cast<MemSpecWideIO2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = 1;
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tRCpb = clk * queryUIntParameter(timings, "RCPB");
memSpec->tRCab = clk * queryUIntParameter(timings, "RCAB");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tXSR = clk * queryUIntParameter(timings, "XSR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB");
memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec)
{
MemSpecHBM2 *memSpec = dynamic_cast<MemSpecHBM2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for HBM2
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
// memSpec->tDQSQ = clk * queryUIntParameter(timings, "DQSQ");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tPL = clk * queryUIntParameter(timings, "PL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
// memSpec->tCCDR = clk * queryUIntParameter(timings, "CCDR");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tRDPDE = memSpec->tRL + memSpec->tPL
+ (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk;
memSpec->tWRPDE = memSpec->tWL + memSpec->tPL
+ (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR;
memSpec->tWRAPDE = memSpec->tWL + memSpec->tPL
+ (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR;
memSpec->tCKESR = memSpec->tCKE + memSpec->clk;
memSpec->tRDSRE = memSpec->tRL + memSpec->tPL
+ (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk;
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCSB = clk * queryUIntParameter(timings, "RFCSB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFISB = clk * queryUIntParameter(timings, "REFISB");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec)
{
MemSpecGDDR5 *memSpec = dynamic_cast<MemSpecGDDR5 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for GDDR5
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tCL = clk * queryUIntParameter(timings, "CL");
memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tXPN = clk * queryUIntParameter(timings, "XPN");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->t32AW = clk * queryUIntParameter(timings, "32AW");
memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk;
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tLK = clk * queryUIntParameter(timings, "LK");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec)
{
MemSpecGDDR5X *memSpec = dynamic_cast<MemSpecGDDR5X *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for GDDR5X
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->t32AW = clk * queryUIntParameter(timings, "32AW");
memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk;
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tLK = clk * queryUIntParameter(timings, "LK");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec)
{
MemSpecGDDR6 *memSpec = dynamic_cast<MemSpecGDDR6 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank;
memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks;
memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks;
// MemTimings specific for GDDR6
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk;
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tLK = clk * queryUIntParameter(timings, "LK");
memSpec->tACTPDE = clk * queryUIntParameter(timings, "ACTPDE");
memSpec->tPREPDE = clk * queryUIntParameter(timings, "PREPDE");
memSpec->tREFPDE = clk * queryUIntParameter(timings, "REFPDE");
// Currents and voltages
// TODO: to be completed
}

9
DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h → DRAMSys/library/src/configuration/ConfigurationLoader.h
View File

@@ -39,8 +39,8 @@
#define CONFIGURATIONLOADER_H
#include <string>
#include "../../../common/third_party/tinyxml2/tinyxml2.h"
#include "../../../common/utils.h"
#include "../common/third_party/tinyxml2/tinyxml2.h"
#include "../common/utils.h"
#include "Configuration.h"
class ConfigurationLoader
@@ -73,6 +73,11 @@ private:
static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadHBM2(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadGDDR5(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadGDDR5X(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadGDDR6(Configuration &config, tinyxml2::XMLElement *memspec);
};

30
DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h → DRAMSys/library/src/configuration/TemperatureSimConfig.h
View File

@@ -41,9 +41,9 @@
#include <iostream>
#include <string>
#include "../../../common/DebugManager.h"
#include "../../../common/third_party/tinyxml2/tinyxml2.h"
#include "../../../common/utils.h"
#include "../common/DebugManager.h"
#include "../common/third_party/tinyxml2/tinyxml2.h"
#include "../common/utils.h"
struct TemperatureSimConfig
{
@@ -76,7 +76,7 @@ struct TemperatureSimConfig
void parsePowerInfoFile()
{
printDebugMessage("Power Info File: " + powerInfoFile);
PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile);
powerInfoFile = pathToResources
+ "/configs/thermalsim/"
@@ -90,7 +90,7 @@ struct TemperatureSimConfig
if (powInfoElem == NULL) {
// Invalid file
std::string errormsg = "Invalid Power Info File " + powerInfoFile;
printDebugMessage(errormsg);
PRINTDEBUGMESSAGE("TemperatureSimConfig", errormsg);
SC_REPORT_FATAL("Temperature Sim Config", errormsg.c_str());
}
@@ -113,23 +113,17 @@ struct TemperatureSimConfig
void showTemperatureSimConfig()
{
int i = 0;
for (auto e : powerInitialValues) {
printDebugMessage("powerInitialValues[" + std::to_string(
i++) + "]: " + std::to_string(e));
int i __attribute__((unused)) = 0;
for (auto e __attribute__((unused)) : powerInitialValues) {
PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerInitialValues["
+ std::to_string(i++) + "]: " + std::to_string(e));
}
i = 0;
for (auto e : powerThresholds) {
printDebugMessage("powerThreshold[" + std::to_string(i++) + "]: " +
std::to_string(e));
for (auto e __attribute__((unused)) : powerThresholds) {
PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerThreshold["
+ std::to_string(i++) + "]: " + std::to_string(e));
}
}
void printDebugMessage(std::string message)
{
DebugManager::getInstance().printDebugMessage("Temperature Sim Config",
message);
}
};
#endif // TEMPERATURESIMCONFIG_H

88
DRAMSys/library/src/controller/core/Slots.cpp → DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -30,58 +30,58 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Robert Gernhardt
* Matthias Jung
* Lukas Steiner
*/
#include "Slots.h"
#include "timingCalculations.h"
#include "MemSpec.h"
#include <systemc.h>
#include <tlm.h>
#include "../../controller/Command.h"
#include "../Configuration.h"
Slots::Slots(sc_time clk) :
clk(clk)
using namespace tlm;
MemSpec::MemSpec()
{
commandLength = std::vector<unsigned>(numberOfCommands(), 1);
}
Slots::~Slots()
const std::vector<Bank> &MemSpec::getBanks() const
{
}
void Slots::moveCommandToNextFreeSlot(ScheduledCommand &command)
{
while (!isFree(command.getStart()))
command.delayStart(clk);
}
void Slots::cleanUpSlots(sc_time time)
{
slotSet.erase(slotSet.begin(), slotSet.lower_bound(time));
}
void Slots::blockSlot(sc_time time)
{
sc_assert(isClkAligned(time, clk));
slotSet.insert(time);
}
bool Slots::isFree(sc_time time)
{
return (slotSet.count(time) == 0);
}
void Slots::blockSlots(sc_time begin, sc_time end, bool excludeBorders)
{
sc_assert(isClkAligned(begin, clk));
sc_assert(isClkAligned(end, clk));
if (excludeBorders) {
begin += clk;
end -= clk;
}
for (sc_time time = begin; time <= end; time += clk) {
blockSlot(time);
static std::vector<Bank> banks;
if (banks.size() == 0) {
for (unsigned int i = 0; i < NumberOfBanks; i++)
banks.push_back(Bank(i));
}
return banks;
}
sc_time MemSpec::getReadAccessTime() const
{
return clk * (BurstLength / DataRate);
}
sc_time MemSpec::getWriteAccessTime() const
{
return clk * (BurstLength / DataRate);
}
unsigned MemSpec::getCommandLength(Command command) const
{
return commandLength[command];
}
//sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const
//{
// if (command == Command::PDEA || command == Command::PDEP)
// return tCKE;
// else if (command == Command::SREFEN)
// return tCKESR;
// else
// {
// SC_REPORT_FATAL("getMinimalExecutionTime",
// "command is not know or command has a fixed execution time");
// return SC_ZERO_TIME;
// }
//}

71
DRAMSys/library/src/controller/scheduler/IScheduler.h → DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -31,40 +31,65 @@
*
* Authors:
* Janik Schlemminger
* Robert Gernhardt
* Matthias Jung
* Lukas Steiner
*/
#ifndef ISCHEDULER_H
#define ISCHEDULER_H
#ifndef MEMSPEC_H
#define MEMSPEC_H
#include <tlm.h>
#include <systemc.h>
#include <vector>
#include "../../common/dramExtensions.h"
#include "../Command.h"
#include "../core/ControllerCore.h"
#include "../../controller/Command.h"
#include "../../common/utils.h"
typedef tlm::tlm_generic_payload gp;
using namespace tlm;
class IScheduler
struct MemSpec
{
public:
virtual ~IScheduler() {}
IScheduler(ControllerCore &controllerCore) : controllerCore(controllerCore) {}
MemSpec();
virtual ~MemSpec() {}
virtual void storeRequest(gp *payload) = 0;
virtual std::pair<Command, gp *> getNextRequest(Bank bank) = 0;
virtual gp *getPendingRequest(Bank bank) = 0;
static std::string sendername;
const std::vector<Bank> &getBanks() const;
protected:
void printDebugMessage(std::string message);
Command getNextCommand(gp &payload);
Command getNextCommand(gp *payload);
sc_time getWriteAccessTime() const;
sc_time getReadAccessTime() const;
Command getReadWriteCommand(gp &payload);
Command getReadWriteCommand(gp *payload);
virtual sc_time getRefreshIntervalAB() const = 0;
virtual sc_time getRefreshIntervalPB() const = 0;
ControllerCore &controllerCore;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0;
unsigned getCommandLength(Command) const;
// Returns the minimum execution time for commands that have a variable execution time
//virtual sc_time getMinExecutionTimeForPowerDownCmd(Command command) const = 0;
std::string MemoryId = "not defined.";
std::string MemoryType = "not defined.";
unsigned int NumberOfRanks;
unsigned int NumberOfBankGroups;
unsigned int NumberOfBanks;
unsigned int NumberOfRows;
unsigned int NumberOfColumns;
unsigned int BurstLength;
unsigned int DataRate;
unsigned int bitWidth;
unsigned int BanksPerRank;
unsigned int BanksPerGroup;
unsigned int GroupsPerRank;
// Clock
double clkMHz;
sc_time clk;
// Command lengths on bus, standardly one clock cycle
std::vector<unsigned> commandLength;
};
#endif // ISCHEDULER_H
#endif // MEMSPEC_H

85
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp Normal file
View File

@@ -0,0 +1,85 @@
/*
* Copyright (c) 2019, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "MemSpecDDR3.h"
sc_time MemSpecDDR3::getRefreshIntervalAB() const
{
return tREFI;
}
sc_time MemSpecDDR3::getRefreshIntervalPB() const
{
SC_REPORT_FATAL("MemSpecDDR3", "Per bank refresh not supported");
return SC_ZERO_TIME;
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const
{
if (command == Command::PRE || command == Command::PREA)
return tRP;
else if (command == Command::ACT)
return tRCD;
else if (command == Command::RD || command == Command::RDA)
return tRL + getReadAccessTime();
else if (command == Command::WR || command == Command::WRA)
return tWL + getWriteAccessTime();
else if (command == Command::REFA)
return tRFC;
else if (command == Command::REFB)
return tRFC;
else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX)
return clk;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
}
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime());
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime());
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
}
}

88
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h Normal file
View File

@@ -0,0 +1,88 @@
/*
* Copyright (c) 2019, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef MEMSPECDDR3_H
#define MEMSPECDDR3_H
#include "MemSpec.h"
struct MemSpecDDR3 final : public MemSpec
{
// Memspec Variables:
sc_time tCKE; // min time in pdna or pdnp
sc_time tCKESR; // min time in sref
sc_time tRAS; // active-time (act -> pre same bank)
sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRCD; // act -> read/write
sc_time tRL; // read latency (read command start to data strobe)
sc_time tRTP; // read to precharge
sc_time tWL; // write latency
sc_time tWR; // write recovery (write to precharge)
sc_time tXP; // min delay to row access command after pdnpx pdnax
sc_time tXS; // min delay to row access command after srefx
sc_time tREFI;
sc_time tRFC;
sc_time tRP;
sc_time tDQSCK;
sc_time tCCD;
sc_time tFAW;
sc_time tRRD;
sc_time tWTR;
sc_time tXPDLL;
sc_time tXSDLL;
sc_time tAL;
// Currents and Voltages:
double iDD0;
double iDD2N;
double iDD3N;
double iDD4R;
double iDD4W;
double iDD5;
double iDD6;
double vDD;
double iDD2P0;
double iDD2P1;
double iDD3P0;
double iDD3P1;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};
#endif // MEMSPECDDR3_H

83
DRAMSys/library/src/controller/scheduler/IScheduler.cpp → DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, University of Kaiserslautern
* Copyright (c) 2019, University of Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,67 +30,54 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Janik Schlemminger
* Robert Gernhardt
* Matthias Jung
* Lukas Steiner
*/
#include "IScheduler.h"
#include "../../common/DebugManager.h"
#include "../core/configuration/Configuration.h"
#include "MemSpecDDR4.h"
std::string IScheduler::sendername = "scheduler";
void IScheduler::printDebugMessage(std::string message)
sc_time MemSpecDDR4::getRefreshIntervalAB() const
{
DebugManager::getInstance().printDebugMessage(IScheduler::sendername, message);
return tREFI;
}
// Get the next command that is necessary to process the request representend by the payload
Command IScheduler::getNextCommand(gp &payload)
sc_time MemSpecDDR4::getRefreshIntervalPB() const
{
Bank bank = DramExtension::getBank(payload);
if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank))
{
return Command::Activate;
}
else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) &&
controllerCore.getRowBufferStates().getRowInRowBuffer(bank) !=
DramExtension::getRow(payload))
{
return Command::Precharge;
}
SC_REPORT_FATAL("MemSpecDDR4", "Per bank refresh not supported");
return SC_ZERO_TIME;
}
// Returns the execution time for commands that have a fixed execution time
sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const
{
if (command == Command::PRE || command == Command::PREA)
return tRP;
else if (command == Command::ACT)
return tRCD;
else if (command == Command::RD || command == Command::RDA)
return tRL + getReadAccessTime();
else if (command == Command::WR || command == Command::WRA)
return tWL + getWriteAccessTime();
else if (command == Command::REFA)
return tRFC;
else if (command == Command::REFB)
return tRFC;
else
{
return getReadWriteCommand(payload);
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
}
Command IScheduler::getNextCommand(gp *payload)
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const
{
return getNextCommand(*payload);
}
Command IScheduler::getReadWriteCommand(gp &payload)
{
if (payload.get_command() == tlm::TLM_READ_COMMAND)
{
if (Configuration::getInstance().OpenPagePolicy)
return Command::Read;
else
return Command::ReadA;
}
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime());
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime());
else
{
if (Configuration::getInstance().OpenPagePolicy)
return Command::Write;
else
return Command::WriteA;
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
}
}
Command IScheduler::getReadWriteCommand(gp *payload)
{
return getReadWriteCommand(*payload);
}

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