From 4c4119803e324937175a2ce1b11b394cfa669dac Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 25 Jun 2019 13:37:49 +0200 Subject: [PATCH 001/183] Included CheckerDDR3. --- DRAMSys/library/library.pro | 6 +- .../src/controller/core/ControllerCore.cpp | 10 - .../core/configuration/Configuration.cpp | 4 - .../core/configuration/Configuration.h | 2 +- .../configuration/ConfigurationLoader.cpp | 12 +- .../controller/core/configuration/MemSpec.h | 2 + .../core/scheduling/checker/CheckerDDR3.cpp | 569 ++++++++++++++++++ .../core/scheduling/checker/CheckerDDR3.h | 59 ++ 8 files changed, 639 insertions(+), 25 deletions(-) create mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp create mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 05098c1f..c8a65529 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -147,7 +147,8 @@ SOURCES += \ src/simulation/DramDDR3.cpp \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ - src/simulation/DramWideIO.cpp + src/simulation/DramWideIO.cpp \ + src/controller/core/scheduling/checker/CheckerDDR3.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -228,7 +229,8 @@ HEADERS += \ src/simulation/DramDDR3.h \ src/simulation/DramDDR4.h \ src/simulation/DramRecordable.h \ - src/simulation/DramWideIO.h + src/simulation/DramWideIO.h \ + src/controller/core/scheduling/checker/CheckerDDR3.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 5c43afcc..73905e3e 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -87,16 +87,6 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, if (config.RowGranularRef) { refreshManager = new RGR("RGR", *this); - // TODO: How to use asserts with new memspec? - /* - assert(config.getTrasb() <= config.memSpec->tRAS); - assert(config.getTrasb() >= config.memSpec->tRCD); - assert(config.getTrrdb_L() <= config.memSpec->tRRD_L); - assert(config.getTrrdb_S() <= config.memSpec->tRRD_S); - assert(config.getTrpb() <= config.memSpec->tRP); - assert(config.getTrcb() <= config.memSpec->tRC); - assert(config.getTfawb() <= config.memSpec->tNAW); - */ } else { if (config.BankwiseLogic) { refreshManager = new RefreshManagerBankwise("refManagerBw", *this); diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index eb0918f3..72811ff4 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -47,10 +47,6 @@ using namespace std; string Configuration::memspecUri = ""; string Configuration::mcconfigUri = ""; -Configuration::Configuration() -{ -} - bool string2bool(string s) { if (s.compare("0") == 0) { diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index 51d4079e..80f7ae87 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -160,7 +160,7 @@ struct Configuration std::string getPathToResources(); private: - Configuration(); + Configuration() {} unsigned int powerDownTimeoutInClk = 3; }; diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index a4d3f94f..81fd0dba 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -143,20 +143,16 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, string memoryType = queryStringParameter(memspec, "memoryType"); if (memoryType == "DDR4") { - Configuration::getInstance().memSpec = - new MemSpecDDR4; + Configuration::getInstance().memSpec = new MemSpecDDR4; loadDDR4(config, memspec); } else if (memoryType == "DDR3") { - Configuration::getInstance().memSpec = - new MemSpecDDR3; + Configuration::getInstance().memSpec = new MemSpecDDR3; loadDDR3(config, memspec); } else if (memoryType == "LPDDR4") { - Configuration::getInstance().memSpec = - new MemSpecLPDDR4; + Configuration::getInstance().memSpec = new MemSpecLPDDR4; loadLPDDR4(config, memspec); } else if (memoryType == "WIDEIO_SDR") { - Configuration::getInstance().memSpec = - new MemSpecWideIO; + Configuration::getInstance().memSpec = new MemSpecWideIO; loadWideIO(config, memspec); } else { reportFatal("ConfigurationLoader", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index d13f2701..28503d19 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -162,6 +162,8 @@ struct MemSpec { return tWTR_L; } + + virtual ~MemSpec() {} }; struct MemSpecDDR3 : public MemSpec diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp new file mode 100644 index 00000000..e5d06288 --- /dev/null +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -0,0 +1,569 @@ +#include "CheckerDDR3.h" + +#include +#include +#include +#include +#include "CheckerDDR3.h" +#include "../../timingCalculations.h" +#include "../../../../common/DebugManager.h" +#include "../../../Command.h" +#include "../../../../common/Utils.h" + +using namespace std; + +void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const +{ + ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); + Command LastCmd = lastCommandOnBank.getCommand(); + Command NextCmd = command.getCommand(); + + if (NextCmd == Command::Activate) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::Precharge: + case Command::PrechargeAll: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP); + break; + case Command::ReadA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRTP + memSpec->tRP); + break; + case Command::WriteA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR + memSpec->tRP); + break; + case Command::PDNPX: + case Command::PDNAX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + case Command::SREFX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXS); + break; + case Command::AutoRefresh: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRFC); + break; + default: + reportFatal("Checker DDR3", + "Activate can not follow " + commandToString(LastCmd)); + } + } + + delay_to_satisfy_activateToActivate_sameBank(command); + + while (!(state.bus.isFree(command.getStart()) && + satsfies_activateToActivate_differentBank(command) && satisfies_nActivateWindow(command))) + { + command.delayStart(memSpec->clk); + } + } + else if (NextCmd == Command::Read || NextCmd == Command::ReadA) + { + delayToSatisfyDLL(command); + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::Activate: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRCD); + break; + case Command::Read: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + CasToCas(lastCommandOnBank, command)); + break; + case Command::Write: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + writeToRead(lastCommandOnBank, command)); + break; + case Command::PDNPX: + case Command::PDNAX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + default: + reportFatal("Checker DDR3", + "Read can not follow " + commandToString(LastCmd) + "First: Activate!"); + } + } + while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) + command.delayStart(memSpec->clk); + } + else if (NextCmd == Command::Write || NextCmd == Command::WriteA) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::Activate: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRCD); + break; + case Command::Read: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + readToWrite(lastCommandOnBank, command)); + break; + case Command::Write: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + CasToCas(lastCommandOnBank, command)); + break; + case Command::PDNPX: + case Command::PDNAX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + default: + reportFatal("Checker DDR3", "Write can not follow " + commandToString(LastCmd)); + } + } + while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) + command.delayStart(memSpec->clk); + } + else if (NextCmd == Command::Precharge) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::Precharge: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP); + break; + case Command::Activate: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRCD); + break; + case Command::Read: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRTP); + break; + case Command::Write: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + memSpec->tWR + + getWriteAccessTime()); + break; + case Command::PDNAX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + default: + reportFatal("Checker DDR3", + "Precharge can not follow " + commandToString(LastCmd)); + } + } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + command.establishMinDistanceFromStart(lastActivate.getStart(), + memSpec->tRAS); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (NextCmd == Command::PrechargeAll) + { + for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) + { + ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); + if (lastCommand.isValidCommand()) + { + switch (lastCommand.getCommand()) + { + case Command::Precharge: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRP); + break; + case Command::Activate: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRCD); + break; + case Command::Read: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRTP); + break; + case Command::Write: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR); + break; + case Command::WriteA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR + memSpec->tRP); + break; + case Command::ReadA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRTP + memSpec->tRP); + break; + case Command::PDNAX: + case Command::PDNPX: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXP); + break; + case Command::SREFX: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXS); + break; + case Command::AutoRefresh: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRFC); + break; + default: + reportFatal("Checker_DDR3", + "Precharge All can not follow " + commandToString(LastCmd)); + } + } + } + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivate.isValidCommand()) + command.establishMinDistanceFromStart(lastActivate.getStart(), + memSpec->tRAS); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (NextCmd == Command::PDNA || NextCmd == Command::PDNP || NextCmd == Command::SREF ) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::Precharge: + case Command::PrechargeAll: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP); + break; + case Command::Read: + case Command::ReadA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRL + getReadAccessTime() + + memSpec->clk); + break; + case Command::Write: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR); + break; + case Command::WriteA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR + memSpec->clk); + break; + case Command::AutoRefresh: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRFC); + break; + case Command::PDNAX: + case Command::PDNPX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + case Command::SREFX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXS); + break; + default: + reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow " + + commandToString(LastCmd) + ".First: Precharge!"); + } + } + state.bus.moveCommandToNextFreeSlot(command); + } + else if (NextCmd == Command::PDNAX) + { + // Leaving Precharge Power Down + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNA, + command.getBank()).getStart(), memSpec->tCKE); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (NextCmd == Command::PDNPX) + { + // Leaving Precharge Power Down + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNP, + command.getBank()).getStart(), memSpec->tCKE); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (NextCmd == Command::SREFX) + { + // Leaving Self Refresh + command.establishMinDistanceFromStart(state.getLastCommand(Command::SREF, + command.getBank()).getStart(), memSpec->tCKESR); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (NextCmd == Command::AutoRefresh) + { + if (config.BankwiseLogic) { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::Precharge: + case Command::PrechargeAll: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP); + break; + case Command::ReadA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRTP + memSpec->tRP); + break; + case Command::WriteA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR + memSpec->tRP); + break; + case Command::AutoRefresh: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRFC); + break; + case Command::PDNPX: + case Command::PDNAX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + case Command::SREFX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXS); + break; + default: + reportFatal("Checker DDR3", + "Refresh can not follow " + commandToString(LastCmd)); + } + } + } + else + { + for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) + { + ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); + + if (lastCommand.isValidCommand()) + { + switch (lastCommand.getCommand()) + { + case Command::Precharge: + case Command::PrechargeAll: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRP); + break; + case Command::Activate: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRCD); + break; + case Command::ReadA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRTP + memSpec->tRP); + break; + case Command::WriteA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tWL + getWriteAccessTime() + + memSpec->tWR + memSpec->tRP); + break; + case Command::AutoRefresh: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRFC); + break; + case Command::PDNPX: + case Command::PDNAX: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXP); + break; + case Command::SREFX: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXS); + break; + default: + reportFatal("Checker DDR3", + "Refresh can not follow " + commandToString(LastCmd)); + } + } + } + } + state.bus.moveCommandToNextFreeSlot(command); + } +} + +/* +* ActivateChecker +*/ + +void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const +{ + ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::Activate, command.getBank()); + if (lastActivateOnBank.isValidCommand()) + command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); +} + +bool CheckerDDR3::satsfies_activateToActivate_differentBank(ScheduledCommand &command) const +{ + for (auto act : state.lastActivates) + { + sc_time time = act.first; + if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) + || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) + return false; + } + return true; + +} + +bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const +{ + /* + * there may be activates scheduled in the future, so emplace + * command in a copied set (not necessarily the last in time), + * and check if the n-act constraint holds for the whole set. + */ + if (state.lastActivates.size() >= memSpec->nActivate) + { + std::map lastActivates = state.lastActivates; + lastActivates.emplace(command.getStart(), command); + auto upper = lastActivates.begin(); + std::advance(upper, memSpec->nActivate); + auto lower = lastActivates.begin(); + + while (upper != lastActivates.end()) + { + if (upper->first - lower->first < memSpec->tNAW) + return false; + upper++; + lower++; + } + } + return true; +} + + +/* + * Read-Checker +*/ + +bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const +{ + for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) + { + if (collidesWithStrobeCommand_RD(read, strobeCommand)) + return true; + } + return false; +} + +bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, + ScheduledCommand &strobeCommand) const +{ + if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA) + { + return getDistance(read.getStart(), + strobeCommand.getStart()) < CasToCas(strobeCommand, read); + } + else if (strobeCommand.getCommand() == Command::Write || strobeCommand.getCommand() == Command::WriteA) + { + if (strobeCommand.getStart() >= read.getStart()) + return getDistance(read.getStart(), + strobeCommand.getStart()) < readToWrite(read, strobeCommand); + else + return getDistance(strobeCommand.getStart(), + read.getStart()) < writeToRead(strobeCommand, read); + } else { + reportFatal("Checker DDR3", + "Invalid strobeCommand in data strobe commands " + commandToString( + strobeCommand.getCommand())); + return true; + } + return false; +} + + +void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const +{ + ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank()); + if (lastSREFX.isValidCommand()) + read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL); +} + + +sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read) +{ + sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); + sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); + + if (write.getBankGroup() == read.getBankGroup()) + { + return memSpec->tWL + getWriteAccessTime() + memSpec->tWTR; + } +} + +/* CAS-CAS */ + +sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) +{ + if (firstCAS.getCommand() == Command::Read || firstCAS.getCommand() == Command::ReadA) + { + if (secondCAS.getCommand() == Command::Read || secondCAS.getCommand() == Command::ReadA) + { + if (firstCAS.getBankGroup() == secondCAS.getBankGroup()) + return std::max(memSpec->tCCD, getReadAccessTime()); + } + } + else if (firstCAS.getCommand() == Command::Write || firstCAS.getCommand() == Command::WriteA) + { + if (secondCAS.getCommand() == Command::Write || secondCAS.getCommand() == Command::WriteA) + { + if (firstCAS.getBankGroup() == secondCAS.getBankGroup()) + return std::max(memSpec->tCCD, getWriteAccessTime()); + } + } +} + +/* +* Write-Checker +*/ + +bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const +{ + for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) + { + if (collidesWithStrobeCommand_WR(write, strobeCommand)) + return true; + } + return false; +} + +bool CheckerDDR3::collidesWithStrobeCommand_WR(ScheduledCommand &write, + ScheduledCommand &strobeCommand) const +{ + if (strobeCommand.getCommand() == Command::Write || strobeCommand.getCommand() == Command::WriteA) + { + // TODO: Cast from sc_time to bool? + return getDistance(write.getStart(), + strobeCommand.getStart()) < CasToCas(strobeCommand, write); + } + else if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA) + { + if (strobeCommand.getStart() >= write.getStart()) + return getDistance(write.getStart(), + strobeCommand.getStart()) < writeToRead(write, strobeCommand); + else + return getDistance(strobeCommand.getStart(), + write.getStart()) < readToWrite(strobeCommand, write); + } + else + { + reportFatal("CheckerDDR3", "Invalid strobeCommand in data strobe commands " + + commandToString(strobeCommand.getCommand())); + return true; + } +} + + +sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write) +{ + sc_assert(read.getCommand() == Command::Read + || read.getCommand() == Command::ReadA); + sc_assert(write.getCommand() == Command::Write + || write.getCommand() == Command::WriteA); + + return memSpec->tRL + getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; +} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h new file mode 100644 index 00000000..dde7204d --- /dev/null +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h @@ -0,0 +1,59 @@ +#ifndef CHECKERDDR3_H +#define CHECKERDDR3_H + +#include "ICommandChecker.h" +#include "../../configuration/Configuration.h" +#include "../../../ControllerState.h" + +//Activate +class CheckerDDR3: public ICommandChecker +{ +public: + CheckerDDR3(const Configuration &config, + ControllerState &state) : config(config), state(state) + { + memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen."); + } + virtual ~CheckerDDR3() {} + + virtual void delayToSatisfyConstraints(ScheduledCommand &command) const + override; + +private: + static MemSpecDDR3 *memSpec; + + //Activate + void delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const; + bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const; + bool satisfies_nActivateWindow(ScheduledCommand &command) const; + + //PowerDown + sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; + + //used for Read + void delayToSatisfyDLL(ScheduledCommand &read) const; + bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; + bool collidesWithStrobeCommand_RD(ScheduledCommand &read, + ScheduledCommand &strobeCommand) const; + + //Write + bool collidesOnDataStrobe_WR(ScheduledCommand &write) const; + bool collidesWithStrobeCommand_WR(ScheduledCommand &write, + ScheduledCommand &strobeCommand) const; + + //handles WR->RD + static sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read); + + //RD->WR + static sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write); + + //CasToCas Commands (WR->WR)(RD->RD) + static sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS); + + const Configuration &config; + ControllerState &state;//TODO make const +}; + +#endif // CHECKERDDR3_H From c0d6231e264b0013453bcbe6fd3123192e6f49b7 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 25 Jun 2019 14:24:39 +0200 Subject: [PATCH 002/183] Adapted timings for CheckerDDR3. --- .../configuration/ConfigurationLoader.cpp | 543 +++++++++--------- .../controller/core/configuration/MemSpec.h | 4 +- .../core/scheduling/checker/CheckerDDR3.cpp | 29 +- .../core/scheduling/checker/CheckerDDR3.h | 2 +- 4 files changed, 296 insertions(+), 282 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 81fd0dba..a20c9e3e 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -167,315 +167,334 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *memspec config.memSpec->MemoryType = queryStringParameter(memspec, "memoryType"); } -void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *memspec) +void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) { - //MemArchitecture - XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); + MemSpecDDR3 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = 1; - config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 4; - config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec->NumberOfColumns = queryUIntParameter(architecture, + //MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->NumberOfBankGroups = 1; + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->nActivate = 4; + memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = true; - config.memSpec->termination = true; + memSpec->bitWidth = queryUIntParameter(architecture, "width"); + memSpec->DLL = true; + memSpec->termination = true; //MemTimings - XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); - sc_time clk = config.memSpec->clk; - config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); - config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->clk = FrequencyToClk(memSpec->clkMHz); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { - config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, - config.memSpec->tREFI); + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tREFI); } // Currents and Volatages: TODO Check if this is correct. - XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec->iDD02 = 0; - config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); - config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); - config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec->iDD62 = 0; - config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec->vDD2 = 0; + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD02 = 0; + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->iDD62 = 0; + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->vDD2 = 0; } -void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *memspec) +void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) { - //MemArchitecture - XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); + MemSpecDDR4 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = queryUIntParameter(architecture, + //MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); - config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 4; - config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec->NumberOfColumns = queryUIntParameter(architecture, + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->nActivate = 4; + memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = true; - config.memSpec->termination = true; + memSpec->bitWidth = queryUIntParameter(architecture, "width"); + memSpec->DLL = true; + memSpec->termination = true; //MemTimings - XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); - sc_time clk = config.memSpec->clk; - config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); - config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); - config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); - config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); - config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); - config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); - config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); - config.memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); - config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->clk = FrequencyToClk(memSpec->clkMHz); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); + memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); + memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); + memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); + memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); + memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { - config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, - config.memSpec->tRFC2, - config.memSpec->tRFC4, - config.memSpec->tREFI); + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tRFC2, + memSpec->tRFC4, + memSpec->tREFI); } // Currents and Volatages: - XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); - config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); - config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } // TODO: change timings for LPDDR4 -void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *memspec) +void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) { - //MemArchitecture: - XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); + MemSpecLPDDR4 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = 1; - config.memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 4; - config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec->NumberOfColumns = queryUIntParameter(architecture, + //MemArchitecture: + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->NumberOfBankGroups = 1; + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->nActivate = 4; + memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = false; // TODO: Correct? - config.memSpec->termination = true; // TODO: Correct? + memSpec->bitWidth = queryUIntParameter(architecture, "width"); + memSpec->DLL = false; // TODO: Correct? + memSpec->termination = true; // TODO: Correct? //MemTimings - XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); - sc_time clk = config.memSpec->clk; - config.memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); - config.memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); - // TODO: config.memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); - // TODO: config.memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); - config.memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->clk = FrequencyToClk(memSpec->clkMHz); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); + // TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); + // TODO: memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - config.memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { - config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, - config.memSpec->tREFI); + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tREFI); } // Currents and Volatages: - XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); - config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); - config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); - config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); - config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) { + MemSpecWideIO *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + //MemSpecification XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - config.memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - config.memSpec->NumberOfBankGroups = 1; - config.memSpec->NumberOfRanks = 1; - config.memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); - config.memSpec->nActivate = 2; - config.memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - config.memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - config.memSpec->NumberOfColumns = queryUIntParameter(architecture, + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->NumberOfBankGroups = 1; + memSpec->NumberOfRanks = 1; + memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->nActivate = 2; + memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); - config.memSpec->bitWidth = queryUIntParameter(architecture, "width"); - config.memSpec->DLL = false; - config.memSpec->termination = false; + memSpec->bitWidth = queryUIntParameter(architecture, "width"); + memSpec->DLL = false; + memSpec->termination = false; //MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - config.memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - config.memSpec->clk = FrequencyToClk(config.memSpec->clkMHz); - sc_time clk = config.memSpec->clk; - config.memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - config.memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - config.memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - config.memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - config.memSpec->tRRD_L = config.memSpec->tRRD_S; - config.memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - config.memSpec->tCCD_L = config.memSpec->tCCD_S; - config.memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - config.memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); - config.memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - config.memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - config.memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - config.memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - config.memSpec->tWTR_L = config.memSpec->tWTR_S; - config.memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - config.memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - config.memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - config.memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - config.memSpec->tXPDLL = config.memSpec->tXP; - config.memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - config.memSpec->tXSRDLL = config.memSpec->tXSR; - config.memSpec->tAL = clk * queryUIntParameter(timings, "AL"); - config.memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - config.memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->clk = FrequencyToClk(memSpec->clkMHz); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L = memSpec->tRRD_S; + memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L = memSpec->tCCD_S; + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L = memSpec->tWTR_S; + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXPDLL = memSpec->tXP; + memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSRDLL = memSpec->tXSR; + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - config.memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; ++i) { - config.memSpec->refreshTimings[Bank(i)] = RefreshTiming(config.memSpec->tRFC, - config.memSpec->tREFI); + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tREFI); } // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - config.memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - config.memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - config.memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); - config.memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); - config.memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - config.memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12"); - config.memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - config.memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2"); - config.memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); - config.memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02"); - config.memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - config.memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12"); - config.memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - config.memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2"); - config.memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - config.memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2"); - config.memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - config.memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2"); - config.memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - config.memSpec->iDD52 = queryDoubleParameter(powers, "idd52"); - config.memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - config.memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - config.memSpec->vDD = queryDoubleParameter(powers, "vdd"); - config.memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD52 = queryDoubleParameter(powers, "idd52"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); + memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 28503d19..a4ab8da5 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -168,7 +168,9 @@ struct MemSpec struct MemSpecDDR3 : public MemSpec { - + sc_time tCCD; + sc_time tRRD; + sc_time tWTR; }; struct MemSpecDDR4 : public MemSpec diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index e5d06288..cc851250 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -45,7 +45,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); + memSpec->tXSR); break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -207,7 +207,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); + memSpec->tXSR); break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -263,7 +263,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); + memSpec->tXSR); break; default: reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow " @@ -325,7 +325,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); + memSpec->tXSR); break; default: reportFatal("Checker DDR3", @@ -372,7 +372,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); + memSpec->tXSR); break; default: reportFatal("Checker DDR3", @@ -480,7 +480,7 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const { ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank()); if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL); + read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSRDLL); } @@ -489,10 +489,7 @@ sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); - if (write.getBankGroup() == read.getBankGroup()) - { - return memSpec->tWL + getWriteAccessTime() + memSpec->tWTR; - } + return memSpec->tWL + getWriteAccessTime() + memSpec->tWTR; } /* CAS-CAS */ @@ -502,19 +499,15 @@ sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &seco if (firstCAS.getCommand() == Command::Read || firstCAS.getCommand() == Command::ReadA) { if (secondCAS.getCommand() == Command::Read || secondCAS.getCommand() == Command::ReadA) - { - if (firstCAS.getBankGroup() == secondCAS.getBankGroup()) - return std::max(memSpec->tCCD, getReadAccessTime()); - } + return std::max(memSpec->tCCD, getReadAccessTime()); } else if (firstCAS.getCommand() == Command::Write || firstCAS.getCommand() == Command::WriteA) { if (secondCAS.getCommand() == Command::Write || secondCAS.getCommand() == Command::WriteA) - { - if (firstCAS.getBankGroup() == secondCAS.getBankGroup()) - return std::max(memSpec->tCCD, getWriteAccessTime()); - } + return std::max(memSpec->tCCD, getWriteAccessTime()); } + SC_REPORT_FATAL("CasToCas", "Exception reached"); + return SC_ZERO_TIME; } /* diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h index dde7204d..55e8c299 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h @@ -14,7 +14,7 @@ public: { memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen."); + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); } virtual ~CheckerDDR3() {} From 51e6ebfed0e8c91d1acb80095cc9e07823a72ab5 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 25 Jun 2019 15:56:22 +0200 Subject: [PATCH 003/183] CheckerDDR3 works, timings may still be wrong. --- .../MICRON_6Gb_LPDDR4-3200_32bit_A.xml | 98 +++++++++++++++++++ .../src/controller/core/ControllerCore.cpp | 5 + .../src/controller/core/ControllerCore.h | 1 + .../core/scheduling/checker/CheckerDDR3.cpp | 6 +- .../core/scheduling/checker/CheckerDDR3.h | 10 +- 5 files changed, 112 insertions(+), 8 deletions(-) create mode 100644 DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml new file mode 100644 index 00000000..506e20b7 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.xml @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 73905e3e..58c75d6f 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -52,6 +52,7 @@ #include "../../common/dramExtensions.h" #include "../../common/utils.h" #include "timingCalculations.h" +#include "scheduling/checker/CheckerDDR3.h" #include "powerdown/PowerDownManager.h" #include "powerdown/PowerDownManagerTimeout.h" @@ -85,6 +86,8 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, commandChecker[Command::PDNPX] = commandChecker[Command::PDNA]; commandChecker[Command::SREFX] = commandChecker[Command::PDNA]; + timingChecker = new CheckerDDR3(config, *state); + if (config.RowGranularRef) { refreshManager = new RGR("RGR", *this); } else { @@ -123,6 +126,7 @@ ControllerCore::~ControllerCore() delete commandChecker[Command::Write]; delete commandChecker[Command::AutoRefresh]; delete commandChecker[Command::PDNA]; + delete timingChecker; delete refreshManager; delete powerDownManager; delete state; @@ -270,6 +274,7 @@ std::vector ControllerCore::getFreeBanks() ICommandChecker &ControllerCore::getCommandChecker(Command command) { return *getElementFromMap(commandChecker, command); + //return *timingChecker; } void ControllerCore::printDebugMessage(string message) diff --git a/DRAMSys/library/src/controller/core/ControllerCore.h b/DRAMSys/library/src/controller/core/ControllerCore.h index f0b7dc99..7a07ae3f 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.h +++ b/DRAMSys/library/src/controller/core/ControllerCore.h @@ -85,6 +85,7 @@ private: ScheduledCommand schedule(Command command, sc_time start, tlm::tlm_generic_payload &payload); std::map commandChecker; + ICommandChecker *timingChecker; void printDebugMessage(string message); }; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index cc851250..dda4e5bc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -484,7 +484,7 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const } -sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read) +sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const { sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); @@ -494,7 +494,7 @@ sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read /* CAS-CAS */ -sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) +sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const { if (firstCAS.getCommand() == Command::Read || firstCAS.getCommand() == Command::ReadA) { @@ -551,7 +551,7 @@ bool CheckerDDR3::collidesWithStrobeCommand_WR(ScheduledCommand &write, } -sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write) +sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const { sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h index 55e8c299..37c26250 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h @@ -6,7 +6,7 @@ #include "../../../ControllerState.h" //Activate -class CheckerDDR3: public ICommandChecker +class CheckerDDR3 : public ICommandChecker { public: CheckerDDR3(const Configuration &config, @@ -22,7 +22,7 @@ public: override; private: - static MemSpecDDR3 *memSpec; + MemSpecDDR3 *memSpec; //Activate void delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const; @@ -44,13 +44,13 @@ private: ScheduledCommand &strobeCommand) const; //handles WR->RD - static sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read); + sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const; //RD->WR - static sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write); + sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const; //CasToCas Commands (WR->WR)(RD->RD) - static sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS); + sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const; const Configuration &config; ControllerState &state;//TODO make const From 2d08d48f8101f1de23a5ed6d7570138390602c9c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 25 Jun 2019 19:49:03 +0200 Subject: [PATCH 004/183] Bugfix: Wrong header included. Removed redundant main function. --- .../src/controller/core/scheduling/checker/CheckerDDR3.cpp | 2 +- DRAMSys/simulator/main.cpp | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index dda4e5bc..e59a403c 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -8,7 +8,7 @@ #include "../../timingCalculations.h" #include "../../../../common/DebugManager.h" #include "../../../Command.h" -#include "../../../../common/Utils.h" +#include "../../../../common/utils.h" using namespace std; diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 956f373e..ca6e6ead 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -53,11 +53,6 @@ string pathOfFile(string file) return file.substr(0, file.find_last_of('/')); } -int main(int argc, char **argv) -{ - return sc_main(argc, argv); -} - int sc_main(int argc, char **argv) { sc_set_time_resolution(1, SC_PS); From e462287d7c5a08524c21d7b56fd1af7799ae93a5 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 25 Jun 2019 22:40:18 +0200 Subject: [PATCH 005/183] Split up timings. --- .../controller/core/configuration/MemSpec.h | 84 ++++++++++++++----- 1 file changed, 61 insertions(+), 23 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index a4ab8da5..4a7bdd2e 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -73,7 +73,7 @@ struct MemSpec std::string MemoryType = "not defined."; unsigned int NumberOfBanks; - unsigned int NumberOfBankGroups; + unsigned int NumberOfBankGroups; unsigned int NumberOfRanks; unsigned int BurstLength; unsigned int nActivate; @@ -87,24 +87,29 @@ struct MemSpec // Memspec Variables: double clkMHz; sc_time clk; - sc_time tRP; //precharge-time (pre -> act same bank - sc_time tRTP; //Read to precharge - sc_time tRCD; //act -> read/write - sc_time tRL; //read latency (read command start to data strobe) - sc_time tWL; //write latency - sc_time tWR; //write recovery (write to precharge) - sc_time tCKESR; //min time in sref - sc_time tCKE; //min time in pdna or pdnp + sc_time tAL; // additive delay (delayed execution in dram) + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + //sc_time tCL; // unused? + sc_time tDQSCK; + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXSR; // min delay to row access command after srefx + + sc_time tRP; //precharge-time (pre -> act same bank sc_time tRFC; //min ref->act delay 1X mode sc_time tRFC2; //min ref->act delay 2X mode sc_time tRFC4; //min ref->act delay 4X mode - sc_time tREFI; //auto refresh must be issued at an average periodic interval tREFI - + sc_time tREFI; // auto refresh must be issued at an average periodic interval tREFI // TODO: move to specific memspecs sc_time tRPAB; //precharge-all time only for LPDDR4 - sc_time tRAS; //active-time (act -> pre same bank) - sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank) sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd sc_time tCCD_L; sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group) @@ -112,12 +117,8 @@ struct MemSpec sc_time tNAW; //n activate window sc_time tWTR_S; //write to read (different bank group) sc_time tWTR_L; //.. (same bank group) - sc_time tXP; //min delay to row access command after pdnpx pdnax - sc_time tXPDLL; //min delay to row access command after pdnpx pdnax for dll commands - sc_time tXSR; //min delay to row access command after srefx - sc_time tXSRDLL; //min delay to row access command after srefx for dll commands - sc_time tAL; //additive delay (delayed execution in dram) - sc_time tDQSCK; + sc_time tXPDLL; // min delay to row access command after pdnpx pdnax for dll commands + sc_time tXSRDLL; // min delay to row access command after srefx for dll commands // Currents and Voltages: double iDD0; @@ -169,23 +170,60 @@ struct MemSpec struct MemSpecDDR3 : public MemSpec { sc_time tCCD; - sc_time tRRD; +// sc_time tFAW; sc_time tWTR; +// sc_time tREFI; +// sc_time tRFC; +// sc_time tRP; + sc_time tRRD; +// sc_time tXPDLL; +// sc_time tXSDLL; }; struct MemSpecDDR4 : public MemSpec { - +// sc_time tCCD_S; +// sc_time tCCD_L; +// sc_time tFAW; +// sc_time tWTR_S; +// sc_time tWTR_L; +// sc_time tREFI; +// sc_time tRFC; +// sc_time tRP; +// sc_time tRRD_S; +// sc_time tRRD_L; +// sc_time tXPDLL; +// sc_time tXSDLL; }; struct MemSpecWideIO : public MemSpec { - +// sc_time tCCD; +// sc_time tWTR; +// sc_time tTAW; +// sc_time tREFI; +// sc_time tRFC; +// sc_time tRP; +// sc_time tRRD; +// sc_time tXPDLL; +// sc_time tXSDLL; }; struct MemSpecLPDDR4 : public MemSpec { - +// sc_time tCCD; +// sc_time tCCDMW; +// sc_time tESCKE; +// sc_time tFAW; +// sc_time tWTR; +// sc_time tPPD; +// sc_time tREFIAB; +// sc_time tREFIPB; +// sc_time tRFCAB; +// sc_time tRFCPB; +// sc_time tRPAB; +// sc_time tRPPB; +// sc_time tRRD; }; #endif // MEMSPEC_H From ac4e4c778369ddcd517115f76e2a1642eab04241 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 27 Jun 2019 16:02:24 +0200 Subject: [PATCH 006/183] Moved specific timing calculation functions to MemSpecs. --- DRAMSys/library/library.pro | 5 +- .../src/controller/core/ControllerCore.cpp | 2 +- .../controller/core/configuration/MemSpec.cpp | 133 +++++++++++++++++ .../controller/core/configuration/MemSpec.h | 25 +++- .../core/powerdown/PowerDownManager.cpp | 7 +- .../powerdown/PowerDownManagerBankwise.cpp | 7 +- .../powerdown/PowerDownManagerTimeout.cpp | 6 +- .../PowerDownManagerTimeoutBankwise.cpp | 5 +- .../core/refresh/RefreshManager.cpp | 8 +- .../core/refresh/RefreshManagerBankwise.cpp | 6 +- .../core/scheduling/ScheduledCommand.cpp | 6 +- .../core/scheduling/checker/ActBChecker.cpp | 4 +- .../scheduling/checker/ActivateChecker.cpp | 4 +- .../core/scheduling/checker/CheckerDDR3.cpp | 27 ++-- .../scheduling/checker/PowerDownChecker.cpp | 6 +- .../core/scheduling/checker/PreBChecker.cpp | 2 +- .../checker/PrechargeAllChecker.cpp | 4 +- .../scheduling/checker/PrechargeChecker.cpp | 2 +- .../core/scheduling/checker/ReadChecker.cpp | 4 +- .../scheduling/checker/RefreshChecker.cpp | 4 +- .../core/scheduling/checker/WriteChecker.cpp | 4 +- .../controller/core/timingCalculations.cpp | 78 ---------- .../src/controller/core/timingCalculations.h | 5 - DRAMSys/library/src/simulation/DRAMSys.h | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 27 ++-- .../library/src/simulation/DramRecordable.cpp | 7 +- .../library/src/simulation/DramRecordable.h | 1 - DRAMSys/library/src/simulation/DramWideIO.cpp | 24 ++-- .../library/src/simulation/RecordableDram.cpp | 135 ------------------ .../library/src/simulation/RecordableDram.h | 78 ---------- 30 files changed, 249 insertions(+), 379 deletions(-) create mode 100644 DRAMSys/library/src/controller/core/configuration/MemSpec.cpp delete mode 100644 DRAMSys/library/src/simulation/RecordableDram.cpp delete mode 100644 DRAMSys/library/src/simulation/RecordableDram.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index c8a65529..48323902 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -137,7 +137,6 @@ SOURCES += \ src/controller/RecordableController.cpp \ src/common/AddressDecoder.cpp \ src/simulation/Dram.cpp \ - src/simulation/RecordableDram.cpp \ src/simulation/Arbiter.cpp \ src/common/CongenAddressDecoder.cpp \ src/common/XmlAddressDecoder.cpp \ @@ -148,7 +147,8 @@ SOURCES += \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ - src/controller/core/scheduling/checker/CheckerDDR3.cpp + src/controller/core/scheduling/checker/CheckerDDR3.cpp \ + src/controller/core/configuration/MemSpec.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -218,7 +218,6 @@ HEADERS += \ src/simulation/IArbiter.h \ src/simulation/SimpleArbiter.h \ src/controller/RecordableController.h \ - src/simulation/RecordableDram.h \ src/common/AddressDecoder.h \ src/common/CongenAddressDecoder.h \ src/common/XmlAddressDecoder.h \ diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 58c75d6f..81db0267 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -190,7 +190,7 @@ ScheduledCommand ControllerCore::schedule(Command command, sc_time start, { ControllerCore::printDebugMessage("Scheduling command " + commandToString( command) + " on " + DramExtension::getBank(payload).toString()); - sc_time executionTime = getExecutionTime(command, payload); + sc_time executionTime = Configuration::getInstance().memSpec->getExecutionTime(command, payload); ScheduledCommand scheduledCommand(command, start, executionTime, DramExtension::getExtension(payload)); getCommandChecker(command).delayToSatisfyConstraints(scheduledCommand); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp new file mode 100644 index 00000000..fddaf10a --- /dev/null +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpec.h" + +#include +#include +#include "../../Command.h" +#include "Configuration.h" + +sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const +{ + if (command == Command::PDNA || command == Command::PDNP) + return tCKE; + else if (command == Command::SREF) + return tCKESR; + else + { + SC_REPORT_FATAL("getMinimalExecutionTime", + "command is not know or command has a fixed execution time"); + return SC_ZERO_TIME; + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const +{ + if (command == Command::PreB) + return Configuration::getInstance().getTrpb(); + else if (command == Command::Precharge || command == Command::PrechargeAll) + return tRP; + else if (command == Command::ActB) + return tRCD; + else if (command == Command::Activate) + return tRCD; + else if (command == Command::Read) + return tRL + getReadAccessTime(); + else if (command == Command::ReadA) + return tRTP + tRP; + else if (command == Command::Write) + return tWL + getWriteAccessTime(); + else if (command == Command::WriteA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::PrechargeAll) + return tRP; + else if (command == Command::AutoRefresh) + { + return getElementFromMap(refreshTimings, + DramExtension::getExtension(payload).getBank()).tRFC; + } + else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) + return clk; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + +sc_time MemSpecDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const +{ + if (command == Command::PreB) + return Configuration::getInstance().getTrpb(); + else if (command == Command::Precharge || command == Command::PrechargeAll) + return tRP; + else if (command == Command::ActB) + return tRCD; + else if (command == Command::Activate) + return tRCD; + else if (command == Command::Read) + return tRL + getReadAccessTime(); + else if (command == Command::ReadA) + return tRTP + tRP; + else if (command == Command::Write) + return tWL + getWriteAccessTime(); + else if (command == Command::WriteA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::PrechargeAll) + return tRP; + else if (command == Command::AutoRefresh) + { + if (Configuration::getInstance().getRefMode() == 4) + return getElementFromMap(refreshTimings, + DramExtension::getExtension(payload).getBank()).tRFC4; + else if (Configuration::getInstance().getRefMode() == 2) + return getElementFromMap(refreshTimings, + DramExtension::getExtension(payload).getBank()).tRFC2; + else + return getElementFromMap(refreshTimings, + DramExtension::getExtension(payload).getBank()).tRFC; + } + else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) + return clk; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 4a7bdd2e..8900b420 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -41,6 +41,7 @@ #include #include #include "../../../common/dramExtensions.h" +#include "../../Command.h" struct RefreshTiming { @@ -57,6 +58,21 @@ struct RefreshTiming struct MemSpec { + sc_time getWriteAccessTime() const + { + return clk * (BurstLength / DataRate); + } + + sc_time getReadAccessTime() const + { + return clk * (BurstLength / DataRate); + } + + // Returns the minimum execution time for commands that have a variable execution time + sc_time getMinExecutionTimeForPowerDownCmd(Command command) const; + + virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; + const std::vector &getBanks() const { static std::vector banks; @@ -103,7 +119,7 @@ struct MemSpec sc_time tXSR; // min delay to row access command after srefx - sc_time tRP; //precharge-time (pre -> act same bank + sc_time tRP; // precharge-time (pre -> act same bank) sc_time tRFC; //min ref->act delay 1X mode sc_time tRFC2; //min ref->act delay 2X mode sc_time tRFC4; //min ref->act delay 4X mode @@ -147,8 +163,8 @@ struct MemSpec double vDD2; - std::map - refreshTimings;//ensure that map is populated completely in memspecloader + std::map refreshTimings; + //ensure that map is populated completely in memspecloader //act and read/write commands remain for this timespan in history sc_time tActHistory() @@ -194,6 +210,9 @@ struct MemSpecDDR4 : public MemSpec // sc_time tRRD_L; // sc_time tXPDLL; // sc_time tXSDLL; + + // Returns the execution time for commands that have a fixed execution time + sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; }; struct MemSpecWideIO : public MemSpec diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp index d5281e05..edc72584 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp @@ -87,7 +87,8 @@ void PowerDownManager::sleep(Bank /*bank*/, sc_time time) } Command cmd = IPowerDownManager::getSleepCommand(state); - ScheduledCommand pdn(cmd, time, getMinExecutionTimeForPowerDownCmd(cmd), + ScheduledCommand pdn(cmd, time, + Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), DramExtension::getExtension(powerDownPayloads[Bank(0)])); controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); @@ -110,7 +111,7 @@ void PowerDownManager::wakeUp(Bank bank, sc_time time) setPowerDownState(PowerDownState::Awake); } else if (isInPowerDown()) { //Request wakes up power down Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); - ScheduledCommand pdn(cmd, time, getExecutionTime(cmd, + ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, powerDownPayloads[Bank(0)]), DramExtension::getExtension(powerDownPayloads[Bank(0)])); controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); @@ -140,7 +141,7 @@ void PowerDownManager::wakeUpForRefresh(Bank /*bank*/, sc_time time) if (isInPowerDown()) { Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); - ScheduledCommand pdn(cmd, time, getExecutionTime(cmd, + ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, powerDownPayloads[Bank(0)]), DramExtension::getExtension(powerDownPayloads[Bank(0)])); diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp index a73d7674..c0175a61 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp @@ -76,7 +76,8 @@ void PowerDownManagerBankwise::sleep(Bank bank, sc_time time) } Command cmd = IPowerDownManager::getSleepCommand(state); - ScheduledCommand pdn(cmd, time, getMinExecutionTimeForPowerDownCmd(cmd), + ScheduledCommand pdn(cmd, time, + Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), DramExtension::getExtension(payload)); controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); @@ -103,7 +104,7 @@ void PowerDownManagerBankwise::wakeUp(Bank bank, sc_time time) // Request wake up from power down. A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); // Mount the command to be scheduled - ScheduledCommand pdnExit(pdnExitCmd, time, getExecutionTime(pdnExitCmd, + ScheduledCommand pdnExit(pdnExitCmd, time, Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, powerDownPayloads[bank]), DramExtension::getExtension(powerDownPayloads[bank])); // Ensure that time constraints are respected controllerCore.getCommandChecker(pdnExitCmd).delayToSatisfyConstraints(pdnExit); @@ -140,7 +141,7 @@ void PowerDownManagerBankwise::wakeUpForRefresh(Bank bank, sc_time time) // A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); // Get the execution time for this request - sc_time executionTime = getExecutionTime(pdnExitCmd, powerDownPayloads[bank]); + sc_time executionTime = Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, powerDownPayloads[bank]); // Mount the command to be scheduled ScheduledCommand pdnExit(pdnExitCmd, time, executionTime, DramExtension::getExtension(powerDownPayloads[bank])); diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp index 997e9c37..08ce7c0a 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp @@ -91,7 +91,8 @@ void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) } else { // PowerDownMode == TimeoutSREF if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { ScheduledCommand prechargeAllMaster(Command::PrechargeAll, time, - getExecutionTime(Command::PrechargeAll, powerDownPayloads[Bank(0)]), + Configuration::getInstance().memSpec->getExecutionTime( + Command::PrechargeAll, powerDownPayloads[Bank(0)]), DramExtension::getExtension(powerDownPayloads[Bank(0)])); controllerCore.getCommandChecker( @@ -116,7 +117,8 @@ void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) } Command cmd = IPowerDownManager::getSleepCommand(newState); - ScheduledCommand pdn(cmd, time, getMinExecutionTimeForPowerDownCmd(cmd), + ScheduledCommand pdn(cmd, time, + Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), DramExtension::getExtension(powerDownPayloads[Bank(0)])); controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp index cd743e02..60142555 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp @@ -91,7 +91,7 @@ void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) } else { // PowerDownMode == TimeoutSREF if (controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)) { ScheduledCommand precharge(Command::Precharge, time, - getExecutionTime(Command::Precharge, powerDownPayloads[bank]), + Configuration::getInstance().memSpec->getExecutionTime(Command::Precharge, powerDownPayloads[bank]), DramExtension::getExtension(powerDownPayloads[bank])); controllerCore.getCommandChecker(Command::Precharge).delayToSatisfyConstraints( @@ -111,7 +111,8 @@ void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) Command cmd = IPowerDownManager::getSleepCommand(newState); - ScheduledCommand pdn(cmd, time, getMinExecutionTimeForPowerDownCmd(cmd), + ScheduledCommand pdn(cmd, time, + Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), DramExtension::getExtension(powerDownPayloads[bank])); controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index b088ca97..c3bf0b8a 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -45,7 +45,7 @@ using namespace tlm; RefreshManager::RefreshManager(sc_module_name, - ControllerCore &controller) : controllerCore(controller), + ControllerCore &controller) : controllerCore(controller), timing(controller.config.memSpec->refreshTimings[Bank(0)]) { auto m = controllerCore.config.getRefMode(); @@ -99,7 +99,8 @@ bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { pre = true; ScheduledCommand prechargeAllMaster(Command::PrechargeAll, time, - getExecutionTime(Command::PrechargeAll, refreshPayloads[Bank(0)]), + Configuration::getInstance().memSpec->getExecutionTime( + Command::PrechargeAll, refreshPayloads[Bank(0)]), refreshPayloads[Bank(0)]); controllerCore.getCommandChecker( Command::PrechargeAll).delayToSatisfyConstraints(prechargeAllMaster); @@ -116,7 +117,8 @@ bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) //Otherwise just the AutoRefresh command is scheduled. ScheduledCommand refreshAllMaster(Command::AutoRefresh, time, - getExecutionTime(Command::AutoRefresh, refreshPayloads[Bank(0)]), + Configuration::getInstance().memSpec->getExecutionTime( + Command::AutoRefresh, refreshPayloads[Bank(0)]), DramExtension::getExtension(refreshPayloads[Bank(0)])); controllerCore.getCommandChecker( Command::AutoRefresh).delayToSatisfyConstraints(refreshAllMaster); diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index c53f779b..be639850 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -102,7 +102,8 @@ bool RefreshManagerBankwise::doRefresh(tlm::tlm_generic_payload &payload, extension.getBank())) { pre = true; ScheduledCommand precharge(Command::Precharge, time, - getExecutionTime(Command::Precharge, refreshPayload), extension); + Configuration::getInstance().memSpec->getExecutionTime( + Command::Precharge, refreshPayload), extension); controllerCore.getCommandChecker(Command::Precharge).delayToSatisfyConstraints( precharge); controllerCore.state->change(precharge); @@ -110,7 +111,8 @@ bool RefreshManagerBankwise::doRefresh(tlm::tlm_generic_payload &payload, } ScheduledCommand refresh(Command::AutoRefresh, time, - getExecutionTime(Command::AutoRefresh, refreshPayload), extension); + Configuration::getInstance().memSpec->getExecutionTime( + Command::AutoRefresh, refreshPayload), extension); controllerCore.getCommandChecker( Command::AutoRefresh).delayToSatisfyConstraints(refresh); controllerCore.state->change(refresh); diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index 4207b9ff..43c4dd31 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -38,6 +38,7 @@ #include "../timingCalculations.h" #include "../../../common/utils.h" #include "../configuration/Configuration.h" +//#include "../configuration/MemSpec.h" bool ScheduledCommand::isNoCommand() const { @@ -131,9 +132,10 @@ TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const if (getCommand() == Command::Read || getCommand() == Command::ReadA) { return TimeInterval(getStart() + timings->tRL, - getStart() + timings->tRL + getReadAccessTime()); + getStart() + timings->tRL + timings->getReadAccessTime()); } else { return TimeInterval(getStart() + timings->tWL - timings->clk / 2, - getStart() + timings->tWL + getWriteAccessTime() - timings->clk / 2); + getStart() + timings->tWL + timings->getWriteAccessTime() + - timings->clk / 2); } } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 16557602..0a57bfa3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -59,8 +59,8 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const config.memSpec->tRTP + config.memSpec->tRP); } else if (lcb.getCommand() == Command::WriteA) { cmd.establishMinDistanceFromStart(lcb.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP); + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + + config.memSpec->tWR + config.memSpec->tRP); } else if (lcb.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index f2bb8033..49cfdbeb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -62,8 +62,8 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP); + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + + config.memSpec->tWR + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index e59a403c..183e1fdb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -9,6 +9,7 @@ #include "../../../../common/DebugManager.h" #include "../../../Command.h" #include "../../../../common/utils.h" +//#include "../../configuration/MemSpec.h" using namespace std; @@ -35,7 +36,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP); break; case Command::PDNPX: @@ -148,7 +149,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::Write: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->tWR - + getWriteAccessTime()); + + memSpec->getWriteAccessTime()); break; case Command::PDNAX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -188,12 +189,12 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::Write: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR); break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP); break; case Command::ReadA: @@ -239,17 +240,17 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::Read: case Command::ReadA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRL + getReadAccessTime() + memSpec->tRL + memSpec->getReadAccessTime() + memSpec->clk); break; case Command::Write: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR); break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->clk); break; case Command::AutoRefresh: @@ -311,7 +312,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP); break; case Command::AutoRefresh: @@ -358,7 +359,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + getWriteAccessTime() + memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP); break; case Command::AutoRefresh: @@ -489,7 +490,7 @@ sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); - return memSpec->tWL + getWriteAccessTime() + memSpec->tWTR; + return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; } /* CAS-CAS */ @@ -499,12 +500,12 @@ sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &seco if (firstCAS.getCommand() == Command::Read || firstCAS.getCommand() == Command::ReadA) { if (secondCAS.getCommand() == Command::Read || secondCAS.getCommand() == Command::ReadA) - return std::max(memSpec->tCCD, getReadAccessTime()); + return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); } else if (firstCAS.getCommand() == Command::Write || firstCAS.getCommand() == Command::WriteA) { if (secondCAS.getCommand() == Command::Write || secondCAS.getCommand() == Command::WriteA) - return std::max(memSpec->tCCD, getWriteAccessTime()); + return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); } SC_REPORT_FATAL("CasToCas", "Exception reached"); return SC_ZERO_TIME; @@ -558,5 +559,5 @@ sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); - return memSpec->tRL + getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; + return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 723c74ec..54317c6e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -47,11 +47,11 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, sc_time constraint; if (lastCmd == Command::Read || lastCmd == Command::ReadA) { - constraint = config.memSpec->tRL + getReadAccessTime() + config.memSpec->clk; + constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; } else if (lastCmd == Command::Write) { - constraint = config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR; + constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; } else if (lastCmd == Command::WriteA) { - constraint = config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->clk; } else if (lastCmd == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 44e23882..95be380a 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -55,7 +55,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRTP); } else if (lastCmd.getCommand() == Command::Write) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR); + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); } else if (lastCmd.getCommand() == Command::PDNAX) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP); } else { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index f6ee06d9..0b6d5867 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -64,10 +64,10 @@ const config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::Write) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR); + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); } else if (lastCommand.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index 75a8ebdc..9ef70882 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -64,7 +64,7 @@ const config.memSpec->tRTP); } else if (lastCommand.getCommand() == Command::Write) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR); + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); } else if (lastCommand.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommand.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 06a121a6..9d0af4aa 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -126,7 +126,7 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? config->tCCD_L : config->tCCD_S; - return max(tCCD, getReadAccessTime()); + return max(tCCD, config->getReadAccessTime()); } sc_time ReadChecker::writeToRead(ScheduledCommand &write, @@ -140,6 +140,6 @@ sc_time ReadChecker::writeToRead(ScheduledCommand &write, MemSpec *config = Configuration::getInstance().memSpec; sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L : config->tWTR_S; - return config->tWL + getWriteAccessTime() + tWTR; + return config->tWL + config->getWriteAccessTime() + tWTR; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index eea8f763..ad964f5e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -56,7 +56,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP); } else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX) { @@ -88,7 +88,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tRTP + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP); } else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index 38eafdaa..58bd856e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -117,7 +117,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? config->tCCD_L : config->tCCD_S; - return max(tCCD, getWriteAccessTime()); + return max(tCCD, config->getWriteAccessTime()); } sc_time WriteChecker::readToWrite(ScheduledCommand &read __attribute__(( @@ -129,6 +129,6 @@ sc_time WriteChecker::readToWrite(ScheduledCommand &read __attribute__(( || write.getCommand() == Command::WriteA); MemSpec *config = Configuration::getInstance().memSpec; - return config->tRL + getReadAccessTime() - config->tWL + config->clk * 2; + return config->tRL + config->getReadAccessTime() - config->tWL + config->clk * 2; } diff --git a/DRAMSys/library/src/controller/core/timingCalculations.cpp b/DRAMSys/library/src/controller/core/timingCalculations.cpp index 077e5d22..2585ea4a 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.cpp +++ b/DRAMSys/library/src/controller/core/timingCalculations.cpp @@ -66,87 +66,9 @@ const sc_time clkAlign(sc_time time, Alignment alignment) return floor(time / clk) * clk; } -// Returns the execution time for commands that have a fixed execution time -sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) -{ - MemSpec *config = Configuration::getInstance().memSpec; - - if (command == Command::PreB) { - return Configuration::getInstance().getTrpb(); - } else if (command == Command::Precharge || command == Command::PrechargeAll) { - return config->tRP; - } else if (command == Command::ActB) { - return config->tRCD; - } else if (command == Command::Activate) { - return config->tRCD; - } else if (command == Command::Read) { - return config->tRL + getReadAccessTime(); - } else if (command == Command::ReadA) { - return config->tRTP + config->tRP; - } else if (command == Command::Write) { - return config->tWL + getWriteAccessTime(); - } else if (command == Command::WriteA) { - return config->tWL + getWriteAccessTime() + config->tWR + config->tRP; - } else if (command == Command::PrechargeAll) { - return config->tRP; - } else if (command == Command::AutoRefresh) { - if (Configuration::getInstance().getRefMode() == 4) - return getElementFromMap(config->refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC4; - else if (Configuration::getInstance().getRefMode() == 2) - return getElementFromMap(config->refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC2; - else - return getElementFromMap(config->refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC; - } else if (command == Command::PDNAX || command == Command::PDNPX - || command == Command::SREFX) { - return config->clk; - } else { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } -} - -// Returns the minimum execution time for commands that have a variable execution time -sc_time getMinExecutionTimeForPowerDownCmd(Command command) -{ - MemSpec *config = Configuration::getInstance().memSpec; - if (command == Command::PDNA || command == Command::PDNP) { - return config->tCKE; - } else if (command == Command::SREF) { - return config->tCKESR; - } else { - SC_REPORT_FATAL("getMinimalExecutionTime", - "command is not know or command has a fixed execution time"); - return SC_ZERO_TIME; - } -} - bool isClkAligned(sc_time time, sc_time clk) { return !((time / clk) - ceil(time / clk)); } -sc_time getReadAccessTime() -{ - Configuration &config = Configuration::getInstance(); - return (config.memSpec->BurstLength / config.memSpec->DataRate) * - config.memSpec->clk; -} - -sc_time getWriteAccessTime() -{ - Configuration &config = Configuration::getInstance(); - - if (config.memSpec->DataRate == 1) { - return config.memSpec->clk * (config.memSpec->BurstLength); - } else { - return config.memSpec->clk * (config.memSpec->BurstLength / - config.memSpec->DataRate); - } -} - - diff --git a/DRAMSys/library/src/controller/core/timingCalculations.h b/DRAMSys/library/src/controller/core/timingCalculations.h index e9f80d4e..4e8966ee 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.h +++ b/DRAMSys/library/src/controller/core/timingCalculations.h @@ -42,11 +42,6 @@ #include "../../common/dramExtensions.h" #include "../Command.h" -sc_time getMinExecutionTimeForPowerDownCmd(Command command); -sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload); - -sc_time getReadAccessTime(); -sc_time getWriteAccessTime(); sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint); diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 288820e8..fa26386b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -42,7 +42,7 @@ #include #include -#include "RecordableDram.h" +#include "DramRecordable.h" #include "Arbiter.h" #include "TraceGenerator.h" #include "ReorderBuffer.h" diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index cc391efc..65a7ebbe 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -202,40 +202,41 @@ Dram::~Dram() tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { + MemSpec *memSpec = Configuration::getInstance().memSpec; + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); + unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); if (phase == BEGIN_PREB) { DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + getExecutionTime(Command::PreB, + sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PreB, payload)); } else if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, - delay + getExecutionTime(Command::PrechargeAll, payload)); + delay + memSpec->getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACTB) { DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + getExecutionTime(Command::ActB, + sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ActB, payload)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::Activate, payload)); } else if (phase == BEGIN_WR) @@ -247,7 +248,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::Write, payload)); } else if (phase == BEGIN_RD) @@ -259,7 +260,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::Read, payload)); } else if (phase == BEGIN_WRA) @@ -271,7 +272,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) @@ -283,20 +284,20 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); } else if (phase == BEGIN_REFB) { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index cc24e5a2..56c5e27e 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -65,17 +65,18 @@ template tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { + MemSpec *memSpec = Configuration::getInstance().memSpec; // Recording time used by the traceAnalyzer sc_time recTime = sc_time_stamp() + delay; // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += getExecutionTime(Command::PDNAX, payload); + recTime += memSpec->getExecutionTime(Command::PDNAX, payload); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += getExecutionTime(Command::PDNPX, payload); + recTime += memSpec->getExecutionTime(Command::PDNPX, payload); else if (phase == END_SREF || phase == END_SREFB) - recTime += getExecutionTime(Command::SREFX, payload); + recTime += memSpec->getExecutionTime(Command::SREFX, payload); unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index 59d6873a..2859b749 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -40,7 +40,6 @@ #include #include "DramDDR3.h" #include "DramDDR4.h" -#include "RecordableDram.h" #include "../common/TlmRecorder.h" using namespace tlm; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 3f69ca7a..9b3655cb 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -72,6 +72,8 @@ DramWideIO::~DramWideIO() tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { + MemSpec *memSpec = Configuration::getInstance().memSpec; + unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: @@ -81,25 +83,25 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PREB) { DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + getExecutionTime(Command::PreB, + sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PreB, payload)); } else if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, - delay + getExecutionTime(Command::PrechargeAll, payload)); + delay + memSpec->getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACTB) { DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + getExecutionTime(Command::ActB, + sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ActB, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -108,7 +110,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::Activate, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); @@ -128,7 +130,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::Write, payload)); } else if (phase == BEGIN_RD) @@ -144,7 +146,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::Read, payload)); } else if (phase == BEGIN_WRA) @@ -160,7 +162,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) @@ -176,14 +178,14 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -193,7 +195,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) diff --git a/DRAMSys/library/src/simulation/RecordableDram.cpp b/DRAMSys/library/src/simulation/RecordableDram.cpp deleted file mode 100644 index 699f0a74..00000000 --- a/DRAMSys/library/src/simulation/RecordableDram.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2018, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Felipe S. Prado - * Matthias Jung - */ - -#include "RecordableDram.h" - -using namespace tlm; - -RecordableDram::RecordableDram(sc_module_name name, TlmRecorder *tlmRecorder) - : Dram(name), tlmRecorder(tlmRecorder) -{ - // Create a thread that is triggered every $powerWindowSize - // to generate a Power over Time plot in the Trace analyzer: - if (Configuration::getInstance().PowerAnalysis - && Configuration::getInstance().EnableWindowing) - SC_THREAD(powerWindow); -} - -RecordableDram::~RecordableDram() -{ - if (Configuration::getInstance().PowerAnalysis) - { - // Obtain the residual energy which was not covered by - // previous windows - DRAMPower->calcEnergy(); - recordPower(); - } - tlmRecorder->closeConnection(); -} - - -tlm_sync_enum RecordableDram::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay) -{ - // Recording time used by the traceAnalyzer - sc_time recTime = sc_time_stamp() + delay; - - // These are terminating phases recorded by the DRAM. The execution - // time of the related command must be taken into consideration. - if (phase == END_PDNA || phase == END_PDNAB) { - recTime += getExecutionTime(Command::PDNAX, payload); - } else if (phase == END_PDNP || phase == END_PDNPB) { - recTime += getExecutionTime(Command::PDNPX, payload); - } else if (phase == END_SREF || phase == END_SREFB) { - recTime += getExecutionTime(Command::SREFX, payload); - } - - unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); - unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); - unsigned int bg = DramExtension::getExtension(payload).getBankGroup().ID(); - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); - - printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + - to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( - bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " at " + recTime.to_string()); - - tlmRecorder->recordPhase(payload, phase, recTime); - - return Dram::nb_transport_fw(payload, phase, delay); -} - -// This Thread is only triggered when Power Simulation is enabled. -// It estimates the current average power which will be stored in the trace database for visualization purposes. -void RecordableDram::powerWindow() -{ - unsigned long long clkCycles = 0; - - do { - // At the very beginning (zero clock cycles) the energy is 0, so we wait first - wait(powerWindowSize); - - clkCycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); - - DRAMPower->calcWindowEnergy(clkCycles); - - // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); - - // Store the time (in seconds) and the current average power (in mW) into the database - recordPower(); - - // Here considering that DRAMPower provides the energy in pJ and the power in mW - printDebugMessage(string("\tWindow Energy: \t") + to_string( - DRAMPower->getEnergy().window_energy * - Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); - printDebugMessage(string("\tWindow Average Power: \t") + to_string( - DRAMPower->getPower().window_average_power * - Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); - - } while (true); -} - -void RecordableDram::recordPower() -{ - tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - DRAMPower->getPower().window_average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM); -} - diff --git a/DRAMSys/library/src/simulation/RecordableDram.h b/DRAMSys/library/src/simulation/RecordableDram.h deleted file mode 100644 index 0434177a..00000000 --- a/DRAMSys/library/src/simulation/RecordableDram.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2018, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Felipe S. Prado - * Matthias Jung - */ - -#ifndef RECORDABLEDRAM_H -#define RECORDABLEDRAM_H - -#include "Dram.h" -#include "../common/TlmRecorder.h" - -using namespace tlm; - -class RecordableDram : public Dram -{ -public: - RecordableDram(sc_module_name, TlmRecorder *tlmRecorder); - SC_HAS_PROCESS(RecordableDram); - - ~RecordableDram(); - -protected: - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay); - -private: - TlmRecorder *tlmRecorder; - sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * - Configuration::getInstance().WindowSize; - - // When working with floats, we have to decide ourselves what is an - // acceptable definition for "equal". Here the number is compared with a - // suitable error margin (0.00001). - bool isEqual(double a, double b, const double epsilon = 1e-05) - { - return std::fabs(a - b) < epsilon; - } - - // This Thread is only triggered when Power Simulation is enabled. - // It estimates the current average power which will be stored in the trace database for visualization purposes. - void powerWindow(); - - void recordPower(); -}; - -#endif // RECORDABLEDRAM_H - From 72152bca8b377efa3bcee7d7c8bbd98315bf203b Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 28 Jun 2019 14:10:09 +0200 Subject: [PATCH 007/183] Included GenericController for later verilator inclusion. --- DRAMSys/library/library.pro | 3 +- DRAMSys/library/src/controller/Controller.cpp | 11 +++-- DRAMSys/library/src/controller/Controller.h | 8 ++-- .../src/controller/GenericController.h | 42 +++++++++++++++++++ .../controller/core/configuration/MemSpec.cpp | 20 +++++++++ .../controller/core/configuration/MemSpec.h | 24 ++--------- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/DRAMSys.h | 3 +- DRAMSys/library/src/simulation/Dram.h | 2 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR3.h | 2 +- DRAMSys/library/src/simulation/DramDDR4.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR4.h | 2 +- 13 files changed, 84 insertions(+), 39 deletions(-) create mode 100644 DRAMSys/library/src/controller/GenericController.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 48323902..0a2ada5c 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -229,7 +229,8 @@ HEADERS += \ src/simulation/DramDDR4.h \ src/simulation/DramRecordable.h \ src/simulation/DramWideIO.h \ - src/controller/core/scheduling/checker/CheckerDDR3.h + src/controller/core/scheduling/checker/CheckerDDR3.h \ + src/controller/GenericController.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 1fac6814..369825f5 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -35,11 +35,13 @@ * Felipe S. Prado */ -#include "core/configuration/Configuration.h" #include "Controller.h" -#include -Controller::Controller(sc_module_name /*name*/) : +#include +#include "core/configuration/Configuration.h" + +Controller::Controller(sc_module_name name) : + GenericController(name), frontendPEQ(this, &Controller::frontendPEQCallback), dramPEQ(this, &Controller::dramPEQCallback), controllerCorePEQ(this, &Controller::controllerCorePEQCallback), @@ -47,9 +49,6 @@ Controller::Controller(sc_module_name /*name*/) : { controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem); buildScheduler(); - iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw); - tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw); - tSocket.register_transport_dbg(this, &Controller::transport_dbg); } Controller::~Controller() diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 282a9224..479d71d8 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -71,13 +71,14 @@ #include "scheduler/FrFcfsGrp.h" #include "scheduler/SMS.h" #include "scheduler/IScheduler.h" +#include "GenericController.h" using namespace std; using namespace tlm; DECLARE_EXTENDED_PHASE(PendingRequest); -class Controller : public sc_module, public IController +class Controller : public GenericController, public IController { public: Controller(sc_module_name); @@ -96,9 +97,6 @@ public: virtual void send(Trigger trigger, sc_time time, tlm_generic_payload &payload) override; - tlm_utils::simple_target_socket tSocket; - tlm_utils::simple_initiator_socket iSocket; - unsigned int getTotalNumberOfPayloadsInSystem(); void scheduleNextFromScheduler(Bank bank) override; @@ -141,7 +139,7 @@ protected: IScheduler *scheduler; std::map numberOfPayloadsInSystem; std::vector refreshCollisionRequets; - tlm::tlm_generic_payload *backpressure = NULL; + tlm_generic_payload *backpressure = NULL; std::queue responseQueue; tlm_utils::peq_with_cb_and_phase frontendPEQ; diff --git a/DRAMSys/library/src/controller/GenericController.h b/DRAMSys/library/src/controller/GenericController.h new file mode 100644 index 00000000..165963aa --- /dev/null +++ b/DRAMSys/library/src/controller/GenericController.h @@ -0,0 +1,42 @@ +#ifndef GENERICCONTROLLER_H +#define GENERICCONTROLLER_H + +#include +#include +#include +#include + +// Utiliy class to pass around the DRAMSys, without having to propagate the template defintions +// throughout all classes +class GenericController : public sc_module +{ +public: + // Already create and bind sockets to the virtual functions + tlm_utils::simple_target_socket tSocket; // DRAMSys side + tlm_utils::simple_initiator_socket iSocket; // DRAM side + + // Bind sockets with virtual functions + SC_HAS_PROCESS(GenericController); + GenericController(sc_module_name name) : + sc_module(name), tSocket("tSocket"), iSocket("iSocket") + { + tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw); + tSocket.register_transport_dbg(this, &GenericController::transport_dbg); + iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw); + } + + // Destructor + virtual ~GenericController() {} + + // Virtual transport functions + virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, + tlm::tlm_phase &phase, + sc_time &delay) = 0; + virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans) = 0; + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, + tlm::tlm_phase &phase, + sc_time &delay) = 0; +}; + + +#endif // GENERICCONTROLLER_H diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index fddaf10a..8d113ddd 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -40,6 +40,26 @@ #include "../../Command.h" #include "Configuration.h" +const std::vector &MemSpec::getBanks() const +{ + static std::vector banks; + if (banks.size() == 0) { + for (unsigned int i = 0; i < NumberOfBanks; i++) + banks.push_back(Bank(i)); + } + return banks; +} + +sc_time MemSpec::getReadAccessTime() const +{ + return clk * (BurstLength / DataRate); +} + +sc_time MemSpec::getWriteAccessTime() const +{ + return clk * (BurstLength / DataRate); +} + sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const { if (command == Command::PDNA || command == Command::PDNP) diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 8900b420..e043404b 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -58,33 +58,17 @@ struct RefreshTiming struct MemSpec { - sc_time getWriteAccessTime() const - { - return clk * (BurstLength / DataRate); - } + const std::vector &getBanks() const; - sc_time getReadAccessTime() const - { - return clk * (BurstLength / DataRate); - } + sc_time getWriteAccessTime() const; + + sc_time getReadAccessTime() const; // Returns the minimum execution time for commands that have a variable execution time sc_time getMinExecutionTimeForPowerDownCmd(Command command) const; virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; - const std::vector &getBanks() const - { - static std::vector banks; - if (banks.size() == 0) { - for (unsigned int i = 0; i < NumberOfBanks; i++) { - banks.push_back(Bank(i)); - } - } - - return banks; - } - std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 8ee7792f..5f1f1fa4 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -252,7 +252,7 @@ void DRAMSys::instantiateModules(const string &traceName, i++) { std::string str = "controller" + std::to_string(i); - Controller *controller; + GenericController *controller; if (recordingEnabled) controller = new RecordableController(str.c_str(), tlmRecorders[i]); else diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index fa26386b..cd4a8fbc 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -52,6 +52,7 @@ #include "../common/third_party/tinyxml2/tinyxml2.h" #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" +#include "../controller/GenericController.h" class DRAMSys : public sc_module { @@ -87,7 +88,7 @@ private: // All transactions pass through the same arbiter Arbiter *arbiter; // Each DRAM unit has a controller - std::vector controllers; + std::vector controllers; // TODO: Each DRAM has a reorder buffer (check this!) ReorderBuffer *reorder; diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 372df02c..6b551f4d 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -43,7 +43,7 @@ #include #include #include -#include "../controller/Controller.h" +#include "../common/protocol.h" #include "../controller/core/configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index ebe78c90..2eff2592 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -41,5 +41,5 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) - SC_REPORT_FATAL("DramDDR3", "Error Model for DDR3 not supported"); + SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); } diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index 0886d25a..1db185df 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -36,9 +36,9 @@ #ifndef DRAMDDR3_H #define DRAMDDR3_H -#include "Dram.h" #include #include +#include "Dram.h" class DramDDR3 : public Dram { diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 8feeb259..1fc81d81 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -41,5 +41,5 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) - SC_REPORT_FATAL("DramDDR4", "Error Model for DDR4 not supported"); + SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index 5cf92424..358ec454 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -36,9 +36,9 @@ #ifndef DRAMDDR4_H #define DRAMDDR4_H -#include "Dram.h" #include #include +#include "Dram.h" class DramDDR4 : public Dram { From 7da2aacfa3ff1e1975d6422663f55f4c10da2783 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 28 Jun 2019 14:40:07 +0200 Subject: [PATCH 008/183] Separate constructors for each DRAM type. --- .../controller/core/configuration/MemSpec.h | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 104 ------------------ DRAMSys/library/src/simulation/DramDDR3.cpp | 102 +++++++++++++++++ DRAMSys/library/src/simulation/DramDDR4.cpp | 102 +++++++++++++++++ DRAMSys/library/src/simulation/DramWideIO.cpp | 102 +++++++++++++++++ 5 files changed, 307 insertions(+), 105 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index e043404b..b43df8e1 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -90,7 +90,7 @@ struct MemSpec sc_time tAL; // additive delay (delayed execution in dram) sc_time tCKE; // min time in pdna or pdnp sc_time tCKESR; // min time in sref - //sc_time tCL; // unused? + sc_time tCL; // unused, will be used in the future sc_time tDQSCK; sc_time tRAS; // active-time (act -> pre same bank) sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 65a7ebbe..a380ceea 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -69,110 +69,6 @@ Dram::Dram(sc_module_name) : tSocket("socket") tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); - - // Parameters for DRAMPower - sc_time clk = Configuration::getInstance().memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = - Configuration::getInstance().memSpec->BurstLength; - memArchSpec.dataRate = Configuration::getInstance().memSpec->DataRate; - memArchSpec.nbrOfRows = - Configuration::getInstance().memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = - Configuration::getInstance().memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = - Configuration::getInstance().memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = - Configuration::getInstance().memSpec->NumberOfRanks; - memArchSpec.width = Configuration::getInstance().memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = - Configuration::getInstance().memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = (Configuration::getInstance().memSpec->vDD2 == 0 - ? false : true); - memArchSpec.dll = Configuration::getInstance().memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = Configuration::getInstance().memSpec->tAL / clk; - memTimingSpec.CCD = Configuration::getInstance().memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = Configuration::getInstance().memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = Configuration::getInstance().memSpec->tCCD_S / clk; - memTimingSpec.CKE = Configuration::getInstance().memSpec->tCKE / clk; - memTimingSpec.CKESR = Configuration::getInstance().memSpec->tCKESR / clk; - memTimingSpec.clkMhz = Configuration::getInstance().memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / Configuration::getInstance().memSpec->clkMHz; - memTimingSpec.DQSCK = Configuration::getInstance().memSpec->tDQSCK / clk; - memTimingSpec.FAW = Configuration::getInstance().memSpec->tNAW / clk; - memTimingSpec.RAS = Configuration::getInstance().memSpec->tRAS / clk; - memTimingSpec.RC = Configuration::getInstance().memSpec->tRC / clk; - memTimingSpec.RCD = Configuration::getInstance().memSpec->tRCD / clk; - memTimingSpec.REFI = Configuration::getInstance().memSpec->tREFI / clk; - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = Configuration::getInstance().memSpec->tRFC / clk; - memTimingSpec.RL = Configuration::getInstance().memSpec->tRL / clk; - memTimingSpec.RP = Configuration::getInstance().memSpec->tRP / clk; - memTimingSpec.RRD = Configuration::getInstance().memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = Configuration::getInstance().memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = Configuration::getInstance().memSpec->tRRD_S / clk; - memTimingSpec.RTP = Configuration::getInstance().memSpec->tRTP / clk; - memTimingSpec.TAW = Configuration::getInstance().memSpec->tNAW / clk; - memTimingSpec.WL = Configuration::getInstance().memSpec->tWL / clk; - memTimingSpec.WR = Configuration::getInstance().memSpec->tWR / clk; - memTimingSpec.WTR = Configuration::getInstance().memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = Configuration::getInstance().memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = Configuration::getInstance().memSpec->tWTR_S / clk; - memTimingSpec.XP = Configuration::getInstance().memSpec->tXP / clk; - memTimingSpec.XPDLL = Configuration::getInstance().memSpec->tXPDLL / clk; - memTimingSpec.XS = Configuration::getInstance().memSpec->tXSR / clk; - memTimingSpec.XSDLL = Configuration::getInstance().memSpec->tXSRDLL / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = Configuration::getInstance().memSpec->iDD0; - memPowerSpec.idd02 = Configuration::getInstance().memSpec->iDD02; - memPowerSpec.idd2p0 = Configuration::getInstance().memSpec->iDD2P0; - memPowerSpec.idd2p02 = Configuration::getInstance().memSpec->iDD2P02; - memPowerSpec.idd2p1 = Configuration::getInstance().memSpec->iDD2P1; - memPowerSpec.idd2p12 = Configuration::getInstance().memSpec->iDD2P12; - memPowerSpec.idd2n = Configuration::getInstance().memSpec->iDD2N; - memPowerSpec.idd2n2 = Configuration::getInstance().memSpec->iDD2N2; - memPowerSpec.idd3p0 = Configuration::getInstance().memSpec->iDD3P0; - memPowerSpec.idd3p02 = Configuration::getInstance().memSpec->iDD3P02; - memPowerSpec.idd3p1 = Configuration::getInstance().memSpec->iDD3P1; - memPowerSpec.idd3p12 = Configuration::getInstance().memSpec->iDD3P12; - memPowerSpec.idd3n = Configuration::getInstance().memSpec->iDD3N; - memPowerSpec.idd3n2 = Configuration::getInstance().memSpec->iDD3N2; - memPowerSpec.idd4r = Configuration::getInstance().memSpec->iDD4R; - memPowerSpec.idd4r2 = Configuration::getInstance().memSpec->iDD4R2; - memPowerSpec.idd4w = Configuration::getInstance().memSpec->iDD4W; - memPowerSpec.idd4w2 = Configuration::getInstance().memSpec->iDD4W2; - memPowerSpec.idd5 = Configuration::getInstance().memSpec->iDD5; - memPowerSpec.idd52 = Configuration::getInstance().memSpec->iDD52; - memPowerSpec.idd6 = Configuration::getInstance().memSpec->iDD6; - memPowerSpec.idd62 = Configuration::getInstance().memSpec->iDD62; - memPowerSpec.vdd = Configuration::getInstance().memSpec->vDD; - memPowerSpec.vdd2 = Configuration::getInstance().memSpec->vDD2; - - MemorySpecification memSpec; - memSpec.id = Configuration::getInstance().memSpec->MemoryId; - memSpec.memoryType = Configuration::getInstance().memSpec->MemoryType; - memSpec.memTimingSpec = memTimingSpec; - memSpec.memPowerSpec = memPowerSpec; - memSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(memSpec, 0); } Dram::~Dram() diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 2eff2592..8453a6da 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -37,9 +37,111 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); + + // Parameters for DRAMPower + MemSpecDDR3 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); + + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXSR / clk; + memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 1fc81d81..bf768f29 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -37,9 +37,111 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); + + // Parameters for DRAMPower + MemSpecDDR4 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); + + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXSR / clk; + memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0);; } diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 9b3655cb..93f80c06 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -40,6 +40,7 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" #include "../error/errormodel.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace tlm; @@ -60,6 +61,107 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) ememory.push_back(em); } } + + // Parameters for DRAMPower + MemSpecWideIO *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); + + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXSR / clk; + memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } DramWideIO::~DramWideIO() From a5fb1327a1d514b5e1b3202d3b719b99ace1df3f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 28 Jun 2019 15:14:47 +0200 Subject: [PATCH 009/183] Renaming of timings. --- .../configuration/ConfigurationLoader.cpp | 16 +++++++------- .../controller/core/configuration/MemSpec.h | 17 +++++++------- .../core/scheduling/checker/ActBChecker.cpp | 2 +- .../scheduling/checker/ActivateChecker.cpp | 2 +- .../core/scheduling/checker/CheckerDDR3.cpp | 12 +++++----- .../scheduling/checker/PowerDownChecker.cpp | 2 +- .../checker/PrechargeAllChecker.cpp | 2 +- .../core/scheduling/checker/ReadChecker.cpp | 2 +- .../scheduling/checker/RefreshChecker.cpp | 4 ++-- DRAMSys/library/src/simulation/DramDDR3.cpp | 4 ++-- DRAMSys/library/src/simulation/DramDDR4.cpp | 4 ++-- DRAMSys/library/src/simulation/DramWideIO.cpp | 4 ++-- DRAMSys/traceAnalyzer/scripts/tests.py | 22 +++++++++---------- 13 files changed, 47 insertions(+), 46 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index a20c9e3e..00c59535 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -216,8 +216,8 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); @@ -295,8 +295,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); @@ -379,8 +379,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); - memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - memSpec->tXSRDLL = clk * queryUIntParameter(timings, "XS"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSDLL = clk * queryUIntParameter(timings, "XS"); memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); // TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); @@ -459,8 +459,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = memSpec->tXP; - memSpec->tXSR = clk * queryUIntParameter(timings, "XS"); - memSpec->tXSRDLL = memSpec->tXSR; + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tXSDLL = memSpec->tXS; memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index b43df8e1..cc78db14 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -73,7 +73,6 @@ struct MemSpec std::string MemoryType = "not defined."; unsigned int NumberOfBanks; - unsigned int NumberOfBankGroups; unsigned int NumberOfRanks; unsigned int BurstLength; unsigned int nActivate; @@ -100,9 +99,12 @@ struct MemSpec sc_time tWL; // write latency sc_time tWR; // write recovery (write to precharge) sc_time tXP; // min delay to row access command after pdnpx pdnax - sc_time tXSR; // min delay to row access command after srefx + sc_time tXS; // min delay to row access command after srefx + unsigned int NumberOfBankGroups; + + sc_time tNAW; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else sc_time tRP; // precharge-time (pre -> act same bank) sc_time tRFC; //min ref->act delay 1X mode sc_time tRFC2; //min ref->act delay 2X mode @@ -114,11 +116,10 @@ struct MemSpec sc_time tCCD_L; sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group) sc_time tRRD_L; //.. (same bank group) - sc_time tNAW; //n activate window sc_time tWTR_S; //write to read (different bank group) sc_time tWTR_L; //.. (same bank group) sc_time tXPDLL; // min delay to row access command after pdnpx pdnax for dll commands - sc_time tXSRDLL; // min delay to row access command after srefx for dll commands + sc_time tXSDLL; // min delay to row access command after srefx for dll commands // Currents and Voltages: double iDD0; @@ -170,7 +171,7 @@ struct MemSpec struct MemSpecDDR3 : public MemSpec { sc_time tCCD; -// sc_time tFAW; + sc_time tFAW; sc_time tWTR; // sc_time tREFI; // sc_time tRFC; @@ -184,7 +185,7 @@ struct MemSpecDDR4 : public MemSpec { // sc_time tCCD_S; // sc_time tCCD_L; -// sc_time tFAW; + sc_time tFAW; // sc_time tWTR_S; // sc_time tWTR_L; // sc_time tREFI; @@ -203,7 +204,7 @@ struct MemSpecWideIO : public MemSpec { // sc_time tCCD; // sc_time tWTR; -// sc_time tTAW; + sc_time tTAW; // sc_time tREFI; // sc_time tRFC; // sc_time tRP; @@ -217,7 +218,7 @@ struct MemSpecLPDDR4 : public MemSpec // sc_time tCCD; // sc_time tCCDMW; // sc_time tESCKE; -// sc_time tFAW; + sc_time tFAW; // sc_time tWTR; // sc_time tPPD; // sc_time tREFIAB; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 0a57bfa3..6dd91aea 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -73,7 +73,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const || lcb.getCommand() == Command::PDNAX) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP); } else if (lcb.getCommand() == Command::SREFX) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXSR); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS); } else { reportFatal("ActB Checker", "ActB can not follow " + commandToString(lcb.getCommand())); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 49cfdbeb..f8940b83 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -81,7 +81,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tXP); } else if (lastCommandOnBank.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tXSR); + config.memSpec->tXS); } else reportFatal("Activate Checker", "Activate can not follow " + commandToString(lastCommandOnBank.getCommand())); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 183e1fdb..68b3607b 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -46,7 +46,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXSR); + memSpec->tXS); break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -208,7 +208,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXSR); + memSpec->tXS); break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -264,7 +264,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXSR); + memSpec->tXS); break; default: reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow " @@ -326,7 +326,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXSR); + memSpec->tXS); break; default: reportFatal("Checker DDR3", @@ -373,7 +373,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::SREFX: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXSR); + memSpec->tXS); break; default: reportFatal("Checker DDR3", @@ -481,7 +481,7 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const { ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank()); if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSRDLL); + read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 54317c6e..49f2bfc7 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -64,7 +64,7 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, } else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) { constraint = config.memSpec->tXP; } else if (lastCmd == Command::SREFX) { - constraint = config.memSpec->tXSR; + constraint = config.memSpec->tXS; } else if (lastCmd == Command::Precharge || lastCmd == Command::PrechargeAll) { constraint = config.memSpec->tRP; } else { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 0b6d5867..9be11621 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -86,7 +86,7 @@ const config.memSpec->tXP); } else if (lastCommand.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXSR); + config.memSpec->tXS); } else reportFatal("Precharge All Checker", "Precharge All can not follow " + commandToString(lastCommand.getCommand())); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 9d0af4aa..d48a0715 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -112,7 +112,7 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), - config.memSpec->tXSRDLL); + config.memSpec->tXSDLL); } sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index ad964f5e..d1089eae 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -64,7 +64,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tXP); } else if (lastCommandOnBank.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tXSR); + config.memSpec->tXS); } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { } else reportFatal("Refresh Checker", @@ -96,7 +96,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tXP); } else if (lastCommand.getCommand() == Command::SREFX) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXSR); + config.memSpec->tXS); } else if (lastCommand.getCommand() == Command::AutoRefresh) { } else reportFatal("Refresh Checker", diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 8453a6da..86e67e5b 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -107,8 +107,8 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memTimingSpec.WTR_S = memSpec->tWTR_S / clk; memTimingSpec.XP = memSpec->tXP / clk; memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXSR / clk; - memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index bf768f29..3beadc82 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -107,8 +107,8 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memTimingSpec.WTR_S = memSpec->tWTR_S / clk; memTimingSpec.XP = memSpec->tXP / clk; memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXSR / clk; - memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 93f80c06..87d84a0e 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -125,8 +125,8 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.WTR_S = memSpec->tWTR_S / clk; memTimingSpec.XP = memSpec->tXP / clk; memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXSR / clk; - memTimingSpec.XSDLL = memSpec->tXSRDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index 2d3becd9..c38e1d2d 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -36,8 +36,8 @@ class DramConfig(object): tCKE = 0 # min time in pdna or pdnp tXP = 0 # min delay to row access command after pdnpx pdnax tXPDLL = 0 # min delay to row access command after pdnpx pdnax for dll commands - tXSR = 0 # min delay to row access command after srefx - tXSRDLL = 0 # min delay to row access command after srefx for dll commands + tXS = 0 # min delay to row access command after srefx + tXSDLL = 0 # min delay to row access command after srefx for dll commands tAL = 0 # additive delay (delayed execution in dram) tRFC = 0 # min ref->act delay 1X tRFC2 = 0 # min ref->act delay 2X @@ -84,8 +84,8 @@ class DramConfig(object): self.tCKE = self.clk * memspec.getIntValue("CKE") self.tXP = self.clk * memspec.getIntValue("XP") self.tXPDLL = self.tXP - self.tXSR = self.clk * memspec.getIntValue("XS") - self.tXSRDLL = self.tXSR + self.tXS = self.clk * memspec.getIntValue("XS") + self.tXSDLL = self.tXS self.tAL = self.clk * memspec.getIntValue("AL") self.tRFC = self.clk * memspec.getIntValue("RFC") self.tREFI = self.clk * memspec.getIntValue("REFI") @@ -111,8 +111,8 @@ class DramConfig(object): self.tCKE = self.clk * memspec.getIntValue("CKE") self.tXP = self.clk * memspec.getIntValue("XP") self.tXPDLL = self.clk * memspec.getIntValue("XPDLL") - self.tXSR = self.clk * memspec.getIntValue("XS") - self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL") + self.tXS = self.clk * memspec.getIntValue("XS") + self.tXSDLL = self.clk * memspec.getIntValue("XSDLL") self.tAL = self.clk * memspec.getIntValue("AL") self.tRFC = self.clk * memspec.getIntValue("RFC") self.tRFC2 = self.clk * memspec.getIntValue("RFC2") @@ -140,8 +140,8 @@ class DramConfig(object): self.tCKE = self.clk * memspec.getIntValue("CKE") self.tXP = self.clk * memspec.getIntValue("XP") self.tXPDLL = self.clk * memspec.getIntValue("XPDLL") - self.tXSR = self.clk * memspec.getIntValue("XS") - self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL") + self.tXS = self.clk * memspec.getIntValue("XS") + self.tXSDLL = self.clk * memspec.getIntValue("XSDLL") self.tAL = self.clk * memspec.getIntValue("AL") self.tRFC = self.clk * memspec.getIntValue("RFC") self.tREFI = self.clk * memspec.getIntValue("REFI") @@ -374,7 +374,7 @@ def timing_constraint(FirstPhase, SecondPhase): return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXP - dramconfig.clk elif (FirstPhaseName == "SREF"): - return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXSR - dramconfig.clk + return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXS - dramconfig.clk return 0 @@ -694,8 +694,8 @@ def read_holds_dll_constraint_after_sref(connection): for currentRow in cursor: if (currentRow[2] in ["RD", "RDA"] and lastRow[2] == 'SREF'): srefEndToRead = currentRow[1] - (lastRow[1] - dramconfig.clk) - if (srefEndToRead < dramconfig.tXSRDLL): - return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}".format(currentRow[0], formatTime(srefEndToRead), lastRow[0], formatTime(dramconfig.tXSRDLL))) + if (srefEndToRead < dramconfig.tXSDLL): + return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}".format(currentRow[0], formatTime(srefEndToRead), lastRow[0], formatTime(dramconfig.tXSDLL))) lastRow = currentRow return TestSuceeded() From 21adf2ac70cb1b608233118c0c0261378f46e854 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 28 Jun 2019 16:26:46 +0200 Subject: [PATCH 010/183] Moved some timings to loadCommons(). --- .../src/controller/core/ControllerCore.cpp | 2 +- .../configuration/ConfigurationLoader.cpp | 167 ++++++------------ .../controller/core/configuration/MemSpec.h | 13 +- 3 files changed, 59 insertions(+), 123 deletions(-) diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 81db0267..36bf1cc6 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -86,7 +86,7 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, commandChecker[Command::PDNPX] = commandChecker[Command::PDNA]; commandChecker[Command::SREFX] = commandChecker[Command::PDNA]; - timingChecker = new CheckerDDR3(config, *state); + //timingChecker = new CheckerDDR3(config, *state); if (config.RowGranularRef) { refreshManager = new RGR("RGR", *this); diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 00c59535..6177f315 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -140,8 +140,9 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) void ConfigurationLoader::loadMemSpec(Configuration &config, XMLElement *memspec) { - string memoryType = queryStringParameter(memspec, "memoryType"); + loadCommons(config, memspec); + string memoryType = queryStringParameter(memspec, "memoryType"); if (memoryType == "DDR4") { Configuration::getInstance().memSpec = new MemSpecDDR4; loadDDR4(config, memspec); @@ -157,14 +158,44 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, } else { reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } - - loadCommons(config, memspec); } -void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *memspec) +void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec) { - config.memSpec->MemoryId = queryStringParameter(memspec, "memoryId"); - config.memSpec->MemoryType = queryStringParameter(memspec, "memoryType"); + MemSpec *memSpec = config.memSpec; + + memSpec->MemoryId = queryStringParameter(xmlSpec, "memoryId"); + memSpec->MemoryType = queryStringParameter(xmlSpec, "memoryType"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); + memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); + memSpec->bitWidth = queryUIntParameter(architecture, "width"); + + // MemTimings + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); + memSpec->clk = FrequencyToClk(memSpec->clkMHz); + sc_time clk = memSpec->clk; + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tCL = clk * queryUIntParameter(timings, "CL"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); } void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) @@ -173,55 +204,31 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) if (memSpec == nullptr) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - //MemArchitecture - XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + // MemArchitecture + //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBankGroups = 1; - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->nActivate = 4; - memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - memSpec->NumberOfColumns = queryUIntParameter(architecture, - "nbrOfColumns"); - memSpec->bitWidth = queryUIntParameter(architecture, "width"); memSpec->DLL = true; memSpec->termination = true; - //MemTimings + // MemTimings XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - memSpec->clk = FrequencyToClk(memSpec->clkMHz); sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { @@ -254,55 +261,30 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) if (memSpec == nullptr) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - //MemArchitecture + // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->NumberOfBankGroups = queryUIntParameter(architecture, - "nbrOfBankGroups"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); memSpec->nActivate = 4; - memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - memSpec->NumberOfColumns = queryUIntParameter(architecture, - "nbrOfColumns"); - memSpec->bitWidth = queryUIntParameter(architecture, "width"); memSpec->DLL = true; memSpec->termination = true; - //MemTimings + // MemTimings XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - memSpec->clk = FrequencyToClk(memSpec->clkMHz); sc_time clk = memSpec->clk; memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { @@ -338,55 +320,31 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) if (memSpec == nullptr) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - //MemArchitecture: - XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + // MemArchitecture: + //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBankGroups = 1; - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->nActivate = 4; - memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - memSpec->NumberOfColumns = queryUIntParameter(architecture, - "nbrOfColumns"); - memSpec->bitWidth = queryUIntParameter(architecture, "width"); memSpec->DLL = false; // TODO: Correct? memSpec->termination = true; // TODO: Correct? - //MemTimings + // MemTimings XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); - memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - memSpec->clk = FrequencyToClk(memSpec->clkMHz); sc_time clk = memSpec->clk; memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XS"); - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); // TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); // TODO: memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { @@ -419,51 +377,30 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) if (memSpec == nullptr) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - //MemSpecification - XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + // MemSpecification + //XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBankGroups = 1; - memSpec->NumberOfRanks = 1; - memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); + //memSpec->NumberOfRanks = 1; TODO: is part of memspec for WideIO memSpec->nActivate = 2; - memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); - memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); - memSpec->NumberOfColumns = queryUIntParameter(architecture, - "nbrOfColumns"); - memSpec->bitWidth = queryUIntParameter(architecture, "width"); memSpec->DLL = false; memSpec->termination = false; - //MemTimings + // MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); - memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); - memSpec->clk = FrequencyToClk(memSpec->clkMHz); sc_time clk = memSpec->clk; memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); memSpec->tRRD_L = memSpec->tRRD_S; memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); memSpec->tCCD_L = memSpec->tCCD_S; - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); memSpec->tWTR_L = memSpec->tWTR_S; - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXPDLL = memSpec->tXP; - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tXSDLL = memSpec->tXS; - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + // TODO: tDQSCK was missing memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index cc78db14..9066e22e 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -80,8 +80,6 @@ struct MemSpec unsigned int NumberOfRows; unsigned int NumberOfColumns; unsigned int bitWidth; - bool DLL; - bool termination; // Memspec Variables: double clkMHz; @@ -99,10 +97,13 @@ struct MemSpec sc_time tWL; // write latency sc_time tWR; // write recovery (write to precharge) sc_time tXP; // min delay to row access command after pdnpx pdnax - sc_time tXS; // min delay to row access command after srefx + sc_time tXS; // min delay to row access command after srefx + // TODO: move to specific memspecs unsigned int NumberOfBankGroups; + bool DLL; + bool termination; sc_time tNAW; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else sc_time tRP; // precharge-time (pre -> act same bank) @@ -110,8 +111,6 @@ struct MemSpec sc_time tRFC2; //min ref->act delay 2X mode sc_time tRFC4; //min ref->act delay 4X mode sc_time tREFI; // auto refresh must be issued at an average periodic interval tREFI - // TODO: move to specific memspecs - sc_time tRPAB; //precharge-all time only for LPDDR4 sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd sc_time tCCD_L; sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group) @@ -119,7 +118,7 @@ struct MemSpec sc_time tWTR_S; //write to read (different bank group) sc_time tWTR_L; //.. (same bank group) sc_time tXPDLL; // min delay to row access command after pdnpx pdnax for dll commands - sc_time tXSDLL; // min delay to row access command after srefx for dll commands + sc_time tXSDLL; // min delay to row access command after srefx for dll commands // Currents and Voltages: double iDD0; @@ -225,7 +224,7 @@ struct MemSpecLPDDR4 : public MemSpec // sc_time tREFIPB; // sc_time tRFCAB; // sc_time tRFCPB; -// sc_time tRPAB; + sc_time tRPAB; // sc_time tRPPB; // sc_time tRRD; }; From 409e49f044823cc323267e541f17a5d1162d5f5e Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 28 Jun 2019 17:36:51 +0200 Subject: [PATCH 011/183] Bugfix: call loadCommons() only after creating a memSpec object. --- .../configuration/ConfigurationLoader.cpp | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 6177f315..6536f5fc 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -140,22 +140,33 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) void ConfigurationLoader::loadMemSpec(Configuration &config, XMLElement *memspec) { - loadCommons(config, memspec); - string memoryType = queryStringParameter(memspec, "memoryType"); - if (memoryType == "DDR4") { + if (memoryType == "DDR4") + { Configuration::getInstance().memSpec = new MemSpecDDR4; + loadCommons(config, memspec); loadDDR4(config, memspec); - } else if (memoryType == "DDR3") { + } + else if (memoryType == "DDR3") + { Configuration::getInstance().memSpec = new MemSpecDDR3; + loadCommons(config, memspec); loadDDR3(config, memspec); - } else if (memoryType == "LPDDR4") { + } + else if (memoryType == "LPDDR4") + { Configuration::getInstance().memSpec = new MemSpecLPDDR4; + loadCommons(config, memspec); loadLPDDR4(config, memspec); - } else if (memoryType == "WIDEIO_SDR") { + } + else if (memoryType == "WIDEIO_SDR") + { Configuration::getInstance().memSpec = new MemSpecWideIO; + loadCommons(config, memspec); loadWideIO(config, memspec); - } else { + } + else + { reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } } From 9b8729c58b279116d28e66f3bcfc8d90091470e6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 28 Jun 2019 17:53:52 +0200 Subject: [PATCH 012/183] Bugfix: nbrOfRanks is only part of some memspecs for WideIO. --- .../core/configuration/ConfigurationLoader.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 6536f5fc..167ef3da 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -181,7 +181,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); @@ -216,7 +216,8 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture - //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = 1; memSpec->nActivate = 4; memSpec->DLL = true; @@ -274,6 +275,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); memSpec->nActivate = 4; memSpec->DLL = true; @@ -332,7 +334,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture: - //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = 1; memSpec->nActivate = 4; memSpec->DLL = false; // TODO: Correct? @@ -391,7 +394,7 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) // MemSpecification //XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBankGroups = 1; - //memSpec->NumberOfRanks = 1; TODO: is part of memspec for WideIO + memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO memSpec->nActivate = 2; memSpec->DLL = false; memSpec->termination = false; From 3b509a7c1766e399a6b0d1aaf40e634868580af9 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 1 Jul 2019 10:23:30 +0200 Subject: [PATCH 013/183] Marked old timing parameters with "_old" for inclusion of new ones without conflicts. --- .../configuration/ConfigurationLoader.cpp | 112 +++++++++--------- .../controller/core/configuration/MemSpec.cpp | 16 +-- .../controller/core/configuration/MemSpec.h | 30 ++--- .../core/refresh/RefreshManager.cpp | 6 +- .../core/refresh/RefreshManagerBankwise.cpp | 6 +- .../core/scheduling/checker/ActBChecker.cpp | 12 +- .../scheduling/checker/ActivateChecker.cpp | 12 +- .../core/scheduling/checker/CheckerDDR3.cpp | 42 +++---- .../scheduling/checker/PowerDownChecker.cpp | 4 +- .../core/scheduling/checker/PreBChecker.cpp | 6 +- .../checker/PrechargeAllChecker.cpp | 8 +- .../scheduling/checker/PrechargeChecker.cpp | 2 +- .../core/scheduling/checker/ReadChecker.cpp | 8 +- .../scheduling/checker/RefreshChecker.cpp | 12 +- .../core/scheduling/checker/WriteChecker.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 32 ++--- DRAMSys/library/src/simulation/DramDDR4.cpp | 32 ++--- DRAMSys/library/src/simulation/DramWideIO.cpp | 32 ++--- 18 files changed, 187 insertions(+), 187 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 167ef3da..8ce8a0fd 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -226,26 +226,26 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemTimings XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); + memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); + memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, - memSpec->tREFI); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, + memSpec->tREFI_old); } // Currents and Volatages: TODO Check if this is correct. @@ -284,27 +284,27 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemTimings XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); - memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); - memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); - memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); - memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); - memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); - memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD_S"); + memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD_L"); + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD_S"); + memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD_L"); + memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR_S"); + memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR_L"); + memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, memSpec->tRFC2, memSpec->tRFC4, - memSpec->tREFI); + memSpec->tREFI_old); } // Currents and Volatages: @@ -344,26 +344,26 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemTimings XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD"); - memSpec->tNAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXPDLL = clk * queryUIntParameter(timings, "XP"); - memSpec->tXSDLL = clk * queryUIntParameter(timings, "XS"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XP"); + memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XS"); + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFCAB"); // TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); + memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB"); // TODO: memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, - memSpec->tREFI); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, + memSpec->tREFI_old); } // Currents and Volatages: @@ -402,24 +402,24 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) // MemTimings XMLElement *timings = memspec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L = memSpec->tRRD_S; - memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L = memSpec->tCCD_S; - memSpec->tNAW = clk * queryUIntParameter(timings, "TAW"); - memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L = memSpec->tWTR_S; - memSpec->tXPDLL = memSpec->tXP; - memSpec->tXSDLL = memSpec->tXS; - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L_old = memSpec->tRRD_S_old; + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L_old = memSpec->tCCD_S_old; + memSpec->tNAW_old = clk * queryUIntParameter(timings, "TAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L_old = memSpec->tWTR_S_old; + memSpec->tXPDLL_old = memSpec->tXP; + memSpec->tXSDLL_old = memSpec->tXS; + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); + memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); // TODO: tDQSCK was missing memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, - memSpec->tREFI); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, + memSpec->tREFI_old); } // Currents and Volatages: diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index 8d113ddd..faaa8449 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -80,7 +80,7 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay if (command == Command::PreB) return Configuration::getInstance().getTrpb(); else if (command == Command::Precharge || command == Command::PrechargeAll) - return tRP; + return tRP_old; else if (command == Command::ActB) return tRCD; else if (command == Command::Activate) @@ -88,13 +88,13 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay else if (command == Command::Read) return tRL + getReadAccessTime(); else if (command == Command::ReadA) - return tRTP + tRP; + return tRTP + tRP_old; else if (command == Command::Write) return tWL + getWriteAccessTime(); else if (command == Command::WriteA) - return tWL + getWriteAccessTime() + tWR + tRP; + return tWL + getWriteAccessTime() + tWR + tRP_old; else if (command == Command::PrechargeAll) - return tRP; + return tRP_old; else if (command == Command::AutoRefresh) { return getElementFromMap(refreshTimings, @@ -115,7 +115,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload if (command == Command::PreB) return Configuration::getInstance().getTrpb(); else if (command == Command::Precharge || command == Command::PrechargeAll) - return tRP; + return tRP_old; else if (command == Command::ActB) return tRCD; else if (command == Command::Activate) @@ -123,13 +123,13 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload else if (command == Command::Read) return tRL + getReadAccessTime(); else if (command == Command::ReadA) - return tRTP + tRP; + return tRTP + tRP_old; else if (command == Command::Write) return tWL + getWriteAccessTime(); else if (command == Command::WriteA) - return tWL + getWriteAccessTime() + tWR + tRP; + return tWL + getWriteAccessTime() + tWR + tRP_old; else if (command == Command::PrechargeAll) - return tRP; + return tRP_old; else if (command == Command::AutoRefresh) { if (Configuration::getInstance().getRefMode() == 4) diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 9066e22e..eb53a3b7 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -105,20 +105,20 @@ struct MemSpec bool DLL; bool termination; - sc_time tNAW; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else - sc_time tRP; // precharge-time (pre -> act same bank) - sc_time tRFC; //min ref->act delay 1X mode + sc_time tNAW_old; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else + sc_time tRP_old; // precharge-time (pre -> act same bank) + sc_time tRFC_old; //min ref->act delay 1X mode sc_time tRFC2; //min ref->act delay 2X mode sc_time tRFC4; //min ref->act delay 4X mode - sc_time tREFI; // auto refresh must be issued at an average periodic interval tREFI - sc_time tCCD_S; //max(bl, tCCD) is relevant for rd->rd - sc_time tCCD_L; - sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group) - sc_time tRRD_L; //.. (same bank group) - sc_time tWTR_S; //write to read (different bank group) - sc_time tWTR_L; //.. (same bank group) - sc_time tXPDLL; // min delay to row access command after pdnpx pdnax for dll commands - sc_time tXSDLL; // min delay to row access command after srefx for dll commands + sc_time tREFI_old; // auto refresh must be issued at an average periodic interval tREFI + sc_time tCCD_S_old; //max(bl, tCCD) is relevant for rd->rd + sc_time tCCD_L_old; + sc_time tRRD_S_old; //min time bw 2 succesive ACT to different banks (different bank group) + sc_time tRRD_L_old; //.. (same bank group) + sc_time tWTR_S_old; //write to read (different bank group) + sc_time tWTR_L_old; //.. (same bank group) + sc_time tXPDLL_old; // min delay to row access command after pdnpx pdnax for dll commands + sc_time tXSDLL_old; // min delay to row access command after srefx for dll commands // Currents and Voltages: double iDD0; @@ -153,15 +153,15 @@ struct MemSpec //act and read/write commands remain for this timespan in history sc_time tActHistory() { - return tNAW; + return tNAW_old; } sc_time tActBHistory() { - return tNAW; + return tNAW_old; } sc_time tDataStrobeHistory() { - return tWTR_L; + return tWTR_L_old; } virtual ~MemSpec() {} diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index c3bf0b8a..719a19d6 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -161,7 +161,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec->tRP; + nrt += controllerCore.config.memSpec->tRP_old; nextRefTiming = nrt; nextState = ST_PULLIN; } else { @@ -177,7 +177,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec->tRP; + nrt += controllerCore.config.memSpec->tRP_old; nextRefTiming = nrt; nextState = ST_PULLIN; } else { @@ -222,7 +222,7 @@ void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, } else { nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec->tRP; + nrt += controllerCore.config.memSpec->tRP_old; nextRefTiming = nrt; nextState = ST_BURST; } diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index be639850..d060ec7d 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -148,7 +148,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec->tRP; + nrt += controllerCore.config.memSpec->tRP_old; nextRefTiming = nrt; nextState[bank] = ST_PULLIN; } else { @@ -164,7 +164,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, pre = doRefresh(payload, time); nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec->tRP; + nrt += controllerCore.config.memSpec->tRP_old; nextRefTiming = nrt; nextState[bank] = ST_PULLIN; } else { @@ -210,7 +210,7 @@ void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, } else { nrt = tRFCx; if (pre) - nrt += controllerCore.config.memSpec->tRP; + nrt += controllerCore.config.memSpec->tRP_old; nextRefTiming = nrt; nextState[bank] = ST_BURST; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 6dd91aea..bb75b65f 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -53,14 +53,14 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const Configuration::getInstance().getTrpb()); } else if (lcb.getCommand() == Command::Precharge || lcb.getCommand() == Command::PrechargeAll) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRP); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRP_old); } else if (lcb.getCommand() == Command::ReadA) { cmd.establishMinDistanceFromStart(lcb.getStart(), - config.memSpec->tRTP + config.memSpec->tRP); + config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lcb.getCommand() == Command::WriteA) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() - + config.memSpec->tWR + config.memSpec->tRP); + + config.memSpec->tWR + config.memSpec->tRP_old); } else if (lcb.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) @@ -68,7 +68,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const else if (m == 2) cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC2); else - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC_old); } else if (lcb.getCommand() == Command::PDNPX || lcb.getCommand() == Command::PDNAX) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP); @@ -81,7 +81,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const } ScheduledCommand lc; if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP); + cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } delay_to_satisfy_activateToActivate_sameBank(cmd); while (!(state.bus.isFree(cmd.getStart()) @@ -121,7 +121,7 @@ bool ActBChecker::satsfies_activateToActivate_differentBank( } for (auto act : state.lastActivates) { sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ? - config.memSpec->tRRD_L : config.memSpec->tRRD_S); + config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old); if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t && t - cmd.getStart() < tRRD)) { return false; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index f8940b83..491241db 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -56,14 +56,14 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const || lastCommandOnBank.getCommand() == Command::Precharge || lastCommandOnBank.getCommand() == Command::PrechargeAll) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRTP + config.memSpec->tRP); + config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() - + config.memSpec->tWR + config.memSpec->tRP); + + config.memSpec->tWR + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) @@ -74,7 +74,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tRFC2); else command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRFC); + config.memSpec->tRFC_old); } else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -121,7 +121,7 @@ bool ActivateChecker::satsfies_activateToActivate_differentBank( for (auto act : state.lastActivates) { sc_time time = act.first; sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? - config.memSpec->tRRD_L : config.memSpec->tRRD_S; + config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old; if ((time < command.getStart() && command.getStart() - time < tRRD) || (command.getStart() <= time && time - command.getStart() < tRRD)) @@ -145,7 +145,7 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand &command) const auto lower = lastActivates.begin(); while (upper != lastActivates.end()) { - if (upper->first - lower->first < config.memSpec->tNAW) + if (upper->first - lower->first < config.memSpec->tNAW_old) return false; ++upper; ++lower; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 68b3607b..0dad72b0 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -28,16 +28,16 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::Precharge: case Command::PrechargeAll: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP); + memSpec->tRP_old); break; case Command::ReadA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP); + memSpec->tRTP + memSpec->tRP_old); break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP); + + memSpec->tWR + memSpec->tRP_old); break; case Command::PDNPX: case Command::PDNAX: @@ -50,7 +50,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC); + memSpec->tRFC_old); break; default: reportFatal("Checker DDR3", @@ -136,7 +136,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const { case Command::Precharge: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP); + memSpec->tRP_old); break; case Command::Activate: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -177,7 +177,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const { case Command::Precharge: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP); + memSpec->tRP_old); break; case Command::Activate: command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -195,11 +195,11 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::WriteA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP); + + memSpec->tWR + memSpec->tRP_old); break; case Command::ReadA: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP); + memSpec->tRTP + memSpec->tRP_old); break; case Command::PDNAX: case Command::PDNPX: @@ -212,7 +212,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC); + memSpec->tRFC_old); break; default: reportFatal("Checker_DDR3", @@ -235,7 +235,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::Precharge: case Command::PrechargeAll: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP); + memSpec->tRP_old); break; case Command::Read: case Command::ReadA: @@ -255,7 +255,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC); + memSpec->tRFC_old); break; case Command::PDNAX: case Command::PDNPX: @@ -304,20 +304,20 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::Precharge: case Command::PrechargeAll: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP); + memSpec->tRP_old); break; case Command::ReadA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP); + memSpec->tRTP + memSpec->tRP_old); break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP); + + memSpec->tWR + memSpec->tRP_old); break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC); + memSpec->tRFC_old); break; case Command::PDNPX: case Command::PDNAX: @@ -347,7 +347,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const case Command::Precharge: case Command::PrechargeAll: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP); + memSpec->tRP_old); break; case Command::Activate: command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -355,16 +355,16 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; case Command::ReadA: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP); + memSpec->tRTP + memSpec->tRP_old); break; case Command::WriteA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP); + + memSpec->tWR + memSpec->tRP_old); break; case Command::AutoRefresh: command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC); + memSpec->tRFC_old); break; case Command::PDNPX: case Command::PDNAX: @@ -427,7 +427,7 @@ bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const while (upper != lastActivates.end()) { - if (upper->first - lower->first < memSpec->tNAW) + if (upper->first - lower->first < memSpec->tNAW_old) return false; upper++; lower++; @@ -481,7 +481,7 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const { ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank()); if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL); + read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 49f2bfc7..4867a332 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -60,13 +60,13 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, else if (m == 2) constraint = config.memSpec->tRFC2; else - constraint = config.memSpec->tRFC; + constraint = config.memSpec->tRFC_old; } else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) { constraint = config.memSpec->tXP; } else if (lastCmd == Command::SREFX) { constraint = config.memSpec->tXS; } else if (lastCmd == Command::Precharge || lastCmd == Command::PrechargeAll) { - constraint = config.memSpec->tRP; + constraint = config.memSpec->tRP_old; } else { reportFatal("Powerdown checker", commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 95be380a..6bce7e60 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -43,9 +43,9 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), Configuration::getInstance().getTrpb()); } else if (lastCmd.getCommand() == Command::Precharge) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); } else if (lastCmd.getCommand() == Command::PrechargeAll) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP); + cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); } else if (lastCmd.getCommand() == Command::ActB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok! @@ -65,7 +65,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const } ScheduledCommand lc; if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP); + cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } if ((lc = state.getLastCommand(Command::Activate, cmd.getBank())).isValidCommand()) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 9be11621..95a33009 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -51,7 +51,7 @@ const if (lastCommand.getCommand() == Command::Precharge || lastCommand.getCommand() == Command::PreB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -61,14 +61,14 @@ const config.memSpec->tRTP); } else if (lastCommand.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRTP + config.memSpec->tRP); + config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::Write) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); } else if (lastCommand.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::AutoRefresh) { auto m = Configuration::getInstance().getRefMode(); if (m == 4) @@ -79,7 +79,7 @@ const config.memSpec->tRFC2); else command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRFC); + config.memSpec->tRFC_old); } else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX) { command.establishMinDistanceFromStart(lastCommand.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index 9ef70882..a18f738d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -52,7 +52,7 @@ const if (lastCommand.getCommand() == Command::Precharge || lastCommand.getCommand() == Command::PreB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index d48a0715..86d7c35a 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -112,7 +112,7 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), - config.memSpec->tXSDLL); + config.memSpec->tXSDLL_old); } sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, @@ -125,7 +125,7 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? - config->tCCD_L : config->tCCD_S; + config->tCCD_L_old : config->tCCD_S_old; return max(tCCD, config->getReadAccessTime()); } @@ -138,8 +138,8 @@ sc_time ReadChecker::writeToRead(ScheduledCommand &write, || write.getCommand() == Command::WriteA); MemSpec *config = Configuration::getInstance().memSpec; - sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L : - config->tWTR_S; + sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L_old : + config->tWTR_S_old; return config->tWL + config->getWriteAccessTime() + tWTR; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index d1089eae..feb18d13 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -50,14 +50,14 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommandOnBank.getCommand() == Command::Precharge || lastCommandOnBank.getCommand() == Command::PrechargeAll) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRTP + config.memSpec->tRP); + config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -78,18 +78,18 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const || lastCommand.getCommand() == Command::PrechargeAll || lastCommand.getCommand() == Command::PreB) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::Activate || lastCommand.getCommand() == Command::ActB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); } else if (lastCommand.getCommand() == Command::ReadA) { command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRTP + config.memSpec->tRP); + config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::WriteA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP); + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX) { command.establishMinDistanceFromStart(lastCommand.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index 58bd856e..a62f2510 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -116,7 +116,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? - config->tCCD_L : config->tCCD_S; + config->tCCD_L_old : config->tCCD_S_old; return max(tCCD, config->getWriteAccessTime()); } diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 86e67e5b..2e7daef2 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -72,43 +72,43 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CCD = memSpec->tCCD_S_old / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; memTimingSpec.CKE = memSpec->tCKE / clk; memTimingSpec.CKESR = memSpec->tCKESR / clk; memTimingSpec.clkMhz = memSpec->clkMHz; // See also MemTimingSpec.cc in DRAMPower memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.FAW = memSpec->tNAW_old / clk; memTimingSpec.RAS = memSpec->tRAS / clk; memTimingSpec.RC = memSpec->tRC / clk; memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.REFI = memSpec->tREFI_old / clk; unsigned m = Configuration::getInstance().getRefMode(); if (m == 4) memTimingSpec.RFC = memSpec->tRFC4 / clk; else if (m == 2) memTimingSpec.RFC = memSpec->tRFC2 / clk; else - memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RFC = memSpec->tRFC_old / clk; memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RP = memSpec->tRP_old / clk; + memTimingSpec.RRD = memSpec->tRRD_S_old / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.TAW = memSpec->tNAW_old / clk; memTimingSpec.WL = memSpec->tWL / clk; memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.WTR = memSpec->tWTR_S_old / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 3beadc82..8a098d7c 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -72,43 +72,43 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CCD = memSpec->tCCD_S_old / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; memTimingSpec.CKE = memSpec->tCKE / clk; memTimingSpec.CKESR = memSpec->tCKESR / clk; memTimingSpec.clkMhz = memSpec->clkMHz; // See also MemTimingSpec.cc in DRAMPower memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.FAW = memSpec->tNAW_old / clk; memTimingSpec.RAS = memSpec->tRAS / clk; memTimingSpec.RC = memSpec->tRC / clk; memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.REFI = memSpec->tREFI_old / clk; unsigned m = Configuration::getInstance().getRefMode(); if (m == 4) memTimingSpec.RFC = memSpec->tRFC4 / clk; else if (m == 2) memTimingSpec.RFC = memSpec->tRFC2 / clk; else - memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RFC = memSpec->tRFC_old / clk; memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RP = memSpec->tRP_old / clk; + memTimingSpec.RRD = memSpec->tRRD_S_old / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.TAW = memSpec->tNAW_old / clk; memTimingSpec.WL = memSpec->tWL / clk; memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.WTR = memSpec->tWTR_S_old / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 87d84a0e..e6da902b 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -90,43 +90,43 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CCD = memSpec->tCCD_S_old / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; memTimingSpec.CKE = memSpec->tCKE / clk; memTimingSpec.CKESR = memSpec->tCKESR / clk; memTimingSpec.clkMhz = memSpec->clkMHz; // See also MemTimingSpec.cc in DRAMPower memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW / clk; + memTimingSpec.FAW = memSpec->tNAW_old / clk; memTimingSpec.RAS = memSpec->tRAS / clk; memTimingSpec.RC = memSpec->tRC / clk; memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.REFI = memSpec->tREFI_old / clk; unsigned m = Configuration::getInstance().getRefMode(); if (m == 4) memTimingSpec.RFC = memSpec->tRFC4 / clk; else if (m == 2) memTimingSpec.RFC = memSpec->tRFC2 / clk; else - memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RFC = memSpec->tRFC_old / clk; memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RP = memSpec->tRP_old / clk; + memTimingSpec.RRD = memSpec->tRRD_S_old / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW / clk; + memTimingSpec.TAW = memSpec->tNAW_old / clk; memTimingSpec.WL = memSpec->tWL / clk; memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.WTR = memSpec->tWTR_S_old / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; From 50f90176a0fa81b54b5511b53d91e463449f5a57 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 1 Jul 2019 11:16:36 +0200 Subject: [PATCH 014/183] Included specific timing parameters for different DRAMs. --- .../configuration/ConfigurationLoader.cpp | 141 ++++++++++++------ .../controller/core/configuration/MemSpec.h | 89 +++++------ 2 files changed, 140 insertions(+), 90 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 8ce8a0fd..c635bbc1 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -223,22 +223,31 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->DLL = true; memSpec->termination = true; - // MemTimings + // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); + + + // TODO: old timings, will me removed + memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); @@ -281,22 +290,38 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->DLL = true; memSpec->termination = true; - // MemTimings + // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); + memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); + memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); + memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); + memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); + memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); + + memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); + memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); + + + // TODO: old timings, will me removed memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD_S"); memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD_L"); memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD_L"); - memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); + memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR_S"); memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR_L"); memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); + memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); - memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); - memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); memSpec->refreshTimings.clear(); @@ -341,24 +366,37 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->DLL = false; // TODO: Correct? memSpec->termination = true; // TODO: Correct? - // MemTimings + // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCDMW = clk * queryUIntParameter(timings, "CCDMW"); + memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); + memSpec->tREFIAB = clk * queryUIntParameter(timings, "REFIAB"); + memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIAB"); + memSpec->tRFCAB = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XP"); - memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XS"); - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFCAB"); - // TODO: memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB"); - // TODO: memSpec->tREFIPB = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tRPPB = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + + + // TODO: old timings, will me removed + memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XP"); + memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XS"); + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { @@ -399,22 +437,33 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->DLL = false; memSpec->termination = false; - // MemTimings + // MemTimings specific for WideIO XMLElement *timings = memspec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); + + + // TODO: old timings, will me removed memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L_old = memSpec->tRRD_S_old; - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L_old = memSpec->tCCD_S_old; - memSpec->tNAW_old = clk * queryUIntParameter(timings, "TAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L_old = memSpec->tWTR_S_old; - memSpec->tXPDLL_old = memSpec->tXP; - memSpec->tXSDLL_old = memSpec->tXS; - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); - memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); - // TODO: tDQSCK was missing + memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_L_old = memSpec->tRRD_S_old; + memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_L_old = memSpec->tCCD_S_old; + memSpec->tNAW_old = clk * queryUIntParameter(timings, "TAW"); + memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); + memSpec->tWTR_L_old = memSpec->tWTR_S_old; + memSpec->tXPDLL_old = memSpec->tXP; + memSpec->tXSDLL_old = memSpec->tXS; + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); + memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index eb53a3b7..09f91b76 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -107,16 +107,17 @@ struct MemSpec sc_time tNAW_old; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else sc_time tRP_old; // precharge-time (pre -> act same bank) - sc_time tRFC_old; //min ref->act delay 1X mode - sc_time tRFC2; //min ref->act delay 2X mode - sc_time tRFC4; //min ref->act delay 4X mode + sc_time tRFC_old; // min ref->act delay 1X mode + // TODO: only available in DDR4? Remove in DramDDR3 and DramWideIO! + sc_time tRFC2; // min ref->act delay 2X mode + sc_time tRFC4; // min ref->act delay 4X mode sc_time tREFI_old; // auto refresh must be issued at an average periodic interval tREFI - sc_time tCCD_S_old; //max(bl, tCCD) is relevant for rd->rd + sc_time tCCD_S_old; // max(bl, tCCD) is relevant for rd->rd sc_time tCCD_L_old; - sc_time tRRD_S_old; //min time bw 2 succesive ACT to different banks (different bank group) - sc_time tRRD_L_old; //.. (same bank group) - sc_time tWTR_S_old; //write to read (different bank group) - sc_time tWTR_L_old; //.. (same bank group) + sc_time tRRD_S_old; // min time bw 2 succesive ACT to different banks (different bank group) + sc_time tRRD_L_old; // .. (same bank group) + sc_time tWTR_S_old; // write to read (different bank group) + sc_time tWTR_L_old; // .. (same bank group) sc_time tXPDLL_old; // min delay to row access command after pdnpx pdnax for dll commands sc_time tXSDLL_old; // min delay to row access command after srefx for dll commands @@ -171,29 +172,29 @@ struct MemSpecDDR3 : public MemSpec { sc_time tCCD; sc_time tFAW; - sc_time tWTR; -// sc_time tREFI; -// sc_time tRFC; -// sc_time tRP; + sc_time tREFI; + sc_time tRFC; + sc_time tRP; sc_time tRRD; -// sc_time tXPDLL; -// sc_time tXSDLL; + sc_time tWTR; + sc_time tXPDLL; + sc_time tXSDLL; }; struct MemSpecDDR4 : public MemSpec { -// sc_time tCCD_S; -// sc_time tCCD_L; + sc_time tCCD_S; + sc_time tCCD_L; sc_time tFAW; -// sc_time tWTR_S; -// sc_time tWTR_L; -// sc_time tREFI; -// sc_time tRFC; -// sc_time tRP; -// sc_time tRRD_S; -// sc_time tRRD_L; -// sc_time tXPDLL; -// sc_time tXSDLL; + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tRRD_S; + sc_time tRRD_L; + sc_time tWTR_S; + sc_time tWTR_L; + sc_time tXPDLL; + sc_time tXSDLL; // Returns the execution time for commands that have a fixed execution time sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; @@ -201,32 +202,32 @@ struct MemSpecDDR4 : public MemSpec struct MemSpecWideIO : public MemSpec { -// sc_time tCCD; -// sc_time tWTR; + sc_time tCCD; + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tRRD; sc_time tTAW; -// sc_time tREFI; -// sc_time tRFC; -// sc_time tRP; -// sc_time tRRD; -// sc_time tXPDLL; -// sc_time tXSDLL; + sc_time tWTR; + sc_time tXPDLL; + sc_time tXSDLL; }; struct MemSpecLPDDR4 : public MemSpec { -// sc_time tCCD; -// sc_time tCCDMW; -// sc_time tESCKE; + sc_time tCCD; + sc_time tCCDMW; + sc_time tESCKE; sc_time tFAW; -// sc_time tWTR; -// sc_time tPPD; -// sc_time tREFIAB; -// sc_time tREFIPB; -// sc_time tRFCAB; -// sc_time tRFCPB; + sc_time tWTR; + sc_time tPPD; + sc_time tREFIAB; + sc_time tREFIPB; + sc_time tRFCAB; + sc_time tRFCPB; sc_time tRPAB; -// sc_time tRPPB; -// sc_time tRRD; + sc_time tRPPB; + sc_time tRRD; }; #endif // MEMSPEC_H From ffdc67945a920e8c170997a8bd305110900ca90b Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 1 Jul 2019 15:00:01 +0200 Subject: [PATCH 015/183] Removed specific DRAMPower configuration in DRAMs. --- .../configuration/ConfigurationLoader.cpp | 14 +-- .../controller/core/configuration/MemSpec.h | 4 +- .../core/scheduling/checker/CheckerDDR3.h | 3 +- DRAMSys/library/src/simulation/Dram.cpp | 97 +++++++++++++++++++ DRAMSys/library/src/simulation/DramDDR3.cpp | 96 +----------------- DRAMSys/library/src/simulation/DramDDR4.cpp | 96 +----------------- .../library/src/simulation/DramRecordable.cpp | 2 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 96 +----------------- 8 files changed, 111 insertions(+), 297 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index c635bbc1..945252f5 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -181,7 +181,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); @@ -216,8 +216,8 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture - XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = 1; memSpec->nActivate = 4; memSpec->DLL = true; @@ -284,7 +284,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); memSpec->nActivate = 4; memSpec->DLL = true; @@ -359,8 +359,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture: - XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = 1; memSpec->nActivate = 4; memSpec->DLL = false; // TODO: Correct? @@ -431,8 +431,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) // MemSpecification //XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); + //memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO memSpec->NumberOfBankGroups = 1; - memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO memSpec->nActivate = 2; memSpec->DLL = false; memSpec->termination = false; diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 09f91b76..abbf49a7 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -108,7 +108,7 @@ struct MemSpec sc_time tNAW_old; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else sc_time tRP_old; // precharge-time (pre -> act same bank) sc_time tRFC_old; // min ref->act delay 1X mode - // TODO: only available in DDR4? Remove in DramDDR3 and DramWideIO! + // TODO: used in DDR4 and LPDDR4, remove in DramDDR3 and DramWideIO or everywhere sc_time tRFC2; // min ref->act delay 2X mode sc_time tRFC4; // min ref->act delay 4X mode sc_time tREFI_old; // auto refresh must be issued at an average periodic interval tREFI @@ -197,7 +197,7 @@ struct MemSpecDDR4 : public MemSpec sc_time tXSDLL; // Returns the execution time for commands that have a fixed execution time - sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; + virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override; }; struct MemSpecWideIO : public MemSpec diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h index 37c26250..28baca01 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h @@ -18,8 +18,7 @@ public: } virtual ~CheckerDDR3() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; + virtual void delayToSatisfyConstraints(ScheduledCommand &command) const override; private: MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index a380ceea..88383062 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -69,6 +69,103 @@ Dram::Dram(sc_module_name) : tSocket("socket") tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); + + MemSpec *memSpec = Configuration::getInstance().memSpec; + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S_old / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW_old / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI_old / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC_old / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP_old / clk; + memTimingSpec.RRD = memSpec->tRRD_S_old / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW_old / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S_old / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } Dram::~Dram() diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 2e7daef2..c75aebe2 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -49,99 +49,5 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); + // TODO: Specific configuration of DRAMPower } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 8a098d7c..e3bc459b 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -49,99 +49,5 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0);; + // TODO: Specific configuration of DRAMPower } diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 56c5e27e..ccf101b1 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -56,7 +56,7 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe template DramRecordable::~DramRecordable() { - BaseDram::DRAMPower->calcEnergy(); + this->DRAMPower->calcEnergy(); recordPower(); tlmRecorder->closeConnection(); } diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index e6da902b..459396e9 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -67,101 +67,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); + // TODO: Specific configuration of DRAMPower } DramWideIO::~DramWideIO() From 41cc447d8657dee72ffcd545fe5c5de4a4032fba Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 2 Jul 2019 14:25:53 +0200 Subject: [PATCH 016/183] Included timing parameters for RGR. --- .../core/configuration/Configuration.h | 2 + .../configuration/ConfigurationLoader.cpp | 38 +++++++++++++++--- .../controller/core/configuration/MemSpec.h | 39 ++++++++++++------- .../core/scheduling/ScheduledCommand.h | 14 ++----- 4 files changed, 64 insertions(+), 29 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index 80f7ae87..fe09ecda 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -88,6 +88,7 @@ struct Configuration unsigned int NumberOfMemChannels = 1; bool ControllerCoreRefDisable = false; bool RowGranularRef = false; + // TODO: will be removed in the future unsigned int trasbclk = 0; sc_time getTrasb(); unsigned int trrdblclk = 0; @@ -100,6 +101,7 @@ struct Configuration sc_time getTrcb(); unsigned int tfawbclk = 0; sc_time getTfawb(); + // ----------------------------------- bool RGRB0 = true; bool RGRB1 = true; bool RGRB2 = true; diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 945252f5..f0aeaf8b 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -199,7 +199,11 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->tCL = clk * queryUIntParameter(timings, "CL"); memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRAS_ORGR = parameterExists(timings, "RAS_ORGR") ? + clk * queryUIntParameter(timings, "RAS_ORGR") : memSpec->tRAS; memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRC_ORGR = parameterExists(timings, "RC_ORGR") ? + clk * queryUIntParameter(timings, "RC_ORGR") : memSpec->tRC; memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tRL = clk * queryUIntParameter(timings, "RL"); memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); @@ -228,10 +232,16 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) sc_time clk = memSpec->clk; memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? + clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? + clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ? + clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD; memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); @@ -296,11 +306,19 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? + clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? + clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); + memSpec->tRRD_S_ORGR = parameterExists(timings, "RRD_S_ORGR") ? + clk * queryUIntParameter(timings, "RRD_S_ORGR") : memSpec->tRRD_S; memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); + memSpec->tRRD_L_ORGR = parameterExists(timings, "RRD_L_ORGR") ? + clk * queryUIntParameter(timings, "RRD_L_ORGR") : memSpec->tRRD_L; memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); @@ -373,19 +391,24 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCCDMW = clk * queryUIntParameter(timings, "CCDMW"); memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? + clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); memSpec->tREFIAB = clk * queryUIntParameter(timings, "REFIAB"); - memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIAB"); + memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); memSpec->tRFCAB = clk * queryUIntParameter(timings, "RFCAB"); memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); memSpec->tRPPB = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRPPB_ORGR = parameterExists(timings, "RPPB_ORGR") ? + clk * queryUIntParameter(timings, "RPPB_ORGR") : memSpec->tRPPB; memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ? + clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD; // TODO: old timings, will me removed - memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); @@ -397,6 +420,7 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XS"); memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFCAB"); memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB"); + memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { @@ -444,11 +468,15 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? + clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ? + clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD; memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); + memSpec->tTAW_ORGR = parameterExists(timings, "TAW_ORGR") ? + clk * queryUIntParameter(timings, "TAW_ORGR") : memSpec->tTAW; memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); // TODO: old timings, will me removed diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index abbf49a7..7a3ad2ca 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -90,7 +90,9 @@ struct MemSpec sc_time tCL; // unused, will be used in the future sc_time tDQSCK; sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRAS_ORGR; sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRC_ORGR; sc_time tRCD; // act -> read/write sc_time tRL; // read latency (read command start to data strobe) sc_time tRTP; // read to precharge @@ -172,10 +174,13 @@ struct MemSpecDDR3 : public MemSpec { sc_time tCCD; sc_time tFAW; + sc_time tFAW_ORGR; sc_time tREFI; sc_time tRFC; sc_time tRP; + sc_time tRP_ORGR; sc_time tRRD; + sc_time tRRD_ORGR; sc_time tWTR; sc_time tXPDLL; sc_time tXSDLL; @@ -186,11 +191,15 @@ struct MemSpecDDR4 : public MemSpec sc_time tCCD_S; sc_time tCCD_L; sc_time tFAW; + sc_time tFAW_ORGR; sc_time tREFI; sc_time tRFC; sc_time tRP; + sc_time tRP_ORGR; sc_time tRRD_S; + sc_time tRRD_S_ORGR; sc_time tRRD_L; + sc_time tRRD_L_ORGR; sc_time tWTR_S; sc_time tWTR_L; sc_time tXPDLL; @@ -200,25 +209,13 @@ struct MemSpecDDR4 : public MemSpec virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override; }; -struct MemSpecWideIO : public MemSpec -{ - sc_time tCCD; - sc_time tREFI; - sc_time tRFC; - sc_time tRP; - sc_time tRRD; - sc_time tTAW; - sc_time tWTR; - sc_time tXPDLL; - sc_time tXSDLL; -}; - struct MemSpecLPDDR4 : public MemSpec { sc_time tCCD; sc_time tCCDMW; sc_time tESCKE; sc_time tFAW; + sc_time tFAW_ORGR; sc_time tWTR; sc_time tPPD; sc_time tREFIAB; @@ -227,7 +224,23 @@ struct MemSpecLPDDR4 : public MemSpec sc_time tRFCPB; sc_time tRPAB; sc_time tRPPB; + sc_time tRPPB_ORGR; sc_time tRRD; + sc_time tRRD_ORGR; +}; + +struct MemSpecWideIO : public MemSpec +{ + sc_time tCCD; + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tRP_ORGR; + sc_time tRRD; + sc_time tRRD_ORGR; + sc_time tTAW; + sc_time tTAW_ORGR; + sc_time tWTR; }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h index bc4721b7..cca521a2 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h @@ -46,27 +46,19 @@ class ScheduledCommand { public: - ScheduledCommand(Command command, sc_time start, sc_time executionTime, const DramExtension &extension) : command(command), start(start), executionTime(executionTime), - end(start + executionTime), - extension(extension) - { - } + end(start + executionTime), extension(extension) {} ScheduledCommand(Command command, sc_time start, sc_time executionTime, const tlm::tlm_generic_payload &payload) : ScheduledCommand(command, start, executionTime, - DramExtension::getExtension(payload)) - { - } + DramExtension::getExtension(payload)) {} ScheduledCommand() : command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), - end(SC_ZERO_TIME), extension() - { - } + end(SC_ZERO_TIME), extension() {} bool isNoCommand() const; bool isValidCommand() const; From 34626448bb287996c093fa90c61d77b6e7119dd4 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 2 Jul 2019 16:25:43 +0200 Subject: [PATCH 017/183] RefMode (tRFC) is now only configurable during initialization. --- .../core/configuration/Configuration.cpp | 2 +- .../configuration/ConfigurationLoader.cpp | 48 ++++++++++--------- .../controller/core/configuration/MemSpec.cpp | 15 ++---- .../controller/core/configuration/MemSpec.h | 11 +---- .../core/refresh/RefreshManager.cpp | 2 +- .../core/refresh/RefreshManagerBankwise.cpp | 2 +- .../core/scheduling/checker/ActBChecker.cpp | 8 +--- .../scheduling/checker/ActivateChecker.cpp | 12 +---- .../scheduling/checker/PowerDownChecker.cpp | 8 +--- .../checker/PrechargeAllChecker.cpp | 12 +---- DRAMSys/library/src/simulation/DRAMSys.cpp | 10 ++-- DRAMSys/library/src/simulation/Dram.cpp | 8 +--- 12 files changed, 46 insertions(+), 92 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index 72811ff4..7e7000b6 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -332,7 +332,7 @@ std::string Configuration::getPathToResources() { return pathToResources; } - +// TODO: Never used void Configuration::setParameters(std::map parameterMap) { diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index f0aeaf8b..8a08be11 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -235,6 +235,7 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + std::cout << "RefMode: " << Configuration::getInstance().getRefMode() << std::endl; memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? @@ -261,11 +262,10 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); - } + memSpec->tREFI_old); // Currents and Volatages: TODO Check if this is correct. XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -309,7 +309,13 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + unsigned refMode = Configuration::getInstance().getRefMode(); + if (refMode == 1) + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + else if (refMode == 2) + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2"); + else // if (refMode == 4) + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; @@ -324,9 +330,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tRFC2 = clk * queryUIntParameter(timings, "RFC2"); - memSpec->tRFC4 = clk * queryUIntParameter(timings, "RFC4"); - // TODO: old timings, will me removed memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); @@ -339,16 +342,19 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR_L"); memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); + unsigned refMode_old = Configuration::getInstance().getRefMode(); + if (refMode_old == 1) + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); + else if (refMode_old == 2) + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC2"); + else // if (refMode_old == 4) + memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC4"); memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tRFC2, - memSpec->tRFC4, - memSpec->tREFI_old); - } + memSpec->tREFI_old); // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -422,11 +428,10 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB"); memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); - } + memSpec->tREFI_old); // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -493,11 +498,10 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) { + memSpec->refreshTimings.clear(); + for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); - } + memSpec->tREFI_old); // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index faaa8449..d130f28f 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -96,10 +96,8 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay else if (command == Command::PrechargeAll) return tRP_old; else if (command == Command::AutoRefresh) - { return getElementFromMap(refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC; - } + DramExtension::getExtension(payload).getBank()).tRFC; else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) return clk; else @@ -132,15 +130,8 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload return tRP_old; else if (command == Command::AutoRefresh) { - if (Configuration::getInstance().getRefMode() == 4) - return getElementFromMap(refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC4; - else if (Configuration::getInstance().getRefMode() == 2) - return getElementFromMap(refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC2; - else - return getElementFromMap(refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC; + return getElementFromMap(refreshTimings, + DramExtension::getExtension(payload).getBank()).tRFC; } else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) return clk; diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 7a3ad2ca..7f5adacd 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -46,13 +46,9 @@ struct RefreshTiming { RefreshTiming() {} - RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tRFC2(SC_ZERO_TIME), - tRFC4(SC_ZERO_TIME), tREFI(tREFI) {} - RefreshTiming(sc_time tRFC, sc_time tRFC2, sc_time tRFC4, - sc_time tREFI) : tRFC(tRFC), tRFC2(tRFC2), tRFC4(tRFC4), tREFI(tREFI) {} + RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {} + sc_time tRFC; - sc_time tRFC2; - sc_time tRFC4; sc_time tREFI; }; @@ -110,9 +106,6 @@ struct MemSpec sc_time tNAW_old; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else sc_time tRP_old; // precharge-time (pre -> act same bank) sc_time tRFC_old; // min ref->act delay 1X mode - // TODO: used in DDR4 and LPDDR4, remove in DramDDR3 and DramWideIO or everywhere - sc_time tRFC2; // min ref->act delay 2X mode - sc_time tRFC4; // min ref->act delay 4X mode sc_time tREFI_old; // auto refresh must be issued at an average periodic interval tREFI sc_time tCCD_S_old; // max(bl, tCCD) is relevant for rd->rd sc_time tCCD_L_old; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index 719a19d6..0a309fce 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -50,7 +50,7 @@ RefreshManager::RefreshManager(sc_module_name, { auto m = controllerCore.config.getRefMode(); tREFIx = timing.tREFI / m; - tRFCx = m == 4 ? timing.tRFC4 : m == 2 ? timing.tRFC2 : timing.tRFC; + tRFCx = timing.tRFC; postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index d060ec7d..8c2b907d 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -48,7 +48,7 @@ RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name, { auto m = controllerCore.config.getRefMode(); tREFIx = timing.tREFI / m; - tRFCx = m == 4 ? timing.tRFC4 : m == 2 ? timing.tRFC2 : timing.tRFC; + tRFCx = timing.tRFC; postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index bb75b65f..d16b788d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -62,13 +62,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); } else if (lcb.getCommand() == Command::AutoRefresh) { - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC4); - else if (m == 2) - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC2); - else - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC_old); + cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC_old); } else if (lcb.getCommand() == Command::PDNPX || lcb.getCommand() == Command::PDNAX) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 491241db..576cc276 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -65,16 +65,8 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRFC4); - else if (m == 2) - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRFC2); - else - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRFC_old); + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + config.memSpec->tRFC_old); } else if (lastCommandOnBank.getCommand() == Command::PDNPX || lastCommandOnBank.getCommand() == Command::PDNAX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 4867a332..fd0b2ef5 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -54,13 +54,7 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->clk; } else if (lastCmd == Command::AutoRefresh) { - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - constraint = config.memSpec->tRFC4; - else if (m == 2) - constraint = config.memSpec->tRFC2; - else - constraint = config.memSpec->tRFC_old; + constraint = config.memSpec->tRFC_old; } else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) { constraint = config.memSpec->tXP; } else if (lastCmd == Command::SREFX) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 95a33009..5c302ef9 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -70,16 +70,8 @@ const config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::AutoRefresh) { - auto m = Configuration::getInstance().getRefMode(); - if (m == 4) - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRFC4); - else if (m == 2) - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRFC2); - else - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRFC_old); + command.establishMinDistanceFromStart(lastCommand.getStart(), + config.memSpec->tRFC_old); } else if (lastCommand.getCommand() == Command::PDNAX || lastCommand.getCommand() == Command::PDNPX) { command.establishMinDistanceFromStart(lastCommand.getStart(), diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 5f1f1fa4..a472c40f 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -108,11 +108,6 @@ DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name, AddressDecoder::getInstance().print(); - ConfigurationLoader::loadMemSpec(Configuration::getInstance(), - pathToResources - + "configs/memspecs/" - + memspec); - // Setup the memory controller with the propriate xml file ConfigurationLoader::loadMCConfig(Configuration::getInstance(), pathToResources @@ -129,6 +124,11 @@ DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name, + "configs/thermalsim/" + thermalconfig); + ConfigurationLoader::loadMemSpec(Configuration::getInstance(), + pathToResources + + "configs/memspecs/" + + memspec); + // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. std::string simName; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 88383062..7228216e 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -108,13 +108,7 @@ Dram::Dram(sc_module_name) : tSocket("socket") memTimingSpec.RC = memSpec->tRC / clk; memTimingSpec.RCD = memSpec->tRCD / clk; memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; + memTimingSpec.RFC = memSpec->tRFC_old / clk; memTimingSpec.RL = memSpec->tRL / clk; memTimingSpec.RP = memSpec->tRP_old / clk; memTimingSpec.RRD = memSpec->tRRD_S_old / clk; From 37b2dc9e4d8e92262a9ff1ed0a923e98493a4a9d Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 4 Jul 2019 10:13:19 +0200 Subject: [PATCH 018/183] Renaming of commands according to DRAMml. --- DRAMSys/library/src/controller/Command.cpp | 64 +++--- DRAMSys/library/src/controller/Command.h | 32 +-- DRAMSys/library/src/controller/Controller.cpp | 32 +-- .../src/controller/ControllerState.cpp | 22 +-- .../src/controller/RecordableController.cpp | 2 +- .../src/controller/core/ControllerCore.cpp | 64 +++--- .../configuration/ConfigurationLoader.cpp | 1 - .../controller/core/configuration/MemSpec.cpp | 48 ++--- .../core/powerdown/IPowerDownManager.h | 12 +- .../core/powerdown/PowerDownManager.cpp | 6 +- .../powerdown/PowerDownManagerBankwise.cpp | 6 +- .../powerdown/PowerDownManagerTimeout.cpp | 16 +- .../PowerDownManagerTimeoutBankwise.cpp | 14 +- .../src/controller/core/refresh/RGR.cpp | 12 +- .../core/refresh/RefreshManager.cpp | 18 +- .../core/refresh/RefreshManagerBankwise.cpp | 14 +- .../core/scheduling/ScheduledCommand.cpp | 8 +- .../core/scheduling/checker/ActBChecker.cpp | 26 +-- .../scheduling/checker/ActivateChecker.cpp | 24 +-- .../core/scheduling/checker/CheckerDDR3.cpp | 182 +++++++++--------- .../scheduling/checker/PowerDownChecker.cpp | 36 ++-- .../core/scheduling/checker/PreBChecker.cpp | 24 +-- .../checker/PrechargeAllChecker.cpp | 28 +-- .../scheduling/checker/PrechargeChecker.cpp | 18 +- .../core/scheduling/checker/ReadChecker.cpp | 42 ++-- .../scheduling/checker/RefreshChecker.cpp | 40 ++-- .../core/scheduling/checker/WriteChecker.cpp | 40 ++-- .../library/src/controller/scheduler/Fifo.cpp | 4 +- .../src/controller/scheduler/FifoStrict.cpp | 6 +- .../src/controller/scheduler/IScheduler.cpp | 12 +- .../library/src/controller/scheduler/SMS.cpp | 6 +- DRAMSys/library/src/simulation/Dram.cpp | 22 +-- .../library/src/simulation/DramRecordable.cpp | 6 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 22 +-- 34 files changed, 454 insertions(+), 455 deletions(-) diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 4ced60b8..ed6310ab 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -42,53 +42,53 @@ std::string commandToString(Command command) { switch (command) { - case Command::Read: + case Command::RD: return "RD"; break; - case Command::ReadA: + case Command::RDA: return "RDA"; break; - case Command::Write: + case Command::WR: return "WR"; break; - case Command::WriteA: + case Command::WRA: return "WRA"; break; - case Command::PreB: + case Command::PREB: return "PREB"; break; - case Command::Precharge: + case Command::PRE: return "PRE"; break; - case Command::ActB: + case Command::ACTB: return "ACTB"; break; - case Command::Activate: + case Command::ACT: return "ACT"; break; - case Command::PrechargeAll: + case Command::PREA: return "PRE_ALL"; break; - case Command::AutoRefresh: + case Command::REFA: return "REF"; break; - case Command::PDNA: + case Command::PDEA: return "PDNA"; break; - case Command::PDNAX: + case Command::PDXA: return "PDNAX"; break; - case Command::PDNP: + case Command::PDEP: return "PDNP"; break; - case Command::PDNPX: + case Command::PDXP: return "PDNPX"; break; - case Command::SREF: + case Command::SREFEN: return "SREF"; break; - case Command::SREFX: + case Command::SREFEX: return "SREFX"; break; @@ -106,22 +106,22 @@ std::string commandToString(Command command) const std::vector &getAllCommands() { - static std::vector allCommands( { Command::PreB, - Command::Precharge, - Command::PrechargeAll, - Command::ActB, - Command::Activate, - Command::Read, - Command::Write, - Command::ReadA, - Command::WriteA, - Command::AutoRefresh, - Command::PDNA, - Command::PDNAX, - Command::PDNP, - Command::PDNPX, - Command::SREF, - Command::SREFX + static std::vector allCommands( { Command::PREB, + Command::PRE, + Command::PREA, + Command::ACTB, + Command::ACT, + Command::RD, + Command::WR, + Command::RDA, + Command::WRA, + Command::REFA, + Command::PDEA, + Command::PDXA, + Command::PDEP, + Command::PDXP, + Command::SREFEN, + Command::SREFEX }); return allCommands; } diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index e8aa28e7..08d51d17 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -41,22 +41,22 @@ enum class Command { NOP, - PreB, - Precharge, - PrechargeAll, - ActB, - Activate, - Read, - Write, - ReadA, - WriteA, - AutoRefresh, - PDNA, - PDNAX, - PDNP, - PDNPX, - SREF, - SREFX + PREB, + PRE, + PREA, + ACTB, + ACT, + RD, + WR, + RDA, + WRA, + REFA, + PDEA, + PDXA, + PDEP, + PDXP, + SREFEN, + SREFEX }; std::string commandToString(Command command); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 369825f5..e9db7911 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -142,70 +142,70 @@ void Controller::send(const ScheduledCommand &command, switch (command.getCommand()) { //TODO: refactor tlm recorder - case Command::Read: + case Command::RD: phase = BEGIN_RD; break; - case Command::ReadA: + case Command::RDA: phase = BEGIN_RDA; break; - case Command::Write: + case Command::WR: phase = BEGIN_WR; break; - case Command::WriteA: + case Command::WRA: phase = BEGIN_WRA; break; - case Command::AutoRefresh: + case Command::REFA: if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_REFA; else phase = BEGIN_REFB; break; - case Command::Activate: + case Command::ACT: phase = BEGIN_ACT; break; - case Command::ActB: + case Command::ACTB: phase = BEGIN_ACTB; break; - case Command::Precharge: + case Command::PRE: phase = BEGIN_PRE; break; - case Command::PreB: + case Command::PREB: phase = BEGIN_PREB; break; - case Command::PrechargeAll: + case Command::PREA: phase = BEGIN_PRE_ALL; break; - case Command::PDNA: + case Command::PDEA: if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_PDNA; else phase = BEGIN_PDNAB; break; - case Command::PDNAX: + case Command::PDXA: if (!Configuration::getInstance().BankwiseLogic) phase = END_PDNA; else phase = END_PDNAB; break; - case Command::PDNP: + case Command::PDEP: if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_PDNP; else phase = BEGIN_PDNPB; break; - case Command::PDNPX: + case Command::PDXP: if (!Configuration::getInstance().BankwiseLogic) phase = END_PDNP; else phase = END_PDNPB; break; - case Command::SREF: + case Command::SREFEN: if (!Configuration::getInstance().BankwiseLogic) phase = BEGIN_SREF; else phase = BEGIN_SREFB; break; - case Command::SREFX: + case Command::SREFEX: if (!Configuration::getInstance().BankwiseLogic) phase = END_SREF; else diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index c7318363..fc56c269 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -105,42 +105,42 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) = scheduledCommand; switch (scheduledCommand.getCommand()) { - case Command::Read: + case Command::RD: lastDataStrobeCommands.emplace_back(scheduledCommand); break; - case Command::ReadA: + case Command::RDA: rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); lastDataStrobeCommands.emplace_back(scheduledCommand); break; - case Command::Write: + case Command::WR: lastDataStrobeCommands.emplace_back(scheduledCommand); break; - case Command::WriteA: + case Command::WRA: rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); lastDataStrobeCommands.emplace_back(scheduledCommand); break; - case Command::AutoRefresh: + case Command::REFA: break; - case Command::ActB: + case Command::ACTB: rowBufferStates->openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow()); lastActivatesB.emplace(scheduledCommand.getStart(), scheduledCommand); break; - case Command::Activate: + case Command::ACT: rowBufferStates->openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow()); lastActivates.emplace(scheduledCommand.getStart(), scheduledCommand); break; - case Command::PreB: + case Command::PREB: rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); break; - case Command::Precharge: + case Command::PRE: rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); break; - case Command::PrechargeAll: + case Command::PREA: rowBufferStates->closeAllRowBuffers(); break; - case Command::SREF: + case Command::SREFEN: rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); break; default: diff --git a/DRAMSys/library/src/controller/RecordableController.cpp b/DRAMSys/library/src/controller/RecordableController.cpp index 51ff4f21..9fd2d70d 100644 --- a/DRAMSys/library/src/controller/RecordableController.cpp +++ b/DRAMSys/library/src/controller/RecordableController.cpp @@ -83,7 +83,7 @@ void RecordableController::recordPhase(tlm::tlm_generic_payload &trans, void RecordableController::schedule(Command command, gp &payload) { Controller::schedule(command, payload); - if (commandIsIn(command, {Command::Read, Command::ReadA, Command::Write, Command::WriteA})) { + if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) { ScheduledCommand scheduledCommand = controllerCore->state->getLastCommand( command, DramExtension::getBank(payload)); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 36bf1cc6..a6bef2cc 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -68,23 +68,23 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, { state = new ControllerState(name(), &config); - commandChecker[Command::ActB] = new ActBChecker(config, *state); - commandChecker[Command::Activate] = new ActivateChecker(config, *state); - commandChecker[Command::PreB] = new PreBChecker(config, *state); - commandChecker[Command::Precharge] = new PrechargeChecker(config, *state); - commandChecker[Command::PrechargeAll] = new PrechargeAllChecker(config, *state); - commandChecker[Command::Read] = new ReadChecker(config, *state); - commandChecker[Command::ReadA] = commandChecker[Command::Read]; - commandChecker[Command::Write] = new WriteChecker(config, *state); - commandChecker[Command::WriteA] = commandChecker[Command::Write]; + commandChecker[Command::ACTB] = new ActBChecker(config, *state); + commandChecker[Command::ACT] = new ActivateChecker(config, *state); + commandChecker[Command::PREB] = new PreBChecker(config, *state); + commandChecker[Command::PRE] = new PrechargeChecker(config, *state); + commandChecker[Command::PREA] = new PrechargeAllChecker(config, *state); + commandChecker[Command::RD] = new ReadChecker(config, *state); + commandChecker[Command::RDA] = commandChecker[Command::RD]; + commandChecker[Command::WR] = new WriteChecker(config, *state); + commandChecker[Command::WRA] = commandChecker[Command::WR]; - commandChecker[Command::AutoRefresh] = new RefreshChecker(config, *state); - commandChecker[Command::PDNA] = new PowerDownChecker(config, *state); - commandChecker[Command::PDNP] = commandChecker[Command::PDNA]; - commandChecker[Command::SREF] = commandChecker[Command::PDNA]; - commandChecker[Command::PDNAX] = commandChecker[Command::PDNA]; - commandChecker[Command::PDNPX] = commandChecker[Command::PDNA]; - commandChecker[Command::SREFX] = commandChecker[Command::PDNA]; + commandChecker[Command::REFA] = new RefreshChecker(config, *state); + commandChecker[Command::PDEA] = new PowerDownChecker(config, *state); + commandChecker[Command::PDEP] = commandChecker[Command::PDEA]; + commandChecker[Command::SREFEN] = commandChecker[Command::PDEA]; + commandChecker[Command::PDXA] = commandChecker[Command::PDEA]; + commandChecker[Command::PDXP] = commandChecker[Command::PDEA]; + commandChecker[Command::SREFEX] = commandChecker[Command::PDEA]; //timingChecker = new CheckerDDR3(config, *state); @@ -119,13 +119,13 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, ControllerCore::~ControllerCore() { - delete commandChecker[Command::Activate]; - delete commandChecker[Command::Precharge]; - delete commandChecker[Command::PrechargeAll]; - delete commandChecker[Command::Read]; - delete commandChecker[Command::Write]; - delete commandChecker[Command::AutoRefresh]; - delete commandChecker[Command::PDNA]; + delete commandChecker[Command::ACT]; + delete commandChecker[Command::PRE]; + delete commandChecker[Command::PREA]; + delete commandChecker[Command::RD]; + delete commandChecker[Command::WR]; + delete commandChecker[Command::REFA]; + delete commandChecker[Command::PDEA]; delete timingChecker; delete refreshManager; delete powerDownManager; @@ -150,7 +150,7 @@ void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload) time); //expects PDNA and PDNP to exit without delay bool pdnpToSrefTransition = false; if (config.PowerDownMode == EPowerDownMode::Staggered) - pdnpToSrefTransition = (state->getLastCommand(Command::PDNPX, + pdnpToSrefTransition = (state->getLastCommand(Command::PDXP, bank).getStart() >= time); if (pdnpToSrefTransition) powerDownManager->sleep(bank, time); @@ -174,7 +174,7 @@ bool ControllerCore::scheduleRequest(Command command, } else { - if (!((command == Command::Precharge || command == Command::Activate) + if (!((command == Command::PRE || command == Command::ACT) && refreshManager->hasCollision(scheduledCommand))) { state->change(scheduledCommand); @@ -221,23 +221,23 @@ bool ControllerCore::bankIsBusy(Bank bank) { return false; } - else if (lastScheduledCommand.commandIsIn({Command::Write, Command::Read})) + else if (lastScheduledCommand.commandIsIn({Command::WR, Command::RD})) { // Read and writes can overlap, so the bank should not be busy during a rd/wr return (time < lastScheduledCommand.getStart()); } - else if (lastScheduledCommand.commandIsIn({Command::WriteA, Command::ReadA, Command::PreB, - Command::Precharge, Command::PrechargeAll, - Command::ActB, Command::Activate})) + else if (lastScheduledCommand.commandIsIn({Command::WRA, Command::RDA, Command::PREB, + Command::PRE, Command::PREA, + Command::ACTB, Command::ACT})) { return (time < lastScheduledCommand.getEnd()); } - else if (lastScheduledCommand.getCommand() == Command::AutoRefresh) + else if (lastScheduledCommand.getCommand() == Command::REFA) { return (time < lastScheduledCommand.getEnd()); } - else if (lastScheduledCommand.commandIsIn({Command::SREFX, Command::PDNPX, Command::PDNAX, - Command::SREF, Command::PDNP, Command::PDNA})) + else if (lastScheduledCommand.commandIsIn({Command::SREFEX, Command::PDXP, Command::PDXA, + Command::SREFEN, Command::PDEP, Command::PDEA})) { return false; } diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 8a08be11..5e3a9b44 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -235,7 +235,6 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); - std::cout << "RefMode: " << Configuration::getInstance().getRefMode() << std::endl; memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index d130f28f..9b01d316 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -62,9 +62,9 @@ sc_time MemSpec::getWriteAccessTime() const sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const { - if (command == Command::PDNA || command == Command::PDNP) + if (command == Command::PDEA || command == Command::PDEP) return tCKE; - else if (command == Command::SREF) + else if (command == Command::SREFEN) return tCKESR; else { @@ -77,28 +77,28 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const // Returns the execution time for commands that have a fixed execution time sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const { - if (command == Command::PreB) + if (command == Command::PREB) return Configuration::getInstance().getTrpb(); - else if (command == Command::Precharge || command == Command::PrechargeAll) + else if (command == Command::PRE || command == Command::PREA) return tRP_old; - else if (command == Command::ActB) + else if (command == Command::ACTB) return tRCD; - else if (command == Command::Activate) + else if (command == Command::ACT) return tRCD; - else if (command == Command::Read) + else if (command == Command::RD) return tRL + getReadAccessTime(); - else if (command == Command::ReadA) + else if (command == Command::RDA) return tRTP + tRP_old; - else if (command == Command::Write) + else if (command == Command::WR) return tWL + getWriteAccessTime(); - else if (command == Command::WriteA) + else if (command == Command::WRA) return tWL + getWriteAccessTime() + tWR + tRP_old; - else if (command == Command::PrechargeAll) + else if (command == Command::PREA) return tRP_old; - else if (command == Command::AutoRefresh) + else if (command == Command::REFA) return getElementFromMap(refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC; - else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) + else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) return clk; else { @@ -110,30 +110,30 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay sc_time MemSpecDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const { - if (command == Command::PreB) + if (command == Command::PREB) return Configuration::getInstance().getTrpb(); - else if (command == Command::Precharge || command == Command::PrechargeAll) + else if (command == Command::PRE || command == Command::PREA) return tRP_old; - else if (command == Command::ActB) + else if (command == Command::ACTB) return tRCD; - else if (command == Command::Activate) + else if (command == Command::ACT) return tRCD; - else if (command == Command::Read) + else if (command == Command::RD) return tRL + getReadAccessTime(); - else if (command == Command::ReadA) + else if (command == Command::RDA) return tRTP + tRP_old; - else if (command == Command::Write) + else if (command == Command::WR) return tWL + getWriteAccessTime(); - else if (command == Command::WriteA) + else if (command == Command::WRA) return tWL + getWriteAccessTime() + tWR + tRP_old; - else if (command == Command::PrechargeAll) + else if (command == Command::PREA) return tRP_old; - else if (command == Command::AutoRefresh) + else if (command == Command::REFA) { return getElementFromMap(refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC; } - else if (command == Command::PDNAX || command == Command::PDNPX || command == Command::SREFX) + else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) return clk; else { diff --git a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h index 9ff8bd39..01aac5ba 100644 --- a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h +++ b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h @@ -70,13 +70,13 @@ inline Command IPowerDownManager::getSleepCommand(PowerDownState state) Command cmd(Command::NOP); switch (state) { case PowerDownState::PDNActive: - cmd = Command::PDNA; + cmd = Command::PDEA; break; case PowerDownState::PDNPrecharge: - cmd = Command::PDNP; + cmd = Command::PDEP; break; case PowerDownState::PDNSelfRefresh: - cmd = Command::SREF; + cmd = Command::SREFEN; break; default: SC_REPORT_FATAL("In PowerDownManager sendPowerdownBegin", @@ -92,13 +92,13 @@ inline Command IPowerDownManager::getWakeUpCommand(PowerDownState state) Command cmd(Command::NOP); switch (state) { case PowerDownState::PDNActive: - cmd = Command::PDNAX; + cmd = Command::PDXA; break; case PowerDownState::PDNPrecharge: - cmd = Command::PDNPX; + cmd = Command::PDXP; break; case PowerDownState::PDNSelfRefresh: - cmd = Command::SREFX; + cmd = Command::SREFEX; break; default: SC_REPORT_FATAL("In PowerDownManager sendPowerdownEnd", diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp index edc72584..98377611 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp @@ -78,8 +78,8 @@ void PowerDownManager::sleep(Bank /*bank*/, sc_time time) PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down sc_assert(controllerCore.state->rowBufferStates->allRowBuffersAreClosed()); - if (controllerCore.state->getLastCommand(Command::PDNA).getStart() - >= controllerCore.state->getLastCommand(Command::PDNP).getStart()) + if (controllerCore.state->getLastCommand(Command::PDEA).getStart() + >= controllerCore.state->getLastCommand(Command::PDEP).getStart()) state = PowerDownState::PDNPrecharge; else { state = PowerDownState::PDNSelfRefresh; @@ -116,7 +116,7 @@ void PowerDownManager::wakeUp(Bank bank, sc_time time) DramExtension::getExtension(powerDownPayloads[Bank(0)])); controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - if (cmd == Command::SREFX) { + if (cmd == Command::SREFEX) { // Leaving Self Refresh. Plan the next refresh. controllerCore.refreshManager->reInitialize(bank, pdn.getEnd()); printDebugMessage("Waking up. Leaving Self Refresh at " + time.to_string() + diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp index c0175a61..8ba7c0d2 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp @@ -67,8 +67,8 @@ void PowerDownManagerBankwise::sleep(Bank bank, sc_time time) PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down sc_assert(!controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)); - if (controllerCore.state->getLastCommand(Command::PDNA, bank).getStart() - >= controllerCore.state->getLastCommand(Command::PDNP, bank).getStart()) + if (controllerCore.state->getLastCommand(Command::PDEA, bank).getStart() + >= controllerCore.state->getLastCommand(Command::PDEP, bank).getStart()) state = PowerDownState::PDNPrecharge; else { state = PowerDownState::PDNSelfRefresh; @@ -109,7 +109,7 @@ void PowerDownManagerBankwise::wakeUp(Bank bank, sc_time time) // Ensure that time constraints are respected controllerCore.getCommandChecker(pdnExitCmd).delayToSatisfyConstraints(pdnExit); - if (pdnExitCmd == Command::SREFX) { + if (pdnExitCmd == Command::SREFEX) { // Leaving Self Refresh. Plan the next refresh. controllerCore.refreshManager->reInitialize(bank, pdnExit.getEnd()); printDebugMessage("Waking up. Leaving Self Refresh on Bank " + to_string( diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp index 08ce7c0a..02c6250e 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp @@ -64,14 +64,14 @@ void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) sc_time lastWriteScheduled; if (Configuration::getInstance().OpenPagePolicy) { lastReadScheduled = controllerCore.state->getLastCommand( - Command::Read).getEnd(); + Command::RD).getEnd(); lastWriteScheduled = controllerCore.state->getLastCommand( - Command::Write).getEnd(); + Command::WR).getEnd(); } else { lastReadScheduled = controllerCore.state->getLastCommand( - Command::ReadA).getEnd(); + Command::RDA).getEnd(); lastWriteScheduled = controllerCore.state->getLastCommand( - Command::WriteA).getEnd(); + Command::WRA).getEnd(); } sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); timeoutTest = (time - lastScheduledCommand) >= @@ -90,19 +90,19 @@ void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) PowerDownState::PDNPrecharge : PowerDownState::PDNActive; } else { // PowerDownMode == TimeoutSREF if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { - ScheduledCommand prechargeAllMaster(Command::PrechargeAll, time, + ScheduledCommand prechargeAllMaster(Command::PREA, time, Configuration::getInstance().memSpec->getExecutionTime( - Command::PrechargeAll, powerDownPayloads[Bank(0)]), + Command::PREA, powerDownPayloads[Bank(0)]), DramExtension::getExtension(powerDownPayloads[Bank(0)])); controllerCore.getCommandChecker( - Command::PrechargeAll).delayToSatisfyConstraints(prechargeAllMaster); + Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); if (controllerCore.refreshManager->hasCollision(prechargeAllMaster)) { return; } else { for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { - ScheduledCommand prechargeAll(Command::PrechargeAll, + ScheduledCommand prechargeAll(Command::PREA, prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), powerDownPayloads[Bank(i)]); controllerCore.state->change(prechargeAll); diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp index 60142555..3f361355 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp @@ -66,14 +66,14 @@ void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) sc_time lastReadScheduled; sc_time lastWriteScheduled; if (Configuration::getInstance().OpenPagePolicy) { - lastReadScheduled = controllerCore.state->getLastCommand(Command::Read, + lastReadScheduled = controllerCore.state->getLastCommand(Command::RD, bank).getEnd(); - lastWriteScheduled = controllerCore.state->getLastCommand(Command::Write, + lastWriteScheduled = controllerCore.state->getLastCommand(Command::WR, bank).getEnd(); } else { - lastReadScheduled = controllerCore.state->getLastCommand(Command::ReadA, + lastReadScheduled = controllerCore.state->getLastCommand(Command::RDA, bank).getEnd(); - lastWriteScheduled = controllerCore.state->getLastCommand(Command::WriteA, + lastWriteScheduled = controllerCore.state->getLastCommand(Command::WRA, bank).getEnd(); } sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); @@ -90,11 +90,11 @@ void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; } else { // PowerDownMode == TimeoutSREF if (controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)) { - ScheduledCommand precharge(Command::Precharge, time, - Configuration::getInstance().memSpec->getExecutionTime(Command::Precharge, powerDownPayloads[bank]), + ScheduledCommand precharge(Command::PRE, time, + Configuration::getInstance().memSpec->getExecutionTime(Command::PRE, powerDownPayloads[bank]), DramExtension::getExtension(powerDownPayloads[bank])); - controllerCore.getCommandChecker(Command::Precharge).delayToSatisfyConstraints( + controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( precharge); if (controllerCore.refreshManager->hasCollision(precharge)) { diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index f5cea5d0..411cff75 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -127,13 +127,13 @@ sc_time RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t) trfcx += trp; if (bwl) { if (ccore.config.getRGRBank(b.ID())) { - ccore.scheduleRequest(Command::PreB, rps[b]); + ccore.scheduleRequest(Command::PREB, rps[b]); } } else { for (Bank b : ccore.getBanks()) { auto rgrb = ccore.config.getRGRBank(b.ID()); if (ccore.state->rowBufferStates->rowBufferIsOpen(b) && rgrb) { - ccore.scheduleRequest(Command::PreB, rps[Bank(b)]); + ccore.scheduleRequest(Command::PREB, rps[Bank(b)]); } } } @@ -143,15 +143,15 @@ sc_time RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t) trfcx += trcd + trp; if (bwl) { if (ccore.config.getRGRBank(b.ID())) { - ccore.scheduleRequest(Command::ActB, rps[b]); - ccore.scheduleRequest(Command::PreB, rps[b]); + ccore.scheduleRequest(Command::ACTB, rps[b]); + ccore.scheduleRequest(Command::PREB, rps[b]); } DramExtension::getExtension(p).incrementRow(); } else { for (Bank b : ccore.getBanks()) { if (ccore.config.getRGRBank(b.ID())) { - ccore.scheduleRequest(Command::ActB, rps[b]); - ccore.scheduleRequest(Command::PreB, rps[b]); + ccore.scheduleRequest(Command::ACTB, rps[b]); + ccore.scheduleRequest(Command::PREB, rps[b]); } DramExtension::getExtension(rps[b]).incrementRow(); } diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index 0a309fce..d71634bc 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -75,7 +75,7 @@ RefreshManager::~RefreshManager() bool RefreshManager::hasCollision(const ScheduledCommand &command) { bool collisionWithPreviousRefEnd = command.getStart() < - controllerCore.state->getLastCommand(Command::AutoRefresh).getEnd(); + controllerCore.state->getLastCommand(Command::REFA).getEnd(); bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh; if (controllerCore.config.ControllerCoreRefEnablePostpone && (postponed < maxpostpone)) { @@ -98,15 +98,15 @@ bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) // If any row is open, precharge all. if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { pre = true; - ScheduledCommand prechargeAllMaster(Command::PrechargeAll, time, + ScheduledCommand prechargeAllMaster(Command::PREA, time, Configuration::getInstance().memSpec->getExecutionTime( - Command::PrechargeAll, refreshPayloads[Bank(0)]), + Command::PREA, refreshPayloads[Bank(0)]), refreshPayloads[Bank(0)]); controllerCore.getCommandChecker( - Command::PrechargeAll).delayToSatisfyConstraints(prechargeAllMaster); + Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { - ScheduledCommand prechargeAll(Command::PrechargeAll, + ScheduledCommand prechargeAll(Command::PREA, prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), refreshPayloads[Bank(i)]); controllerCore.state->change(prechargeAll); @@ -116,15 +116,15 @@ bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) } //Otherwise just the AutoRefresh command is scheduled. - ScheduledCommand refreshAllMaster(Command::AutoRefresh, time, + ScheduledCommand refreshAllMaster(Command::REFA, time, Configuration::getInstance().memSpec->getExecutionTime( - Command::AutoRefresh, refreshPayloads[Bank(0)]), + Command::REFA, refreshPayloads[Bank(0)]), DramExtension::getExtension(refreshPayloads[Bank(0)])); controllerCore.getCommandChecker( - Command::AutoRefresh).delayToSatisfyConstraints(refreshAllMaster); + Command::REFA).delayToSatisfyConstraints(refreshAllMaster); for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { - ScheduledCommand refresh(Command::AutoRefresh, refreshAllMaster.getStart(), + ScheduledCommand refresh(Command::REFA, refreshAllMaster.getStart(), refreshAllMaster.getExecutionTime(), refreshPayloads[Bank(i)]); controllerCore.state->change(refresh); DramExtension::getExtension(refreshPayloads[Bank(i)]).incrementRow(); diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index 8c2b907d..1a44d304 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -73,7 +73,7 @@ bool RefreshManagerBankwise::hasCollision(const ScheduledCommand &command) { Bank bank = command.getBank(); bool collisionWithPreviousRefEnd = command.getStart() < - controllerCore.state->getLastCommand(Command::AutoRefresh, bank).getEnd(); + controllerCore.state->getLastCommand(Command::REFA, bank).getEnd(); bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefreshs[bank]; if (controllerCore.config.ControllerCoreRefEnablePostpone && (postponed[bank] < maxpostpone)) { @@ -101,20 +101,20 @@ bool RefreshManagerBankwise::doRefresh(tlm::tlm_generic_payload &payload, if (controllerCore.state->rowBufferStates->rowBufferIsOpen( extension.getBank())) { pre = true; - ScheduledCommand precharge(Command::Precharge, time, + ScheduledCommand precharge(Command::PRE, time, Configuration::getInstance().memSpec->getExecutionTime( - Command::Precharge, refreshPayload), extension); - controllerCore.getCommandChecker(Command::Precharge).delayToSatisfyConstraints( + Command::PRE, refreshPayload), extension); + controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( precharge); controllerCore.state->change(precharge); controllerCore.controller.send(precharge, refreshPayload); } - ScheduledCommand refresh(Command::AutoRefresh, time, + ScheduledCommand refresh(Command::REFA, time, Configuration::getInstance().memSpec->getExecutionTime( - Command::AutoRefresh, refreshPayload), extension); + Command::REFA, refreshPayload), extension); controllerCore.getCommandChecker( - Command::AutoRefresh).delayToSatisfyConstraints(refresh); + Command::REFA).delayToSatisfyConstraints(refresh); controllerCore.state->change(refresh); extension.incrementRow(); controllerCore.controller.send(refresh, refreshPayload); diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index 43c4dd31..6933c521 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -124,13 +124,13 @@ bool ScheduledCommand::commandIsIn(const std::vector &commandSet) const TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const { //only read and write commands have an assoicated time on the data strobe - sc_assert(getCommand() == Command::Read || getCommand() == Command::ReadA - || getCommand() == Command::Write - || getCommand() == Command::WriteA); + sc_assert(getCommand() == Command::RD || getCommand() == Command::RDA + || getCommand() == Command::WR + || getCommand() == Command::WRA); MemSpec *timings = Configuration::getInstance().memSpec; - if (getCommand() == Command::Read || getCommand() == Command::ReadA) { + if (getCommand() == Command::RD || getCommand() == Command::RDA) { return TimeInterval(getStart() + timings->tRL, getStart() + timings->tRL + timings->getReadAccessTime()); } else { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index d16b788d..68bff558 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -45,28 +45,28 @@ using namespace std; void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const { - sc_assert(cmd.getCommand() == Command::ActB); + sc_assert(cmd.getCommand() == Command::ACTB); ScheduledCommand lcb = state.getLastScheduledCommand(cmd.getBank()); if (lcb.isValidCommand()) { - if (lcb.getCommand() == Command::PreB) { + if (lcb.getCommand() == Command::PREB) { cmd.establishMinDistanceFromStart(lcb.getStart(), Configuration::getInstance().getTrpb()); - } else if (lcb.getCommand() == Command::Precharge - || lcb.getCommand() == Command::PrechargeAll) { + } else if (lcb.getCommand() == Command::PRE + || lcb.getCommand() == Command::PREA) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRP_old); - } else if (lcb.getCommand() == Command::ReadA) { + } else if (lcb.getCommand() == Command::RDA) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lcb.getCommand() == Command::WriteA) { + } else if (lcb.getCommand() == Command::WRA) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lcb.getCommand() == Command::AutoRefresh) { + } else if (lcb.getCommand() == Command::REFA) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC_old); - } else if (lcb.getCommand() == Command::PDNPX - || lcb.getCommand() == Command::PDNAX) { + } else if (lcb.getCommand() == Command::PDXP + || lcb.getCommand() == Command::PDXA) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP); - } else if (lcb.getCommand() == Command::SREFX) { + } else if (lcb.getCommand() == Command::SREFEX) { cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS); } else { reportFatal("ActB Checker", @@ -74,7 +74,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const } } ScheduledCommand lc; - if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) { + if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } delay_to_satisfy_activateToActivate_sameBank(cmd); @@ -88,12 +88,12 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const void ActBChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand &cmd) const { - ScheduledCommand lastActOnBank = state.getLastCommand(Command::Activate, + ScheduledCommand lastActOnBank = state.getLastCommand(Command::ACT, cmd.getBank()); if (lastActOnBank.isValidCommand()) { cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec->tRC); } - ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ActB, + ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ACTB, cmd.getBank()); if (lastActBOnBank.isValidCommand()) { cmd.establishMinDistanceFromStart(lastActBOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 576cc276..34eebb18 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -47,31 +47,31 @@ using namespace std; void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { - sc_assert(command.getCommand() == Command::Activate); + sc_assert(command.getCommand() == Command::ACT); ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand( command.getBank()); if (lastCommandOnBank.isValidCommand()) { - if (lastCommandOnBank.getCommand() == Command::PreB - || lastCommandOnBank.getCommand() == Command::Precharge - || lastCommandOnBank.getCommand() == Command::PrechargeAll) { + if (lastCommandOnBank.getCommand() == Command::PREB + || lastCommandOnBank.getCommand() == Command::PRE + || lastCommandOnBank.getCommand() == Command::PREA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::ReadA) { + } else if (lastCommandOnBank.getCommand() == Command::RDA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::WriteA) { + } else if (lastCommandOnBank.getCommand() == Command::WRA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { + } else if (lastCommandOnBank.getCommand() == Command::REFA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tRFC_old); - } else if (lastCommandOnBank.getCommand() == Command::PDNPX - || lastCommandOnBank.getCommand() == Command::PDNAX) { + } else if (lastCommandOnBank.getCommand() == Command::PDXP + || lastCommandOnBank.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tXP); - } else if (lastCommandOnBank.getCommand() == Command::SREFX) { + } else if (lastCommandOnBank.getCommand() == Command::SREFEX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tXS); } else @@ -92,14 +92,14 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand &command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::Activate, + ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); if (lastActivateOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), config.memSpec->tRC); } - ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ActB, + ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ACTB, command.getBank()); if (lastActBOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 0dad72b0..f1081579 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -19,36 +19,36 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const Command LastCmd = lastCommandOnBank.getCommand(); Command NextCmd = command.getCommand(); - if (NextCmd == Command::Activate) + if (NextCmd == Command::ACT) { if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) { - case Command::Precharge: - case Command::PrechargeAll: + case Command::PRE: + case Command::PREA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRP_old); break; - case Command::ReadA: + case Command::RDA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRTP + memSpec->tRP_old); break; - case Command::WriteA: + case Command::WRA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP_old); break; - case Command::PDNPX: - case Command::PDNAX: + case Command::PDXP: + case Command::PDXA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXP); break; - case Command::SREFX: + case Command::SREFEX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXS); break; - case Command::AutoRefresh: + case Command::REFA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRFC_old); break; @@ -66,27 +66,27 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const command.delayStart(memSpec->clk); } } - else if (NextCmd == Command::Read || NextCmd == Command::ReadA) + else if (NextCmd == Command::RD || NextCmd == Command::RDA) { delayToSatisfyDLL(command); if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) { - case Command::Activate: + case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRCD); break; - case Command::Read: + case Command::RD: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), CasToCas(lastCommandOnBank, command)); break; - case Command::Write: + case Command::WR: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), writeToRead(lastCommandOnBank, command)); break; - case Command::PDNPX: - case Command::PDNAX: + case Command::PDXP: + case Command::PDXA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXP); break; @@ -98,26 +98,26 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) command.delayStart(memSpec->clk); } - else if (NextCmd == Command::Write || NextCmd == Command::WriteA) + else if (NextCmd == Command::WR || NextCmd == Command::WRA) { if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) { - case Command::Activate: + case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRCD); break; - case Command::Read: + case Command::RD: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), readToWrite(lastCommandOnBank, command)); break; - case Command::Write: + case Command::WR: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), CasToCas(lastCommandOnBank, command)); break; - case Command::PDNPX: - case Command::PDNAX: + case Command::PDXP: + case Command::PDXA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXP); break; @@ -128,30 +128,30 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) command.delayStart(memSpec->clk); } - else if (NextCmd == Command::Precharge) + else if (NextCmd == Command::PRE) { if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) { - case Command::Precharge: + case Command::PRE: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRP_old); break; - case Command::Activate: + case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRCD); break; - case Command::Read: + case Command::RD: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRTP); break; - case Command::Write: + case Command::WR: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->tWR + memSpec->getWriteAccessTime()); break; - case Command::PDNAX: + case Command::PDXA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXP); break; @@ -160,13 +160,13 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const "Precharge can not follow " + commandToString(LastCmd)); } } - ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) command.establishMinDistanceFromStart(lastActivate.getStart(), memSpec->tRAS); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PrechargeAll) + else if (NextCmd == Command::PREA) { for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) { @@ -175,42 +175,42 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const { switch (lastCommand.getCommand()) { - case Command::Precharge: + case Command::PRE: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP_old); break; - case Command::Activate: + case Command::ACT: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); break; - case Command::Read: + case Command::RD: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); break; - case Command::Write: + case Command::WR: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR); break; - case Command::WriteA: + case Command::WRA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP_old); break; - case Command::ReadA: + case Command::RDA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP_old); break; - case Command::PDNAX: - case Command::PDNPX: + case Command::PDXA: + case Command::PDXP: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); break; - case Command::SREFX: + case Command::SREFEX: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); break; - case Command::AutoRefresh: + case Command::REFA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC_old); break; @@ -220,49 +220,49 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const } } } - ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, command.getBank()); + ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) command.establishMinDistanceFromStart(lastActivate.getStart(), memSpec->tRAS); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDNA || NextCmd == Command::PDNP || NextCmd == Command::SREF ) + else if (NextCmd == Command::PDEA || NextCmd == Command::PDEP || NextCmd == Command::SREFEN ) { if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) { - case Command::Precharge: - case Command::PrechargeAll: + case Command::PRE: + case Command::PREA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRP_old); break; - case Command::Read: - case Command::ReadA: + case Command::RD: + case Command::RDA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRL + memSpec->getReadAccessTime() + memSpec->clk); break; - case Command::Write: + case Command::WR: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR); break; - case Command::WriteA: + case Command::WRA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->clk); break; - case Command::AutoRefresh: + case Command::REFA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRFC_old); break; - case Command::PDNAX: - case Command::PDNPX: + case Command::PDXA: + case Command::PDXP: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXP); break; - case Command::SREFX: + case Command::SREFEX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXS); break; @@ -273,58 +273,58 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const } state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDNAX) + else if (NextCmd == Command::PDXA) { // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNA, + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, command.getBank()).getStart(), memSpec->tCKE); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDNPX) + else if (NextCmd == Command::PDXP) { // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNP, + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, command.getBank()).getStart(), memSpec->tCKE); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::SREFX) + else if (NextCmd == Command::SREFEX) { // Leaving Self Refresh - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREF, + command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, command.getBank()).getStart(), memSpec->tCKESR); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::AutoRefresh) + else if (NextCmd == Command::REFA) { if (config.BankwiseLogic) { if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) { - case Command::Precharge: - case Command::PrechargeAll: + case Command::PRE: + case Command::PREA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRP_old); break; - case Command::ReadA: + case Command::RDA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRTP + memSpec->tRP_old); break; - case Command::WriteA: + case Command::WRA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP_old); break; - case Command::AutoRefresh: + case Command::REFA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tRFC_old); break; - case Command::PDNPX: - case Command::PDNAX: + case Command::PDXP: + case Command::PDXA: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXP); break; - case Command::SREFX: + case Command::SREFEX: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), memSpec->tXS); break; @@ -344,34 +344,34 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const { switch (lastCommand.getCommand()) { - case Command::Precharge: - case Command::PrechargeAll: + case Command::PRE: + case Command::PREA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP_old); break; - case Command::Activate: + case Command::ACT: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); break; - case Command::ReadA: + case Command::RDA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP_old); break; - case Command::WriteA: + case Command::WRA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWR + memSpec->tRP_old); break; - case Command::AutoRefresh: + case Command::REFA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC_old); break; - case Command::PDNPX: - case Command::PDNAX: + case Command::PDXP: + case Command::PDXA: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); break; - case Command::SREFX: + case Command::SREFEX: command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); break; @@ -392,7 +392,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::Activate, command.getBank()); + ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); if (lastActivateOnBank.isValidCommand()) command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); } @@ -454,12 +454,12 @@ bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, ScheduledCommand &strobeCommand) const { - if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA) + if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) { return getDistance(read.getStart(), strobeCommand.getStart()) < CasToCas(strobeCommand, read); } - else if (strobeCommand.getCommand() == Command::Write || strobeCommand.getCommand() == Command::WriteA) + else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) { if (strobeCommand.getStart() >= read.getStart()) return getDistance(read.getStart(), @@ -479,7 +479,7 @@ bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const { - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, read.getBank()); + ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); } @@ -487,8 +487,8 @@ void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const { - sc_assert(read.getCommand() == Command::Read || read.getCommand() == Command::ReadA); - sc_assert(write.getCommand() == Command::Write || write.getCommand() == Command::WriteA); + sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); + sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA); return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; } @@ -497,14 +497,14 @@ sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const { - if (firstCAS.getCommand() == Command::Read || firstCAS.getCommand() == Command::ReadA) + if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA) { - if (secondCAS.getCommand() == Command::Read || secondCAS.getCommand() == Command::ReadA) + if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA) return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); } - else if (firstCAS.getCommand() == Command::Write || firstCAS.getCommand() == Command::WriteA) + else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA) { - if (secondCAS.getCommand() == Command::Write || secondCAS.getCommand() == Command::WriteA) + if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA) return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); } SC_REPORT_FATAL("CasToCas", "Exception reached"); @@ -528,13 +528,13 @@ bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const bool CheckerDDR3::collidesWithStrobeCommand_WR(ScheduledCommand &write, ScheduledCommand &strobeCommand) const { - if (strobeCommand.getCommand() == Command::Write || strobeCommand.getCommand() == Command::WriteA) + if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) { // TODO: Cast from sc_time to bool? return getDistance(write.getStart(), strobeCommand.getStart()) < CasToCas(strobeCommand, write); } - else if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA) + else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) { if (strobeCommand.getStart() >= write.getStart()) return getDistance(write.getStart(), @@ -554,10 +554,10 @@ bool CheckerDDR3::collidesWithStrobeCommand_WR(ScheduledCommand &write, sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const { - sc_assert(read.getCommand() == Command::Read - || read.getCommand() == Command::ReadA); - sc_assert(write.getCommand() == Command::Write - || write.getCommand() == Command::WriteA); + sc_assert(read.getCommand() == Command::RD + || read.getCommand() == Command::RDA); + sc_assert(write.getCommand() == Command::WR + || write.getCommand() == Command::WRA); return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index fd0b2ef5..3da88984 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -41,25 +41,25 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const { - sc_assert(pdnCmd == Command::SREF || pdnCmd == Command::PDNA - || pdnCmd == Command::PDNP); + sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA + || pdnCmd == Command::PDEP); sc_time constraint; - if (lastCmd == Command::Read || lastCmd == Command::ReadA) { + if (lastCmd == Command::RD || lastCmd == Command::RDA) { constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; - } else if (lastCmd == Command::Write) { + } else if (lastCmd == Command::WR) { constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; - } else if (lastCmd == Command::WriteA) { + } else if (lastCmd == Command::WRA) { constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->clk; - } else if (lastCmd == Command::AutoRefresh) { + } else if (lastCmd == Command::REFA) { constraint = config.memSpec->tRFC_old; - } else if (lastCmd == Command::PDNPX || lastCmd == Command::PDNAX) { + } else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) { constraint = config.memSpec->tXP; - } else if (lastCmd == Command::SREFX) { + } else if (lastCmd == Command::SREFEX) { constraint = config.memSpec->tXS; - } else if (lastCmd == Command::Precharge || lastCmd == Command::PrechargeAll) { + } else if (lastCmd == Command::PRE || lastCmd == Command::PREA) { constraint = config.memSpec->tRP_old; } else { reportFatal("Powerdown checker", @@ -72,7 +72,7 @@ sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { - sc_assert(command.commandIsIn({Command::PDNA, Command::PDNP, Command::SREF, Command::PDNAX, Command::PDNPX, Command::SREFX})); + sc_assert(command.commandIsIn({Command::PDEA, Command::PDEP, Command::SREFEN, Command::PDXA, Command::PDXP, Command::SREFEX})); // Power Down commmand (one of the listed above) Command pdnCmd = command.getCommand(); @@ -80,8 +80,8 @@ const sc_time timeConstraint; - if (pdnCmd == Command::PDNA || pdnCmd == Command::PDNP - || pdnCmd == Command::SREF) { + if (pdnCmd == Command::PDEA || pdnCmd == Command::PDEP + || pdnCmd == Command::SREFEN) { // Entering in one of the Power Down modes: // PDNA - Active Power Down // PDNP - Precharge Power Down @@ -109,20 +109,20 @@ const command.establishMinDistanceFromStart(lastSchedCmdStart, timeConstraint); } - } else if (pdnCmd == Command::PDNAX) { + } else if (pdnCmd == Command::PDXA) { // Leaving Active Power Down timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNA, + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, bank).getStart(), timeConstraint); - } else if (pdnCmd == Command::PDNPX) { + } else if (pdnCmd == Command::PDXP) { // Leaving Precharge Power Down timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDNP, + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, bank).getStart(), timeConstraint); - } else if (pdnCmd == Command::SREFX) { + } else if (pdnCmd == Command::SREFEX) { // Leaving Self Refresh timeConstraint = config.memSpec->tCKESR; - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREF, + command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, bank).getStart(), timeConstraint); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 6bce7e60..2d879775 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -36,27 +36,27 @@ #include "../../timingCalculations.h" void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const { - sc_assert(cmd.getCommand() == Command::PreB); + sc_assert(cmd.getCommand() == Command::PREB); ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank()); if (lastCmd.isValidCommand()) { - if (lastCmd.getCommand() == Command::PreB) { + if (lastCmd.getCommand() == Command::PREB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), Configuration::getInstance().getTrpb()); - } else if (lastCmd.getCommand() == Command::Precharge) { + } else if (lastCmd.getCommand() == Command::PRE) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); - } else if (lastCmd.getCommand() == Command::PrechargeAll) { + } else if (lastCmd.getCommand() == Command::PREA) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); - } else if (lastCmd.getCommand() == Command::ActB) { + } else if (lastCmd.getCommand() == Command::ACTB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok! - } else if (lastCmd.getCommand() == Command::Activate) { + } else if (lastCmd.getCommand() == Command::ACT) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); - } else if (lastCmd.getCommand() == Command::Read) { + } else if (lastCmd.getCommand() == Command::RD) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRTP); - } else if (lastCmd.getCommand() == Command::Write) { + } else if (lastCmd.getCommand() == Command::WR) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); - } else if (lastCmd.getCommand() == Command::PDNAX) { + } else if (lastCmd.getCommand() == Command::PDXA) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP); } else { reportFatal("PreB Checker", @@ -64,14 +64,14 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const } } ScheduledCommand lc; - if ((lc = state.getLastCommand(Command::PrechargeAll)).isValidCommand()) { + if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } - if ((lc = state.getLastCommand(Command::Activate, + if ((lc = state.getLastCommand(Command::ACT, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); } - if ((lc = state.getLastCommand(Command::ActB, + if ((lc = state.getLastCommand(Command::ACTB, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), Configuration::getInstance().getTrasb()); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 5c302ef9..5c934c64 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -42,41 +42,41 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { - sc_assert(command.getCommand() == Command::PrechargeAll); + sc_assert(command.getCommand() == Command::PREA); // Consider all banks for the constraints, since precharge all command is supposed to happen at the same time on all banks for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::Precharge - || lastCommand.getCommand() == Command::PreB) { + if (lastCommand.getCommand() == Command::PRE + || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::Activate - || lastCommand.getCommand() == Command::ActB) { + } else if (lastCommand.getCommand() == Command::ACT + || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::Read) { + } else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP); - } else if (lastCommand.getCommand() == Command::ReadA) { + } else if (lastCommand.getCommand() == Command::RDA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::Write) { + } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); - } else if (lastCommand.getCommand() == Command::WriteA) { + } else if (lastCommand.getCommand() == Command::WRA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::AutoRefresh) { + } else if (lastCommand.getCommand() == Command::REFA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRFC_old); - } else if (lastCommand.getCommand() == Command::PDNAX - || lastCommand.getCommand() == Command::PDNPX) { + } else if (lastCommand.getCommand() == Command::PDXA + || lastCommand.getCommand() == Command::PDXP) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); - } else if (lastCommand.getCommand() == Command::SREFX) { + } else if (lastCommand.getCommand() == Command::SREFEX) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXS); } else @@ -85,7 +85,7 @@ const } } - ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, + ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index a18f738d..de3ff162 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -42,31 +42,31 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { //return; - sc_assert(command.getCommand() == Command::Precharge); + sc_assert(command.getCommand() == Command::PRE); ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); if (lastCommand.isValidCommand()) { // the first two cases happen when a resfresh interrups the command sequence of a transaction // (e.g. commands to process transaction are PRE-ACT-RD and refresh happens after the PRE or after the ACT) - if (lastCommand.getCommand() == Command::Precharge - || lastCommand.getCommand() == Command::PreB) { + if (lastCommand.getCommand() == Command::PRE + || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::Activate - || lastCommand.getCommand() == Command::ActB) { + } else if (lastCommand.getCommand() == Command::ACT + || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); } - else if (lastCommand.getCommand() == Command::Read) { + else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP); - } else if (lastCommand.getCommand() == Command::Write) { + } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); - } else if (lastCommand.getCommand() == Command::PDNAX) { + } else if (lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else @@ -74,7 +74,7 @@ const "Precharge can not follow " + commandToString(lastCommand.getCommand())); } - ScheduledCommand lastActivate = state.getLastCommand(Command::Activate, + ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 86d7c35a..9abd6981 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -43,24 +43,24 @@ using namespace std; void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { - sc_assert(command.getCommand() == Command::Read - || command.getCommand() == Command::ReadA); + sc_assert(command.getCommand() == Command::RD + || command.getCommand() == Command::RDA); delayToSatisfyDLL(command); ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::Activate - || lastCommand.getCommand() == Command::ActB) { + if (lastCommand.getCommand() == Command::ACT + || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::Read) { + } else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), ReadChecker::readToRead(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::Write) { + } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), ReadChecker::writeToRead(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::PDNPX - || lastCommand.getCommand() == Command::PDNAX) { + } else if (lastCommand.getCommand() == Command::PDXP + || lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else @@ -86,12 +86,12 @@ bool ReadChecker::collidesOnDataStrobe(ScheduledCommand &read) const bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand &read, ScheduledCommand &strobeCommand) const { - if (strobeCommand.getCommand() == Command::Read - || strobeCommand.getCommand() == Command::ReadA) { + if (strobeCommand.getCommand() == Command::RD + || strobeCommand.getCommand() == Command::RDA) { return getDistance(read.getStart(), strobeCommand.getStart()) < ReadChecker::readToRead(strobeCommand, read); - } else if (strobeCommand.getCommand() == Command::Write - || strobeCommand.getCommand() == Command::WriteA) { + } else if (strobeCommand.getCommand() == Command::WR + || strobeCommand.getCommand() == Command::WRA) { if (strobeCommand.getStart() >= read.getStart()) return getDistance(read.getStart(), strobeCommand.getStart()) < WriteChecker::readToWrite(read, strobeCommand); @@ -108,7 +108,7 @@ bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand &read, void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const { - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFX, + ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), @@ -118,10 +118,10 @@ void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, ScheduledCommand &secondRead) { - sc_assert(firstRead.getCommand() == Command::Read - || firstRead.getCommand() == Command::ReadA); - sc_assert(secondRead.getCommand() == Command::Read - || secondRead.getCommand() == Command::ReadA); + sc_assert(firstRead.getCommand() == Command::RD + || firstRead.getCommand() == Command::RDA); + sc_assert(secondRead.getCommand() == Command::RD + || secondRead.getCommand() == Command::RDA); MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? @@ -132,10 +132,10 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, sc_time ReadChecker::writeToRead(ScheduledCommand &write, ScheduledCommand &read) { - sc_assert(read.getCommand() == Command::Read - || read.getCommand() == Command::ReadA); - sc_assert(write.getCommand() == Command::Write - || write.getCommand() == Command::WriteA); + sc_assert(read.getCommand() == Command::RD + || read.getCommand() == Command::RDA); + sc_assert(write.getCommand() == Command::WR + || write.getCommand() == Command::WRA); MemSpec *config = Configuration::getInstance().memSpec; sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L_old : diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index feb18d13..fd618673 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -40,32 +40,32 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { - sc_assert(command.getCommand() == Command::AutoRefresh); + sc_assert(command.getCommand() == Command::REFA); if (config.BankwiseLogic) { ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand( command.getBank()); if (lastCommandOnBank.isValidCommand()) { - if (lastCommandOnBank.getCommand() == Command::Precharge - || lastCommandOnBank.getCommand() == Command::PrechargeAll) { + if (lastCommandOnBank.getCommand() == Command::PRE + || lastCommandOnBank.getCommand() == Command::PREA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::ReadA) { + } else if (lastCommandOnBank.getCommand() == Command::RDA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::WriteA) { + } else if (lastCommandOnBank.getCommand() == Command::WRA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::PDNPX - || lastCommandOnBank.getCommand() == Command::PDNAX) { + } else if (lastCommandOnBank.getCommand() == Command::PDXP + || lastCommandOnBank.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tXP); - } else if (lastCommandOnBank.getCommand() == Command::SREFX) { + } else if (lastCommandOnBank.getCommand() == Command::SREFEX) { command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), config.memSpec->tXS); - } else if (lastCommandOnBank.getCommand() == Command::AutoRefresh) { + } else if (lastCommandOnBank.getCommand() == Command::REFA) { } else reportFatal("Refresh Checker", "Refresh can not follow " + commandToString(lastCommandOnBank.getCommand())); @@ -74,30 +74,30 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::Precharge - || lastCommand.getCommand() == Command::PrechargeAll - || lastCommand.getCommand() == Command::PreB) { + if (lastCommand.getCommand() == Command::PRE + || lastCommand.getCommand() == Command::PREA + || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::Activate - || lastCommand.getCommand() == Command::ActB) { + } else if (lastCommand.getCommand() == Command::ACT + || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::ReadA) { + } else if (lastCommand.getCommand() == Command::RDA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::WriteA) { + } else if (lastCommand.getCommand() == Command::WRA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::PDNAX - || lastCommand.getCommand() == Command::PDNPX) { + } else if (lastCommand.getCommand() == Command::PDXA + || lastCommand.getCommand() == Command::PDXP) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); - } else if (lastCommand.getCommand() == Command::SREFX) { + } else if (lastCommand.getCommand() == Command::SREFEX) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXS); - } else if (lastCommand.getCommand() == Command::AutoRefresh) { + } else if (lastCommand.getCommand() == Command::REFA) { } else reportFatal("Refresh Checker", "Refresh can not follow " + commandToString(lastCommand.getCommand())); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index a62f2510..1d262b08 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -43,24 +43,24 @@ using namespace std; void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { - sc_assert(command.getCommand() == Command::Write - || command.getCommand() == Command::WriteA); + sc_assert(command.getCommand() == Command::WR + || command.getCommand() == Command::WRA); ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::Activate - || lastCommand.getCommand() == Command::ActB) { + if (lastCommand.getCommand() == Command::ACT + || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::Read) { + } else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), WriteChecker::readToWrite(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::Write) { + } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), WriteChecker::writeToWrite(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::PDNPX - || lastCommand.getCommand() == Command::PDNAX) { + } else if (lastCommand.getCommand() == Command::PDXP + || lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else @@ -86,12 +86,12 @@ bool WriteChecker::collidesOnDataStrobe(ScheduledCommand &write) const bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand &write, ScheduledCommand &strobeCommand) const { - if (strobeCommand.getCommand() == Command::Write - || strobeCommand.getCommand() == Command::WriteA) { + if (strobeCommand.getCommand() == Command::WR + || strobeCommand.getCommand() == Command::WRA) { return getDistance(write.getStart(), strobeCommand.getStart()) < WriteChecker::writeToWrite(strobeCommand, write); - } else if (strobeCommand.getCommand() == Command::Read - || strobeCommand.getCommand() == Command::ReadA) { + } else if (strobeCommand.getCommand() == Command::RD + || strobeCommand.getCommand() == Command::RDA) { if (strobeCommand.getStart() >= write.getStart()) return getDistance(write.getStart(), strobeCommand.getStart()) < ReadChecker::writeToRead(write, strobeCommand); @@ -109,10 +109,10 @@ bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand &write, sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, ScheduledCommand &secondWrite) { - sc_assert(firstWrite.getCommand() == Command::Write - || firstWrite.getCommand() == Command::WriteA); - sc_assert(secondWrite.getCommand() == Command::Write - || secondWrite.getCommand() == Command::WriteA); + sc_assert(firstWrite.getCommand() == Command::WR + || firstWrite.getCommand() == Command::WRA); + sc_assert(secondWrite.getCommand() == Command::WR + || secondWrite.getCommand() == Command::WRA); MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? @@ -123,10 +123,10 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, sc_time WriteChecker::readToWrite(ScheduledCommand &read __attribute__(( unused)), ScheduledCommand &write __attribute__((unused))) { - sc_assert(read.getCommand() == Command::Read - || read.getCommand() == Command::ReadA); - sc_assert(write.getCommand() == Command::Write - || write.getCommand() == Command::WriteA); + sc_assert(read.getCommand() == Command::RD + || read.getCommand() == Command::RDA); + sc_assert(write.getCommand() == Command::WR + || write.getCommand() == Command::WRA); MemSpec *config = Configuration::getInstance().memSpec; return config->tRL + config->getReadAccessTime() - config->tWL + config->clk * 2; diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.cpp b/DRAMSys/library/src/controller/scheduler/Fifo.cpp index cc2ddb11..b3cc5689 100644 --- a/DRAMSys/library/src/controller/scheduler/Fifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/Fifo.cpp @@ -48,8 +48,8 @@ std::pair Fifo::getNextRequest(Bank bank) { gp *payload = buffer[bank].front(); Command command = IScheduler::getNextCommand(payload); - if (command == Command::Read || command == Command::ReadA - || command == Command::Write || command == Command::WriteA) + if (command == Command::RD || command == Command::RDA + || command == Command::WR || command == Command::WRA) { buffer[bank].pop_front(); } diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp index 4b890433..caebc826 100644 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp +++ b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp @@ -77,7 +77,7 @@ std::pair FifoStrict::getNextRequest( // Command command = IScheduler::getNextCommand(payload); - if (commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { + if (commandIsIn(command, {Command::RD, Command::WR, Command::RDA, Command::WRA})) { buffer.pop_front(); // Check if the next transaction is a blocked read or write @@ -85,7 +85,7 @@ std::pair FifoStrict::getNextRequest( if (!buffer.empty()) { tlm::tlm_generic_payload *p = buffer.front().second; Command cmd = IScheduler::getNextCommand(p); - if (commandIsIn(cmd, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { + if (commandIsIn(cmd, {Command::RD, Command::WR, Command::RDA, Command::WRA})) { Bank b = DramExtension::getBank(p); controller.blockedRequests.push(b); } @@ -111,7 +111,7 @@ std::pair FifoStrict::getNextRequest( // scheduler executes all read and writes in a strict // order. Command command = getNextCommand(payload); - if (commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { + if (commandIsIn(command, {Command::RD, Command::WR, Command::RDA, Command::WRA})) { // Reads and writes must be executed in order. Then if // the next command for this request is read or write // NOP will be returned and no operation will be diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp index 2a9b6eff..7e1aa462 100644 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp +++ b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp @@ -52,13 +52,13 @@ Command IScheduler::getNextCommand(gp &payload) Bank bank = DramExtension::getBank(payload); if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) { - return Command::Activate; + return Command::ACT; } else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && controllerCore.getRowBufferStates().getRowInRowBuffer(bank) != DramExtension::getRow(payload)) { - return Command::Precharge; + return Command::PRE; } else { @@ -76,16 +76,16 @@ Command IScheduler::getReadWriteCommand(gp &payload) if (payload.get_command() == tlm::TLM_READ_COMMAND) { if (Configuration::getInstance().OpenPagePolicy) - return Command::Read; + return Command::RD; else - return Command::ReadA; + return Command::RDA; } else { if (Configuration::getInstance().OpenPagePolicy) - return Command::Write; + return Command::WR; else - return Command::WriteA; + return Command::WRA; } } diff --git a/DRAMSys/library/src/controller/scheduler/SMS.cpp b/DRAMSys/library/src/controller/scheduler/SMS.cpp index f01267d7..80fe5c43 100644 --- a/DRAMSys/library/src/controller/scheduler/SMS.cpp +++ b/DRAMSys/library/src/controller/scheduler/SMS.cpp @@ -31,9 +31,9 @@ std::pair SMS::getNextRequest(Bank bank) } else { gp *payload = bankBuffers[bank].front(); Command command = IScheduler::getNextCommand(payload); - if (command == Command::Read || command == Command::ReadA - || command == Command::Write - || command == Command::WriteA) { + if (command == Command::RD || command == Command::RDA + || command == Command::WR + || command == Command::WRA) { inFlightMemRequestCounter[DramExtension::getExtension(payload).getThread()]--; bankBuffers[bank].pop_front(); } diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 7228216e..2d0eb8d2 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -199,31 +199,31 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PREB) { DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PreB, + sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB, payload)); } else if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::Precharge, + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); } else if (phase == BEGIN_PRE_ALL) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, - delay + memSpec->getExecutionTime(Command::PrechargeAll, payload)); + delay + memSpec->getExecutionTime(Command::PREA, payload)); } else if (phase == BEGIN_ACTB) { DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ActB, + sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB, payload)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::Activate, + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); } else if (phase == BEGIN_WR) @@ -235,7 +235,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::Write, + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); } else if (phase == BEGIN_RD) @@ -247,7 +247,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::Read, + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); } else if (phase == BEGIN_WRA) @@ -259,7 +259,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WriteA, + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } else if (phase == BEGIN_RDA) @@ -271,20 +271,20 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::ReadA, + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } else if (phase == BEGIN_REFB) { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index ccf101b1..0ed6f553 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -72,11 +72,11 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += memSpec->getExecutionTime(Command::PDNAX, payload); + recTime += memSpec->getExecutionTime(Command::PDXA, payload); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += memSpec->getExecutionTime(Command::PDNPX, payload); + recTime += memSpec->getExecutionTime(Command::PDXP, payload); else if (phase == END_SREF || phase == END_SREFB) - recTime += memSpec->getExecutionTime(Command::SREFX, payload); + recTime += memSpec->getExecutionTime(Command::SREFEX, payload); unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 459396e9..4d5cc597 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -91,25 +91,25 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PREB) { DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PreB, + sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB, payload)); } else if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::Precharge, + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); } else if (phase == BEGIN_PRE_ALL) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, - delay + memSpec->getExecutionTime(Command::PrechargeAll, payload)); + delay + memSpec->getExecutionTime(Command::PREA, payload)); } else if (phase == BEGIN_ACTB) { DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ActB, + sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -118,7 +118,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::Activate, + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); @@ -138,7 +138,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::Write, + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); } else if (phase == BEGIN_RD) @@ -154,7 +154,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::Read, + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); } else if (phase == BEGIN_WRA) @@ -170,7 +170,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WriteA, + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } else if (phase == BEGIN_RDA) @@ -186,14 +186,14 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::ReadA, + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -203,7 +203,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::AutoRefresh, payload)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) From cb393b8abf33c301dddd7088f413c14ac6a99aad Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 5 Jul 2019 16:17:52 +0200 Subject: [PATCH 019/183] Renaming of commands, TODOs in timing checkers. --- DRAMSys/library/src/controller/Command.cpp | 16 ++--- .../core/scheduling/checker/ActBChecker.cpp | 2 +- .../scheduling/checker/ActivateChecker.cpp | 2 +- .../scheduling/checker/PowerDownChecker.cpp | 67 ++++++++++--------- .../core/scheduling/checker/PreBChecker.cpp | 6 +- .../checker/PrechargeAllChecker.cpp | 8 ++- .../scheduling/checker/PrechargeChecker.cpp | 5 +- .../core/scheduling/checker/ReadChecker.cpp | 7 +- .../scheduling/checker/RefreshChecker.cpp | 2 +- .../core/scheduling/checker/WriteChecker.cpp | 7 +- 10 files changed, 69 insertions(+), 53 deletions(-) diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index ed6310ab..fc2474ce 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -67,29 +67,29 @@ std::string commandToString(Command command) return "ACT"; break; case Command::PREA: - return "PRE_ALL"; + return "PREA"; break; case Command::REFA: - return "REF"; + return "REFA"; break; case Command::PDEA: - return "PDNA"; + return "PDEA"; break; case Command::PDXA: - return "PDNAX"; + return "PDXA"; break; case Command::PDEP: - return "PDNP"; + return "PDEP"; break; case Command::PDXP: - return "PDNPX"; + return "PDXP"; break; case Command::SREFEN: - return "SREF"; + return "SREFEN"; break; case Command::SREFEX: - return "SREFX"; + return "SREFEX"; break; case Command::NOP: diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 68bff558..31c33d15 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -70,7 +70,7 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS); } else { reportFatal("ActB Checker", - "ActB can not follow " + commandToString(lcb.getCommand())); + "ACTB can not follow " + commandToString(lcb.getCommand())); } } ScheduledCommand lc; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 34eebb18..db6e0b86 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -76,7 +76,7 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const config.memSpec->tXS); } else reportFatal("Activate Checker", - "Activate can not follow " + commandToString(lastCommandOnBank.getCommand())); + "ACT can not follow " + commandToString(lastCommandOnBank.getCommand())); } delay_to_satisfy_activateToActivate_sameBank(command); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 3da88984..48c35d9e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -38,37 +38,6 @@ #include "PowerDownChecker.h" #include "../../timingCalculations.h" -sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, - Command pdnCmd) const -{ - sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA - || pdnCmd == Command::PDEP); - - sc_time constraint; - - if (lastCmd == Command::RD || lastCmd == Command::RDA) { - constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; - } else if (lastCmd == Command::WR) { - constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; - } else if (lastCmd == Command::WRA) { - constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->clk; - } else if (lastCmd == Command::REFA) { - constraint = config.memSpec->tRFC_old; - } else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) { - constraint = config.memSpec->tXP; - } else if (lastCmd == Command::SREFEX) { - constraint = config.memSpec->tXS; - } else if (lastCmd == Command::PRE || lastCmd == Command::PREA) { - constraint = config.memSpec->tRP_old; - } else { - reportFatal("Powerdown checker", - commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); - } - - return constraint; -} - void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand &command) const { @@ -97,7 +66,7 @@ const { lastSchedCmd = state.getLastScheduledCommand(); } - + // TODO: Why do we only need to check the last scheduled command? bank_0_RDA -> bank_1_PRE -> SREFEN violates timing if (lastSchedCmd.isValidCommand()) { // Get the start time for the last scheduled command sc_time lastSchedCmdStart = lastSchedCmd.getStart(); @@ -129,3 +98,37 @@ const state.bus.moveCommandToNextFreeSlot(command); } +sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, + Command pdnCmd) const +{ + sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA + || pdnCmd == Command::PDEP); + + sc_time constraint; + + if (lastCmd == Command::RD || lastCmd == Command::RDA) { + constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; + } else if (lastCmd == Command::WR) { + constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; + } else if (lastCmd == Command::WRA) { + constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + + config.memSpec->clk; + // TODO: for SREFEN the constraint is tRFC, for PDEP it is tREFPDEN, PDEA cannot be the next command after REFA (all banks closed) + } else if (lastCmd == Command::REFA) { + constraint = config.memSpec->tRFC_old; + // TODO: for PDEA/PDEP the constraint is tCLK, for SREFEN it is tXP + } else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) { + constraint = config.memSpec->tXP; + } else if (lastCmd == Command::SREFEX) { + constraint = config.memSpec->tXS; + // TODO: for PDEA/PDEP the constraint is tPRPDEN, for SREFEN the constraint is tRP + } else if (lastCmd == Command::PRE || lastCmd == Command::PREA) { + constraint = config.memSpec->tRP_old; + // TODO: ACT -> PDEA missing (tACTPDEN) + } else { + reportFatal("Powerdown checker", + commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); + } + + return constraint; +} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 2d879775..907dcb73 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -39,6 +39,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const sc_assert(cmd.getCommand() == Command::PREB); ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank()); if (lastCmd.isValidCommand()) { + // TODO: unused? if (lastCmd.getCommand() == Command::PREB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), Configuration::getInstance().getTrpb()); @@ -46,6 +47,7 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); } else if (lastCmd.getCommand() == Command::PREA) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); + // ------------ } else if (lastCmd.getCommand() == Command::ACTB) { cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok! @@ -60,13 +62,15 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP); } else { reportFatal("PreB Checker", - "PreB can not follow " + commandToString(lastCmd.getCommand())); + "PREB can not follow " + commandToString(lastCmd.getCommand())); } } ScheduledCommand lc; + // TODO: unused? if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } + // ------------ if ((lc = state.getLastCommand(Command::ACT, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index 5c934c64..aede0f2d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -48,10 +48,12 @@ const for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); if (lastCommand.isValidCommand()) { + // TODO: Where do these dependencies come from? if (lastCommand.getCommand() == Command::PRE || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRP_old); + // TODO: Why tRCD and not tRAS? } else if (lastCommand.getCommand() == Command::ACT || lastCommand.getCommand() == Command::ACTB) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -59,12 +61,14 @@ const } else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP); + // TODO: missing } else if (lastCommand.getCommand() == Command::RDA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP + config.memSpec->tRP_old); } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); + // TODO: missing } else if (lastCommand.getCommand() == Command::WRA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + @@ -72,6 +76,7 @@ const } else if (lastCommand.getCommand() == Command::REFA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRFC_old); + // TODO: PREA after PDXP possible? } else if (lastCommand.getCommand() == Command::PDXA || lastCommand.getCommand() == Command::PDXP) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -81,12 +86,13 @@ const config.memSpec->tXS); } else reportFatal("Precharge All Checker", - "Precharge All can not follow " + commandToString(lastCommand.getCommand())); + "PREA can not follow " + commandToString(lastCommand.getCommand())); } } ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + // TODO: Why do we only check the ACT of one bank? (always bank 0) if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), config.memSpec->tRAS); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index de3ff162..50c67c43 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -49,6 +49,7 @@ const if (lastCommand.isValidCommand()) { // the first two cases happen when a resfresh interrups the command sequence of a transaction // (e.g. commands to process transaction are PRE-ACT-RD and refresh happens after the PRE or after the ACT) + // TODO: unused? if (lastCommand.getCommand() == Command::PRE || lastCommand.getCommand() == Command::PREB) { command.establishMinDistanceFromStart(lastCommand.getStart(), @@ -58,7 +59,7 @@ const command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRCD); } - + // ------------- else if (lastCommand.getCommand() == Command::RD) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tRTP); @@ -71,7 +72,7 @@ const config.memSpec->tXP); } else reportFatal("Precharge Checker", - "Precharge can not follow " + commandToString(lastCommand.getCommand())); + "PRE can not follow " + commandToString(lastCommand.getCommand())); } ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 9abd6981..1683a30b 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -59,13 +59,13 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), ReadChecker::writeToRead(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::PDXP - || lastCommand.getCommand() == Command::PDXA) { + } else if (/*lastCommand.getCommand() == Command::PDXP + || */lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else reportFatal("Read Checker", - "Read can not follow " + commandToString(lastCommand.getCommand())); + "RD/RDA can not follow " + commandToString(lastCommand.getCommand())); } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { @@ -126,6 +126,7 @@ sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? config->tCCD_L_old : config->tCCD_S_old; + // TODO: When is tCCD smaller than readAccessTime? return max(tCCD, config->getReadAccessTime()); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp index fd618673..48b45eeb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp @@ -68,7 +68,7 @@ void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommandOnBank.getCommand() == Command::REFA) { } else reportFatal("Refresh Checker", - "Refresh can not follow " + commandToString(lastCommandOnBank.getCommand())); + "REFA can not follow " + commandToString(lastCommandOnBank.getCommand())); } } else { for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index 1d262b08..e9136ef7 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -59,13 +59,13 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const } else if (lastCommand.getCommand() == Command::WR) { command.establishMinDistanceFromStart(lastCommand.getStart(), WriteChecker::writeToWrite(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::PDXP - || lastCommand.getCommand() == Command::PDXA) { + } else if (/*lastCommand.getCommand() == Command::PDXP + || */lastCommand.getCommand() == Command::PDXA) { command.establishMinDistanceFromStart(lastCommand.getStart(), config.memSpec->tXP); } else reportFatal("Write Checker", - "Write can not follow " + commandToString(lastCommand.getCommand())); + "WR/WRA can not follow " + commandToString(lastCommand.getCommand())); } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { @@ -117,6 +117,7 @@ sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, MemSpec *config = Configuration::getInstance().memSpec; sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? config->tCCD_L_old : config->tCCD_S_old; + // TODO: When is tCCD smaller than writeAccessTime? return max(tCCD, config->getWriteAccessTime()); } From 3e4e8e940897627769f0959877b590c452636973 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 9 Jul 2019 15:52:09 +0200 Subject: [PATCH 020/183] Included new timing checker for DDR3. --- DRAMSys/library/library.pro | 6 +- .../scheduling/checker/CheckerDDR3New.cpp | 562 ++++++++++++++++++ .../core/scheduling/checker/CheckerDDR3New.h | 58 ++ 3 files changed, 624 insertions(+), 2 deletions(-) create mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp create mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 0a2ada5c..188d67ef 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -148,7 +148,8 @@ SOURCES += \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ src/controller/core/scheduling/checker/CheckerDDR3.cpp \ - src/controller/core/configuration/MemSpec.cpp + src/controller/core/configuration/MemSpec.cpp \ + src/controller/core/scheduling/checker/CheckerDDR3New.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -230,7 +231,8 @@ HEADERS += \ src/simulation/DramRecordable.h \ src/simulation/DramWideIO.h \ src/controller/core/scheduling/checker/CheckerDDR3.h \ - src/controller/GenericController.h + src/controller/GenericController.h \ + src/controller/core/scheduling/checker/CheckerDDR3New.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp new file mode 100644 index 00000000..c7469dab --- /dev/null +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -0,0 +1,562 @@ +#include "CheckerDDR3New.h" + +#include +#include +#include +#include +#include "../../timingCalculations.h" +#include "../../../../common/DebugManager.h" +#include "../../../Command.h" +#include "../../../../common/utils.h" +//#include "../../configuration/MemSpec.h" + +using namespace std; + +void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const +{ + ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); + Command LastCmd = lastCommandOnBank.getCommand(); + Command nextCmd = command.getCommand(); + + if (nextCmd == Command::ACT) + { + // TODO: WRA_bank0 -> PREA -> ACT_bank0: WRA_bank0 and ACT_bank0 have TD, + // but we only consider PREA -> ACT_bank0 TD + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::PRE: + case Command::PREA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP_old); + break; + case Command::RDA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRTP + memSpec->tRP_old); + break; + case Command::WRA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR + memSpec->tRP_old); + break; + case Command::PDXP: + case Command::PDXA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + case Command::SREFEX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXS); + break; + case Command::REFA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRFC_old); + break; + default: + reportFatal("CheckerDDR3New", + "Activate can not follow " + commandToString(LastCmd)); + } + } + + delayToSatisfyACTtoACTsameBank(command); + + while (!(state.bus.isFree(command.getStart()) && + satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command))) + command.delayStart(memSpec->clk); + } + else if (nextCmd == Command::RD || nextCmd == Command::RDA) + { + delayToSatisfyDLL(command); + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::ACT: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRCD); + break; + case Command::RD: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + CasToCas(lastCommandOnBank, command)); + break; + case Command::WR: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + writeToRead(lastCommandOnBank, command)); + break; + case Command::PDXP: + case Command::PDXA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + default: + reportFatal("CheckerDDR3New", + "Read can not follow " + commandToString(LastCmd) + "First: Activate!"); + } + } + while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) + command.delayStart(memSpec->clk); + } + else if (nextCmd == Command::WR || nextCmd == Command::WRA) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::ACT: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRCD); + break; + case Command::RD: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + readToWrite(lastCommandOnBank, command)); + break; + case Command::WR: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + CasToCas(lastCommandOnBank, command)); + break; + case Command::PDXP: + case Command::PDXA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + default: + reportFatal("CheckerDDR3New", "Write can not follow " + commandToString(LastCmd)); + } + } + while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) + command.delayStart(memSpec->clk); + } + else if (nextCmd == Command::PRE) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::PRE: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP_old); + break; + case Command::ACT: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRCD); + break; + case Command::RD: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRTP); + break; + case Command::WR: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + memSpec->tWR + + memSpec->getWriteAccessTime()); + break; + case Command::PDXA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + default: + reportFatal("CheckerDDR3New", + "Precharge can not follow " + commandToString(LastCmd)); + } + } + ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + if (lastActivate.isValidCommand()) + command.establishMinDistanceFromStart(lastActivate.getStart(), + memSpec->tRAS); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::PREA) + { + for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) + { + ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); + if (lastCommand.isValidCommand()) + { + switch (lastCommand.getCommand()) + { + case Command::PRE: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRP_old); + break; + case Command::ACT: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRCD); + break; + case Command::RD: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRTP); + break; + case Command::WR: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR); + break; + case Command::WRA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR + memSpec->tRP_old); + break; + case Command::RDA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRTP + memSpec->tRP_old); + break; + case Command::PDXA: + case Command::PDXP: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXP); + break; + case Command::SREFEX: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXS); + break; + case Command::REFA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRFC_old); + break; + default: + reportFatal("CheckerDDR3New", + "Precharge All can not follow " + commandToString(LastCmd)); + } + } + } + ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + if (lastActivate.isValidCommand()) + command.establishMinDistanceFromStart(lastActivate.getStart(), + memSpec->tRAS); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::PDEA || nextCmd == Command::PDEP || nextCmd == Command::SREFEN ) + { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::PRE: + case Command::PREA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP_old); + break; + case Command::RD: + case Command::RDA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRL + memSpec->getReadAccessTime() + + memSpec->clk); + break; + case Command::WR: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR); + break; + case Command::WRA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR + memSpec->clk); + break; + case Command::REFA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRFC_old); + break; + case Command::PDXA: + case Command::PDXP: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + case Command::SREFEX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXS); + break; + default: + reportFatal("CheckerDDR3New", commandToString(nextCmd) + " can not follow " + + commandToString(LastCmd) + ".First: Precharge!"); + } + } + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::PDXA) + { + // Leaving Precharge Power Down + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, + command.getBank()).getStart(), memSpec->tCKE); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::PDXP) + { + // Leaving Precharge Power Down + command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, + command.getBank()).getStart(), memSpec->tCKE); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::SREFEX) + { + // Leaving Self Refresh + command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, + command.getBank()).getStart(), memSpec->tCKESR); + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::REFA) + { + if (config.BankwiseLogic) { + if (lastCommandOnBank.isValidCommand()) + { + switch (LastCmd) + { + case Command::PRE: + case Command::PREA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRP_old); + break; + case Command::RDA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRTP + memSpec->tRP_old); + break; + case Command::WRA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR + memSpec->tRP_old); + break; + case Command::REFA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tRFC_old); + break; + case Command::PDXP: + case Command::PDXA: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXP); + break; + case Command::SREFEX: + command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), + memSpec->tXS); + break; + default: + reportFatal("CheckerDDR3New", + "Refresh can not follow " + commandToString(LastCmd)); + } + } + } + else + { + for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) + { + ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); + + if (lastCommand.isValidCommand()) + { + switch (lastCommand.getCommand()) + { + case Command::PRE: + case Command::PREA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRP_old); + break; + case Command::ACT: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRCD); + break; + case Command::RDA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRTP + memSpec->tRP_old); + break; + case Command::WRA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tWL + memSpec->getWriteAccessTime() + + memSpec->tWR + memSpec->tRP_old); + break; + case Command::REFA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tRFC_old); + break; + case Command::PDXP: + case Command::PDXA: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXP); + break; + case Command::SREFEX: + command.establishMinDistanceFromStart(lastCommand.getStart(), + memSpec->tXS); + break; + default: + reportFatal("CheckerDDR3New", + "Refresh can not follow " + commandToString(LastCmd)); + } + } + } + } + state.bus.moveCommandToNextFreeSlot(command); + } +} + +/* +* ActivateChecker +*/ + +void CheckerDDR3New::delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const +{ + ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); + if (lastActivateOnBank.isValidCommand()) + command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); +} + +bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const +{ + for (auto act : state.lastActivates) + { + sc_time time = act.first; + if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) + || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) + return false; + } + return true; + +} + +bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const +{ + /* + * there may be activates scheduled in the future, so emplace + * command in a copied set (not necessarily the last in time), + * and check if the n-act constraint holds for the whole set. + */ + if (state.lastActivates.size() >= memSpec->nActivate) + { + std::map lastActivates = state.lastActivates; + lastActivates.emplace(command.getStart(), command); + auto upper = lastActivates.begin(); + std::advance(upper, memSpec->nActivate); + auto lower = lastActivates.begin(); + + while (upper != lastActivates.end()) + { + if (upper->first - lower->first < memSpec->tNAW_old) + return false; + upper++; + lower++; + } + } + return true; +} + + +/* + * Read-Checker +*/ + +bool CheckerDDR3New::collidesOnDataStrobe_RD(ScheduledCommand &read) const +{ + for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) + { + if (collidesWithStrobeCommand_RD(read, strobeCommand)) + return true; + } + return false; +} + +bool CheckerDDR3New::collidesWithStrobeCommand_RD(ScheduledCommand &read, + ScheduledCommand &strobeCommand) const +{ + if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) + { + return getDistance(read.getStart(), + strobeCommand.getStart()) < CasToCas(strobeCommand, read); + } + else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) + { + if (strobeCommand.getStart() >= read.getStart()) + return getDistance(read.getStart(), + strobeCommand.getStart()) < readToWrite(read, strobeCommand); + else + return getDistance(strobeCommand.getStart(), + read.getStart()) < writeToRead(strobeCommand, read); + } else { + reportFatal("CheckerDDR3New", + "Invalid strobeCommand in data strobe commands " + commandToString( + strobeCommand.getCommand())); + return true; + } + return false; +} + + +void CheckerDDR3New::delayToSatisfyDLL(ScheduledCommand &read) const +{ + ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, read.getBank()); + if (lastSREFX.isValidCommand()) + read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); +} + + +sc_time CheckerDDR3New::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const +{ + sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); + sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA); + + return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; +} + +/* CAS-CAS */ + +sc_time CheckerDDR3New::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const +{ + if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA) + { + if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA) + return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); + } + else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA) + { + if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA) + return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); + } + SC_REPORT_FATAL("CasToCas", "Exception reached"); + return SC_ZERO_TIME; +} + +/* +* Write-Checker +*/ + +bool CheckerDDR3New::collidesOnDataStrobe_WR(ScheduledCommand &write) const +{ + for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) + { + if (collidesWithStrobeCommand_WR(write, strobeCommand)) + return true; + } + return false; +} + +bool CheckerDDR3New::collidesWithStrobeCommand_WR(ScheduledCommand &write, + ScheduledCommand &strobeCommand) const +{ + if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) + { + // TODO: Cast from sc_time to bool? + return getDistance(write.getStart(), + strobeCommand.getStart()) < CasToCas(strobeCommand, write); + } + else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) + { + if (strobeCommand.getStart() >= write.getStart()) + return getDistance(write.getStart(), + strobeCommand.getStart()) < writeToRead(write, strobeCommand); + else + return getDistance(strobeCommand.getStart(), + write.getStart()) < readToWrite(strobeCommand, write); + } + else + { + reportFatal("CheckerDDR3New", "Invalid strobeCommand in data strobe commands " + + commandToString(strobeCommand.getCommand())); + return true; + } +} + + +sc_time CheckerDDR3New::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const +{ + sc_assert(read.getCommand() == Command::RD + || read.getCommand() == Command::RDA); + sc_assert(write.getCommand() == Command::WR + || write.getCommand() == Command::WRA); + + return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; +} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h new file mode 100644 index 00000000..53ff3fe3 --- /dev/null +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -0,0 +1,58 @@ +#ifndef CHECKERDDR3NEW_H +#define CHECKERDDR3NEW_H + +#include "ICommandChecker.h" +#include "../../configuration/Configuration.h" +#include "../../../ControllerState.h" + +//Activate +class CheckerDDR3New : public ICommandChecker +{ +public: + CheckerDDR3New(const Configuration &config, + ControllerState &state) : config(config), state(state) + { + memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + } + virtual ~CheckerDDR3New() {} + + virtual void delayToSatisfyConstraints(ScheduledCommand &command) const override; + +private: + MemSpecDDR3 *memSpec; + + //Activate + void delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const; + bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const; + bool satisfiesNActivateWindow(ScheduledCommand &command) const; + + //PowerDown + sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; + + //used for Read + void delayToSatisfyDLL(ScheduledCommand &read) const; + bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; + bool collidesWithStrobeCommand_RD(ScheduledCommand &read, + ScheduledCommand &strobeCommand) const; + + //Write + bool collidesOnDataStrobe_WR(ScheduledCommand &write) const; + bool collidesWithStrobeCommand_WR(ScheduledCommand &write, + ScheduledCommand &strobeCommand) const; + + //handles WR->RD + sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const; + + //RD->WR + sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const; + + //CasToCas Commands (WR->WR)(RD->RD) + sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const; + + const Configuration &config; + ControllerState &state;//TODO make const +}; + +#endif // CHECKERDDR3NEW_H From 9be64edaa94ead811257cc6f91b5aabad5a812d8 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 10 Jul 2019 15:55:45 +0200 Subject: [PATCH 021/183] Added commands ACT, PRE, PREA, RD, RDA, WR, WRA, PDEA, PDEP to new timing checker. --- .../src/controller/core/ControllerCore.cpp | 3 +- .../scheduling/checker/CheckerDDR3New.cpp | 376 +++++++++--------- 2 files changed, 196 insertions(+), 183 deletions(-) diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index a6bef2cc..b2827ddf 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -53,6 +53,7 @@ #include "../../common/utils.h" #include "timingCalculations.h" #include "scheduling/checker/CheckerDDR3.h" +#include "scheduling/checker/CheckerDDR3New.h" #include "powerdown/PowerDownManager.h" #include "powerdown/PowerDownManagerTimeout.h" @@ -86,7 +87,7 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, commandChecker[Command::PDXP] = commandChecker[Command::PDEA]; commandChecker[Command::SREFEX] = commandChecker[Command::PDEA]; - //timingChecker = new CheckerDDR3(config, *state); + timingChecker = new CheckerDDR3New(config, *state); if (config.RowGranularRef) { refreshManager = new RGR("RGR", *this); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index c7469dab..5bd49387 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -17,215 +17,228 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); Command LastCmd = lastCommandOnBank.getCommand(); Command nextCmd = command.getCommand(); + ScheduledCommand lastCommand; if (nextCmd == Command::ACT) { // TODO: WRA_bank0 -> PREA -> ACT_bank0: WRA_bank0 and ACT_bank0 have TD, // but we only consider PREA -> ACT_bank0 TD - if (lastCommandOnBank.isValidCommand()) - { - switch (LastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - default: - reportFatal("CheckerDDR3New", - "Activate can not follow " + commandToString(LastCmd)); - } - } + // REFA -> PDEP -> PDXP -> ACT + + lastCommand = state.getLastCommand(Command::RDA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP); + + lastCommand = state.getLastCommand(Command::WRA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PRE, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PREA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::REFA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); + + lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); delayToSatisfyACTtoACTsameBank(command); - while (!(state.bus.isFree(command.getStart()) && - satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command))) + while (!(state.bus.isFree(command.getStart()) && satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command))) command.delayStart(memSpec->clk); } else if (nextCmd == Command::RD || nextCmd == Command::RDA) { - delayToSatisfyDLL(command); - if (lastCommandOnBank.isValidCommand()) - { - switch (LastCmd) - { - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - CasToCas(lastCommandOnBank, command)); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - writeToRead(lastCommandOnBank, command)); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("CheckerDDR3New", - "Read can not follow " + commandToString(LastCmd) + "First: Activate!"); - } - } + lastCommand = state.getLastCommand(Command::ACT, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); + + lastCommand = state.getLastCommand(Command::RD, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCCD); + + lastCommand = state.getLastCommand(Command::WR, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + + lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXSDLL); + while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) command.delayStart(memSpec->clk); } else if (nextCmd == Command::WR || nextCmd == Command::WRA) { - if (lastCommandOnBank.isValidCommand()) - { - switch (LastCmd) - { - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - readToWrite(lastCommandOnBank, command)); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - CasToCas(lastCommandOnBank, command)); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("CheckerDDR3New", "Write can not follow " + commandToString(LastCmd)); - } - } + lastCommand = state.getLastCommand(Command::ACT, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); + + lastCommand = state.getLastCommand(Command::RD, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + + lastCommand = state.getLastCommand(Command::WR, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCCD); + + lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXSDLL); + while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) command.delayStart(memSpec->clk); } else if (nextCmd == Command::PRE) { - if (lastCommandOnBank.isValidCommand()) - { - switch (LastCmd) - { - case Command::PRE: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->tWR - + memSpec->getWriteAccessTime()); - break; - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("CheckerDDR3New", - "Precharge can not follow " + commandToString(LastCmd)); - } - } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); - if (lastActivate.isValidCommand()) - command.establishMinDistanceFromStart(lastActivate.getStart(), - memSpec->tRAS); + lastCommand = state.getLastCommand(Command::ACT, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRAS); + + lastCommand = state.getLastCommand(Command::RD, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); + + lastCommand = state.getLastCommand(Command::WR, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); + + lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + state.bus.moveCommandToNextFreeSlot(command); } else if (nextCmd == Command::PREA) { - for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) - { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - if (lastCommand.isValidCommand()) - { - switch (lastCommand.getCommand()) - { - case Command::PRE: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::PDXA: - case Command::PDXP: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC_old); - break; - default: - reportFatal("CheckerDDR3New", - "Precharge All can not follow " + commandToString(LastCmd)); - } - } - } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); - if (lastActivate.isValidCommand()) - command.establishMinDistanceFromStart(lastActivate.getStart(), - memSpec->tRAS); + lastCommand = state.getLastCommand(Command::ACT); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRAS); + + lastCommand = state.getLastCommand(Command::RD); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); + + lastCommand = state.getLastCommand(Command::RDA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); + + lastCommand = state.getLastCommand(Command::WR); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); + + lastCommand = state.getLastCommand(Command::WRA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); + + lastCommand = state.getLastCommand(Command::PDXA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::REFA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); + state.bus.moveCommandToNextFreeSlot(command); } - else if (nextCmd == Command::PDEA || nextCmd == Command::PDEP || nextCmd == Command::SREFEN ) + else if (nextCmd == Command::PDEA) + { + // TODO: Remove? + lastCommand = state.getLastCommand(Command::ACT); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); + + lastCommand = state.getLastCommand(Command::RD); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); + + lastCommand = state.getLastCommand(Command::RDA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); + + lastCommand = state.getLastCommand(Command::WR); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 4 * memSpec->clk + memSpec->tWR); + + lastCommand = state.getLastCommand(Command::WRA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + // TODO: Remove? + lastCommand = state.getLastCommand(Command::PRE); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); + + lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); + + state.bus.moveCommandToNextFreeSlot(command); + } + else if (nextCmd == Command::PDEP) + { + lastCommand = state.getLastCommand(Command::RD); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); + + lastCommand = state.getLastCommand(Command::RDA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); + + lastCommand = state.getLastCommand(Command::WRA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + // TODO: Remove? + lastCommand = state.getLastCommand(Command::PRE); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); + + // TODO: Remove? + lastCommand = state.getLastCommand(Command::PREA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); + + lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); + + // TODO: Remove? + lastCommand = state.getLastCommand(Command::REFA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); + + lastCommand = state.getLastCommand(Command::SREFEX); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); + + state.bus.moveCommandToNextFreeSlot(command); + } + // TODO: current position in code + else if (nextCmd == Command::SREFEN) { if (lastCommandOnBank.isValidCommand()) { @@ -529,7 +542,6 @@ bool CheckerDDR3New::collidesWithStrobeCommand_WR(ScheduledCommand &write, { if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) { - // TODO: Cast from sc_time to bool? return getDistance(write.getStart(), strobeCommand.getStart()) < CasToCas(strobeCommand, write); } From be83ad01cb76805d8d8a3edd84952b7268cb752c Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 11 Jul 2019 15:22:09 +0200 Subject: [PATCH 022/183] Included remaining commands. --- .../core/scheduling/checker/CheckerDDR3.cpp | 2 - .../scheduling/checker/CheckerDDR3New.cpp | 195 +++++++----------- .../core/scheduling/checker/CheckerDDR3New.h | 1 - 3 files changed, 79 insertions(+), 119 deletions(-) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index f1081579..068a57a9 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -4,12 +4,10 @@ #include #include #include -#include "CheckerDDR3.h" #include "../../timingCalculations.h" #include "../../../../common/DebugManager.h" #include "../../../Command.h" #include "../../../../common/utils.h" -//#include "../../configuration/MemSpec.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 5bd49387..34ea33fa 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -8,7 +8,6 @@ #include "../../../../common/DebugManager.h" #include "../../../Command.h" #include "../../../../common/utils.h" -//#include "../../configuration/MemSpec.h" using namespace std; @@ -24,7 +23,6 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const // TODO: WRA_bank0 -> PREA -> ACT_bank0: WRA_bank0 and ACT_bank0 have TD, // but we only consider PREA -> ACT_bank0 TD // REFA -> PDEP -> PDXP -> ACT - lastCommand = state.getLastCommand(Command::RDA, command.getBank()); if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP); @@ -65,7 +63,7 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const else if (nextCmd == Command::RD || nextCmd == Command::RDA) { lastCommand = state.getLastCommand(Command::ACT, command.getBank()); - if (lastCommand.isValidCommand()) + //if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); lastCommand = state.getLastCommand(Command::RD, command.getBank()); @@ -90,7 +88,7 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const else if (nextCmd == Command::WR || nextCmd == Command::WRA) { lastCommand = state.getLastCommand(Command::ACT, command.getBank()); - if (lastCommand.isValidCommand()) + //if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); lastCommand = state.getLastCommand(Command::RD, command.getBank()); @@ -115,7 +113,7 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const else if (nextCmd == Command::PRE) { lastCommand = state.getLastCommand(Command::ACT, command.getBank()); - if (lastCommand.isValidCommand()) + //if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRAS); lastCommand = state.getLastCommand(Command::RD, command.getBank()); @@ -154,11 +152,11 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); - lastCommand = state.getLastCommand(Command::PDXA); + lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - lastCommand = state.getLastCommand(Command::REFA); + lastCommand = state.getLastCommand(Command::REFA, command.getBank()); if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); @@ -168,7 +166,7 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const { // TODO: Remove? lastCommand = state.getLastCommand(Command::ACT); - if (lastCommand.isValidCommand()) + //if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); lastCommand = state.getLastCommand(Command::RD); @@ -231,84 +229,72 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); - lastCommand = state.getLastCommand(Command::SREFEX); + lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); state.bus.moveCommandToNextFreeSlot(command); } - // TODO: current position in code else if (nextCmd == Command::SREFEN) { - if (lastCommandOnBank.isValidCommand()) - { - switch (LastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RD: - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRL + memSpec->getReadAccessTime() - + memSpec->clk); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->clk); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXA: - case Command::PDXP: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - default: - reportFatal("CheckerDDR3New", commandToString(nextCmd) + " can not follow " - + commandToString(LastCmd) + ".First: Precharge!"); - } - } + lastCommand = state.getLastCommand(Command::RDA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); + + lastCommand = state.getLastCommand(Command::WRA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + lastCommand = state.getLastCommand(Command::PRE); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PREA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); + state.bus.moveCommandToNextFreeSlot(command); } else if (nextCmd == Command::PDXA) { - // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, - command.getBank()).getStart(), memSpec->tCKE); + lastCommand = state.getLastScheduledCommand(command.getBank()); + if (lastCommand.getCommand() != Command::PDEA) + reportFatal("CheckerDDR3New", "PDXA can not follow " + commandToString(lastCommand.getCommand())); + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); + state.bus.moveCommandToNextFreeSlot(command); } else if (nextCmd == Command::PDXP) { - // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, - command.getBank()).getStart(), memSpec->tCKE); + lastCommand = state.getLastScheduledCommand(command.getBank()); + if (lastCommand.getCommand() != Command::PDEP) + reportFatal("CheckerDDR3New", "PDXP can not follow " + commandToString(lastCommand.getCommand())); + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); + state.bus.moveCommandToNextFreeSlot(command); } else if (nextCmd == Command::SREFEX) { - // Leaving Self Refresh - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, - command.getBank()).getStart(), memSpec->tCKESR); + lastCommand = state.getLastScheduledCommand(command.getBank()); + if (lastCommand.getCommand() != Command::SREFEN) + reportFatal("CheckerDDR3New", "SREFEX can not follow " + commandToString(lastCommand.getCommand())); + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKESR); + state.bus.moveCommandToNextFreeSlot(command); } else if (nextCmd == Command::REFA) { - if (config.BankwiseLogic) { + // TODO: Bankwise logic + if (config.BankwiseLogic) + { if (lastCommandOnBank.isValidCommand()) { switch (LastCmd) @@ -348,54 +334,40 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const } else { - for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) - { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); + lastCommand = state.getLastCommand(Command::RDA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP); - if (lastCommand.isValidCommand()) - { - switch (lastCommand.getCommand()) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRCD); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); - break; - default: - reportFatal("CheckerDDR3New", - "Refresh can not follow " + commandToString(LastCmd)); - } - } - } + lastCommand = state.getLastCommand(Command::WRA); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PRE); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PREA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + + lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + + lastCommand = state.getLastCommand(Command::REFA, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); + + lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); } state.bus.moveCommandToNextFreeSlot(command); } + else + { + reportFatal("CheckerDDR3New", "Unknown command!"); + } } /* @@ -488,15 +460,6 @@ bool CheckerDDR3New::collidesWithStrobeCommand_RD(ScheduledCommand &read, return false; } - -void CheckerDDR3New::delayToSatisfyDLL(ScheduledCommand &read) const -{ - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, read.getBank()); - if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); -} - - sc_time CheckerDDR3New::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const { sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 53ff3fe3..ad202aca 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -32,7 +32,6 @@ private: sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; //used for Read - void delayToSatisfyDLL(ScheduledCommand &read) const; bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; bool collidesWithStrobeCommand_RD(ScheduledCommand &read, ScheduledCommand &strobeCommand) const; From f43ea71e9542c1fba1d2873ed523aa0444d9be86 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 16 Jul 2019 15:52:02 +0200 Subject: [PATCH 023/183] Minor changes in new timing checker. --- .../memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml | 55 +++++++++++++++++++ DRAMSys/library/src/controller/Controller.cpp | 1 - .../scheduling/checker/CheckerDDR3New.cpp | 12 +--- .../core/scheduling/checker/CheckerDDR3New.h | 1 - 4 files changed, 58 insertions(+), 11 deletions(-) create mode 100644 DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml new file mode 100644 index 00000000..262feb17 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index e9db7911..adc1b75a 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -305,7 +305,6 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload, else if (phase == END_RESP) { // Bandwidth IDLE - // TODO: getTotalNumberOfPayloadsInSystem() == 1 && !idleState ?? if (getTotalNumberOfPayloadsInSystem() == 1) startBandwidthIdleCollector(); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 34ea33fa..451158cf 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -55,7 +55,9 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const if (lastCommand.isValidCommand()) command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); - delayToSatisfyACTtoACTsameBank(command); + lastCommand = state.getLastCommand(Command::ACT, command.getBank()); + if (lastCommand.isValidCommand()) + command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRC); while (!(state.bus.isFree(command.getStart()) && satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command))) command.delayStart(memSpec->clk); @@ -373,14 +375,6 @@ void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const /* * ActivateChecker */ - -void CheckerDDR3New::delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const -{ - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); - if (lastActivateOnBank.isValidCommand()) - command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); -} - bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const { for (auto act : state.lastActivates) diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index ad202aca..6daff0dc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -24,7 +24,6 @@ private: MemSpecDDR3 *memSpec; //Activate - void delayToSatisfyACTtoACTsameBank(ScheduledCommand &command) const; bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const; bool satisfiesNActivateWindow(ScheduledCommand &command) const; From 41e2db0b5a897d97e4ea55e24fd27fc8347bc322 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 19 Jul 2019 10:29:14 +0200 Subject: [PATCH 024/183] Removed refresh and power down. --- DRAMSys/library/src/controller/Controller.cpp | 25 +- .../src/controller/core/ControllerCore.cpp | 134 ++--- .../src/controller/core/ControllerCore.h | 6 +- .../core/powerdown/IPowerDownManager.h | 226 ++++---- .../controller/core/powerdown/NoPowerDown.cpp | 114 ++-- .../controller/core/powerdown/NoPowerDown.h | 108 ++-- .../core/powerdown/PowerDownManager.cpp | 370 ++++++------- .../core/powerdown/PowerDownManager.h | 122 ++--- .../powerdown/PowerDownManagerBankwise.cpp | 372 ++++++------- .../core/powerdown/PowerDownManagerBankwise.h | 144 ++--- .../powerdown/PowerDownManagerTimeout.cpp | 250 ++++----- .../core/powerdown/PowerDownManagerTimeout.h | 110 ++-- .../PowerDownManagerTimeoutBankwise.cpp | 240 ++++---- .../PowerDownManagerTimeoutBankwise.h | 110 ++-- .../controller/core/refresh/IRefreshManager.h | 120 ++-- .../src/controller/core/refresh/RGR.cpp | 514 ++++++++--------- .../library/src/controller/core/refresh/RGR.h | 150 ++--- .../core/refresh/RefreshManager.cpp | 516 +++++++++--------- .../controller/core/refresh/RefreshManager.h | 146 ++--- .../core/refresh/RefreshManagerBankwise.cpp | 498 ++++++++--------- .../core/refresh/RefreshManagerBankwise.h | 146 ++--- 21 files changed, 2211 insertions(+), 2210 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index adc1b75a..aa79c3d2 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -249,12 +249,12 @@ void Controller::controllerCorePEQCallback(tlm_generic_payload &payload, { if (phase == REF_TRIGGER) { - controllerCore->triggerRefresh(payload); + //controllerCore->triggerRefresh(payload); } else if (phase == PDN_TRIGGER) { - controllerCore->powerDownManager->sleep(DramExtension::getExtension( - payload).getBank(), sc_time_stamp()); + //controllerCore->powerDownManager->sleep(DramExtension::getExtension( + // payload).getBank(), sc_time_stamp()); } else { @@ -343,6 +343,7 @@ void Controller::frontendPEQCallback(tlm_generic_payload &payload, sendToFrontend(payload, END_REQ, SC_ZERO_TIME); scheduler->storeRequest(&payload); + // TODO: remove this scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); } } @@ -403,7 +404,7 @@ void Controller::payloadLeavesSystem(tlm_generic_payload &payload) "Payload left system on bank " + to_string(bank.ID()) + ". Total number of payloads in Controller: " + to_string(getTotalNumberOfPayloadsInSystem())); - controllerCore->powerDownManager->triggerSleep(bank, sc_time_stamp()); + //controllerCore->powerDownManager->triggerSleep(bank, sc_time_stamp()); } unsigned int Controller::getTotalNumberOfPayloadsInSystem() @@ -477,8 +478,8 @@ void Controller::scheduleNextFromScheduler(Bank bank) void Controller::schedule(Command command, gp &payload) { - controllerCore->powerDownManager->wakeUp(DramExtension::getBank(payload), - sc_time_stamp()); + //controllerCore->powerDownManager->wakeUp(DramExtension::getBank(payload), + // sc_time_stamp()); if (controllerCore->scheduleRequest(command, payload)) { printDebugMessage("\t-> Next payload was scheduled by core [" + commandToString( @@ -538,15 +539,15 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload, scheduleNextFromScheduler(bank); } } - if (sleepy == true) - controllerCore->powerDownManager->sleep(0, sc_time_stamp()); + //if (sleepy == true) + //controllerCore->powerDownManager->sleep(0, sc_time_stamp()); } else if (phase == END_REFB) { printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID())); - if (numberOfPayloadsInSystem[bank] == 0) - controllerCore->powerDownManager->sleep(bank, sc_time_stamp()); + if (numberOfPayloadsInSystem[bank] == 0) {} + //controllerCore->powerDownManager->sleep(bank, sc_time_stamp()); else scheduleNextFromScheduler(bank); @@ -603,10 +604,10 @@ void Controller::terminateSimulation() { if (Configuration::getInstance().BankwiseLogic) { for (Bank bank : controllerCore->getBanks()) { - controllerCore->powerDownManager->wakeUp(bank, clkAlign(sc_time_stamp())); + //controllerCore->powerDownManager->wakeUp(bank, clkAlign(sc_time_stamp())); } } else { - controllerCore->powerDownManager->wakeUp(0, clkAlign(sc_time_stamp())); + //controllerCore->powerDownManager->wakeUp(0, clkAlign(sc_time_stamp())); } endTime = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index b2827ddf..4ec38ff6 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -89,33 +89,33 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, timingChecker = new CheckerDDR3New(config, *state); - if (config.RowGranularRef) { - refreshManager = new RGR("RGR", *this); - } else { - if (config.BankwiseLogic) { - refreshManager = new RefreshManagerBankwise("refManagerBw", *this); - } else { - refreshManager = new RefreshManager("refManager", *this); - } - } +// if (config.RowGranularRef) { +// refreshManager = new RGR("RGR", *this); +// } else { +// if (config.BankwiseLogic) { +// refreshManager = new RefreshManagerBankwise("refManagerBw", *this); +// } else { +// refreshManager = new RefreshManager("refManager", *this); +// } +// } - if (config.PowerDownMode == EPowerDownMode::Staggered) { - if (config.BankwiseLogic) - powerDownManager = new PowerDownManagerBankwise("pdnManagerBw", *this); - else - powerDownManager = new PowerDownManager("pdnManager", *this); - } else if (config.PowerDownMode == EPowerDownMode::TimeoutPDN - || config.PowerDownMode == EPowerDownMode::TimeoutSREF) { - if (config.BankwiseLogic) - powerDownManager = new PowerDownManagerTimeoutBankwise("pdnManagerBw", *this); - else - powerDownManager = new PowerDownManagerTimeout("pdnManager", *this); - } else if (config.PowerDownMode == EPowerDownMode::NoPowerDown) { - powerDownManager = new NoPowerDown(); - } else { - SC_REPORT_FATAL(0, - "Unsupported powerdown mode in constructor of controller core"); - } +// if (config.PowerDownMode == EPowerDownMode::Staggered) { +// if (config.BankwiseLogic) +// powerDownManager = new PowerDownManagerBankwise("pdnManagerBw", *this); +// else +// powerDownManager = new PowerDownManager("pdnManager", *this); +// } else if (config.PowerDownMode == EPowerDownMode::TimeoutPDN +// || config.PowerDownMode == EPowerDownMode::TimeoutSREF) { +// if (config.BankwiseLogic) +// powerDownManager = new PowerDownManagerTimeoutBankwise("pdnManagerBw", *this); +// else +// powerDownManager = new PowerDownManagerTimeout("pdnManager", *this); +// } else if (config.PowerDownMode == EPowerDownMode::NoPowerDown) { +// powerDownManager = new NoPowerDown(); +// } else { +// SC_REPORT_FATAL(0, +// "Unsupported powerdown mode in constructor of controller core"); +// } } ControllerCore::~ControllerCore() @@ -128,38 +128,38 @@ ControllerCore::~ControllerCore() delete commandChecker[Command::REFA]; delete commandChecker[Command::PDEA]; delete timingChecker; - delete refreshManager; - delete powerDownManager; + //delete refreshManager; + //delete powerDownManager; delete state; } -void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload) -{ - /* Refresh can be disabled for tests purpose */ - if (config.ControllerCoreRefDisable == false) - { - sc_time time = sc_time_stamp(); - Bank bank = DramExtension::getExtension(payload).getBank(); +//void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload) +//{ +// /* Refresh can be disabled for tests purpose */ +// if (config.ControllerCoreRefDisable == false) +// { +// sc_time time = sc_time_stamp(); +// Bank bank = DramExtension::getExtension(payload).getBank(); - state->cleanUp(time); +// state->cleanUp(time); - if (!refreshManager->isInvalidated(payload, time) - && !powerDownManager->isInSelfRefresh(bank)) - { - printDebugMessage("Triggering refresh on bank " + to_string(bank.ID())); - powerDownManager->wakeUpForRefresh(bank, - time); //expects PDNA and PDNP to exit without delay - bool pdnpToSrefTransition = false; - if (config.PowerDownMode == EPowerDownMode::Staggered) - pdnpToSrefTransition = (state->getLastCommand(Command::PDXP, - bank).getStart() >= time); - if (pdnpToSrefTransition) - powerDownManager->sleep(bank, time); - else - refreshManager->scheduleRefresh(payload, time); - } - } -} +// if (!refreshManager->isInvalidated(payload, time) +// && !powerDownManager->isInSelfRefresh(bank)) +// { +// printDebugMessage("Triggering refresh on bank " + to_string(bank.ID())); +// powerDownManager->wakeUpForRefresh(bank, +// time); //expects PDNA and PDNP to exit without delay +// bool pdnpToSrefTransition = false; +// if (config.PowerDownMode == EPowerDownMode::Staggered) +// pdnpToSrefTransition = (state->getLastCommand(Command::PDXP, +// bank).getStart() >= time); +// if (pdnpToSrefTransition) +// powerDownManager->sleep(bank, time); +// else +// refreshManager->scheduleRefresh(payload, time); +// } +// } +//} bool ControllerCore::scheduleRequest(Command command, tlm::tlm_generic_payload &payload) @@ -167,23 +167,23 @@ bool ControllerCore::scheduleRequest(Command command, sc_time start = clkAlign(sc_time_stamp()); state->cleanUp(start); ScheduledCommand scheduledCommand = schedule(command, start, payload); - if (config.ControllerCoreRefDisable) - { + //if (config.ControllerCoreRefDisable) + //{ state->change(scheduledCommand); controller.send(scheduledCommand, payload); return true; - } - else - { - if (!((command == Command::PRE || command == Command::ACT) - && refreshManager->hasCollision(scheduledCommand))) - { - state->change(scheduledCommand); - controller.send(scheduledCommand, payload); - return true; - } - } - return false; +// } +// else +// { +// if (!((command == Command::PRE || command == Command::ACT) +// && refreshManager->hasCollision(scheduledCommand))) +// { +// state->change(scheduledCommand); +// controller.send(scheduledCommand, payload); +// return true; +// } +// } +// return false; } ScheduledCommand ControllerCore::schedule(Command command, sc_time start, diff --git a/DRAMSys/library/src/controller/core/ControllerCore.h b/DRAMSys/library/src/controller/core/ControllerCore.h index 7a07ae3f..291ba905 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.h +++ b/DRAMSys/library/src/controller/core/ControllerCore.h @@ -59,7 +59,7 @@ public: virtual ~ControllerCore(); bool scheduleRequest(Command command, tlm::tlm_generic_payload &payload); - void triggerRefresh(tlm::tlm_generic_payload &payload); + //void triggerRefresh(tlm::tlm_generic_payload &payload); const std::vector &getBanks(); std::vector getFreeBanks(); @@ -76,8 +76,8 @@ public: Configuration config; ControllerState *state; IController &controller; - IPowerDownManager *powerDownManager; - IRefreshManager *refreshManager; + //IPowerDownManager *powerDownManager; + //IRefreshManager *refreshManager; std::map &numberOfPayloads; private: diff --git a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h index 01aac5ba..047cb407 100644 --- a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h +++ b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h @@ -1,129 +1,129 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// */ -#ifndef IPOWERDOWNMANAGER_H -#define IPOWERDOWNMANAGER_H +//#ifndef IPOWERDOWNMANAGER_H +//#define IPOWERDOWNMANAGER_H -#include -#include "../../../common/dramExtensions.h" -#include "../../Command.h" +//#include +//#include "../../../common/dramExtensions.h" +//#include "../../Command.h" -enum class PowerDownState { - Awake, AwakeForRefresh, PDNActive, PDNPrecharge, PDNSelfRefresh -}; +//enum class PowerDownState { +// Awake, AwakeForRefresh, PDNActive, PDNPrecharge, PDNSelfRefresh +//}; -class IPowerDownManager -{ -public: - virtual ~IPowerDownManager() {} +//class IPowerDownManager +//{ +//public: +// virtual ~IPowerDownManager() {} - virtual void sleep(Bank bank, sc_time time) = 0; - virtual void triggerSleep(Bank bank, sc_time time) = 0; +// virtual void sleep(Bank bank, sc_time time) = 0; +// virtual void triggerSleep(Bank bank, sc_time time) = 0; - virtual void wakeUp(Bank bank, sc_time time) = 0; - virtual void wakeUpForRefresh(Bank bank, sc_time time) = 0; +// virtual void wakeUp(Bank bank, sc_time time) = 0; +// virtual void wakeUpForRefresh(Bank bank, sc_time time) = 0; - virtual bool isInSelfRefresh(Bank bank) = 0; +// virtual bool isInSelfRefresh(Bank bank) = 0; -protected: - Command getSleepCommand(PowerDownState state); - Command getWakeUpCommand(PowerDownState state); +//protected: +// Command getSleepCommand(PowerDownState state); +// Command getWakeUpCommand(PowerDownState state); -}; +//}; -inline Command IPowerDownManager::getSleepCommand(PowerDownState state) -{ - Command cmd(Command::NOP); - switch (state) { - case PowerDownState::PDNActive: - cmd = Command::PDEA; - break; - case PowerDownState::PDNPrecharge: - cmd = Command::PDEP; - break; - case PowerDownState::PDNSelfRefresh: - cmd = Command::SREFEN; - break; - default: - SC_REPORT_FATAL("In PowerDownManager sendPowerdownBegin", - "invalid powerDownState"); - break; - } - return cmd; -} +//inline Command IPowerDownManager::getSleepCommand(PowerDownState state) +//{ +// Command cmd(Command::NOP); +// switch (state) { +// case PowerDownState::PDNActive: +// cmd = Command::PDEA; +// break; +// case PowerDownState::PDNPrecharge: +// cmd = Command::PDEP; +// break; +// case PowerDownState::PDNSelfRefresh: +// cmd = Command::SREFEN; +// break; +// default: +// SC_REPORT_FATAL("In PowerDownManager sendPowerdownBegin", +// "invalid powerDownState"); +// break; +// } +// return cmd; +//} -inline Command IPowerDownManager::getWakeUpCommand(PowerDownState state) +//inline Command IPowerDownManager::getWakeUpCommand(PowerDownState state) -{ - Command cmd(Command::NOP); - switch (state) { - case PowerDownState::PDNActive: - cmd = Command::PDXA; - break; - case PowerDownState::PDNPrecharge: - cmd = Command::PDXP; - break; - case PowerDownState::PDNSelfRefresh: - cmd = Command::SREFEX; - break; - default: - SC_REPORT_FATAL("In PowerDownManager sendPowerdownEnd", - "invalid powerDownState"); - } - return cmd; -} +//{ +// Command cmd(Command::NOP); +// switch (state) { +// case PowerDownState::PDNActive: +// cmd = Command::PDXA; +// break; +// case PowerDownState::PDNPrecharge: +// cmd = Command::PDXP; +// break; +// case PowerDownState::PDNSelfRefresh: +// cmd = Command::SREFEX; +// break; +// default: +// SC_REPORT_FATAL("In PowerDownManager sendPowerdownEnd", +// "invalid powerDownState"); +// } +// return cmd; +//} -inline std::string powerDownStateToString(PowerDownState powerDownState) -{ - switch (powerDownState) { - case PowerDownState::Awake: - return "Awake"; - case PowerDownState::AwakeForRefresh: - return "Awake for refresh"; - case PowerDownState::PDNActive: - return "PDN Active"; - case PowerDownState::PDNPrecharge: - return "PDN Precharged"; - case PowerDownState::PDNSelfRefresh: - return "PDN Self refresh"; - default: - return "unknown state"; - } -} +//inline std::string powerDownStateToString(PowerDownState powerDownState) +//{ +// switch (powerDownState) { +// case PowerDownState::Awake: +// return "Awake"; +// case PowerDownState::AwakeForRefresh: +// return "Awake for refresh"; +// case PowerDownState::PDNActive: +// return "PDN Active"; +// case PowerDownState::PDNPrecharge: +// return "PDN Precharged"; +// case PowerDownState::PDNSelfRefresh: +// return "PDN Self refresh"; +// default: +// return "unknown state"; +// } +//} -#endif // IPOWERDOWNMANAGER_H +//#endif // IPOWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp index d148c8c0..97c8bd30 100644 --- a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp @@ -1,63 +1,63 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// */ -#include "NoPowerDown.h" +//#include "NoPowerDown.h" -void NoPowerDown::triggerSleep(Bank /*bank*/, sc_time /*time*/) -{ - return; -} +//void NoPowerDown::triggerSleep(Bank /*bank*/, sc_time /*time*/) +//{ +// return; +//} -void NoPowerDown::sleep(Bank /*bank*/, sc_time /*time*/) -{ - return; -} +//void NoPowerDown::sleep(Bank /*bank*/, sc_time /*time*/) +//{ +// return; +//} -void NoPowerDown::wakeUp(Bank /*bank*/, sc_time /*time*/) -{ - return; -} +//void NoPowerDown::wakeUp(Bank /*bank*/, sc_time /*time*/) +//{ +// return; +//} -void NoPowerDown::wakeUpForRefresh(Bank /*bank*/, sc_time /*time*/) -{ - return; -} +//void NoPowerDown::wakeUpForRefresh(Bank /*bank*/, sc_time /*time*/) +//{ +// return; +//} -bool NoPowerDown::isInSelfRefresh(Bank /*bank*/) -{ - return false; -} +//bool NoPowerDown::isInSelfRefresh(Bank /*bank*/) +//{ +// return false; +//} diff --git a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h index 19a53403..4dd70adc 100644 --- a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h +++ b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h @@ -1,65 +1,65 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// */ -#ifndef NOPOWERDOWN_H -#define NOPOWERDOWN_H +//#ifndef NOPOWERDOWN_H +//#define NOPOWERDOWN_H -#include "PowerDownManager.h" -#include -#include "../../../common/dramExtensions.h" -#include "../scheduling/ScheduledCommand.h" +//#include "PowerDownManager.h" +//#include +//#include "../../../common/dramExtensions.h" +//#include "../scheduling/ScheduledCommand.h" -class NoPowerDown : public IPowerDownManager -{ -public: - NoPowerDown() {} - virtual ~NoPowerDown() {} +//class NoPowerDown : public IPowerDownManager +//{ +//public: +// NoPowerDown() {} +// virtual ~NoPowerDown() {} - virtual void triggerSleep(Bank bank, sc_time time) override; - virtual void sleep(Bank bank, sc_time time) override; +// virtual void triggerSleep(Bank bank, sc_time time) override; +// virtual void sleep(Bank bank, sc_time time) override; - virtual void wakeUp(Bank bank, sc_time time) override; - virtual void wakeUpForRefresh(Bank bank, sc_time time) override; +// virtual void wakeUp(Bank bank, sc_time time) override; +// virtual void wakeUpForRefresh(Bank bank, sc_time time) override; - virtual bool isInSelfRefresh(Bank bank) override; -}; +// virtual bool isInSelfRefresh(Bank bank) override; +//}; -#endif // NOPOWERDOWN_H +//#endif // NOPOWERDOWN_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp index 98377611..15ddf00a 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp @@ -1,220 +1,220 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Felipe S. Prado - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// * Felipe S. Prado +// */ -#include -#include -#include "PowerDownManager.h" -#include "../ControllerCore.h" -#include "../timingCalculations.h" -#include "../../../common/DebugManager.h" -#include -#include "../../../common/utils.h" +//#include +//#include +//#include "PowerDownManager.h" +//#include "../ControllerCore.h" +//#include "../timingCalculations.h" +//#include "../../../common/DebugManager.h" +//#include +//#include "../../../common/utils.h" -using namespace tlm; -using namespace std; +//using namespace tlm; +//using namespace std; -PowerDownManager::PowerDownManager(sc_module_name /*name*/, - ControllerCore &controller) : - controllerCore(controller) -{ - powerDownState = PowerDownState::Awake; - for (Bank bank : controller.getBanks()) { - setUpDummy(powerDownPayloads[bank], bank); - } - //controllerCore.controller.send(PDNTrigger, sc_time_stamp(), powerDownPayloads[Bank(0)]); -} +//PowerDownManager::PowerDownManager(sc_module_name /*name*/, +// ControllerCore &controller) : +// controllerCore(controller) +//{ +// powerDownState = PowerDownState::Awake; +// for (Bank bank : controller.getBanks()) { +// setUpDummy(powerDownPayloads[bank], bank); +// } +// //controllerCore.controller.send(PDNTrigger, sc_time_stamp(), powerDownPayloads[Bank(0)]); +//} -PowerDownManager::~PowerDownManager() -{ +//PowerDownManager::~PowerDownManager() +//{ -} +//} -void PowerDownManager::sleep(Bank /*bank*/, sc_time time) -{ - if (!canSleep() || isInPowerDown()) - return; +//void PowerDownManager::sleep(Bank /*bank*/, sc_time time) +//{ +// if (!canSleep() || isInPowerDown()) +// return; - PowerDownState state = powerDownState; +// PowerDownState state = powerDownState; - if (state == PowerDownState::Awake) { //coming from active - state = controllerCore.state->rowBufferStates->allRowBuffersAreClosed() ? - PowerDownState::PDNPrecharge : PowerDownState::PDNActive; - } else if (state == - PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down - sc_assert(controllerCore.state->rowBufferStates->allRowBuffersAreClosed()); +// if (state == PowerDownState::Awake) { //coming from active +// state = controllerCore.state->rowBufferStates->allRowBuffersAreClosed() ? +// PowerDownState::PDNPrecharge : PowerDownState::PDNActive; +// } else if (state == +// PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down +// sc_assert(controllerCore.state->rowBufferStates->allRowBuffersAreClosed()); - if (controllerCore.state->getLastCommand(Command::PDEA).getStart() - >= controllerCore.state->getLastCommand(Command::PDEP).getStart()) - state = PowerDownState::PDNPrecharge; - else { - state = PowerDownState::PDNSelfRefresh; - } - } +// if (controllerCore.state->getLastCommand(Command::PDEA).getStart() +// >= controllerCore.state->getLastCommand(Command::PDEP).getStart()) +// state = PowerDownState::PDNPrecharge; +// else { +// state = PowerDownState::PDNSelfRefresh; +// } +// } - Command cmd = IPowerDownManager::getSleepCommand(state); - ScheduledCommand pdn(cmd, time, - Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), - DramExtension::getExtension(powerDownPayloads[Bank(0)])); +// Command cmd = IPowerDownManager::getSleepCommand(state); +// ScheduledCommand pdn(cmd, time, +// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), +// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); +// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - if (state != PowerDownState::PDNSelfRefresh - && controllerCore.refreshManager->hasCollision(pdn)) { - return; - } else { - setPowerDownState(state); - sendPowerDownPayload(pdn); - } -} +// if (state != PowerDownState::PDNSelfRefresh +// && controllerCore.refreshManager->hasCollision(pdn)) { +// return; +// } else { +// setPowerDownState(state); +// sendPowerDownPayload(pdn); +// } +//} -void PowerDownManager::wakeUp(Bank bank, sc_time time) -{ - printDebugMessage("Waking up at " + time.to_string() + - " current power down state is " + powerDownStateToString(powerDownState)); +//void PowerDownManager::wakeUp(Bank bank, sc_time time) +//{ +// printDebugMessage("Waking up at " + time.to_string() + +// " current power down state is " + powerDownStateToString(powerDownState)); - if (isAwakeForRefresh()) { //Request enters system during Refresh - setPowerDownState(PowerDownState::Awake); - } else if (isInPowerDown()) { //Request wakes up power down - Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); - ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, - powerDownPayloads[Bank(0)]), - DramExtension::getExtension(powerDownPayloads[Bank(0)])); - controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); +// if (isAwakeForRefresh()) { //Request enters system during Refresh +// setPowerDownState(PowerDownState::Awake); +// } else if (isInPowerDown()) { //Request wakes up power down +// Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); +// ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, +// powerDownPayloads[Bank(0)]), +// DramExtension::getExtension(powerDownPayloads[Bank(0)])); +// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - if (cmd == Command::SREFEX) { - // Leaving Self Refresh. Plan the next refresh. - controllerCore.refreshManager->reInitialize(bank, pdn.getEnd()); - printDebugMessage("Waking up. Leaving Self Refresh at " + time.to_string() + - " next refresh planned to " + pdn.getEnd().to_string()); - } +// if (cmd == Command::SREFEX) { +// // Leaving Self Refresh. Plan the next refresh. +// controllerCore.refreshManager->reInitialize(bank, pdn.getEnd()); +// printDebugMessage("Waking up. Leaving Self Refresh at " + time.to_string() + +// " next refresh planned to " + pdn.getEnd().to_string()); +// } - setPowerDownState(PowerDownState::Awake); +// setPowerDownState(PowerDownState::Awake); - printDebugMessage("Sending power down exit command " + commandToString( - cmd) + " on all banks"); - sendPowerDownPayload(pdn); - } +// printDebugMessage("Sending power down exit command " + commandToString( +// cmd) + " on all banks"); +// sendPowerDownPayload(pdn); +// } - printDebugMessage("Awaken at " + time.to_string() + - " current power down state is " + powerDownStateToString(powerDownState)); -} +// printDebugMessage("Awaken at " + time.to_string() + +// " current power down state is " + powerDownStateToString(powerDownState)); +//} -void PowerDownManager::wakeUpForRefresh(Bank /*bank*/, sc_time time) -{ - printDebugMessage("Waking up for refresh at " + time.to_string() + - " current power down state is " + powerDownStateToString(powerDownState)); +//void PowerDownManager::wakeUpForRefresh(Bank /*bank*/, sc_time time) +//{ +// printDebugMessage("Waking up for refresh at " + time.to_string() + +// " current power down state is " + powerDownStateToString(powerDownState)); - if (isInPowerDown()) { - Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); - ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, - powerDownPayloads[Bank(0)]), - DramExtension::getExtension(powerDownPayloads[Bank(0)])); +// if (isInPowerDown()) { +// Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); +// ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, +// powerDownPayloads[Bank(0)]), +// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - setPowerDownState(PowerDownState::AwakeForRefresh); +// setPowerDownState(PowerDownState::AwakeForRefresh); - printDebugMessage("Sending power down exit command " + commandToString( - cmd) + " on all banks"); - sendPowerDownPayload(pdn); - } +// printDebugMessage("Sending power down exit command " + commandToString( +// cmd) + " on all banks"); +// sendPowerDownPayload(pdn); +// } - printDebugMessage("Awaken for refresh at " + time.to_string() + - " current power down state is " + powerDownStateToString(powerDownState)); -} +// printDebugMessage("Awaken for refresh at " + time.to_string() + +// " current power down state is " + powerDownStateToString(powerDownState)); +//} -void PowerDownManager::sendPowerDownPayload(ScheduledCommand &pdnToSend) -{ - controllerCore.state->bus.moveCommandToNextFreeSlot(pdnToSend); - for (size_t bank = 1; bank < controllerCore.getBanks().size(); bank++) { - tlm_generic_payload &payloadToSend = powerDownPayloads[bank]; +//void PowerDownManager::sendPowerDownPayload(ScheduledCommand &pdnToSend) +//{ +// controllerCore.state->bus.moveCommandToNextFreeSlot(pdnToSend); +// for (size_t bank = 1; bank < controllerCore.getBanks().size(); bank++) { +// tlm_generic_payload &payloadToSend = powerDownPayloads[bank]; - ScheduledCommand pdn(pdnToSend.getCommand(), pdnToSend.getStart(), - pdnToSend.getExecutionTime(), DramExtension::getExtension(payloadToSend)); - controllerCore.state->change(pdn); +// ScheduledCommand pdn(pdnToSend.getCommand(), pdnToSend.getStart(), +// pdnToSend.getExecutionTime(), DramExtension::getExtension(payloadToSend)); +// controllerCore.state->change(pdn); - } - controllerCore.state->change(pdnToSend); - controllerCore.controller.send(pdnToSend, powerDownPayloads[Bank(0)]); - printDebugMessage("Sending power down command " + commandToString( - pdnToSend.getCommand()) + " on bank " + to_string(pdnToSend.getBank().ID()) + - " start time " + pdnToSend.getStart().to_string() + " end time " + - pdnToSend.getEnd().to_string()); -} +// } +// controllerCore.state->change(pdnToSend); +// controllerCore.controller.send(pdnToSend, powerDownPayloads[Bank(0)]); +// printDebugMessage("Sending power down command " + commandToString( +// pdnToSend.getCommand()) + " on bank " + to_string(pdnToSend.getBank().ID()) + +// " start time " + pdnToSend.getStart().to_string() + " end time " + +// pdnToSend.getEnd().to_string()); +//} -void PowerDownManager::setPowerDownState(PowerDownState state) -{ - powerDownState = state; - printDebugMessage("Is now in state " + powerDownStateToString( - powerDownState) + " on all banks"); -} +//void PowerDownManager::setPowerDownState(PowerDownState state) +//{ +// powerDownState = state; +// printDebugMessage("Is now in state " + powerDownStateToString( +// powerDownState) + " on all banks"); +//} -bool PowerDownManager::isInPowerDown() -{ - return (powerDownState == PowerDownState::PDNActive - || powerDownState == PowerDownState::PDNPrecharge - || powerDownState == PowerDownState::PDNSelfRefresh); -} +//bool PowerDownManager::isInPowerDown() +//{ +// return (powerDownState == PowerDownState::PDNActive +// || powerDownState == PowerDownState::PDNPrecharge +// || powerDownState == PowerDownState::PDNSelfRefresh); +//} -bool PowerDownManager::canSleep() -{ - for (Bank bank : controllerCore.getBanks()) { - if (!controllerCore.numberOfPayloads[bank] == 0) - return false; - } - return true; -} +//bool PowerDownManager::canSleep() +//{ +// for (Bank bank : controllerCore.getBanks()) { +// if (!controllerCore.numberOfPayloads[bank] == 0) +// return false; +// } +// return true; +//} -bool PowerDownManager::isInSelfRefresh(Bank /*bank*/) -{ - return powerDownState == PowerDownState::PDNSelfRefresh; -} +//bool PowerDownManager::isInSelfRefresh(Bank /*bank*/) +//{ +// return powerDownState == PowerDownState::PDNSelfRefresh; +//} -bool PowerDownManager::isAwakeForRefresh() -{ - return powerDownState == PowerDownState::AwakeForRefresh; -} +//bool PowerDownManager::isAwakeForRefresh() +//{ +// return powerDownState == PowerDownState::AwakeForRefresh; +//} -void PowerDownManager::triggerSleep(Bank bank, sc_time time) -{ - sleep(bank, time); -} +//void PowerDownManager::triggerSleep(Bank bank, sc_time time) +//{ +// sleep(bank, time); +//} -void PowerDownManager::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} +//void PowerDownManager::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage(this->name(), message); +//} diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h index ee90629e..bd7ffd3d 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h @@ -1,71 +1,71 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// */ -#ifndef POWERDOWNMANAGER_H -#define POWERDOWNMANAGER_H +//#ifndef POWERDOWNMANAGER_H +//#define POWERDOWNMANAGER_H -#include "PowerDownManagerBankwise.h" +//#include "PowerDownManagerBankwise.h" -class ControllerCore; +//class ControllerCore; -class PowerDownManager: public IPowerDownManager, public sc_module -{ -public: - PowerDownManager(sc_module_name /*name*/, ControllerCore &controllerCore); - virtual ~PowerDownManager(); +//class PowerDownManager: public IPowerDownManager, public sc_module +//{ +//public: +// PowerDownManager(sc_module_name /*name*/, ControllerCore &controllerCore); +// virtual ~PowerDownManager(); - virtual void triggerSleep(Bank bank, sc_time time) override; - virtual void sleep(Bank /*bank*/, sc_time time) override; - virtual void wakeUp(Bank bank, sc_time time) override; - virtual void wakeUpForRefresh(Bank bank, sc_time time) override; - virtual bool isInSelfRefresh(Bank bank) override; +// virtual void triggerSleep(Bank bank, sc_time time) override; +// virtual void sleep(Bank /*bank*/, sc_time time) override; +// virtual void wakeUp(Bank bank, sc_time time) override; +// virtual void wakeUpForRefresh(Bank bank, sc_time time) override; +// virtual bool isInSelfRefresh(Bank bank) override; -protected: - void sendPowerDownPayload(ScheduledCommand &pdnToSend); - bool isInPowerDown(); - void setPowerDownState(PowerDownState state); - bool canSleep(); - bool isAwakeForRefresh(); +//protected: +// void sendPowerDownPayload(ScheduledCommand &pdnToSend); +// bool isInPowerDown(); +// void setPowerDownState(PowerDownState state); +// bool canSleep(); +// bool isAwakeForRefresh(); - PowerDownState powerDownState; - std::map powerDownPayloads; - ControllerCore &controllerCore; - void printDebugMessage(std::string message); -}; +// PowerDownState powerDownState; +// std::map powerDownPayloads; +// ControllerCore &controllerCore; +// void printDebugMessage(std::string message); +//}; -#endif // POWERDOWNMANAGER_H +//#endif // POWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp index 8ba7c0d2..4b9e125c 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp @@ -1,216 +1,216 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// */ -#include "PowerDownManager.h" -#include "../ControllerCore.h" -#include "../../../common/utils.h" -#include "../../../common/DebugManager.h" -#include "../timingCalculations.h" +//#include "PowerDownManager.h" +//#include "../ControllerCore.h" +//#include "../../../common/utils.h" +//#include "../../../common/DebugManager.h" +//#include "../timingCalculations.h" -using namespace tlm; +//using namespace tlm; -PowerDownManagerBankwise::PowerDownManagerBankwise(sc_module_name /*name*/, - ControllerCore &controllerCore) : controllerCore(controllerCore) -{ - for (Bank bank : controllerCore.getBanks()) { - setUpDummy(powerDownPayloads[bank], bank); - powerDownStates[bank] = PowerDownState::Awake; - //controllerCore.controller.send(PDNTrigger, sc_time_stamp(), powerDownPayloads[bank]); - } -} +//PowerDownManagerBankwise::PowerDownManagerBankwise(sc_module_name /*name*/, +// ControllerCore &controllerCore) : controllerCore(controllerCore) +//{ +// for (Bank bank : controllerCore.getBanks()) { +// setUpDummy(powerDownPayloads[bank], bank); +// powerDownStates[bank] = PowerDownState::Awake; +// //controllerCore.controller.send(PDNTrigger, sc_time_stamp(), powerDownPayloads[bank]); +// } +//} -void PowerDownManagerBankwise::sleep(Bank bank, sc_time time) -{ - if (!canSleep(bank) || isInPowerDown(bank)) - return; +//void PowerDownManagerBankwise::sleep(Bank bank, sc_time time) +//{ +// if (!canSleep(bank) || isInPowerDown(bank)) +// return; - tlm_generic_payload &payload = powerDownPayloads[bank]; +// tlm_generic_payload &payload = powerDownPayloads[bank]; - PowerDownState state = powerDownStates[bank]; - if (state == PowerDownState::Awake) { //coming from active - state = controllerCore.state->rowBufferStates->rowBufferIsOpen( - bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; - } else if (state == - PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down - sc_assert(!controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)); +// PowerDownState state = powerDownStates[bank]; +// if (state == PowerDownState::Awake) { //coming from active +// state = controllerCore.state->rowBufferStates->rowBufferIsOpen( +// bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; +// } else if (state == +// PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down +// sc_assert(!controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)); - if (controllerCore.state->getLastCommand(Command::PDEA, bank).getStart() - >= controllerCore.state->getLastCommand(Command::PDEP, bank).getStart()) - state = PowerDownState::PDNPrecharge; - else { - state = PowerDownState::PDNSelfRefresh; - } - } +// if (controllerCore.state->getLastCommand(Command::PDEA, bank).getStart() +// >= controllerCore.state->getLastCommand(Command::PDEP, bank).getStart()) +// state = PowerDownState::PDNPrecharge; +// else { +// state = PowerDownState::PDNSelfRefresh; +// } +// } - Command cmd = IPowerDownManager::getSleepCommand(state); - ScheduledCommand pdn(cmd, time, - Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), - DramExtension::getExtension(payload)); - controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); +// Command cmd = IPowerDownManager::getSleepCommand(state); +// ScheduledCommand pdn(cmd, time, +// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), +// DramExtension::getExtension(payload)); +// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - if (state != PowerDownState::PDNSelfRefresh - && controllerCore.refreshManager->hasCollision(pdn)) { - return; - } else { - setPowerDownState(state, bank); - sendPowerDownPayload(pdn); - } -} +// if (state != PowerDownState::PDNSelfRefresh +// && controllerCore.refreshManager->hasCollision(pdn)) { +// return; +// } else { +// setPowerDownState(state, bank); +// sendPowerDownPayload(pdn); +// } +//} -void PowerDownManagerBankwise::wakeUp(Bank bank, sc_time time) -{ - printDebugMessage("Waking up on bank " + to_string(bank.ID()) + " at " + - time.to_string() + " current power down state is " + powerDownStateToString( - powerDownStates[bank])); +//void PowerDownManagerBankwise::wakeUp(Bank bank, sc_time time) +//{ +// printDebugMessage("Waking up on bank " + to_string(bank.ID()) + " at " + +// time.to_string() + " current power down state is " + powerDownStateToString( +// powerDownStates[bank])); - if (isAwakeForRefresh(bank)) { - printDebugMessage("It was already awake for refresh on bank " + to_string( - bank.ID()) + " at " + time.to_string()); - setPowerDownState(PowerDownState::Awake, bank); - } else if (isInPowerDown(bank)) { - // Request wake up from power down. A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). - Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); - // Mount the command to be scheduled - ScheduledCommand pdnExit(pdnExitCmd, time, Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, - powerDownPayloads[bank]), DramExtension::getExtension(powerDownPayloads[bank])); - // Ensure that time constraints are respected - controllerCore.getCommandChecker(pdnExitCmd).delayToSatisfyConstraints(pdnExit); +// if (isAwakeForRefresh(bank)) { +// printDebugMessage("It was already awake for refresh on bank " + to_string( +// bank.ID()) + " at " + time.to_string()); +// setPowerDownState(PowerDownState::Awake, bank); +// } else if (isInPowerDown(bank)) { +// // Request wake up from power down. A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). +// Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); +// // Mount the command to be scheduled +// ScheduledCommand pdnExit(pdnExitCmd, time, Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, +// powerDownPayloads[bank]), DramExtension::getExtension(powerDownPayloads[bank])); +// // Ensure that time constraints are respected +// controllerCore.getCommandChecker(pdnExitCmd).delayToSatisfyConstraints(pdnExit); - if (pdnExitCmd == Command::SREFEX) { - // Leaving Self Refresh. Plan the next refresh. - controllerCore.refreshManager->reInitialize(bank, pdnExit.getEnd()); - printDebugMessage("Waking up. Leaving Self Refresh on Bank " + to_string( - bank.ID()) + " at " + time.to_string() + " next refresh planned to " + - pdnExit.getEnd().to_string()); - } +// if (pdnExitCmd == Command::SREFEX) { +// // Leaving Self Refresh. Plan the next refresh. +// controllerCore.refreshManager->reInitialize(bank, pdnExit.getEnd()); +// printDebugMessage("Waking up. Leaving Self Refresh on Bank " + to_string( +// bank.ID()) + " at " + time.to_string() + " next refresh planned to " + +// pdnExit.getEnd().to_string()); +// } - setPowerDownState(PowerDownState::Awake, bank); +// setPowerDownState(PowerDownState::Awake, bank); - printDebugMessage("Sending power down exit command " + commandToString( - pdnExitCmd) + " on bank " + to_string(bank.ID()) + " at " + time.to_string() + - " start time " + pdnExit.getStart().to_string() + " end time " + - pdnExit.getEnd().to_string()); - sendPowerDownPayload(pdnExit); - } +// printDebugMessage("Sending power down exit command " + commandToString( +// pdnExitCmd) + " on bank " + to_string(bank.ID()) + " at " + time.to_string() + +// " start time " + pdnExit.getStart().to_string() + " end time " + +// pdnExit.getEnd().to_string()); +// sendPowerDownPayload(pdnExit); +// } - printDebugMessage("Awaken on bank " + to_string(bank.ID()) + " at " + - time.to_string() + " current power down state is " + powerDownStateToString( - powerDownStates[bank])); -} +// printDebugMessage("Awaken on bank " + to_string(bank.ID()) + " at " + +// time.to_string() + " current power down state is " + powerDownStateToString( +// powerDownStates[bank])); +//} -void PowerDownManagerBankwise::wakeUpForRefresh(Bank bank, sc_time time) -{ - printDebugMessage("Waking up for refresh on bank " + to_string( - bank.ID()) + " at " + time.to_string() + " current power down state is " + - powerDownStateToString(powerDownStates[bank])); +//void PowerDownManagerBankwise::wakeUpForRefresh(Bank bank, sc_time time) +//{ +// printDebugMessage("Waking up for refresh on bank " + to_string( +// bank.ID()) + " at " + time.to_string() + " current power down state is " + +// powerDownStateToString(powerDownStates[bank])); - if (isInPowerDown(bank)) { - // A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). - Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); - // Get the execution time for this request - sc_time executionTime = Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, powerDownPayloads[bank]); - // Mount the command to be scheduled - ScheduledCommand pdnExit(pdnExitCmd, time, executionTime, - DramExtension::getExtension(powerDownPayloads[bank])); +// if (isInPowerDown(bank)) { +// // A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). +// Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); +// // Get the execution time for this request +// sc_time executionTime = Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, powerDownPayloads[bank]); +// // Mount the command to be scheduled +// ScheduledCommand pdnExit(pdnExitCmd, time, executionTime, +// DramExtension::getExtension(powerDownPayloads[bank])); - setPowerDownState(PowerDownState::AwakeForRefresh, bank); +// setPowerDownState(PowerDownState::AwakeForRefresh, bank); - printDebugMessage("Sending power down exit command " + commandToString( - pdnExitCmd) + " on bank " + to_string(bank.ID()) + " at " + time.to_string() + - " start time " + pdnExit.getStart().to_string() + " end time " + - pdnExit.getEnd().to_string()); - sendPowerDownPayload(pdnExit); - } +// printDebugMessage("Sending power down exit command " + commandToString( +// pdnExitCmd) + " on bank " + to_string(bank.ID()) + " at " + time.to_string() + +// " start time " + pdnExit.getStart().to_string() + " end time " + +// pdnExit.getEnd().to_string()); +// sendPowerDownPayload(pdnExit); +// } - printDebugMessage("Awaken for refresh on bank " + to_string( - bank.ID()) + " at " + time.to_string() + " current power down state is " + - powerDownStateToString(powerDownStates[bank])); -} +// printDebugMessage("Awaken for refresh on bank " + to_string( +// bank.ID()) + " at " + time.to_string() + " current power down state is " + +// powerDownStateToString(powerDownStates[bank])); +//} -bool PowerDownManagerBankwise::isInPowerDown(Bank bank) -{ - return isIn(powerDownStates[bank], { PowerDownState::PDNActive, PowerDownState::PDNPrecharge, PowerDownState::PDNSelfRefresh }); -} +//bool PowerDownManagerBankwise::isInPowerDown(Bank bank) +//{ +// return isIn(powerDownStates[bank], { PowerDownState::PDNActive, PowerDownState::PDNPrecharge, PowerDownState::PDNSelfRefresh }); +//} -bool PowerDownManagerBankwise::isInSelfRefresh(Bank bank) -{ - return powerDownStates[bank] == PowerDownState::PDNSelfRefresh; -} +//bool PowerDownManagerBankwise::isInSelfRefresh(Bank bank) +//{ +// return powerDownStates[bank] == PowerDownState::PDNSelfRefresh; +//} -bool PowerDownManagerBankwise::isAwakeForRefresh(Bank bank) -{ - return powerDownStates[bank] == PowerDownState::AwakeForRefresh; -} +//bool PowerDownManagerBankwise::isAwakeForRefresh(Bank bank) +//{ +// return powerDownStates[bank] == PowerDownState::AwakeForRefresh; +//} -bool PowerDownManagerBankwise::isAwake(Bank bank) -{ - return powerDownStates[bank] == PowerDownState::Awake; -} +//bool PowerDownManagerBankwise::isAwake(Bank bank) +//{ +// return powerDownStates[bank] == PowerDownState::Awake; +//} -void PowerDownManagerBankwise::setPowerDownState(PowerDownState state, - Bank bank) -{ - PowerDownState &bankstate = powerDownStates[bank]; - bankstate = state; - printDebugMessage("Is now in state " + powerDownStateToString( - state) + " on Bank " + to_string(bank.ID())); -} +//void PowerDownManagerBankwise::setPowerDownState(PowerDownState state, +// Bank bank) +//{ +// PowerDownState &bankstate = powerDownStates[bank]; +// bankstate = state; +// printDebugMessage("Is now in state " + powerDownStateToString( +// state) + " on Bank " + to_string(bank.ID())); +//} -void PowerDownManagerBankwise::sendPowerDownPayload(ScheduledCommand &pdn) -{ - controllerCore.state->bus.moveCommandToNextFreeSlot(pdn); - controllerCore.state->change(pdn); - printDebugMessage("Sending power down command " + commandToString( - pdn.getCommand()) + " on bank " + to_string(pdn.getBank().ID()) + " start time " - + pdn.getStart().to_string() + " end time " + pdn.getEnd().to_string()); - controllerCore.controller.send(pdn, powerDownPayloads[pdn.getBank()]); -} +//void PowerDownManagerBankwise::sendPowerDownPayload(ScheduledCommand &pdn) +//{ +// controllerCore.state->bus.moveCommandToNextFreeSlot(pdn); +// controllerCore.state->change(pdn); +// printDebugMessage("Sending power down command " + commandToString( +// pdn.getCommand()) + " on bank " + to_string(pdn.getBank().ID()) + " start time " +// + pdn.getStart().to_string() + " end time " + pdn.getEnd().to_string()); +// controllerCore.controller.send(pdn, powerDownPayloads[pdn.getBank()]); +//} -bool PowerDownManagerBankwise::canSleep(Bank bank) -{ - return controllerCore.numberOfPayloads[bank] == 0; -} +//bool PowerDownManagerBankwise::canSleep(Bank bank) +//{ +// return controllerCore.numberOfPayloads[bank] == 0; +//} -void PowerDownManagerBankwise::triggerSleep(Bank bank, sc_time time) -{ - sleep(bank, time); -} +//void PowerDownManagerBankwise::triggerSleep(Bank bank, sc_time time) +//{ +// sleep(bank, time); +//} -void PowerDownManagerBankwise::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} +//void PowerDownManagerBankwise::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage(this->name(), message); +//} diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h index 69382538..07d32ba1 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h @@ -1,86 +1,86 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// */ -#ifndef POWERDOWNMANAGERBANKWISE_H -#define POWERDOWNMANAGERBANKWISE_H +//#ifndef POWERDOWNMANAGERBANKWISE_H +//#define POWERDOWNMANAGERBANKWISE_H -#include -#include -#include -#include -#include "../../Command.h" -#include "../../../common/dramExtensions.h" -#include "../scheduling/ScheduledCommand.h" -#include "IPowerDownManager.h" +//#include +//#include +//#include +//#include +//#include "../../Command.h" +//#include "../../../common/dramExtensions.h" +//#include "../scheduling/ScheduledCommand.h" +//#include "IPowerDownManager.h" -class ControllerCore; +//class ControllerCore; -class PowerDownManagerBankwise : public sc_module, public IPowerDownManager -{ -public: - PowerDownManagerBankwise(sc_module_name /*name*/, - ControllerCore &controllerCore); - virtual ~PowerDownManagerBankwise() {} - virtual void triggerSleep(Bank bank, sc_time time) override; - virtual void sleep(Bank bank, sc_time time) override; - virtual void wakeUp(Bank bank, sc_time time) override; - virtual void wakeUpForRefresh(Bank bank, sc_time time) override; - virtual bool isInSelfRefresh(Bank bank) override; +//class PowerDownManagerBankwise : public sc_module, public IPowerDownManager +//{ +//public: +// PowerDownManagerBankwise(sc_module_name /*name*/, +// ControllerCore &controllerCore); +// virtual ~PowerDownManagerBankwise() {} +// virtual void triggerSleep(Bank bank, sc_time time) override; +// virtual void sleep(Bank bank, sc_time time) override; +// virtual void wakeUp(Bank bank, sc_time time) override; +// virtual void wakeUpForRefresh(Bank bank, sc_time time) override; +// virtual bool isInSelfRefresh(Bank bank) override; -protected: - virtual bool isInPowerDown(Bank bank); - virtual bool isAwake(Bank bank); - virtual bool isAwakeForRefresh(Bank bank); +//protected: +// virtual bool isInPowerDown(Bank bank); +// virtual bool isAwake(Bank bank); +// virtual bool isAwakeForRefresh(Bank bank); - ControllerCore &controllerCore; - std::map powerDownPayloads; - std::map powerDownStates; +// ControllerCore &controllerCore; +// std::map powerDownPayloads; +// std::map powerDownStates; - virtual bool canSleep(Bank bank); +// virtual bool canSleep(Bank bank); - void setPowerDownState(PowerDownState state, Bank bank); +// void setPowerDownState(PowerDownState state, Bank bank); - Command getWakeUpCommand(PowerDownState state); - Command getSleepCommand(PowerDownState state); +// Command getWakeUpCommand(PowerDownState state); +// Command getSleepCommand(PowerDownState state); - void sendPowerDownPayload(ScheduledCommand &pdn); +// void sendPowerDownPayload(ScheduledCommand &pdn); - void printDebugMessage(std::string message); -}; +// void printDebugMessage(std::string message); +//}; -#endif // POWERDOWNMANAGERBANKWISE_H +//#endif // POWERDOWNMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp index 02c6250e..65a9a45d 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp @@ -1,142 +1,142 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// * Felipe S. Prado +// */ -#include "PowerDownManagerTimeout.h" -#include "../ControllerCore.h" -#include "../../../common/utils.h" -#include "../../../common/DebugManager.h" -#include "../timingCalculations.h" +//#include "PowerDownManagerTimeout.h" +//#include "../ControllerCore.h" +//#include "../../../common/utils.h" +//#include "../../../common/DebugManager.h" +//#include "../timingCalculations.h" -using namespace tlm; +//using namespace tlm; -PowerDownManagerTimeout::PowerDownManagerTimeout(sc_module_name name, - ControllerCore &controllerCore): - PowerDownManager(name, controllerCore) -{ - //controllerCore.controller.send(PDNTrigger, Configuration::getInstance().getPowerDownTimeout(), powerDownPayloads[Bank(0)]); -} +//PowerDownManagerTimeout::PowerDownManagerTimeout(sc_module_name name, +// ControllerCore &controllerCore): +// PowerDownManager(name, controllerCore) +//{ +// //controllerCore.controller.send(PDNTrigger, Configuration::getInstance().getPowerDownTimeout(), powerDownPayloads[Bank(0)]); +//} -PowerDownManagerTimeout::~PowerDownManagerTimeout() -{ - // TODO Auto-generated destructor stub -} +//PowerDownManagerTimeout::~PowerDownManagerTimeout() +//{ +// // TODO Auto-generated destructor stub +//} -void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) -{ - bool timeoutTest; - if (!isAwakeForRefresh()) { - sc_time lastReadScheduled; - sc_time lastWriteScheduled; - if (Configuration::getInstance().OpenPagePolicy) { - lastReadScheduled = controllerCore.state->getLastCommand( - Command::RD).getEnd(); - lastWriteScheduled = controllerCore.state->getLastCommand( - Command::WR).getEnd(); - } else { - lastReadScheduled = controllerCore.state->getLastCommand( - Command::RDA).getEnd(); - lastWriteScheduled = controllerCore.state->getLastCommand( - Command::WRA).getEnd(); - } - sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); - timeoutTest = (time - lastScheduledCommand) >= - Configuration::getInstance().getPowerDownTimeout(); - } else { - timeoutTest = true; - } +//void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) +//{ +// bool timeoutTest; +// if (!isAwakeForRefresh()) { +// sc_time lastReadScheduled; +// sc_time lastWriteScheduled; +// if (Configuration::getInstance().OpenPagePolicy) { +// lastReadScheduled = controllerCore.state->getLastCommand( +// Command::RD).getEnd(); +// lastWriteScheduled = controllerCore.state->getLastCommand( +// Command::WR).getEnd(); +// } else { +// lastReadScheduled = controllerCore.state->getLastCommand( +// Command::RDA).getEnd(); +// lastWriteScheduled = controllerCore.state->getLastCommand( +// Command::WRA).getEnd(); +// } +// sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); +// timeoutTest = (time - lastScheduledCommand) >= +// Configuration::getInstance().getPowerDownTimeout(); +// } else { +// timeoutTest = true; +// } - //test_awakeForRefresh = false; +// //test_awakeForRefresh = false; - if ( canSleep() && !isInPowerDown() && timeoutTest) { +// if ( canSleep() && !isInPowerDown() && timeoutTest) { - PowerDownState newState; - if (Configuration::getInstance().PowerDownMode == EPowerDownMode::TimeoutPDN) { - newState = controllerCore.state->rowBufferStates->allRowBuffersAreClosed() ? - PowerDownState::PDNPrecharge : PowerDownState::PDNActive; - } else { // PowerDownMode == TimeoutSREF - if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { - ScheduledCommand prechargeAllMaster(Command::PREA, time, - Configuration::getInstance().memSpec->getExecutionTime( - Command::PREA, powerDownPayloads[Bank(0)]), - DramExtension::getExtension(powerDownPayloads[Bank(0)])); +// PowerDownState newState; +// if (Configuration::getInstance().PowerDownMode == EPowerDownMode::TimeoutPDN) { +// newState = controllerCore.state->rowBufferStates->allRowBuffersAreClosed() ? +// PowerDownState::PDNPrecharge : PowerDownState::PDNActive; +// } else { // PowerDownMode == TimeoutSREF +// if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { +// ScheduledCommand prechargeAllMaster(Command::PREA, time, +// Configuration::getInstance().memSpec->getExecutionTime( +// Command::PREA, powerDownPayloads[Bank(0)]), +// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - controllerCore.getCommandChecker( - Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); +// controllerCore.getCommandChecker( +// Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); - if (controllerCore.refreshManager->hasCollision(prechargeAllMaster)) { - return; - } else { - for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { - ScheduledCommand prechargeAll(Command::PREA, - prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), - powerDownPayloads[Bank(i)]); - controllerCore.state->change(prechargeAll); - } - controllerCore.state->change(prechargeAllMaster); - controllerCore.controller.send(prechargeAllMaster, powerDownPayloads[Bank(0)]); - } +// if (controllerCore.refreshManager->hasCollision(prechargeAllMaster)) { +// return; +// } else { +// for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { +// ScheduledCommand prechargeAll(Command::PREA, +// prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), +// powerDownPayloads[Bank(i)]); +// controllerCore.state->change(prechargeAll); +// } +// controllerCore.state->change(prechargeAllMaster); +// controllerCore.controller.send(prechargeAllMaster, powerDownPayloads[Bank(0)]); +// } - } +// } - newState = PowerDownState::PDNSelfRefresh; - } +// newState = PowerDownState::PDNSelfRefresh; +// } - Command cmd = IPowerDownManager::getSleepCommand(newState); - ScheduledCommand pdn(cmd, time, - Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), - DramExtension::getExtension(powerDownPayloads[Bank(0)])); +// Command cmd = IPowerDownManager::getSleepCommand(newState); +// ScheduledCommand pdn(cmd, time, +// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), +// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); +// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - if (controllerCore.refreshManager->hasCollision(pdn)) { - return; - } else { - setPowerDownState(newState); - sendPowerDownPayload(pdn); - } - } -} +// if (controllerCore.refreshManager->hasCollision(pdn)) { +// return; +// } else { +// setPowerDownState(newState); +// sendPowerDownPayload(pdn); +// } +// } +//} -void PowerDownManagerTimeout::triggerSleep(Bank /*bank*/, sc_time time) -{ - if (canSleep() && !isInPowerDown()) { - controllerCore.controller.send(PDNTrigger, - time + controllerCore.config.getPowerDownTimeout(), powerDownPayloads[Bank(0)]); - } -} +//void PowerDownManagerTimeout::triggerSleep(Bank /*bank*/, sc_time time) +//{ +// if (canSleep() && !isInPowerDown()) { +// controllerCore.controller.send(PDNTrigger, +// time + controllerCore.config.getPowerDownTimeout(), powerDownPayloads[Bank(0)]); +// } +//} diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h index d56675f5..48b36b0b 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h @@ -1,63 +1,63 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// * Felipe S. Prado +// */ -#ifndef POWERDOWNMANAGERTIMEOUT_H -#define POWERDOWNMANAGERTIMEOUT_H +//#ifndef POWERDOWNMANAGERTIMEOUT_H +//#define POWERDOWNMANAGERTIMEOUT_H -#include "PowerDownManager.h" -#include -#include "../../../common/dramExtensions.h" -#include "../scheduling/ScheduledCommand.h" -#include +//#include "PowerDownManager.h" +//#include +//#include "../../../common/dramExtensions.h" +//#include "../scheduling/ScheduledCommand.h" +//#include -class ControllerCore; +//class ControllerCore; -class PowerDownManagerTimeout: public PowerDownManager -{ -public: - PowerDownManagerTimeout(sc_module_name /*name*/, - ControllerCore &controllerCore); - virtual ~PowerDownManagerTimeout(); +//class PowerDownManagerTimeout: public PowerDownManager +//{ +//public: +// PowerDownManagerTimeout(sc_module_name /*name*/, +// ControllerCore &controllerCore); +// virtual ~PowerDownManagerTimeout(); - virtual void triggerSleep(Bank /*bank*/, sc_time time); - virtual void sleep(Bank /*bank*/, sc_time time); -}; +// virtual void triggerSleep(Bank /*bank*/, sc_time time); +// virtual void sleep(Bank /*bank*/, sc_time time); +//}; -#endif // POWERDOWNMANAGERTIMEOUT_H +//#endif // POWERDOWNMANAGERTIMEOUT_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp index 3f361355..83535fc6 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp @@ -1,135 +1,135 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// * Felipe S. Prado +// */ -#include "PowerDownManagerTimeoutBankwise.h" -#include "../ControllerCore.h" -#include "../../../common/utils.h" -#include "../../../common/DebugManager.h" -#include "../timingCalculations.h" +//#include "PowerDownManagerTimeoutBankwise.h" +//#include "../ControllerCore.h" +//#include "../../../common/utils.h" +//#include "../../../common/DebugManager.h" +//#include "../timingCalculations.h" -using namespace tlm; +//using namespace tlm; -PowerDownManagerTimeoutBankwise::PowerDownManagerTimeoutBankwise( - sc_module_name name, ControllerCore &controllerCore): - PowerDownManagerBankwise(name, controllerCore) -{ - /*for (Bank bank : controllerCore.getBanks()) - { - controllerCore.controller.send(PDNTrigger, controllerCore.config.getPowerDownTimeout(), powerDownPayloads[bank]); - }*/ -} +//PowerDownManagerTimeoutBankwise::PowerDownManagerTimeoutBankwise( +// sc_module_name name, ControllerCore &controllerCore): +// PowerDownManagerBankwise(name, controllerCore) +//{ +// /*for (Bank bank : controllerCore.getBanks()) +// { +// controllerCore.controller.send(PDNTrigger, controllerCore.config.getPowerDownTimeout(), powerDownPayloads[bank]); +// }*/ +//} -PowerDownManagerTimeoutBankwise::~PowerDownManagerTimeoutBankwise() -{ - // TODO Auto-generated destructor stub -} +//PowerDownManagerTimeoutBankwise::~PowerDownManagerTimeoutBankwise() +//{ +// // TODO Auto-generated destructor stub +//} -void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) -{ - bool timeoutTest; - if (!isAwakeForRefresh(bank)) { - sc_time lastReadScheduled; - sc_time lastWriteScheduled; - if (Configuration::getInstance().OpenPagePolicy) { - lastReadScheduled = controllerCore.state->getLastCommand(Command::RD, - bank).getEnd(); - lastWriteScheduled = controllerCore.state->getLastCommand(Command::WR, - bank).getEnd(); - } else { - lastReadScheduled = controllerCore.state->getLastCommand(Command::RDA, - bank).getEnd(); - lastWriteScheduled = controllerCore.state->getLastCommand(Command::WRA, - bank).getEnd(); - } - sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); - timeoutTest = (time - lastScheduledCommand) >= - Configuration::getInstance().getPowerDownTimeout(); - } else { - timeoutTest = true; - } +//void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) +//{ +// bool timeoutTest; +// if (!isAwakeForRefresh(bank)) { +// sc_time lastReadScheduled; +// sc_time lastWriteScheduled; +// if (Configuration::getInstance().OpenPagePolicy) { +// lastReadScheduled = controllerCore.state->getLastCommand(Command::RD, +// bank).getEnd(); +// lastWriteScheduled = controllerCore.state->getLastCommand(Command::WR, +// bank).getEnd(); +// } else { +// lastReadScheduled = controllerCore.state->getLastCommand(Command::RDA, +// bank).getEnd(); +// lastWriteScheduled = controllerCore.state->getLastCommand(Command::WRA, +// bank).getEnd(); +// } +// sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); +// timeoutTest = (time - lastScheduledCommand) >= +// Configuration::getInstance().getPowerDownTimeout(); +// } else { +// timeoutTest = true; +// } - if ( canSleep(bank) && !isInPowerDown(bank) && timeoutTest) { - PowerDownState newState; - if (Configuration::getInstance().PowerDownMode == EPowerDownMode::TimeoutPDN) { - newState = controllerCore.state->rowBufferStates->rowBufferIsOpen( - bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; - } else { // PowerDownMode == TimeoutSREF - if (controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)) { - ScheduledCommand precharge(Command::PRE, time, - Configuration::getInstance().memSpec->getExecutionTime(Command::PRE, powerDownPayloads[bank]), - DramExtension::getExtension(powerDownPayloads[bank])); +// if ( canSleep(bank) && !isInPowerDown(bank) && timeoutTest) { +// PowerDownState newState; +// if (Configuration::getInstance().PowerDownMode == EPowerDownMode::TimeoutPDN) { +// newState = controllerCore.state->rowBufferStates->rowBufferIsOpen( +// bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; +// } else { // PowerDownMode == TimeoutSREF +// if (controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)) { +// ScheduledCommand precharge(Command::PRE, time, +// Configuration::getInstance().memSpec->getExecutionTime(Command::PRE, powerDownPayloads[bank]), +// DramExtension::getExtension(powerDownPayloads[bank])); - controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( - precharge); +// controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( +// precharge); - if (controllerCore.refreshManager->hasCollision(precharge)) { - return; - } else { - controllerCore.state->change(precharge); - controllerCore.controller.send(precharge, powerDownPayloads[bank]); - } +// if (controllerCore.refreshManager->hasCollision(precharge)) { +// return; +// } else { +// controllerCore.state->change(precharge); +// controllerCore.controller.send(precharge, powerDownPayloads[bank]); +// } - } +// } - newState = PowerDownState::PDNSelfRefresh; - } +// newState = PowerDownState::PDNSelfRefresh; +// } - Command cmd = IPowerDownManager::getSleepCommand(newState); - ScheduledCommand pdn(cmd, time, - Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), - DramExtension::getExtension(powerDownPayloads[bank])); +// Command cmd = IPowerDownManager::getSleepCommand(newState); +// ScheduledCommand pdn(cmd, time, +// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), +// DramExtension::getExtension(powerDownPayloads[bank])); - controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); +// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - if (controllerCore.refreshManager->hasCollision(pdn)) { - return; - } else { - setPowerDownState(newState, bank); - sendPowerDownPayload(pdn); - } - } -} +// if (controllerCore.refreshManager->hasCollision(pdn)) { +// return; +// } else { +// setPowerDownState(newState, bank); +// sendPowerDownPayload(pdn); +// } +// } +//} -void PowerDownManagerTimeoutBankwise::triggerSleep(Bank bank, sc_time time) -{ - if (canSleep(bank) && !isInPowerDown(bank)) { - controllerCore.controller.send(PDNTrigger, - time + controllerCore.config.getPowerDownTimeout(), powerDownPayloads[bank]); - } -} +//void PowerDownManagerTimeoutBankwise::triggerSleep(Bank bank, sc_time time) +//{ +// if (canSleep(bank) && !isInPowerDown(bank)) { +// controllerCore.controller.send(PDNTrigger, +// time + controllerCore.config.getPowerDownTimeout(), powerDownPayloads[bank]); +// } +//} diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h index e4a43bed..440a482d 100644 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h +++ b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h @@ -1,63 +1,63 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// * Felipe S. Prado +// */ -#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H -#define POWERDOWNMANAGERTIMEOUTBANKWISE_H +//#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H +//#define POWERDOWNMANAGERTIMEOUTBANKWISE_H -#include "PowerDownManager.h" -#include -#include "../../../common/dramExtensions.h" -#include "../scheduling/ScheduledCommand.h" -#include +//#include "PowerDownManager.h" +//#include +//#include "../../../common/dramExtensions.h" +//#include "../scheduling/ScheduledCommand.h" +//#include -class ControllerCore; +//class ControllerCore; -class PowerDownManagerTimeoutBankwise: public PowerDownManagerBankwise -{ -public: - PowerDownManagerTimeoutBankwise(sc_module_name /*name*/, - ControllerCore &controllerCore); - virtual ~PowerDownManagerTimeoutBankwise(); +//class PowerDownManagerTimeoutBankwise: public PowerDownManagerBankwise +//{ +//public: +// PowerDownManagerTimeoutBankwise(sc_module_name /*name*/, +// ControllerCore &controllerCore); +// virtual ~PowerDownManagerTimeoutBankwise(); - virtual void triggerSleep(Bank bank, sc_time time); - virtual void sleep(Bank bank, sc_time time); -}; +// virtual void triggerSleep(Bank bank, sc_time time); +// virtual void sleep(Bank bank, sc_time time); +//}; -#endif // POWERDOWNMANAGERTIMEOUTBANKWISE_H +//#endif // POWERDOWNMANAGERTIMEOUTBANKWISE_H diff --git a/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h b/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h index 9b2f581b..54d535dc 100644 --- a/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h +++ b/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h @@ -1,66 +1,66 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Robert Gernhardt +// * Matthias Jung +// */ -#ifndef IREFRESHMANAGER_H -#define IREFRESHMANAGER_H +//#ifndef IREFRESHMANAGER_H +//#define IREFRESHMANAGER_H -#include -#include "../scheduling/ScheduledCommand.h" +//#include +//#include "../scheduling/ScheduledCommand.h" -// Flex. refresh (pull-in, postpone) -typedef enum { - ST_REFRESH = 0, - ST_PULLIN, - ST_POSTPONE, - ST_SKIP, - ST_BURST, - ST_ALIGN -} ref_fsm_state_t; +//// Flex. refresh (pull-in, postpone) +//typedef enum { +// ST_REFRESH = 0, +// ST_PULLIN, +// ST_POSTPONE, +// ST_SKIP, +// ST_BURST, +// ST_ALIGN +//} ref_fsm_state_t; -class IRefreshManager -{ -public: - virtual ~IRefreshManager() {}; - virtual bool hasCollision(const ScheduledCommand &command) = 0; - virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, - sc_time time) = 0; - virtual void reInitialize(Bank bank, sc_time time) = 0; - virtual bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) = 0; -}; +//class IRefreshManager +//{ +//public: +// virtual ~IRefreshManager() {}; +// virtual bool hasCollision(const ScheduledCommand &command) = 0; +// virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, +// sc_time time) = 0; +// virtual void reInitialize(Bank bank, sc_time time) = 0; +// virtual bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) = 0; +//}; -#endif // IREFRESHMANAGER_H +//#endif // IREFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp index 411cff75..ed8fee75 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RGR.cpp @@ -1,275 +1,275 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Éder F. Zulian - */ +///* +// * Copyright (c) 2017, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Author: Éder F. Zulian +// */ -#include +//#include -#include "RGR.h" -#include "../ControllerCore.h" -#include "../timingCalculations.h" -#include "../../../common/utils.h" +//#include "RGR.h" +//#include "../ControllerCore.h" +//#include "../timingCalculations.h" +//#include "../../../common/utils.h" -#define TRUE 1 -#define FALSE !(TRUE) -#define INITIAL_DISPLACEMENT FALSE +//#define TRUE 1 +//#define FALSE !(TRUE) +//#define INITIAL_DISPLACEMENT FALSE -using namespace std; +//using namespace std; -RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), - timing(ctrlcore.config.memSpec->refreshTimings[ccore.getBanks()[0]]) -{ - fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst; - bwl = ccore.config.BankwiseLogic; - ri = ccore.config.getRowInc(); - auto nr = ccore.config.memSpec->NumberOfRows; - auto nar = ccore.config.getNumAR(); - auto m = ccore.config.getRefMode(); - rpr = (nr / m) / nar; - assert(rpr > 0); - tREFIx = timing.tREFI / m; - trp = ccore.config.getTrpb(); - trcd = ccore.config.memSpec->tRCD; - postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone; - pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn; - maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m; - maxpullin = ccore.config.ControllerCoreRefMaxPulledIn * m; - for (Bank b : ccore.getBanks()) { - pulledin[b] = 0; - postponed[b] = 0; - currentState[b] = ST_REFRESH; - previousState[b] = ST_REFRESH; - nextState[b] = ST_REFRESH; - setUpDummy(rps[b], b); - } -#if INITIAL_DISPLACEMENT == TRUE - if (bwl) { - auto nbs = ccore.config.memSpec->NumberOfBanks; - for (Bank b : ccore.getBanks()) { - nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs; - } - } -#else - for (Bank b : ccore.getBanks()) { - nextPlannedRefreshs[b] = SC_ZERO_TIME; - } -#endif - if (bwl) { - for (Bank b : ccore.getBanks()) { - planNextRefresh(b, tREFIx, false); - } - } else { - planNextRefresh(ccore.getBanks()[0], tREFIx, false); - } -} +//RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), +// timing(ctrlcore.config.memSpec->refreshTimings[ccore.getBanks()[0]]) +//{ +// fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst; +// bwl = ccore.config.BankwiseLogic; +// ri = ccore.config.getRowInc(); +// auto nr = ccore.config.memSpec->NumberOfRows; +// auto nar = ccore.config.getNumAR(); +// auto m = ccore.config.getRefMode(); +// rpr = (nr / m) / nar; +// assert(rpr > 0); +// tREFIx = timing.tREFI / m; +// trp = ccore.config.getTrpb(); +// trcd = ccore.config.memSpec->tRCD; +// postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone; +// pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn; +// maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m; +// maxpullin = ccore.config.ControllerCoreRefMaxPulledIn * m; +// for (Bank b : ccore.getBanks()) { +// pulledin[b] = 0; +// postponed[b] = 0; +// currentState[b] = ST_REFRESH; +// previousState[b] = ST_REFRESH; +// nextState[b] = ST_REFRESH; +// setUpDummy(rps[b], b); +// } +//#if INITIAL_DISPLACEMENT == TRUE +// if (bwl) { +// auto nbs = ccore.config.memSpec->NumberOfBanks; +// for (Bank b : ccore.getBanks()) { +// nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs; +// } +// } +//#else +// for (Bank b : ccore.getBanks()) { +// nextPlannedRefreshs[b] = SC_ZERO_TIME; +// } +//#endif +// if (bwl) { +// for (Bank b : ccore.getBanks()) { +// planNextRefresh(b, tREFIx, false); +// } +// } else { +// planNextRefresh(ccore.getBanks()[0], tREFIx, false); +// } +//} -RGR::~RGR() -{ -} +//RGR::~RGR() +//{ +//} -bool RGR::hasCollision(const ScheduledCommand &cmd) -{ - Bank b = cmd.getBank(); - if (currentState[b] == ST_BURST) { - // A burst due to postponed refreshes shall not be interrupted. - return true; - } - return false; -} +//bool RGR::hasCollision(const ScheduledCommand &cmd) +//{ +// Bank b = cmd.getBank(); +// if (currentState[b] == ST_BURST) { +// // A burst due to postponed refreshes shall not be interrupted. +// return true; +// } +// return false; +//} -sc_time RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t) -{ - sc_assert(!isInvalidated(p, t)); - Bank b = DramExtension::getExtension(p).getBank(); - bool openBank = ccore.state->rowBufferStates->rowBufferIsOpen(b); - bool allClosed = ccore.state->rowBufferStates->allRowBuffersAreClosed(); - bool pre = bwl ? openBank : !allClosed; - sc_time trfcx = SC_ZERO_TIME; +//sc_time RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t) +//{ +// sc_assert(!isInvalidated(p, t)); +// Bank b = DramExtension::getExtension(p).getBank(); +// bool openBank = ccore.state->rowBufferStates->rowBufferIsOpen(b); +// bool allClosed = ccore.state->rowBufferStates->allRowBuffersAreClosed(); +// bool pre = bwl ? openBank : !allClosed; +// sc_time trfcx = SC_ZERO_TIME; - if (!bwl) { - for (Bank b : ccore.getBanks()) { - currentRefresh[b] = t; - } - } else { - currentRefresh[b] = t; - } +// if (!bwl) { +// for (Bank b : ccore.getBanks()) { +// currentRefresh[b] = t; +// } +// } else { +// currentRefresh[b] = t; +// } - if (pre) { - trfcx += trp; - if (bwl) { - if (ccore.config.getRGRBank(b.ID())) { - ccore.scheduleRequest(Command::PREB, rps[b]); - } - } else { - for (Bank b : ccore.getBanks()) { - auto rgrb = ccore.config.getRGRBank(b.ID()); - if (ccore.state->rowBufferStates->rowBufferIsOpen(b) && rgrb) { - ccore.scheduleRequest(Command::PREB, rps[Bank(b)]); - } - } - } - } +// if (pre) { +// trfcx += trp; +// if (bwl) { +// if (ccore.config.getRGRBank(b.ID())) { +// ccore.scheduleRequest(Command::PREB, rps[b]); +// } +// } else { +// for (Bank b : ccore.getBanks()) { +// auto rgrb = ccore.config.getRGRBank(b.ID()); +// if (ccore.state->rowBufferStates->rowBufferIsOpen(b) && rgrb) { +// ccore.scheduleRequest(Command::PREB, rps[Bank(b)]); +// } +// } +// } +// } - for (unsigned r = 0; r < rpr; r += ri) { - trfcx += trcd + trp; - if (bwl) { - if (ccore.config.getRGRBank(b.ID())) { - ccore.scheduleRequest(Command::ACTB, rps[b]); - ccore.scheduleRequest(Command::PREB, rps[b]); - } - DramExtension::getExtension(p).incrementRow(); - } else { - for (Bank b : ccore.getBanks()) { - if (ccore.config.getRGRBank(b.ID())) { - ccore.scheduleRequest(Command::ACTB, rps[b]); - ccore.scheduleRequest(Command::PREB, rps[b]); - } - DramExtension::getExtension(rps[b]).incrementRow(); - } - } - } +// for (unsigned r = 0; r < rpr; r += ri) { +// trfcx += trcd + trp; +// if (bwl) { +// if (ccore.config.getRGRBank(b.ID())) { +// ccore.scheduleRequest(Command::ACTB, rps[b]); +// ccore.scheduleRequest(Command::PREB, rps[b]); +// } +// DramExtension::getExtension(p).incrementRow(); +// } else { +// for (Bank b : ccore.getBanks()) { +// if (ccore.config.getRGRBank(b.ID())) { +// ccore.scheduleRequest(Command::ACTB, rps[b]); +// ccore.scheduleRequest(Command::PREB, rps[b]); +// } +// DramExtension::getExtension(rps[b]).incrementRow(); +// } +// } +// } - return trfcx; -} +// return trfcx; +//} -void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t) -{ - sc_time nrt; - sc_time trfcx; - Bank b = DramExtension::getExtension(p).getBank(); - bool preq = bwl ? ccore.hasPendingRequests(b) : ccore.hasPendingRequests(); - bool postpone = postponeEnabled && preq && (postponed[b] < maxpostpone); - bool pullIn = pullInEnabled && !preq && (pulledin[b] < maxpullin); - previousState[b] = currentState[b]; - currentState[b] = nextState[b]; - bool align = false; +//void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t) +//{ +// sc_time nrt; +// sc_time trfcx; +// Bank b = DramExtension::getExtension(p).getBank(); +// bool preq = bwl ? ccore.hasPendingRequests(b) : ccore.hasPendingRequests(); +// bool postpone = postponeEnabled && preq && (postponed[b] < maxpostpone); +// bool pullIn = pullInEnabled && !preq && (pulledin[b] < maxpullin); +// previousState[b] = currentState[b]; +// currentState[b] = nextState[b]; +// bool align = false; - switch (currentState[b]) { - case ST_REFRESH: - assert(pulledin[b] == 0 && postponed[b] == 0); - if (postpone) { - nrt = SC_ZERO_TIME; - nextState[b] = ST_POSTPONE; - } else if (pullIn) { - trfcx = doRefresh(p, t); - nrt = trfcx; - nextState[b] = ST_PULLIN; - } else { - doRefresh(p, t); - nrt = tREFIx; - nextState[b] = ST_REFRESH; - } - break; - case ST_PULLIN: - if (pullIn) { - trfcx = doRefresh(p, t); - pulledin[b]++; - nrt = trfcx; - nextState[b] = ST_PULLIN; - } else { - nrt = SC_ZERO_TIME; - nextState[b] = ST_ALIGN; - } - break; - case ST_SKIP: - if (pulledin[b] == 0) { - nrt = SC_ZERO_TIME; - nextState[b] = ST_REFRESH; - } else { - pulledin[b]--; - nrt = tREFIx; - nextState[b] = ST_SKIP; - } - break; - case ST_POSTPONE: - postponed[b]++; - if ((postponed[b] > maxpostpone) || (!preq && !fmb)) { - // Burst triggered by inactivity or max postpone value reached. - nrt = SC_ZERO_TIME; - nextState[b] = ST_BURST; - } else { - nrt = tREFIx; - nextState[b] = ST_POSTPONE; - } - break; - case ST_BURST: - doRefresh(p, t); - postponed[b]--; - if (postponed[b] == 0) { - nrt = SC_ZERO_TIME; - nextState[b] = ST_ALIGN; - } else { - nrt = SC_ZERO_TIME; - nextState[b] = ST_BURST; - } - break; - case ST_ALIGN: - nrt = tREFIx; - align = true; - if (previousState[b] == ST_PULLIN) { - nextState[b] = ST_SKIP; - } else { - nextState[b] = ST_REFRESH; - } - break; - default: - SC_REPORT_FATAL(this->name(), "RGR flex FSM invalid state."); - break; - } - planNextRefresh(bwl ? b : ccore.getBanks()[0], nrt, align); -} +// switch (currentState[b]) { +// case ST_REFRESH: +// assert(pulledin[b] == 0 && postponed[b] == 0); +// if (postpone) { +// nrt = SC_ZERO_TIME; +// nextState[b] = ST_POSTPONE; +// } else if (pullIn) { +// trfcx = doRefresh(p, t); +// nrt = trfcx; +// nextState[b] = ST_PULLIN; +// } else { +// doRefresh(p, t); +// nrt = tREFIx; +// nextState[b] = ST_REFRESH; +// } +// break; +// case ST_PULLIN: +// if (pullIn) { +// trfcx = doRefresh(p, t); +// pulledin[b]++; +// nrt = trfcx; +// nextState[b] = ST_PULLIN; +// } else { +// nrt = SC_ZERO_TIME; +// nextState[b] = ST_ALIGN; +// } +// break; +// case ST_SKIP: +// if (pulledin[b] == 0) { +// nrt = SC_ZERO_TIME; +// nextState[b] = ST_REFRESH; +// } else { +// pulledin[b]--; +// nrt = tREFIx; +// nextState[b] = ST_SKIP; +// } +// break; +// case ST_POSTPONE: +// postponed[b]++; +// if ((postponed[b] > maxpostpone) || (!preq && !fmb)) { +// // Burst triggered by inactivity or max postpone value reached. +// nrt = SC_ZERO_TIME; +// nextState[b] = ST_BURST; +// } else { +// nrt = tREFIx; +// nextState[b] = ST_POSTPONE; +// } +// break; +// case ST_BURST: +// doRefresh(p, t); +// postponed[b]--; +// if (postponed[b] == 0) { +// nrt = SC_ZERO_TIME; +// nextState[b] = ST_ALIGN; +// } else { +// nrt = SC_ZERO_TIME; +// nextState[b] = ST_BURST; +// } +// break; +// case ST_ALIGN: +// nrt = tREFIx; +// align = true; +// if (previousState[b] == ST_PULLIN) { +// nextState[b] = ST_SKIP; +// } else { +// nextState[b] = ST_REFRESH; +// } +// break; +// default: +// SC_REPORT_FATAL(this->name(), "RGR flex FSM invalid state."); +// break; +// } +// planNextRefresh(bwl ? b : ccore.getBanks()[0], nrt, align); +//} -void RGR::planNextRefresh(Bank b, sc_time t, bool align) -{ - if (align) { - nextPlannedRefreshs[b] = trunc(nextPlannedRefreshs[b].to_double() / - tREFIx.to_double()) * tREFIx; - } - nextPlannedRefreshs[b] += t; - ccore.controller.send(REFTrigger, nextPlannedRefreshs[b], rps[b]); -} +//void RGR::planNextRefresh(Bank b, sc_time t, bool align) +//{ +// if (align) { +// nextPlannedRefreshs[b] = trunc(nextPlannedRefreshs[b].to_double() / +// tREFIx.to_double()) * tREFIx; +// } +// nextPlannedRefreshs[b] += t; +// ccore.controller.send(REFTrigger, nextPlannedRefreshs[b], rps[b]); +//} -void RGR::reInitialize(Bank b, sc_time t) -{ - nextPlannedRefreshs[b] = clkAlign(t, Alignment::DOWN); - planNextRefresh(b, tREFIx, true); -} +//void RGR::reInitialize(Bank b, sc_time t) +//{ +// nextPlannedRefreshs[b] = clkAlign(t, Alignment::DOWN); +// planNextRefresh(b, tREFIx, true); +//} -bool RGR::isInvalidated(tlm::tlm_generic_payload &p, sc_time t) -{ - return nextPlannedRefreshs[DramExtension::getExtension(p).getBank()] > t; -} +//bool RGR::isInvalidated(tlm::tlm_generic_payload &p, sc_time t) +//{ +// return nextPlannedRefreshs[DramExtension::getExtension(p).getBank()] > t; +//} -void RGR::printDebugMessage(std::string msg) -{ - DebugManager::getInstance().printDebugMessage(this->name(), msg); -} +//void RGR::printDebugMessage(std::string msg) +//{ +// DebugManager::getInstance().printDebugMessage(this->name(), msg); +//} diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.h b/DRAMSys/library/src/controller/core/refresh/RGR.h index bfe8e444..00524a29 100644 --- a/DRAMSys/library/src/controller/core/refresh/RGR.h +++ b/DRAMSys/library/src/controller/core/refresh/RGR.h @@ -1,81 +1,81 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Éder F. Zulian - */ +///* +// * Copyright (c) 2017, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Author: Éder F. Zulian +// */ -#ifndef RGR_H -#define RGR_H +//#ifndef RGR_H +//#define RGR_H -#include "../../../common/dramExtensions.h" -#include "../configuration/MemSpec.h" -#include "IRefreshManager.h" +//#include "../../../common/dramExtensions.h" +//#include "../configuration/MemSpec.h" +//#include "IRefreshManager.h" -class ControllerCore; +//class ControllerCore; -class RGR : public IRefreshManager, public sc_module -{ -public: - RGR(sc_module_name, ControllerCore &ctrlcore); - virtual ~RGR(); - virtual bool hasCollision(const ScheduledCommand &cmd) override; - virtual void scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t) override; - void reInitialize(Bank bank, sc_time time) override; - bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override; -private: - bool fmb; - bool bwl; - unsigned int ri; - unsigned int rpr; - sc_time trp; - sc_time trcd; - sc_time tREFIx; - ControllerCore &ccore; - RefreshTiming &timing; - std::map rps; - std::map nextPlannedRefreshs; - std::map currentRefresh; - bool postponeEnabled; - bool pullInEnabled; - unsigned int maxpostpone; - unsigned int maxpullin; - std::map pulledin; - std::map postponed; - std::map currentState; - std::map previousState; - std::map nextState; - sc_time doRefresh(tlm::tlm_generic_payload &p, sc_time t); - void planNextRefresh(Bank b, sc_time t, bool align); - void printDebugMessage(std::string message); -}; +//class RGR : public IRefreshManager, public sc_module +//{ +//public: +// RGR(sc_module_name, ControllerCore &ctrlcore); +// virtual ~RGR(); +// virtual bool hasCollision(const ScheduledCommand &cmd) override; +// virtual void scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t) override; +// void reInitialize(Bank bank, sc_time time) override; +// bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override; +//private: +// bool fmb; +// bool bwl; +// unsigned int ri; +// unsigned int rpr; +// sc_time trp; +// sc_time trcd; +// sc_time tREFIx; +// ControllerCore &ccore; +// RefreshTiming &timing; +// std::map rps; +// std::map nextPlannedRefreshs; +// std::map currentRefresh; +// bool postponeEnabled; +// bool pullInEnabled; +// unsigned int maxpostpone; +// unsigned int maxpullin; +// std::map pulledin; +// std::map postponed; +// std::map currentState; +// std::map previousState; +// std::map nextState; +// sc_time doRefresh(tlm::tlm_generic_payload &p, sc_time t); +// void planNextRefresh(Bank b, sc_time t, bool align); +// void printDebugMessage(std::string message); +//}; -#endif // RGR_H +//#endif // RGR_H diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp index d71634bc..f229cb80 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp @@ -1,275 +1,275 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - * Ana Mativi - * Éder F. Zulian - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Robert Gernhardt +// * Matthias Jung +// * Felipe S. Prado +// * Ana Mativi +// * Éder F. Zulian +// */ -#include "RefreshManager.h" -#include "../ControllerCore.h" -#include "../timingCalculations.h" -#include "../../../common/utils.h" +//#include "RefreshManager.h" +//#include "../ControllerCore.h" +//#include "../timingCalculations.h" +//#include "../../../common/utils.h" -using namespace tlm; +//using namespace tlm; -RefreshManager::RefreshManager(sc_module_name, - ControllerCore &controller) : controllerCore(controller), - timing(controller.config.memSpec->refreshTimings[Bank(0)]) -{ - auto m = controllerCore.config.getRefMode(); - tREFIx = timing.tREFI / m; - tRFCx = timing.tRFC; - postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; - pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; - maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; - maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; - pulledin = 0; - postponed = 0; - currentState = ST_REFRESH; - previousState = ST_REFRESH; - nextState = ST_REFRESH; - nextPlannedRefresh = SC_ZERO_TIME; - for (Bank bank : controller.getBanks()) { - setUpDummy(refreshPayloads[bank], bank); - } - planNextRefresh(tREFIx, false); -} +//RefreshManager::RefreshManager(sc_module_name, +// ControllerCore &controller) : controllerCore(controller), +// timing(controller.config.memSpec->refreshTimings[Bank(0)]) +//{ +// auto m = controllerCore.config.getRefMode(); +// tREFIx = timing.tREFI / m; +// tRFCx = timing.tRFC; +// postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; +// pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; +// maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; +// maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; +// pulledin = 0; +// postponed = 0; +// currentState = ST_REFRESH; +// previousState = ST_REFRESH; +// nextState = ST_REFRESH; +// nextPlannedRefresh = SC_ZERO_TIME; +// for (Bank bank : controller.getBanks()) { +// setUpDummy(refreshPayloads[bank], bank); +// } +// planNextRefresh(tREFIx, false); +//} -RefreshManager::~RefreshManager() -{ -} +//RefreshManager::~RefreshManager() +//{ +//} -//Check if a command will be scheduled during the next refresh period -bool RefreshManager::hasCollision(const ScheduledCommand &command) -{ - bool collisionWithPreviousRefEnd = command.getStart() < - controllerCore.state->getLastCommand(Command::REFA).getEnd(); - bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh; - if (controllerCore.config.ControllerCoreRefEnablePostpone - && (postponed < maxpostpone)) { - // Flexible refresh is on and have "credits" to postpone. - // Then there will not be a collision with next refresh because - // nextPlannedRefresh will be updated. - collisionWithNextRefStart = false; - } - if (currentState == ST_BURST) { - // A burst due to postponed refreshes shall not be interrupted. - collisionWithNextRefStart = true; - } - return collisionWithPreviousRefEnd || collisionWithNextRefStart; -} +////Check if a command will be scheduled during the next refresh period +//bool RefreshManager::hasCollision(const ScheduledCommand &command) +//{ +// bool collisionWithPreviousRefEnd = command.getStart() < +// controllerCore.state->getLastCommand(Command::REFA).getEnd(); +// bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh; +// if (controllerCore.config.ControllerCoreRefEnablePostpone +// && (postponed < maxpostpone)) { +// // Flexible refresh is on and have "credits" to postpone. +// // Then there will not be a collision with next refresh because +// // nextPlannedRefresh will be updated. +// collisionWithNextRefStart = false; +// } +// if (currentState == ST_BURST) { +// // A burst due to postponed refreshes shall not be interrupted. +// collisionWithNextRefStart = true; +// } +// return collisionWithPreviousRefEnd || collisionWithNextRefStart; +//} -bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) -{ - sc_assert(!isInvalidated(payload, time)); - bool pre = false; - // If any row is open, precharge all. - if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { - pre = true; - ScheduledCommand prechargeAllMaster(Command::PREA, time, - Configuration::getInstance().memSpec->getExecutionTime( - Command::PREA, refreshPayloads[Bank(0)]), - refreshPayloads[Bank(0)]); - controllerCore.getCommandChecker( - Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); +//bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) +//{ +// sc_assert(!isInvalidated(payload, time)); +// bool pre = false; +// // If any row is open, precharge all. +// if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { +// pre = true; +// ScheduledCommand prechargeAllMaster(Command::PREA, time, +// Configuration::getInstance().memSpec->getExecutionTime( +// Command::PREA, refreshPayloads[Bank(0)]), +// refreshPayloads[Bank(0)]); +// controllerCore.getCommandChecker( +// Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); - for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { - ScheduledCommand prechargeAll(Command::PREA, - prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), - refreshPayloads[Bank(i)]); - controllerCore.state->change(prechargeAll); - } - controllerCore.state->change(prechargeAllMaster); - controllerCore.controller.send(prechargeAllMaster, refreshPayloads[Bank(0)]); - } +// for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { +// ScheduledCommand prechargeAll(Command::PREA, +// prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), +// refreshPayloads[Bank(i)]); +// controllerCore.state->change(prechargeAll); +// } +// controllerCore.state->change(prechargeAllMaster); +// controllerCore.controller.send(prechargeAllMaster, refreshPayloads[Bank(0)]); +// } - //Otherwise just the AutoRefresh command is scheduled. - ScheduledCommand refreshAllMaster(Command::REFA, time, - Configuration::getInstance().memSpec->getExecutionTime( - Command::REFA, refreshPayloads[Bank(0)]), - DramExtension::getExtension(refreshPayloads[Bank(0)])); - controllerCore.getCommandChecker( - Command::REFA).delayToSatisfyConstraints(refreshAllMaster); +// //Otherwise just the AutoRefresh command is scheduled. +// ScheduledCommand refreshAllMaster(Command::REFA, time, +// Configuration::getInstance().memSpec->getExecutionTime( +// Command::REFA, refreshPayloads[Bank(0)]), +// DramExtension::getExtension(refreshPayloads[Bank(0)])); +// controllerCore.getCommandChecker( +// Command::REFA).delayToSatisfyConstraints(refreshAllMaster); - for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { - ScheduledCommand refresh(Command::REFA, refreshAllMaster.getStart(), - refreshAllMaster.getExecutionTime(), refreshPayloads[Bank(i)]); - controllerCore.state->change(refresh); - DramExtension::getExtension(refreshPayloads[Bank(i)]).incrementRow(); - } - controllerCore.state->change(refreshAllMaster); - DramExtension::getExtension(refreshPayloads[Bank(0)]).incrementRow(); - controllerCore.controller.send(refreshAllMaster, refreshPayloads[Bank(0)]); - return pre; -} +// for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { +// ScheduledCommand refresh(Command::REFA, refreshAllMaster.getStart(), +// refreshAllMaster.getExecutionTime(), refreshPayloads[Bank(i)]); +// controllerCore.state->change(refresh); +// DramExtension::getExtension(refreshPayloads[Bank(i)]).incrementRow(); +// } +// controllerCore.state->change(refreshAllMaster); +// DramExtension::getExtension(refreshPayloads[Bank(0)]).incrementRow(); +// controllerCore.controller.send(refreshAllMaster, refreshPayloads[Bank(0)]); +// return pre; +//} -void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, - sc_time time) -{ - sc_time nextRefTiming; - bool pendingReq = controllerCore.hasPendingRequests(); - bool canPostpone = postponeEnabled && pendingReq && (postponed < maxpostpone); - bool canPullIn = pullInEnabled && !pendingReq && (pulledin < maxpullin); - previousState = currentState; - currentState = nextState; - bool align = false; - sc_time nrt; - bool pre; +//void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, +// sc_time time) +//{ +// sc_time nextRefTiming; +// bool pendingReq = controllerCore.hasPendingRequests(); +// bool canPostpone = postponeEnabled && pendingReq && (postponed < maxpostpone); +// bool canPullIn = pullInEnabled && !pendingReq && (pulledin < maxpullin); +// previousState = currentState; +// currentState = nextState; +// bool align = false; +// sc_time nrt; +// bool pre; - switch (currentState) { - case ST_REFRESH: - // Regular Refresh. It's possible to migrate from this to the flexible - // refresh states - assert(pulledin == 0 && postponed == 0); - if (canPostpone) { - nextRefTiming = SC_ZERO_TIME; - nextState = ST_POSTPONE; - } else if (canPullIn) { - pre = doRefresh(payload, time); - nrt = tRFCx; - if (pre) - nrt += controllerCore.config.memSpec->tRP_old; - nextRefTiming = nrt; - nextState = ST_PULLIN; - } else { - doRefresh(payload, time); - nextRefTiming = tREFIx; - nextState = ST_REFRESH; - } - break; - case ST_PULLIN: - // Pull-in a refresh. Try to pull-in refreshes as long it is possible. - if (canPullIn) { - pulledin++; - pre = doRefresh(payload, time); - nrt = tRFCx; - if (pre) - nrt += controllerCore.config.memSpec->tRP_old; - nextRefTiming = nrt; - nextState = ST_PULLIN; - } else { - nextRefTiming = SC_ZERO_TIME; - nextState = ST_ALIGN; - } - break; - case ST_SKIP: - // Skip the pulled-in refreshes. - if (pulledin == 0) { - nextRefTiming = SC_ZERO_TIME; - nextState = ST_REFRESH; - } else { - pulledin--; - nextRefTiming = tREFIx; - nextState = ST_SKIP; - } - break; - case ST_POSTPONE: - // Postpone Refresh. Delaying refreshes as long as there are pending - // requests and credits to postpone. Should be followed by a burst - // refresh. - postponed++; - if ((postponed > maxpostpone) || (!pendingReq - && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { - // Burst triggered by inactivity or max postpone value reached. - nextRefTiming = SC_ZERO_TIME; - nextState = ST_BURST; - } else { - nextRefTiming = tREFIx; - nextState = ST_POSTPONE; - } - break; - case ST_BURST: - // Burst postponed refreshes. - pre = doRefresh(payload, time); - postponed--; - if (postponed == 0) { - // All refreshes issued, next state will align to tREFIx - nextRefTiming = SC_ZERO_TIME; - nextState = ST_ALIGN; - } else { - nrt = tRFCx; - if (pre) - nrt += controllerCore.config.memSpec->tRP_old; - nextRefTiming = nrt; - nextState = ST_BURST; - } - break; - case ST_ALIGN: - // Align Refresh. Adjusting the timing so the next REF timing will be - // a in a time multiple of tREFIx - nextRefTiming = tREFIx; - align = true; - if (previousState == ST_PULLIN) { - nextState = ST_SKIP; - } else { - nextState = ST_REFRESH; - } - break; - default: - SC_REPORT_FATAL(this->name(), "Invalid state in flexible refresh FSM."); - break; - } - planNextRefresh(nextRefTiming, align); -} +// switch (currentState) { +// case ST_REFRESH: +// // Regular Refresh. It's possible to migrate from this to the flexible +// // refresh states +// assert(pulledin == 0 && postponed == 0); +// if (canPostpone) { +// nextRefTiming = SC_ZERO_TIME; +// nextState = ST_POSTPONE; +// } else if (canPullIn) { +// pre = doRefresh(payload, time); +// nrt = tRFCx; +// if (pre) +// nrt += controllerCore.config.memSpec->tRP_old; +// nextRefTiming = nrt; +// nextState = ST_PULLIN; +// } else { +// doRefresh(payload, time); +// nextRefTiming = tREFIx; +// nextState = ST_REFRESH; +// } +// break; +// case ST_PULLIN: +// // Pull-in a refresh. Try to pull-in refreshes as long it is possible. +// if (canPullIn) { +// pulledin++; +// pre = doRefresh(payload, time); +// nrt = tRFCx; +// if (pre) +// nrt += controllerCore.config.memSpec->tRP_old; +// nextRefTiming = nrt; +// nextState = ST_PULLIN; +// } else { +// nextRefTiming = SC_ZERO_TIME; +// nextState = ST_ALIGN; +// } +// break; +// case ST_SKIP: +// // Skip the pulled-in refreshes. +// if (pulledin == 0) { +// nextRefTiming = SC_ZERO_TIME; +// nextState = ST_REFRESH; +// } else { +// pulledin--; +// nextRefTiming = tREFIx; +// nextState = ST_SKIP; +// } +// break; +// case ST_POSTPONE: +// // Postpone Refresh. Delaying refreshes as long as there are pending +// // requests and credits to postpone. Should be followed by a burst +// // refresh. +// postponed++; +// if ((postponed > maxpostpone) || (!pendingReq +// && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { +// // Burst triggered by inactivity or max postpone value reached. +// nextRefTiming = SC_ZERO_TIME; +// nextState = ST_BURST; +// } else { +// nextRefTiming = tREFIx; +// nextState = ST_POSTPONE; +// } +// break; +// case ST_BURST: +// // Burst postponed refreshes. +// pre = doRefresh(payload, time); +// postponed--; +// if (postponed == 0) { +// // All refreshes issued, next state will align to tREFIx +// nextRefTiming = SC_ZERO_TIME; +// nextState = ST_ALIGN; +// } else { +// nrt = tRFCx; +// if (pre) +// nrt += controllerCore.config.memSpec->tRP_old; +// nextRefTiming = nrt; +// nextState = ST_BURST; +// } +// break; +// case ST_ALIGN: +// // Align Refresh. Adjusting the timing so the next REF timing will be +// // a in a time multiple of tREFIx +// nextRefTiming = tREFIx; +// align = true; +// if (previousState == ST_PULLIN) { +// nextState = ST_SKIP; +// } else { +// nextState = ST_REFRESH; +// } +// break; +// default: +// SC_REPORT_FATAL(this->name(), "Invalid state in flexible refresh FSM."); +// break; +// } +// planNextRefresh(nextRefTiming, align); +//} -void RefreshManager::planNextRefresh(sc_time nextRefTiming, bool align) -{ - if (align) { - nextPlannedRefresh = trunc(nextPlannedRefresh.to_double() / tREFIx.to_double()) - * tREFIx; - } - nextPlannedRefresh += nextRefTiming; - controllerCore.controller.send(REFTrigger, nextPlannedRefresh, - refreshPayloads[Bank(0)]); -} +//void RefreshManager::planNextRefresh(sc_time nextRefTiming, bool align) +//{ +// if (align) { +// nextPlannedRefresh = trunc(nextPlannedRefresh.to_double() / tREFIx.to_double()) +// * tREFIx; +// } +// nextPlannedRefresh += nextRefTiming; +// controllerCore.controller.send(REFTrigger, nextPlannedRefresh, +// refreshPayloads[Bank(0)]); +//} -void RefreshManager::reInitialize(Bank, sc_time time) -{ - nextPlannedRefresh = clkAlign(time, Alignment::DOWN); - planNextRefresh(tREFIx, true); -} +//void RefreshManager::reInitialize(Bank, sc_time time) +//{ +// nextPlannedRefresh = clkAlign(time, Alignment::DOWN); +// planNextRefresh(tREFIx, true); +//} -bool RefreshManager::isInvalidated(tlm::tlm_generic_payload &payload - __attribute__((unused)), sc_time time) -{ - return nextPlannedRefresh > time; -} +//bool RefreshManager::isInvalidated(tlm::tlm_generic_payload &payload +// __attribute__((unused)), sc_time time) +//{ +// return nextPlannedRefresh > time; +//} -void RefreshManager::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} +//void RefreshManager::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage(this->name(), message); +//} diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h index c89fa12b..b4f5c0fc 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h @@ -1,82 +1,82 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - * Éder F. Zulian - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Robert Gernhardt +// * Matthias Jung +// * Éder F. Zulian +// */ -#ifndef REFRESHMANAGER_H -#define REFRESHMANAGER_H +//#ifndef REFRESHMANAGER_H +//#define REFRESHMANAGER_H -#include "IRefreshManager.h" -#include "../configuration/MemSpec.h" +//#include "IRefreshManager.h" +//#include "../configuration/MemSpec.h" -class ControllerCore; +//class ControllerCore; -class RefreshManager : public IRefreshManager, public sc_module -{ -public: - RefreshManager(sc_module_name /*name*/, ControllerCore &controllerCore); - virtual ~RefreshManager(); +//class RefreshManager : public IRefreshManager, public sc_module +//{ +//public: +// RefreshManager(sc_module_name /*name*/, ControllerCore &controllerCore); +// virtual ~RefreshManager(); - virtual bool hasCollision(const ScheduledCommand &command) override; - virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, - sc_time time) override; - void reInitialize(Bank bank, sc_time time) override; - virtual bool isInvalidated(tlm::tlm_generic_payload &payload, - sc_time time) override; +// virtual bool hasCollision(const ScheduledCommand &command) override; +// virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, +// sc_time time) override; +// void reInitialize(Bank bank, sc_time time) override; +// virtual bool isInvalidated(tlm::tlm_generic_payload &payload, +// sc_time time) override; -private: - ControllerCore &controllerCore; - RefreshTiming &timing; - sc_time nextPlannedRefresh; - sc_time tREFIx; - sc_time tRFCx; - std::map refreshPayloads; - bool postponeEnabled; - bool pullInEnabled; - unsigned int maxpostpone; - unsigned int maxpullin; - unsigned int pulledin; - unsigned int postponed; - ref_fsm_state_t currentState; - ref_fsm_state_t previousState; - ref_fsm_state_t nextState; +//private: +// ControllerCore &controllerCore; +// RefreshTiming &timing; +// sc_time nextPlannedRefresh; +// sc_time tREFIx; +// sc_time tRFCx; +// std::map refreshPayloads; +// bool postponeEnabled; +// bool pullInEnabled; +// unsigned int maxpostpone; +// unsigned int maxpullin; +// unsigned int pulledin; +// unsigned int postponed; +// ref_fsm_state_t currentState; +// ref_fsm_state_t previousState; +// ref_fsm_state_t nextState; - bool doRefresh(tlm::tlm_generic_payload &payload, sc_time time); - void planNextRefresh(sc_time time, bool align); - void printDebugMessage(std::string message); -}; +// bool doRefresh(tlm::tlm_generic_payload &payload, sc_time time); +// void planNextRefresh(sc_time time, bool align); +// void printDebugMessage(std::string message); +//}; -#endif // REFRESHMANAGER_H +//#endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp index 1a44d304..373204c2 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp @@ -1,265 +1,265 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Éder F. Zulian - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// * Éder F. Zulian +// */ -#include "RefreshManagerBankwise.h" -#include "../ControllerCore.h" -#include "../timingCalculations.h" -#include "../../../common/utils.h" +//#include "RefreshManagerBankwise.h" +//#include "../ControllerCore.h" +//#include "../timingCalculations.h" +//#include "../../../common/utils.h" -using namespace std; +//using namespace std; -RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name, - ControllerCore &controller) : controllerCore(controller), - timing(controller.config.memSpec->refreshTimings[Bank(0)]) -{ - auto m = controllerCore.config.getRefMode(); - tREFIx = timing.tREFI / m; - tRFCx = timing.tRFC; - postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; - pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; - maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; - maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; - for (Bank bank : controller.getBanks()) { - nextPlannedRefreshs[bank] = SC_ZERO_TIME; - pulledin[bank] = 0; - postponed[bank] = 0; - currentState[bank] = ST_REFRESH; - previousState[bank] = ST_REFRESH; - nextState[bank] = ST_REFRESH; - setUpDummy(refreshPayloads[bank], bank); - planNextRefresh(bank, tREFIx, false); - } -} +//RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name, +// ControllerCore &controller) : controllerCore(controller), +// timing(controller.config.memSpec->refreshTimings[Bank(0)]) +//{ +// auto m = controllerCore.config.getRefMode(); +// tREFIx = timing.tREFI / m; +// tRFCx = timing.tRFC; +// postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; +// pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; +// maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; +// maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; +// for (Bank bank : controller.getBanks()) { +// nextPlannedRefreshs[bank] = SC_ZERO_TIME; +// pulledin[bank] = 0; +// postponed[bank] = 0; +// currentState[bank] = ST_REFRESH; +// previousState[bank] = ST_REFRESH; +// nextState[bank] = ST_REFRESH; +// setUpDummy(refreshPayloads[bank], bank); +// planNextRefresh(bank, tREFIx, false); +// } +//} -RefreshManagerBankwise::~RefreshManagerBankwise() -{ -} +//RefreshManagerBankwise::~RefreshManagerBankwise() +//{ +//} -bool RefreshManagerBankwise::hasCollision(const ScheduledCommand &command) -{ - Bank bank = command.getBank(); - bool collisionWithPreviousRefEnd = command.getStart() < - controllerCore.state->getLastCommand(Command::REFA, bank).getEnd(); - bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefreshs[bank]; - if (controllerCore.config.ControllerCoreRefEnablePostpone - && (postponed[bank] < maxpostpone)) { - // Flexible refresh is on and have "credits" to postpone. - // Then there will not be a collision with next refresh because - // nextPlannedRefresh will be updated. - collisionWithNextRefStart = false; - } - if (currentState[bank] == ST_BURST) { - // A burst due to postponed refreshes shall not be interrupted. - collisionWithNextRefStart = true; - } - return collisionWithPreviousRefEnd || collisionWithNextRefStart; -} +//bool RefreshManagerBankwise::hasCollision(const ScheduledCommand &command) +//{ +// Bank bank = command.getBank(); +// bool collisionWithPreviousRefEnd = command.getStart() < +// controllerCore.state->getLastCommand(Command::REFA, bank).getEnd(); +// bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefreshs[bank]; +// if (controllerCore.config.ControllerCoreRefEnablePostpone +// && (postponed[bank] < maxpostpone)) { +// // Flexible refresh is on and have "credits" to postpone. +// // Then there will not be a collision with next refresh because +// // nextPlannedRefresh will be updated. +// collisionWithNextRefStart = false; +// } +// if (currentState[bank] == ST_BURST) { +// // A burst due to postponed refreshes shall not be interrupted. +// collisionWithNextRefStart = true; +// } +// return collisionWithPreviousRefEnd || collisionWithNextRefStart; +//} -bool RefreshManagerBankwise::doRefresh(tlm::tlm_generic_payload &payload, - sc_time time) -{ - sc_assert(!isInvalidated(payload, time)); - bool pre = false; - tlm::tlm_generic_payload &refreshPayload = - refreshPayloads[DramExtension::getExtension(payload).getBank()]; - DramExtension &extension = DramExtension::getExtension(refreshPayload); +//bool RefreshManagerBankwise::doRefresh(tlm::tlm_generic_payload &payload, +// sc_time time) +//{ +// sc_assert(!isInvalidated(payload, time)); +// bool pre = false; +// tlm::tlm_generic_payload &refreshPayload = +// refreshPayloads[DramExtension::getExtension(payload).getBank()]; +// DramExtension &extension = DramExtension::getExtension(refreshPayload); - if (controllerCore.state->rowBufferStates->rowBufferIsOpen( - extension.getBank())) { - pre = true; - ScheduledCommand precharge(Command::PRE, time, - Configuration::getInstance().memSpec->getExecutionTime( - Command::PRE, refreshPayload), extension); - controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( - precharge); - controllerCore.state->change(precharge); - controllerCore.controller.send(precharge, refreshPayload); - } +// if (controllerCore.state->rowBufferStates->rowBufferIsOpen( +// extension.getBank())) { +// pre = true; +// ScheduledCommand precharge(Command::PRE, time, +// Configuration::getInstance().memSpec->getExecutionTime( +// Command::PRE, refreshPayload), extension); +// controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( +// precharge); +// controllerCore.state->change(precharge); +// controllerCore.controller.send(precharge, refreshPayload); +// } - ScheduledCommand refresh(Command::REFA, time, - Configuration::getInstance().memSpec->getExecutionTime( - Command::REFA, refreshPayload), extension); - controllerCore.getCommandChecker( - Command::REFA).delayToSatisfyConstraints(refresh); - controllerCore.state->change(refresh); - extension.incrementRow(); - controllerCore.controller.send(refresh, refreshPayload); - return pre; -} +// ScheduledCommand refresh(Command::REFA, time, +// Configuration::getInstance().memSpec->getExecutionTime( +// Command::REFA, refreshPayload), extension); +// controllerCore.getCommandChecker( +// Command::REFA).delayToSatisfyConstraints(refresh); +// controllerCore.state->change(refresh); +// extension.incrementRow(); +// controllerCore.controller.send(refresh, refreshPayload); +// return pre; +//} -void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, - sc_time time) -{ - sc_time nextRefTiming; - Bank bank = DramExtension::getExtension(payload).getBank(); - bool pendingReq = controllerCore.hasPendingRequests(bank); - bool canPostpone = postponeEnabled && pendingReq - && (postponed[bank] < maxpostpone); - bool canPullIn = pullInEnabled && !pendingReq && (pulledin[bank] < maxpullin); - previousState[bank] = currentState[bank]; - currentState[bank] = nextState[bank]; - bool align = false; - sc_time nrt; - bool pre; +//void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, +// sc_time time) +//{ +// sc_time nextRefTiming; +// Bank bank = DramExtension::getExtension(payload).getBank(); +// bool pendingReq = controllerCore.hasPendingRequests(bank); +// bool canPostpone = postponeEnabled && pendingReq +// && (postponed[bank] < maxpostpone); +// bool canPullIn = pullInEnabled && !pendingReq && (pulledin[bank] < maxpullin); +// previousState[bank] = currentState[bank]; +// currentState[bank] = nextState[bank]; +// bool align = false; +// sc_time nrt; +// bool pre; - switch (currentState[bank]) { - case ST_REFRESH: - // Regular Refresh. It's possible to migrate from this to the flexible - // refresh states - assert(pulledin[bank] == 0 && postponed[bank] == 0); - if (canPostpone) { - nextRefTiming = SC_ZERO_TIME; - nextState[bank] = ST_POSTPONE; - } else if (canPullIn) { - pre = doRefresh(payload, time); - nrt = tRFCx; - if (pre) - nrt += controllerCore.config.memSpec->tRP_old; - nextRefTiming = nrt; - nextState[bank] = ST_PULLIN; - } else { - doRefresh(payload, time); - nextRefTiming = tREFIx; - nextState[bank] = ST_REFRESH; - } - break; - case ST_PULLIN: - // Pull-in a refresh. Try to pull-in refreshes as long it is possible. - if (canPullIn) { - pulledin[bank]++; - pre = doRefresh(payload, time); - nrt = tRFCx; - if (pre) - nrt += controllerCore.config.memSpec->tRP_old; - nextRefTiming = nrt; - nextState[bank] = ST_PULLIN; - } else { - nextRefTiming = SC_ZERO_TIME; - nextState[bank] = ST_ALIGN; - } - break; - case ST_SKIP: - // Skip the pulled-in refreshes. - if (pulledin[bank] == 0) { - nextRefTiming = SC_ZERO_TIME; - nextState[bank] = ST_REFRESH; - } else { - pulledin[bank]--; - nextRefTiming = tREFIx; - nextState[bank] = ST_SKIP; - } - break; - case ST_POSTPONE: - // Postpone Refresh. Delaying refreshes as long as there are pending - // requests and credits to postpone. Should be followed by a burst - // refresh. - postponed[bank]++; - if ((postponed[bank] > maxpostpone) || (!pendingReq - && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { - // Burst triggered by inactivity or max postpone value reached. - nextRefTiming = SC_ZERO_TIME; - nextState[bank] = ST_BURST; - } else { - nextRefTiming = tREFIx; - nextState[bank] = ST_POSTPONE; - } - break; +// switch (currentState[bank]) { +// case ST_REFRESH: +// // Regular Refresh. It's possible to migrate from this to the flexible +// // refresh states +// assert(pulledin[bank] == 0 && postponed[bank] == 0); +// if (canPostpone) { +// nextRefTiming = SC_ZERO_TIME; +// nextState[bank] = ST_POSTPONE; +// } else if (canPullIn) { +// pre = doRefresh(payload, time); +// nrt = tRFCx; +// if (pre) +// nrt += controllerCore.config.memSpec->tRP_old; +// nextRefTiming = nrt; +// nextState[bank] = ST_PULLIN; +// } else { +// doRefresh(payload, time); +// nextRefTiming = tREFIx; +// nextState[bank] = ST_REFRESH; +// } +// break; +// case ST_PULLIN: +// // Pull-in a refresh. Try to pull-in refreshes as long it is possible. +// if (canPullIn) { +// pulledin[bank]++; +// pre = doRefresh(payload, time); +// nrt = tRFCx; +// if (pre) +// nrt += controllerCore.config.memSpec->tRP_old; +// nextRefTiming = nrt; +// nextState[bank] = ST_PULLIN; +// } else { +// nextRefTiming = SC_ZERO_TIME; +// nextState[bank] = ST_ALIGN; +// } +// break; +// case ST_SKIP: +// // Skip the pulled-in refreshes. +// if (pulledin[bank] == 0) { +// nextRefTiming = SC_ZERO_TIME; +// nextState[bank] = ST_REFRESH; +// } else { +// pulledin[bank]--; +// nextRefTiming = tREFIx; +// nextState[bank] = ST_SKIP; +// } +// break; +// case ST_POSTPONE: +// // Postpone Refresh. Delaying refreshes as long as there are pending +// // requests and credits to postpone. Should be followed by a burst +// // refresh. +// postponed[bank]++; +// if ((postponed[bank] > maxpostpone) || (!pendingReq +// && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { +// // Burst triggered by inactivity or max postpone value reached. +// nextRefTiming = SC_ZERO_TIME; +// nextState[bank] = ST_BURST; +// } else { +// nextRefTiming = tREFIx; +// nextState[bank] = ST_POSTPONE; +// } +// break; - case ST_BURST: - // Burst postponed refreshes. - pre = doRefresh(payload, time); - postponed[bank]--; - if (postponed[bank] == 0) { - // All refreshes issued, next state will align to tREFIx - nextRefTiming = SC_ZERO_TIME; - nextState[bank] = ST_ALIGN; - } else { - nrt = tRFCx; - if (pre) - nrt += controllerCore.config.memSpec->tRP_old; - nextRefTiming = nrt; - nextState[bank] = ST_BURST; - } - break; - case ST_ALIGN: - // Align Refresh. Adjusting the timing so the next REF timing will be - // a in a time multiple of tREFIx - nextRefTiming = tREFIx; - align = true; - if (previousState[bank] == ST_PULLIN) { - nextState[bank] = ST_SKIP; - } else { - nextState[bank] = ST_REFRESH; - } - break; - default: - SC_REPORT_FATAL(this->name(), "Invalid state in bw flex. ref. FSM."); - break; - } - planNextRefresh(bank, nextRefTiming, align); -} +// case ST_BURST: +// // Burst postponed refreshes. +// pre = doRefresh(payload, time); +// postponed[bank]--; +// if (postponed[bank] == 0) { +// // All refreshes issued, next state will align to tREFIx +// nextRefTiming = SC_ZERO_TIME; +// nextState[bank] = ST_ALIGN; +// } else { +// nrt = tRFCx; +// if (pre) +// nrt += controllerCore.config.memSpec->tRP_old; +// nextRefTiming = nrt; +// nextState[bank] = ST_BURST; +// } +// break; +// case ST_ALIGN: +// // Align Refresh. Adjusting the timing so the next REF timing will be +// // a in a time multiple of tREFIx +// nextRefTiming = tREFIx; +// align = true; +// if (previousState[bank] == ST_PULLIN) { +// nextState[bank] = ST_SKIP; +// } else { +// nextState[bank] = ST_REFRESH; +// } +// break; +// default: +// SC_REPORT_FATAL(this->name(), "Invalid state in bw flex. ref. FSM."); +// break; +// } +// planNextRefresh(bank, nextRefTiming, align); +//} -void RefreshManagerBankwise::planNextRefresh(Bank bank, sc_time nextRefTiming, - bool align) -{ - if (align) { - nextPlannedRefreshs[bank] = trunc(nextPlannedRefreshs[bank].to_double() / - tREFIx.to_double()) * tREFIx; - } - nextPlannedRefreshs[bank] += nextRefTiming; - controllerCore.controller.send(REFTrigger, nextPlannedRefreshs[bank], - refreshPayloads[bank]); -} +//void RefreshManagerBankwise::planNextRefresh(Bank bank, sc_time nextRefTiming, +// bool align) +//{ +// if (align) { +// nextPlannedRefreshs[bank] = trunc(nextPlannedRefreshs[bank].to_double() / +// tREFIx.to_double()) * tREFIx; +// } +// nextPlannedRefreshs[bank] += nextRefTiming; +// controllerCore.controller.send(REFTrigger, nextPlannedRefreshs[bank], +// refreshPayloads[bank]); +//} -void RefreshManagerBankwise::reInitialize(Bank bank, sc_time time) -{ - nextPlannedRefreshs[bank] = clkAlign(time, Alignment::DOWN); - planNextRefresh(bank, tREFIx, true); -} +//void RefreshManagerBankwise::reInitialize(Bank bank, sc_time time) +//{ +// nextPlannedRefreshs[bank] = clkAlign(time, Alignment::DOWN); +// planNextRefresh(bank, tREFIx, true); +//} -bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload &payload, - sc_time time) -{ - return nextPlannedRefreshs[DramExtension::getExtension(payload).getBank()] > - time; -} +//bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload &payload, +// sc_time time) +//{ +// return nextPlannedRefreshs[DramExtension::getExtension(payload).getBank()] > +// time; +//} -void RefreshManagerBankwise::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} +//void RefreshManagerBankwise::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage(this->name(), message); +//} diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h index a4728f4e..bf094bfc 100644 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h @@ -1,83 +1,83 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Éder F. Zulian - */ +///* +// * Copyright (c) 2015, University of Kaiserslautern +// * All rights reserved. +// * +// * Redistribution and use in source and binary forms, with or without +// * modification, are permitted provided that the following conditions are +// * met: +// * +// * 1. Redistributions of source code must retain the above copyright notice, +// * this list of conditions and the following disclaimer. +// * +// * 2. Redistributions in binary form must reproduce the above copyright +// * notice, this list of conditions and the following disclaimer in the +// * documentation and/or other materials provided with the distribution. +// * +// * 3. Neither the name of the copyright holder nor the names of its +// * contributors may be used to endorse or promote products derived from +// * this software without specific prior written permission. +// * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// * +// * Authors: +// * Janik Schlemminger +// * Matthias Jung +// * Éder F. Zulian +// */ -#ifndef REFRESHMANAGERBANKWISE_H -#define REFRESHMANAGERBANKWISE_H +//#ifndef REFRESHMANAGERBANKWISE_H +//#define REFRESHMANAGERBANKWISE_H -//#include "../../../common/dramExtension.h" -#include "IRefreshManager.h" -#include "../configuration/MemSpec.h" +////#include "../../../common/dramExtension.h" +//#include "IRefreshManager.h" +//#include "../configuration/MemSpec.h" -class ControllerCore; +//class ControllerCore; -class RefreshManagerBankwise : public IRefreshManager, public sc_module -{ -public: - RefreshManagerBankwise(sc_module_name /*name*/, ControllerCore &controllerCore); - virtual ~RefreshManagerBankwise(); +//class RefreshManagerBankwise : public IRefreshManager, public sc_module +//{ +//public: +// RefreshManagerBankwise(sc_module_name /*name*/, ControllerCore &controllerCore); +// virtual ~RefreshManagerBankwise(); - virtual bool hasCollision(const ScheduledCommand &command) override; - virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, - sc_time time) override; - void reInitialize(Bank bank, sc_time time) override; - bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override; +// virtual bool hasCollision(const ScheduledCommand &command) override; +// virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, +// sc_time time) override; +// void reInitialize(Bank bank, sc_time time) override; +// bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override; -private: - ControllerCore &controllerCore; - RefreshTiming &timing; - std::map nextPlannedRefreshs; - sc_time tREFIx; - sc_time tRFCx; - std::map refreshPayloads; - bool postponeEnabled; - bool pullInEnabled; - unsigned int maxpostpone; - unsigned int maxpullin; - std::map pulledin; - std::map postponed; - std::map currentState; - std::map previousState; - std::map nextState; +//private: +// ControllerCore &controllerCore; +// RefreshTiming &timing; +// std::map nextPlannedRefreshs; +// sc_time tREFIx; +// sc_time tRFCx; +// std::map refreshPayloads; +// bool postponeEnabled; +// bool pullInEnabled; +// unsigned int maxpostpone; +// unsigned int maxpullin; +// std::map pulledin; +// std::map postponed; +// std::map currentState; +// std::map previousState; +// std::map nextState; - bool doRefresh(tlm::tlm_generic_payload &payload, sc_time time); - void planNextRefresh(Bank bank, sc_time time, bool align); - void printDebugMessage(std::string message); -}; +// bool doRefresh(tlm::tlm_generic_payload &payload, sc_time time); +// void planNextRefresh(Bank bank, sc_time time, bool align); +// void printDebugMessage(std::string message); +//}; -#endif // REFRESHMANAGERBANKWISE_H +//#endif // REFRESHMANAGERBANKWISE_H From cd5b5cb423f84597e32580acc071a1caa719be2e Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Sat, 20 Jul 2019 15:53:30 +0200 Subject: [PATCH 025/183] Included new controller classes. --- DRAMSys/library/library.pro | 10 ++++- .../library/src/controller/BankMachine.cpp | 13 +++++++ DRAMSys/library/src/controller/BankMachine.h | 32 ++++++++++++++++ DRAMSys/library/src/controller/CommandMux.cpp | 22 +++++++++++ DRAMSys/library/src/controller/CommandMux.h | 27 +++++++++++++ .../library/src/controller/ControllerNew.cpp | 36 ++++++++++++++++++ .../library/src/controller/ControllerNew.h | 38 +++++++++++++++++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 31 ++++++++------- DRAMSys/library/src/simulation/DRAMSys.h | 4 +- 9 files changed, 196 insertions(+), 17 deletions(-) create mode 100644 DRAMSys/library/src/controller/BankMachine.cpp create mode 100644 DRAMSys/library/src/controller/BankMachine.h create mode 100644 DRAMSys/library/src/controller/CommandMux.cpp create mode 100644 DRAMSys/library/src/controller/CommandMux.h create mode 100644 DRAMSys/library/src/controller/ControllerNew.cpp create mode 100644 DRAMSys/library/src/controller/ControllerNew.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 188d67ef..c40e2e8a 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -149,7 +149,10 @@ SOURCES += \ src/simulation/DramWideIO.cpp \ src/controller/core/scheduling/checker/CheckerDDR3.cpp \ src/controller/core/configuration/MemSpec.cpp \ - src/controller/core/scheduling/checker/CheckerDDR3New.cpp + src/controller/core/scheduling/checker/CheckerDDR3New.cpp \ + src/controller/BankMachine.cpp \ + src/controller/CommandMux.cpp \ + src/controller/ControllerNew.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -232,7 +235,10 @@ HEADERS += \ src/simulation/DramWideIO.h \ src/controller/core/scheduling/checker/CheckerDDR3.h \ src/controller/GenericController.h \ - src/controller/core/scheduling/checker/CheckerDDR3New.h + src/controller/core/scheduling/checker/CheckerDDR3New.h \ + src/controller/BankMachine.h \ + src/controller/CommandMux.h \ + src/controller/ControllerNew.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp new file mode 100644 index 00000000..f0ea3287 --- /dev/null +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -0,0 +1,13 @@ +#include "BankMachine.h" +#include "Command.h" + +BankMachine::BankMachine(ControllerNew &controller) : + currentPayload(nullptr), + currentState(BmState::Precharged), + currentRow(Row(0)), + nextCommand(Command::NOP), + earliestTime(SC_ZERO_TIME), + controller(controller) +{ + +} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h new file mode 100644 index 00000000..8a573e63 --- /dev/null +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -0,0 +1,32 @@ +#ifndef BANKMACHINE_H +#define BANKMACHINE_H + +#include +#include +#include "../common/dramExtensions.h" +#include "Command.h" + +using namespace tlm; + +class ControllerNew; + +enum class BmState +{ + Precharged, + Activated +}; + +class BankMachine +{ +public: + BankMachine(ControllerNew &); +private: + tlm_generic_payload *currentPayload; + BmState currentState; + Row currentRow; + Command nextCommand; + sc_time earliestTime; + ControllerNew &controller; +}; + +#endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp new file mode 100644 index 00000000..9129e9de --- /dev/null +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -0,0 +1,22 @@ +#include "CommandMux.h" +#include "core/configuration/Configuration.h" + +CommandMux::CommandMux(sc_module_name name, ControllerNew &controller) : + sc_module(name), + controller(controller), + state("CommandMux", &Configuration::getInstance()), + checker(Configuration::getInstance(), state) +{ + SC_METHOD(compute); + sensitive << triggerEvent; +} + +void CommandMux::triggerAtTime(sc_time triggerTime) +{ + triggerEvent.notify(triggerTime); +} + +void CommandMux::compute() +{ + +} diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h new file mode 100644 index 00000000..b06118b3 --- /dev/null +++ b/DRAMSys/library/src/controller/CommandMux.h @@ -0,0 +1,27 @@ +#ifndef COMMANDMUX_H +#define COMMANDMUX_H + +#include +#include +#include "ControllerState.h" +#include "core/scheduling/checker/CheckerDDR3New.h" + +using namespace tlm; + +class ControllerNew; + +class CommandMux : public sc_module +{ +public: + CommandMux(sc_module_name, ControllerNew &); + SC_HAS_PROCESS(CommandMux); + void triggerAtTime(sc_time triggerTime); +private: + void compute(); + sc_event triggerEvent; + ControllerState state; + CheckerDDR3New checker; + ControllerNew &controller; +}; + +#endif // COMMANDMUX_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp new file mode 100644 index 00000000..b036602f --- /dev/null +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -0,0 +1,36 @@ +#include "ControllerNew.h" +#include "core/configuration/Configuration.h" +#include "scheduler/FifoStrict.h" + +ControllerNew::ControllerNew(sc_module_name name) : + sc_module(name), commandMux("CommandMux", *this) +{ + tSocket.register_nb_transport_fw(this, &ControllerNew::nb_transport_fw); + tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg); + iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw); + + for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = std::unique_ptr(new BankMachine(*this)); +} + +ControllerNew::~ControllerNew() +{ +} + +tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) +{ + +} + +unsigned int ControllerNew::transport_dbg(__attribute__((unused)) tlm_generic_payload &trans) +{ + SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); + return 0; +} + +tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) +{ + +} diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h new file mode 100644 index 00000000..c7b22c8c --- /dev/null +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -0,0 +1,38 @@ +#ifndef CONTROLLERNEW_H +#define CONTROLLERNEW_H + +#include +#include +#include +#include +#include +#include "../common/dramExtensions.h" +#include "BankMachine.h" +#include "CommandMux.h" +#include "scheduler/IScheduler.h" + +using namespace tlm; + +class ControllerNew : public sc_module +{ +public: + ControllerNew(sc_module_name); + SC_HAS_PROCESS(ControllerNew); + ~ControllerNew(); + + tlm_utils::simple_target_socket tSocket; + tlm_utils::simple_initiator_socket iSocket; + +private: + tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay); + unsigned int transport_dbg(tlm_generic_payload &trans); + tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay); + + std::map> bankMachines; + CommandMux commandMux; + IScheduler *scheduler; +}; + +#endif // CONTROLLERNEW_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index a472c40f..335cdfaf 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -58,6 +58,7 @@ #include "DramDDR3.h" #include "DramDDR4.h" #include "DramWideIO.h" +#include "../controller/ControllerNew.h" using namespace std; @@ -247,17 +248,19 @@ void DRAMSys::instantiateModules(const string &traceName, // Create DRAM std::string memoryType = Configuration::getInstance().memSpec->MemoryType; - for (size_t i = 0; - i < Configuration::getInstance().NumberOfMemChannels; - i++) { + for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) + { std::string str = "controller" + std::to_string(i); - GenericController *controller; - if (recordingEnabled) - controller = new RecordableController(str.c_str(), tlmRecorders[i]); - else - controller = new Controller(str.c_str()); - controllers.push_back(controller); +// GenericController *controller; +// if (recordingEnabled) +// controller = new RecordableController(str.c_str(), tlmRecorders[i]); +// else +// controller = new Controller(str.c_str()); +// controllers.push_back(controller); + + ControllerNew *controller = new ControllerNew(str.c_str()); + newControllers.push_back(controller); str = "dram" + std::to_string(i); Dram *dram; @@ -315,15 +318,15 @@ void DRAMSys::bindSockets() i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind( - controllers[i]->tSocket); - controllers[i]->iSocket.bind(drams[i]->tSocket); + newControllers[i]->tSocket); + newControllers[i]->iSocket.bind(drams[i]->tSocket); } } else { for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) { - arbiter->iSocket.bind(controllers[i]->tSocket); - controllers[i]->iSocket.bind(drams[i]->tSocket); + arbiter->iSocket.bind(newControllers[i]->tSocket); + newControllers[i]->iSocket.bind(drams[i]->tSocket); } } } @@ -351,7 +354,7 @@ DRAMSys::~DRAMSys() delete tlmChecker; } - for (auto controller : controllers) { + for (auto controller : newControllers) { delete controller; } } diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index cd4a8fbc..7123e4ad 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -53,6 +53,7 @@ #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" #include "../controller/GenericController.h" +#include "../controller/ControllerNew.h" class DRAMSys : public sc_module { @@ -88,7 +89,8 @@ private: // All transactions pass through the same arbiter Arbiter *arbiter; // Each DRAM unit has a controller - std::vector controllers; + std::vector newControllers; + //std::vector controllers; // TODO: Each DRAM has a reorder buffer (check this!) ReorderBuffer *reorder; From 9204a88a2870bff1dc6a116dfc3b7c3b1c78f7c3 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 20 Jul 2019 23:32:37 +0200 Subject: [PATCH 026/183] Included some functionality, included scheduler. --- DRAMSys/library/library.pro | 6 +- .../library/src/controller/BankMachine.cpp | 13 ++- DRAMSys/library/src/controller/BankMachine.h | 16 ++-- DRAMSys/library/src/controller/CommandMux.cpp | 21 ++--- DRAMSys/library/src/controller/CommandMux.h | 11 +-- .../library/src/controller/ControllerNew.cpp | 92 ++++++++++++++++++- .../library/src/controller/ControllerNew.h | 32 ++++++- .../library/src/controller/SchedulerNew.cpp | 25 +++++ DRAMSys/library/src/controller/SchedulerNew.h | 22 +++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- 10 files changed, 196 insertions(+), 44 deletions(-) create mode 100644 DRAMSys/library/src/controller/SchedulerNew.cpp create mode 100644 DRAMSys/library/src/controller/SchedulerNew.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index c40e2e8a..adae5930 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -152,7 +152,8 @@ SOURCES += \ src/controller/core/scheduling/checker/CheckerDDR3New.cpp \ src/controller/BankMachine.cpp \ src/controller/CommandMux.cpp \ - src/controller/ControllerNew.cpp + src/controller/ControllerNew.cpp \ + src/controller/SchedulerNew.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -238,7 +239,8 @@ HEADERS += \ src/controller/core/scheduling/checker/CheckerDDR3New.h \ src/controller/BankMachine.h \ src/controller/CommandMux.h \ - src/controller/ControllerNew.h + src/controller/ControllerNew.h \ + src/controller/SchedulerNew.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index f0ea3287..dda0cd81 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -1,13 +1,12 @@ #include "BankMachine.h" #include "Command.h" -BankMachine::BankMachine(ControllerNew &controller) : - currentPayload(nullptr), - currentState(BmState::Precharged), - currentRow(Row(0)), - nextCommand(Command::NOP), - earliestTime(SC_ZERO_TIME), - controller(controller) +BankMachine::BankMachine(ControllerNew *controller) : controller(controller) { } + +void BankMachine::setResultReady(sc_time time) +{ + resultReady = time; +} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 8a573e63..130bb0d7 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -19,14 +19,16 @@ enum class BmState class BankMachine { public: - BankMachine(ControllerNew &); + BankMachine(ControllerNew *); + void setResultReady(sc_time); private: - tlm_generic_payload *currentPayload; - BmState currentState; - Row currentRow; - Command nextCommand; - sc_time earliestTime; - ControllerNew &controller; + tlm_generic_payload *currentPayload = nullptr; + BmState currentState = BmState::Precharged; + Row currentRow = Row(0); + Command nextCommand = Command::NOP; + sc_time timeToSchedule = SC_ZERO_TIME; + sc_time resultReady = SC_ZERO_TIME; + ControllerNew *controller; }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 9129e9de..0f5db035 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -1,22 +1,19 @@ #include "CommandMux.h" #include "core/configuration/Configuration.h" -CommandMux::CommandMux(sc_module_name name, ControllerNew &controller) : - sc_module(name), +CommandMux::CommandMux(ControllerNew *controller) : controller(controller), state("CommandMux", &Configuration::getInstance()), - checker(Configuration::getInstance(), state) -{ - SC_METHOD(compute); - sensitive << triggerEvent; -} - -void CommandMux::triggerAtTime(sc_time triggerTime) -{ - triggerEvent.notify(triggerTime); -} + checker(Configuration::getInstance(), state) {} +/* void CommandMux::compute() { + // Handling of backpressure from / to arbiter!!! + /* END_RESP from arbiter: check for successful transaction, remove payload from response queue, numberOfPayloads-- + * END_RD / END_WR from DRAM: check for successful transaction, move payload from BM to response queue, send result to arbiter (delay??) + * BEGIN_REQ from arbiter: check for transaction, move to scheduler map + * Trigger by BM: get transactions from all BM, choose one, send one, change state on BM, postpone all BM to next point in time } +*/ diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h index b06118b3..9312e57b 100644 --- a/DRAMSys/library/src/controller/CommandMux.h +++ b/DRAMSys/library/src/controller/CommandMux.h @@ -10,18 +10,17 @@ using namespace tlm; class ControllerNew; -class CommandMux : public sc_module +class CommandMux { public: - CommandMux(sc_module_name, ControllerNew &); + CommandMux(ControllerNew *); SC_HAS_PROCESS(CommandMux); - void triggerAtTime(sc_time triggerTime); + void triggerEventAtTime(sc_time triggerTime); + void triggerEventQueueAtTime(sc_time triggerTime); private: - void compute(); - sc_event triggerEvent; ControllerState state; CheckerDDR3New checker; - ControllerNew &controller; + ControllerNew *controller; }; #endif // COMMANDMUX_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index b036602f..4c41219c 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -1,29 +1,64 @@ #include "ControllerNew.h" #include "core/configuration/Configuration.h" #include "scheduler/FifoStrict.h" +#include "../common/dramExtensions.h" +#include "../common/protocol.h" -ControllerNew::ControllerNew(sc_module_name name) : - sc_module(name), commandMux("CommandMux", *this) +ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : + sc_module(name), tlmRecorder(tlmRecorder), debugManager(&DebugManager::getInstance()) { + SC_METHOD(control); + sensitive << triggerEvent << triggerEventQueue; + tSocket.register_nb_transport_fw(this, &ControllerNew::nb_transport_fw); tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg); iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = std::unique_ptr(new BankMachine(*this)); + bankMachines[Bank(bankID)] = new BankMachine(this); + commandMux = new CommandMux(this); + scheduler = new SchedulerNew(); } ControllerNew::~ControllerNew() { + tlmRecorder->closeConnection(); + for (auto it : bankMachines) + delete it.second; + delete commandMux; + delete scheduler; } tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { + sc_time notDelay = delay; + if (phase == BEGIN_REQ) + { + notDelay += Configuration::getInstance().memSpec->clk; + payloadToAcquire = &trans; + } + else if (phase = END_RESP) + { + // FIXME: synchronization! + notDelay += Configuration::getInstance().memSpec->clk; + payloadToRelease = &trans; + } + else + { + SC_REPORT_FATAL(0, + "Front-end PEQ in controller wrapper was triggered with unknown phase"); + } + + printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + + notDelay.to_string()); + triggerEventQueue.notify(notDelay); + + return TLM_ACCEPTED; } -unsigned int ControllerNew::transport_dbg(__attribute__((unused)) tlm_generic_payload &trans) +unsigned int ControllerNew::transport_dbg(tlm_generic_payload &trans) { SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); return 0; @@ -31,6 +66,55 @@ unsigned int ControllerNew::transport_dbg(__attribute__((unused)) tlm_generic_pa tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) +{ + // only for END_RD and END_WR + if (phase == END_RD || phase == END_WR) + { + printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + + delay.to_string()); + Bank bank = DramExtension::getExtension(trans).getBank(); + sc_time triggerTime = sc_time_stamp() + delay; + bankMachines[bank]->setResultReady(triggerTime); + triggerEventQueueAtTime(triggerTime); + } + return TLM_ACCEPTED; +} + +void ControllerNew::printDebugMessage(string message) +{ + debugManager->printDebugMessage(name(), message); +} + +void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) +{ + sc_time recTime = delay + sc_time_stamp(); + + unsigned int thr = DramExtension::getExtension(trans).getThread().ID(); + unsigned int ch = DramExtension::getExtension(trans).getChannel().ID(); + unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID(); + unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); + unsigned int row = DramExtension::getExtension(trans).getRow().ID(); + unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); + + printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( + bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + + to_string(col) + " at " + recTime.to_string()); + + tlmRecorder->recordPhase(trans, phase, recTime); +} + +void ControllerNew::triggerEventAtTime(sc_time triggerTime) +{ + triggerEvent.notify(triggerTime); +} + +void ControllerNew::triggerEventQueueAtTime(sc_time triggerTime) +{ + triggerEventQueue.notify(triggerTime); +} + +void ControllerNew::control() { } diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index c7b22c8c..5210a2d2 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -2,6 +2,7 @@ #define CONTROLLERNEW_H #include +#include #include #include #include @@ -9,30 +10,51 @@ #include "../common/dramExtensions.h" #include "BankMachine.h" #include "CommandMux.h" -#include "scheduler/IScheduler.h" +#include "SchedulerNew.h" +#include "../common/TlmRecorder.h" +#include "../common/DebugManager.h" using namespace tlm; +class SchedulerNew; + class ControllerNew : public sc_module { public: - ControllerNew(sc_module_name); + ControllerNew(sc_module_name, TlmRecorder *); SC_HAS_PROCESS(ControllerNew); ~ControllerNew(); tlm_utils::simple_target_socket tSocket; tlm_utils::simple_initiator_socket iSocket; + void triggerEventAtTime(sc_time triggerTime); + void triggerEventQueueAtTime(sc_time triggerTime); + private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); unsigned int transport_dbg(tlm_generic_payload &trans); tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); + void printDebugMessage(string message); + void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay); - std::map> bankMachines; - CommandMux commandMux; - IScheduler *scheduler; + unsigned numberOfPayloads = 0; + tlm_generic_payload *payloadToAcquire = nullptr; + tlm_generic_payload *payloadToRelease = nullptr; + std::queue responseQueue; + + std::map bankMachines; + CommandMux *commandMux; + SchedulerNew *scheduler; + + TlmRecorder *tlmRecorder; + DebugManager *debugManager; + + void control(); + sc_event triggerEvent; + sc_event_queue triggerEventQueue; }; #endif // CONTROLLERNEW_H diff --git a/DRAMSys/library/src/controller/SchedulerNew.cpp b/DRAMSys/library/src/controller/SchedulerNew.cpp new file mode 100644 index 00000000..7f3d5df3 --- /dev/null +++ b/DRAMSys/library/src/controller/SchedulerNew.cpp @@ -0,0 +1,25 @@ +#include "SchedulerNew.h" +#include "../common/DebugManager.h" + +void SchedulerNew::storeRequest(tlm_generic_payload *payload) +{ + Bank bank = DramExtension::getExtension(payload).getBank(); + buffer[bank].emplace_back(payload); +} + +tlm_generic_payload *SchedulerNew::getNextRequest(Bank bank) +{ + if (!buffer[bank].empty()) + { + tlm_generic_payload *payload = buffer[bank].front(); + buffer[bank].pop_front(); + return payload; + } + else + return nullptr; +} + +void SchedulerNew::printDebugMessage(std::string message) +{ + DebugManager::getInstance().printDebugMessage("Scheduler", message); +} diff --git a/DRAMSys/library/src/controller/SchedulerNew.h b/DRAMSys/library/src/controller/SchedulerNew.h new file mode 100644 index 00000000..1dd17fab --- /dev/null +++ b/DRAMSys/library/src/controller/SchedulerNew.h @@ -0,0 +1,22 @@ +#ifndef SCHEDULERNEW_H +#define SCHEDULERNEW_H + +#include +#include +#include "../common/dramExtensions.h" +#include "ControllerNew.h" +#include + +using namespace tlm; + +class SchedulerNew +{ +public: + void storeRequest(tlm_generic_payload *); + tlm_generic_payload *getNextRequest(Bank bank); +private: + void printDebugMessage(std::string message); + std::map> buffer; +}; + +#endif // SCHEDULERNEW_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 335cdfaf..d4482924 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -259,7 +259,7 @@ void DRAMSys::instantiateModules(const string &traceName, // controller = new Controller(str.c_str()); // controllers.push_back(controller); - ControllerNew *controller = new ControllerNew(str.c_str()); + ControllerNew *controller = new ControllerNew(str.c_str(), tlmRecorders[i]); newControllers.push_back(controller); str = "dram" + std::to_string(i); From ef011ad52cf6740122ba0a0dceec87fa6cb55dbd Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 22 Jul 2019 00:23:12 +0200 Subject: [PATCH 027/183] Ready for debugging. --- .../resources/configs/simulator/ddr3.xml | 2 +- .../library/src/controller/BankMachine.cpp | 84 +++- DRAMSys/library/src/controller/BankMachine.h | 21 +- DRAMSys/library/src/controller/CommandMux.cpp | 49 +- DRAMSys/library/src/controller/CommandMux.h | 18 +- .../library/src/controller/ControllerNew.cpp | 163 ++++++- .../library/src/controller/ControllerNew.h | 32 +- .../src/controller/core/ControllerCore.cpp | 4 +- .../src/controller/core/ControllerCore.h | 2 +- .../scheduling/checker/CheckerDDR3New.cpp | 443 +++++------------- .../core/scheduling/checker/CheckerDDR3New.h | 6 +- 11 files changed, 437 insertions(+), 387 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index 1613737f..f43e4b8c 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,6 +1,6 @@ - + diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index dda0cd81..d372b4e1 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -1,12 +1,88 @@ #include "BankMachine.h" #include "Command.h" +#include "core/scheduling/checker/CheckerDDR3New.h" -BankMachine::BankMachine(ControllerNew *controller) : controller(controller) +BankMachine::BankMachine(ControllerNew *controller, SchedulerNew *scheduler, CheckerDDR3New *checker, Bank bank) + : controller(controller), scheduler(scheduler), checker(checker), bank(bank) {} + +void BankMachine::setCommandFinishedTime(sc_time time) { - + commandFinishedTime = time; } -void BankMachine::setResultReady(sc_time time) +tlm_generic_payload *BankMachine::getNextStateAndResult() { - resultReady = time; + tlm_generic_payload *payloadToReturn = nullptr; + + if (commandFinishedTime == sc_time_stamp()) + { + if (currentState == BmState::Activating) + currentState = BmState::Activated; + else if (currentState == BmState::Precharging) + currentState = BmState::Precharged; + else if (currentState == BmState::Reading || currentState == BmState::Writing) + { + currentState = BmState::Activated; + payloadToReturn = currentPayload; + currentPayload = nullptr; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong command!"); + } + return payloadToReturn; +} + +void BankMachine::startBankMachine(sc_time minDelay) +{ + if (currentPayload == nullptr) + { + currentPayload = scheduler->getNextRequest(bank); + if (currentPayload == nullptr) + return; + } + if (currentState == BmState::Precharged) + { + sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::ACT, bank)); + controller->triggerEventAfterDelay(delay); + nextCommand = Command::ACT; + timeToSchedule = sc_time_stamp() + delay; + } + else if (currentState == BmState::Activated) + { + DramExtension extension = DramExtension::getExtension(currentPayload); + if (extension.getRow() == currentRow) + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::RD, bank)); + controller->triggerEventAfterDelay(delay); + nextCommand = Command::RD; + timeToSchedule = sc_time_stamp() + delay; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::WR, bank)); + controller->triggerEventAfterDelay(delay); + nextCommand = Command::WR; + timeToSchedule = sc_time_stamp() + delay; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + else + { + sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::PRE, bank)); + controller->triggerEventAfterDelay(delay); + nextCommand = Command::PRE; + timeToSchedule = sc_time_stamp() + delay; + } + } +} + +std::pair BankMachine::getNextCommand() +{ + if (timeToSchedule == sc_time_stamp()) + return std::pair(nextCommand, currentPayload); + else + return std::pair(Command::NOP, nullptr); } diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 130bb0d7..c583d455 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -5,30 +5,43 @@ #include #include "../common/dramExtensions.h" #include "Command.h" +#include "SchedulerNew.h" using namespace tlm; class ControllerNew; +class SchedulerNew; +class CheckerDDR3New; enum class BmState { Precharged, - Activated + Activated, + Precharging, + Activating, + Reading, + Writing }; class BankMachine { public: - BankMachine(ControllerNew *); - void setResultReady(sc_time); + BankMachine(ControllerNew *, SchedulerNew *, CheckerDDR3New*, Bank); + void setCommandFinishedTime(sc_time); + tlm_generic_payload *getNextStateAndResult(); + void startBankMachine(sc_time minDelay); + std::pair getNextCommand(); private: tlm_generic_payload *currentPayload = nullptr; BmState currentState = BmState::Precharged; + Bank bank; Row currentRow = Row(0); Command nextCommand = Command::NOP; sc_time timeToSchedule = SC_ZERO_TIME; - sc_time resultReady = SC_ZERO_TIME; + sc_time commandFinishedTime = SC_ZERO_TIME; ControllerNew *controller; + SchedulerNew *scheduler; + CheckerDDR3New *checker; }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 0f5db035..65d290a5 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -1,19 +1,42 @@ #include "CommandMux.h" #include "core/configuration/Configuration.h" -CommandMux::CommandMux(ControllerNew *controller) : - controller(controller), - state("CommandMux", &Configuration::getInstance()), - checker(Configuration::getInstance(), state) {} +CommandMux::CommandMux(ControllerNew *controller, ControllerState *state, std::map &bankMachines) : + controller(controller), state(state), bankMachines(bankMachines) {} -/* -void CommandMux::compute() +void CommandMux::insertPayload(tlm_generic_payload *payload) { - // Handling of backpressure from / to arbiter!!! - - /* END_RESP from arbiter: check for successful transaction, remove payload from response queue, numberOfPayloads-- - * END_RD / END_WR from DRAM: check for successful transaction, move payload from BM to response queue, send result to arbiter (delay??) - * BEGIN_REQ from arbiter: check for transaction, move to scheduler map - * Trigger by BM: get transactions from all BM, choose one, send one, change state on BM, postpone all BM to next point in time + payloadOrder.push(payload); +} + +void CommandMux::selectCommand() +{ + for (auto it : bankMachines) + { + std::pair result = it.second->getNextCommand(); + if (result.first != Command::NOP) + readyCommands.push_back(result); + } + for (auto it : readyCommands) + { + if (it.first == Command::ACT || it.first == Command::PRE) + { + controller->sendToDram(it.first, it.second); + readyCommands.clear(); + return; + } + } + for (auto it : readyCommands) + { + if (it.first == Command::RD || it.first == Command::WR) + { + if (it.second == payloadOrder.front()) + { + payloadOrder.pop(); + controller->sendToDram(it.first, it.second); + readyCommands.clear(); + return; + } + } + } } -*/ diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h index 9312e57b..ba74115c 100644 --- a/DRAMSys/library/src/controller/CommandMux.h +++ b/DRAMSys/library/src/controller/CommandMux.h @@ -1,26 +1,30 @@ #ifndef COMMANDMUX_H #define COMMANDMUX_H +#include #include #include #include "ControllerState.h" -#include "core/scheduling/checker/CheckerDDR3New.h" +#include "BankMachine.h" +#include "ControllerNew.h" using namespace tlm; class ControllerNew; +class BankMachine; class CommandMux { public: - CommandMux(ControllerNew *); - SC_HAS_PROCESS(CommandMux); - void triggerEventAtTime(sc_time triggerTime); - void triggerEventQueueAtTime(sc_time triggerTime); + CommandMux(ControllerNew *, ControllerState*, std::map &); + void insertPayload(tlm_generic_payload *); + void selectCommand(); private: - ControllerState state; - CheckerDDR3New checker; + ControllerState *state; ControllerNew *controller; + std::queue payloadOrder; + std::map &bankMachines; + std::vector> readyCommands; }; #endif // COMMANDMUX_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 4c41219c..8fff7670 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -3,26 +3,32 @@ #include "scheduler/FifoStrict.h" #include "../common/dramExtensions.h" #include "../common/protocol.h" +#include "core/scheduling/ScheduledCommand.h" ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : sc_module(name), tlmRecorder(tlmRecorder), debugManager(&DebugManager::getInstance()) { - SC_METHOD(control); + SC_METHOD(controllerMethod); sensitive << triggerEvent << triggerEventQueue; + dont_initialize(); tSocket.register_nb_transport_fw(this, &ControllerNew::nb_transport_fw); tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg); iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw); - for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachine(this); - commandMux = new CommandMux(this); + state = new ControllerState("Controller", &Configuration::getInstance()); + checker = new CheckerDDR3New(Configuration::getInstance(), *state); scheduler = new SchedulerNew(); + for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachine(this, scheduler, checker, Bank(bankID)); + commandMux = new CommandMux(this, state, bankMachines); } ControllerNew::~ControllerNew() { tlmRecorder->closeConnection(); + delete state; + delete checker; for (auto it : bankMachines) delete it.second; delete commandMux; @@ -32,18 +38,20 @@ ControllerNew::~ControllerNew() tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { + recordPhase(trans, phase, delay); sc_time notDelay = delay; if (phase == BEGIN_REQ) { notDelay += Configuration::getInstance().memSpec->clk; payloadToAcquire = &trans; + timeToAcquire = sc_time_stamp() + notDelay; } else if (phase = END_RESP) { // FIXME: synchronization! notDelay += Configuration::getInstance().memSpec->clk; - payloadToRelease = &trans; + timeToRelease = sc_time_stamp() + notDelay; } else { @@ -67,16 +75,12 @@ unsigned int ControllerNew::transport_dbg(tlm_generic_payload &trans) tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - // only for END_RD and END_WR - if (phase == END_RD || phase == END_WR) - { - printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + - delay.to_string()); - Bank bank = DramExtension::getExtension(trans).getBank(); - sc_time triggerTime = sc_time_stamp() + delay; - bankMachines[bank]->setResultReady(triggerTime); - triggerEventQueueAtTime(triggerTime); - } + recordPhase(trans, phase, delay); + printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + + delay.to_string()); + Bank bank = DramExtension::getExtension(trans).getBank(); + bankMachines[bank]->setCommandFinishedTime(sc_time_stamp() + delay); + triggerEventQueue.notify(delay); return TLM_ACCEPTED; } @@ -104,17 +108,136 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ tlmRecorder->recordPhase(trans, phase, recTime); } -void ControllerNew::triggerEventAtTime(sc_time triggerTime) +void ControllerNew::triggerEventAfterDelay(sc_time delay) { - triggerEvent.notify(triggerTime); + triggerEvent.notify(delay); } -void ControllerNew::triggerEventQueueAtTime(sc_time triggerTime) +void ControllerNew::triggerEventQueueAfterDelay(sc_time delay) { - triggerEventQueue.notify(triggerTime); + triggerEventQueue.notify(delay); } -void ControllerNew::control() +void ControllerNew::controllerMethod() { + std::cout << sc_time_stamp() << std::endl; + releasePayload(); + acquirePayload(); + getNextBmStates(); + sendToFrontend(); + startBankMachines(); + commandMux->selectCommand(); + restartBankMachines(); +} + +void ControllerNew::releasePayload() +{ + if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) + { + responseQueue.pop(); + payloadToRelease->release(); + payloadToRelease = nullptr; + numberOfPayloads--; + // TODO: insert payload ID + printDebugMessage("Payload ID left system."); + } +} + +void ControllerNew::acquirePayload() +{ + if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + { + if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) + { + payloadToAcquire->acquire(); + scheduler->storeRequest(payloadToAcquire); + commandMux->insertPayload(payloadToAcquire); + payloadToAcquire = nullptr; + numberOfPayloads++; + // TODO: insert payload ID + printDebugMessage("Payload ID entered system."); + payloadToAcquire->set_response_status(TLM_OK_RESPONSE); + tlm_phase tPhase = END_REQ; + sc_time tDelay = SC_ZERO_TIME; + recordPhase(*payloadToAcquire, tPhase, tDelay); + tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); + } + else + printDebugMessage("Total number of payloads exceeded, backpressure!"); + } +} + +void ControllerNew::sendToFrontend() +{ + if (payloadToRelease == nullptr) + { + if (!responseQueue.empty()) + { + payloadToRelease = responseQueue.front(); + tlm_phase tPhase = END_REQ; + sc_time tDelay = SC_ZERO_TIME; + tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay); + } + } +} + +void ControllerNew::getNextBmStates() +{ + for (auto it : bankMachines) + { + tlm_generic_payload *result = it.second->getNextStateAndResult(); + if (result != nullptr) + { + responseQueue.push(result); + } + } } + +void ControllerNew::startBankMachines() +{ + for (auto it : bankMachines) + it.second->startBankMachine(SC_ZERO_TIME); +} + +void ControllerNew::restartBankMachines() +{ + sc_time minDelay = Configuration::getInstance().memSpec->clk; + for (auto it : bankMachines) + it.second->startBankMachine(minDelay); +} + +void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) +{ + sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); + ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); + state->cleanUp(sc_time_stamp()); + state->change(scheduledCommand); + + sc_time delay = SC_ZERO_TIME; + tlm_phase phase; + if (command == Command::ACT) + phase = BEGIN_ACT; + else if (command == Command::PRE) + phase = BEGIN_PRE; + else if (command == Command::RD) + phase = BEGIN_RD; + else if (command == Command::WR) + phase = BEGIN_WR; + else + SC_REPORT_FATAL("ControllerNew", "Unknown phase"); + iSocket->nb_transport_fw(*payload, phase, delay); +} + + +//void CommandMux::compute() +//{ +// // Handling of backpressure from / to arbiter!!! + +// /* END_RESP from arbiter: check for successful transaction, remove payload from response queue, numberOfPayloads-- +// * END_RD / END_WR from DRAM: check for successful transaction, move payload from BM to response queue, send result to arbiter (delay??) +// * BEGIN_REQ from arbiter: check for transaction, move to scheduler map +// * Trigger by BM: get transactions from all BM, choose one, send one, change state on BM, postpone all BM to next point in time +// */ +//} + diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 5210a2d2..0e161c6a 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -13,10 +14,14 @@ #include "SchedulerNew.h" #include "../common/TlmRecorder.h" #include "../common/DebugManager.h" +#include "core/scheduling/checker/CheckerDDR3New.h" +#include "ControllerState.h" using namespace tlm; class SchedulerNew; +class BankMachine; +class CommandMux; class ControllerNew : public sc_module { @@ -28,8 +33,16 @@ public: tlm_utils::simple_target_socket tSocket; tlm_utils::simple_initiator_socket iSocket; - void triggerEventAtTime(sc_time triggerTime); - void triggerEventQueueAtTime(sc_time triggerTime); + void triggerEventAfterDelay(sc_time); + void triggerEventQueueAfterDelay(sc_time); + + ControllerState *state; + std::map bankMachines; + CommandMux *commandMux; + SchedulerNew *scheduler; + CheckerDDR3New *checker; + + void sendToDram(Command, tlm_generic_payload *); private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, @@ -40,19 +53,24 @@ private: void printDebugMessage(string message); void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay); + void releasePayload(); + void acquirePayload(); + void getNextBmStates(); + void sendToFrontend(); + void startBankMachines(); + void restartBankMachines(); + unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; + sc_time timeToAcquire = SC_ZERO_TIME; tlm_generic_payload *payloadToRelease = nullptr; + sc_time timeToRelease = SC_ZERO_TIME; std::queue responseQueue; - std::map bankMachines; - CommandMux *commandMux; - SchedulerNew *scheduler; - TlmRecorder *tlmRecorder; DebugManager *debugManager; - void control(); + void controllerMethod(); sc_event triggerEvent; sc_event_queue triggerEventQueue; }; diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 4ec38ff6..8b5c87ab 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -87,7 +87,7 @@ ControllerCore::ControllerCore(sc_module_name /*name*/, commandChecker[Command::PDXP] = commandChecker[Command::PDEA]; commandChecker[Command::SREFEX] = commandChecker[Command::PDEA]; - timingChecker = new CheckerDDR3New(config, *state); + //timingChecker = new CheckerDDR3New(config, *state); // if (config.RowGranularRef) { // refreshManager = new RGR("RGR", *this); @@ -127,7 +127,7 @@ ControllerCore::~ControllerCore() delete commandChecker[Command::WR]; delete commandChecker[Command::REFA]; delete commandChecker[Command::PDEA]; - delete timingChecker; + //delete timingChecker; //delete refreshManager; //delete powerDownManager; delete state; diff --git a/DRAMSys/library/src/controller/core/ControllerCore.h b/DRAMSys/library/src/controller/core/ControllerCore.h index 291ba905..424998f3 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.h +++ b/DRAMSys/library/src/controller/core/ControllerCore.h @@ -85,7 +85,7 @@ private: ScheduledCommand schedule(Command command, sc_time start, tlm::tlm_generic_payload &payload); std::map commandChecker; - ICommandChecker *timingChecker; + //ICommandChecker *timingChecker; void printDebugMessage(string message); }; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 451158cf..696f7b02 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -11,365 +11,158 @@ using namespace std; -void CheckerDDR3New::delayToSatisfyConstraints(ScheduledCommand &command) const +sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) { - ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); - Command LastCmd = lastCommandOnBank.getCommand(); - Command nextCmd = command.getCommand(); ScheduledCommand lastCommand; - if (nextCmd == Command::ACT) + sc_time minTimeToWait = sc_time_stamp(); + + if (command == Command::ACT) { - // TODO: WRA_bank0 -> PREA -> ACT_bank0: WRA_bank0 and ACT_bank0 have TD, - // but we only consider PREA -> ACT_bank0 TD - // REFA -> PDEP -> PDXP -> ACT - lastCommand = state.getLastCommand(Command::RDA, command.getBank()); + lastCommand = state.getLastCommand(Command::RDA, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - lastCommand = state.getLastCommand(Command::WRA, command.getBank()); + lastCommand = state.getLastCommand(Command::WRA, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PRE, command.getBank()); + lastCommand = state.getLastCommand(Command::PRE, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PREA, command.getBank()); + lastCommand = state.getLastCommand(Command::PREA, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); + lastCommand = state.getLastCommand(Command::PDXA, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); + lastCommand = state.getLastCommand(Command::PDXP, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::REFA, command.getBank()); + lastCommand = state.getLastCommand(Command::REFA, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); - lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); + lastCommand = state.getLastCommand(Command::SREFEX, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); - lastCommand = state.getLastCommand(Command::ACT, command.getBank()); + lastCommand = state.getLastCommand(Command::ACT, bank); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRC); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); - while (!(state.bus.isFree(command.getStart()) && satsfiesACTtoACTdifferentBank(command) && satisfiesNActivateWindow(command))) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::RD || nextCmd == Command::RDA) - { - lastCommand = state.getLastCommand(Command::ACT, command.getBank()); - //if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); - - lastCommand = state.getLastCommand(Command::RD, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCCD); - - lastCommand = state.getLastCommand(Command::WR, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - - lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - - lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXSDLL); - - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::WR || nextCmd == Command::WRA) - { - lastCommand = state.getLastCommand(Command::ACT, command.getBank()); - //if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRCD); - - lastCommand = state.getLastCommand(Command::RD, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - - lastCommand = state.getLastCommand(Command::WR, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCCD); - - lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - - lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXSDLL); - - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::PRE) - { - lastCommand = state.getLastCommand(Command::ACT, command.getBank()); - //if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRAS); - - lastCommand = state.getLastCommand(Command::RD, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); - - lastCommand = state.getLastCommand(Command::WR, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); - - lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PREA) - { - lastCommand = state.getLastCommand(Command::ACT); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRAS); - - lastCommand = state.getLastCommand(Command::RD); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); - - lastCommand = state.getLastCommand(Command::RDA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP); - - lastCommand = state.getLastCommand(Command::WR); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); - - lastCommand = state.getLastCommand(Command::WRA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR); - - lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - - lastCommand = state.getLastCommand(Command::REFA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDEA) - { - // TODO: Remove? - lastCommand = state.getLastCommand(Command::ACT); - //if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); - - lastCommand = state.getLastCommand(Command::RD); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); - - lastCommand = state.getLastCommand(Command::RDA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); - - lastCommand = state.getLastCommand(Command::WR); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 4 * memSpec->clk + memSpec->tWR); - - lastCommand = state.getLastCommand(Command::WRA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); - - // TODO: Remove? - lastCommand = state.getLastCommand(Command::PRE); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); - - lastCommand = state.getLastCommand(Command::PDXA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDEP) - { - lastCommand = state.getLastCommand(Command::RD); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); - - lastCommand = state.getLastCommand(Command::RDA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); - - lastCommand = state.getLastCommand(Command::WRA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); - - // TODO: Remove? - lastCommand = state.getLastCommand(Command::PRE); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); - - // TODO: Remove? - lastCommand = state.getLastCommand(Command::PREA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); - - lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); - - // TODO: Remove? - lastCommand = state.getLastCommand(Command::REFA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->clk); - - lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::SREFEN) - { - lastCommand = state.getLastCommand(Command::RDA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRL + 5 * memSpec->clk); - - lastCommand = state.getLastCommand(Command::WRA); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); - - lastCommand = state.getLastCommand(Command::PRE); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); - - lastCommand = state.getLastCommand(Command::PREA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); - - lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - - lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDXA) - { - lastCommand = state.getLastScheduledCommand(command.getBank()); - if (lastCommand.getCommand() != Command::PDEA) - reportFatal("CheckerDDR3New", "PDXA can not follow " + commandToString(lastCommand.getCommand())); - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDXP) - { - lastCommand = state.getLastScheduledCommand(command.getBank()); - if (lastCommand.getCommand() != Command::PDEP) - reportFatal("CheckerDDR3New", "PDXP can not follow " + commandToString(lastCommand.getCommand())); - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKE); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::SREFEX) - { - lastCommand = state.getLastScheduledCommand(command.getBank()); - if (lastCommand.getCommand() != Command::SREFEN) - reportFatal("CheckerDDR3New", "SREFEX can not follow " + commandToString(lastCommand.getCommand())); - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tCKESR); - - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::REFA) - { - // TODO: Bankwise logic - if (config.BankwiseLogic) + for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - if (lastCommandOnBank.isValidCommand()) - { - switch (LastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - default: - reportFatal("CheckerDDR3New", - "Refresh can not follow " + commandToString(LastCmd)); - } - } + lastCommand = state.getLastCommand(Command::ACT, Bank(bankID)); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); } - else + + if (!state.bus.isFree(sc_time_stamp())) + minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommand = state.getLastCommand(Command::ACT, bank); + //if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); + +// lastCommand = state.getLastCommand(Command::RD, bank); +// if (lastCommand.isValidCommand()) +// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + +// lastCommand = state.getLastCommand(Command::WR, bank); +// if (lastCommand.isValidCommand()) +// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + + lastCommand = state.getLastCommand(Command::PDXA, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + lastCommand = state.getLastCommand(Command::SREFEX, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + + if (!state.bus.isFree(sc_time_stamp())) + minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); + + for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::RDA); + lastCommand = state.getLastCommand(Command::RD, Bank(bankID)); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRTP + memSpec->tRP); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - lastCommand = state.getLastCommand(Command::WRA); + lastCommand = state.getLastCommand(Command::WR, Bank(bankID)); if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - - lastCommand = state.getLastCommand(Command::PRE); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); - - lastCommand = state.getLastCommand(Command::PREA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRP); - - lastCommand = state.getLastCommand(Command::PDXP, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXP); - - lastCommand = state.getLastCommand(Command::REFA, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tRFC); - - lastCommand = state.getLastCommand(Command::SREFEX, command.getBank()); - if (lastCommand.isValidCommand()) - command.establishMinDistanceFromStart(lastCommand.getStart(), memSpec->tXS); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); } - state.bus.moveCommandToNextFreeSlot(command); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommand = state.getLastCommand(Command::ACT, bank); + //if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); + +// lastCommand = state.getLastCommand(Command::RD, bank); +// if (lastCommand.isValidCommand()) +// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + +// lastCommand = state.getLastCommand(Command::WR, bank); +// if (lastCommand.isValidCommand()) +// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + + lastCommand = state.getLastCommand(Command::PDXA, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + lastCommand = state.getLastCommand(Command::SREFEX, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + + if (!state.bus.isFree(sc_time_stamp())) + minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); + + for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) + { + lastCommand = state.getLastCommand(Command::RD, Bank(bankID)); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + + lastCommand = state.getLastCommand(Command::WR, Bank(bankID)); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + } + } + else if (command == Command::PRE) + { + lastCommand = state.getLastCommand(Command::ACT, bank); + //if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); + + lastCommand = state.getLastCommand(Command::RD, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); + + lastCommand = state.getLastCommand(Command::WR, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + + lastCommand = state.getLastCommand(Command::PDXA, bank); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + if (!state.bus.isFree(sc_time_stamp())) + minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); } else { reportFatal("CheckerDDR3New", "Unknown command!"); } + return (minTimeToWait - sc_time_stamp()); } /* diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 6daff0dc..349b250d 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -6,7 +6,7 @@ #include "../../../ControllerState.h" //Activate -class CheckerDDR3New : public ICommandChecker +class CheckerDDR3New { public: CheckerDDR3New(const Configuration &config, @@ -16,9 +16,9 @@ public: if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); } - virtual ~CheckerDDR3New() {} + ~CheckerDDR3New() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const override; + sc_time delayToSatisfyConstraints(Command command, Bank bank); private: MemSpecDDR3 *memSpec; From 1ce8996ece1412258d9968ef3b669f89264cc1ba Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 22 Jul 2019 01:53:18 +0200 Subject: [PATCH 028/183] Some bugs are fixed, still not running. --- .../library/src/controller/BankMachine.cpp | 23 ++++++++++++--- DRAMSys/library/src/controller/BankMachine.h | 1 + .../library/src/controller/ControllerNew.cpp | 29 ++++++++++++------- .../library/src/controller/ControllerNew.h | 4 +-- 4 files changed, 41 insertions(+), 16 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index d372b4e1..91967030 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -43,7 +43,7 @@ void BankMachine::startBankMachine(sc_time minDelay) if (currentState == BmState::Precharged) { sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::ACT, bank)); - controller->triggerEventAfterDelay(delay); + controller->triggerEventAfterDelay(delay, "startBankMachine 1"); nextCommand = Command::ACT; timeToSchedule = sc_time_stamp() + delay; } @@ -55,14 +55,14 @@ void BankMachine::startBankMachine(sc_time minDelay) if (currentPayload->get_command() == TLM_READ_COMMAND) { sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::RD, bank)); - controller->triggerEventAfterDelay(delay); + controller->triggerEventAfterDelay(delay, "startBankMachine 2"); nextCommand = Command::RD; timeToSchedule = sc_time_stamp() + delay; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::WR, bank)); - controller->triggerEventAfterDelay(delay); + controller->triggerEventAfterDelay(delay, "startBankMachine 3"); nextCommand = Command::WR; timeToSchedule = sc_time_stamp() + delay; } @@ -72,7 +72,7 @@ void BankMachine::startBankMachine(sc_time minDelay) else { sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::PRE, bank)); - controller->triggerEventAfterDelay(delay); + controller->triggerEventAfterDelay(delay, "startBankMachine 4"); nextCommand = Command::PRE; timeToSchedule = sc_time_stamp() + delay; } @@ -86,3 +86,18 @@ std::pair BankMachine::getNextCommand() else return std::pair(Command::NOP, nullptr); } + +void BankMachine::updateState(Command command) +{ + if (command == Command::ACT) + currentState = BmState::Activating; + else if (command == Command::PRE) + currentState = BmState::Precharging; + else if (command == Command::RD) + currentState = BmState::Reading; + else if (command == Command::WR) + currentState = BmState::Writing; + else + SC_REPORT_FATAL("BankMachine", "Unknown phase"); + +} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index c583d455..08e029f8 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -31,6 +31,7 @@ public: tlm_generic_payload *getNextStateAndResult(); void startBankMachine(sc_time minDelay); std::pair getNextCommand(); + void updateState(Command); private: tlm_generic_payload *currentPayload = nullptr; BmState currentState = BmState::Precharged; diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 8fff7670..9b4df842 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -38,6 +38,7 @@ ControllerNew::~ControllerNew() tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { + std::cout << "Controller: " << sc_time_stamp() << std::endl; recordPhase(trans, phase, delay); sc_time notDelay = delay; @@ -61,7 +62,7 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + notDelay.to_string()); - triggerEventQueue.notify(notDelay); + triggerEventQueueAfterDelay(notDelay, "nb_transport_fw"); return TLM_ACCEPTED; } @@ -80,7 +81,7 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, delay.to_string()); Bank bank = DramExtension::getExtension(trans).getBank(); bankMachines[bank]->setCommandFinishedTime(sc_time_stamp() + delay); - triggerEventQueue.notify(delay); + triggerEventQueueAfterDelay(delay, "nb_transport_bw"); return TLM_ACCEPTED; } @@ -108,19 +109,23 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ tlmRecorder->recordPhase(trans, phase, recTime); } -void ControllerNew::triggerEventAfterDelay(sc_time delay) +void ControllerNew::triggerEventAfterDelay(sc_time delay, string sender) { - triggerEvent.notify(delay); + std::cout << "Delay: " << delay << " by " + sender << std::endl; + if (delay != SC_ZERO_TIME) + triggerEvent.notify(delay); } -void ControllerNew::triggerEventQueueAfterDelay(sc_time delay) +void ControllerNew::triggerEventQueueAfterDelay(sc_time delay, string sender) { - triggerEventQueue.notify(delay); + std::cout << "Delayqueue: " << delay << " by " + sender << std::endl; + if (delay != SC_ZERO_TIME) + triggerEventQueue.notify(delay); } void ControllerNew::controllerMethod() { - std::cout << sc_time_stamp() << std::endl; + std::cout << "ControllerMethod triggered at " << sc_time_stamp() << std::endl; releasePayload(); acquirePayload(); getNextBmStates(); @@ -132,7 +137,7 @@ void ControllerNew::controllerMethod() void ControllerNew::releasePayload() { - if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) + if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) { responseQueue.pop(); payloadToRelease->release(); @@ -152,15 +157,15 @@ void ControllerNew::acquirePayload() payloadToAcquire->acquire(); scheduler->storeRequest(payloadToAcquire); commandMux->insertPayload(payloadToAcquire); - payloadToAcquire = nullptr; numberOfPayloads++; // TODO: insert payload ID printDebugMessage("Payload ID entered system."); - payloadToAcquire->set_response_status(TLM_OK_RESPONSE); + payloadToAcquire->set_response_status(tlm::TLM_OK_RESPONSE); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; recordPhase(*payloadToAcquire, tPhase, tDelay); tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); + payloadToAcquire = nullptr; } else printDebugMessage("Total number of payloads exceeded, backpressure!"); @@ -213,6 +218,9 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); state->cleanUp(sc_time_stamp()); state->change(scheduledCommand); + Bank bank = scheduledCommand.getBank(); + bankMachines[bank]->updateState(command); + std::cout << sc_time_stamp() << ": Sending command " << commandToString(command) << " on bank " << bank.toString() << std::endl; sc_time delay = SC_ZERO_TIME; tlm_phase phase; @@ -226,6 +234,7 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) phase = BEGIN_WR; else SC_REPORT_FATAL("ControllerNew", "Unknown phase"); + iSocket->nb_transport_fw(*payload, phase, delay); } diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 0e161c6a..5db8eb24 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -33,8 +33,8 @@ public: tlm_utils::simple_target_socket tSocket; tlm_utils::simple_initiator_socket iSocket; - void triggerEventAfterDelay(sc_time); - void triggerEventQueueAfterDelay(sc_time); + void triggerEventAfterDelay(sc_time, string); + void triggerEventQueueAfterDelay(sc_time, string); ControllerState *state; std::map bankMachines; From f69771e7be76c707f47cc4685d060bc3d514237e Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 22 Jul 2019 17:59:51 +0200 Subject: [PATCH 029/183] Simulation is running to the end, results may still be wrong. --- .../resources/configs/simulator/ddr3.xml | 2 +- .../library/src/controller/BankMachine.cpp | 4 +-- .../library/src/controller/ControllerNew.cpp | 33 ++++++++++--------- .../library/src/controller/ControllerNew.h | 1 + DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- .../library/src/simulation/DramRecordable.cpp | 6 ++-- 6 files changed, 26 insertions(+), 22 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index f43e4b8c..94bc52c6 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,7 +1,7 @@ - + diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 91967030..54a20c85 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -27,7 +27,7 @@ tlm_generic_payload *BankMachine::getNextStateAndResult() currentPayload = nullptr; } else - SC_REPORT_FATAL("BankMachine", "Wrong command!"); + SC_REPORT_FATAL(("BankMachine " + bank.toString()).c_str(), "Wrong command!"); } return payloadToReturn; } @@ -75,6 +75,7 @@ void BankMachine::startBankMachine(sc_time minDelay) controller->triggerEventAfterDelay(delay, "startBankMachine 4"); nextCommand = Command::PRE; timeToSchedule = sc_time_stamp() + delay; + currentRow = extension.getRow(); } } } @@ -99,5 +100,4 @@ void BankMachine::updateState(Command command) currentState = BmState::Writing; else SC_REPORT_FATAL("BankMachine", "Unknown phase"); - } diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 9b4df842..5e2f396c 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -26,7 +26,7 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : ControllerNew::~ControllerNew() { - tlmRecorder->closeConnection(); + //tlmRecorder->closeConnection(); delete state; delete checker; for (auto it : bankMachines) @@ -38,7 +38,6 @@ ControllerNew::~ControllerNew() tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - std::cout << "Controller: " << sc_time_stamp() << std::endl; recordPhase(trans, phase, delay); sc_time notDelay = delay; @@ -106,33 +105,38 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + to_string(col) + " at " + recTime.to_string()); - tlmRecorder->recordPhase(trans, phase, recTime); + //tlmRecorder->recordPhase(trans, phase, recTime); } void ControllerNew::triggerEventAfterDelay(sc_time delay, string sender) { - std::cout << "Delay: " << delay << " by " + sender << std::endl; if (delay != SC_ZERO_TIME) + { triggerEvent.notify(delay); + } } void ControllerNew::triggerEventQueueAfterDelay(sc_time delay, string sender) { - std::cout << "Delayqueue: " << delay << " by " + sender << std::endl; if (delay != SC_ZERO_TIME) + { triggerEventQueue.notify(delay); + } } void ControllerNew::controllerMethod() { - std::cout << "ControllerMethod triggered at " << sc_time_stamp() << std::endl; - releasePayload(); - acquirePayload(); - getNextBmStates(); - sendToFrontend(); - startBankMachines(); - commandMux->selectCommand(); - restartBankMachines(); + if (lastTimeCalled != sc_time_stamp()) + { + lastTimeCalled = sc_time_stamp(); + releasePayload(); + acquirePayload(); + getNextBmStates(); + sendToFrontend(); + startBankMachines(); + commandMux->selectCommand(); + restartBankMachines(); + } } void ControllerNew::releasePayload() @@ -179,7 +183,7 @@ void ControllerNew::sendToFrontend() if (!responseQueue.empty()) { payloadToRelease = responseQueue.front(); - tlm_phase tPhase = END_REQ; + tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = SC_ZERO_TIME; tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay); } @@ -220,7 +224,6 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) state->change(scheduledCommand); Bank bank = scheduledCommand.getBank(); bankMachines[bank]->updateState(command); - std::cout << sc_time_stamp() << ": Sending command " << commandToString(command) << " on bank " << bank.toString() << std::endl; sc_time delay = SC_ZERO_TIME; tlm_phase phase; diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 5db8eb24..d24429a1 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -73,6 +73,7 @@ private: void controllerMethod(); sc_event triggerEvent; sc_event_queue triggerEventQueue; + sc_time lastTimeCalled = SC_ZERO_TIME; }; #endif // CONTROLLERNEW_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index d4482924..46ef928a 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -259,7 +259,7 @@ void DRAMSys::instantiateModules(const string &traceName, // controller = new Controller(str.c_str()); // controllers.push_back(controller); - ControllerNew *controller = new ControllerNew(str.c_str(), tlmRecorders[i]); + ControllerNew *controller = new ControllerNew(str.c_str(), nullptr); newControllers.push_back(controller); str = "dram" + std::to_string(i); diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 0ed6f553..2dbe1800 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -50,14 +50,14 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe { // Create a thread that is triggered every $powerWindowSize // to generate a Power over Time plot in the Trace analyzer: - SC_THREAD(powerWindow); + //SC_THREAD(powerWindow); } template DramRecordable::~DramRecordable() { - this->DRAMPower->calcEnergy(); - recordPower(); + //this->DRAMPower->calcEnergy(); + //recordPower(); tlmRecorder->closeConnection(); } From 6aa2533edd6e7558fd963be81992a8e533776802 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 22 Jul 2019 20:31:17 +0200 Subject: [PATCH 030/183] New controller is working. --- .../library/resources/configs/simulator/ddr3.xml | 4 ++-- DRAMSys/library/src/controller/ControllerNew.cpp | 14 ++++++++++++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/DramRecordable.cpp | 6 +++--- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index 94bc52c6..1613737f 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,7 +1,7 @@ - - + + diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 5e2f396c..3c591783 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -26,7 +26,6 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : ControllerNew::~ControllerNew() { - //tlmRecorder->closeConnection(); delete state; delete checker; for (auto it : bankMachines) @@ -105,7 +104,7 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + to_string(col) + " at " + recTime.to_string()); - //tlmRecorder->recordPhase(trans, phase, recTime); + tlmRecorder->recordPhase(trans, phase, recTime); } void ControllerNew::triggerEventAfterDelay(sc_time delay, string sender) @@ -185,6 +184,7 @@ void ControllerNew::sendToFrontend() payloadToRelease = responseQueue.front(); tlm_phase tPhase = BEGIN_RESP; sc_time tDelay = SC_ZERO_TIME; + recordPhase(*payloadToRelease, tPhase, tDelay); tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay); } } @@ -232,9 +232,19 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::PRE) phase = BEGIN_PRE; else if (command == Command::RD) + { phase = BEGIN_RD; + ScheduledCommand scheduledCommand = state->getLastCommand(command, bank); + TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); + tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); + } else if (command == Command::WR) + { phase = BEGIN_WR; + ScheduledCommand scheduledCommand = state->getLastCommand(command, bank); + TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); + tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); + } else SC_REPORT_FATAL("ControllerNew", "Unknown phase"); diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 46ef928a..d4482924 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -259,7 +259,7 @@ void DRAMSys::instantiateModules(const string &traceName, // controller = new Controller(str.c_str()); // controllers.push_back(controller); - ControllerNew *controller = new ControllerNew(str.c_str(), nullptr); + ControllerNew *controller = new ControllerNew(str.c_str(), tlmRecorders[i]); newControllers.push_back(controller); str = "dram" + std::to_string(i); diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 2dbe1800..0ed6f553 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -50,14 +50,14 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe { // Create a thread that is triggered every $powerWindowSize // to generate a Power over Time plot in the Trace analyzer: - //SC_THREAD(powerWindow); + SC_THREAD(powerWindow); } template DramRecordable::~DramRecordable() { - //this->DRAMPower->calcEnergy(); - //recordPower(); + this->DRAMPower->calcEnergy(); + recordPower(); tlmRecorder->closeConnection(); } From 0d0c7415b26e94e3d63ccfbc1dc9d3c68fd02ec5 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 23 Jul 2019 14:13:51 +0200 Subject: [PATCH 031/183] Fixed clk cycle waiting for fifo strict transaction order. --- .../library/src/controller/BankMachine.cpp | 14 +++---- DRAMSys/library/src/controller/BankMachine.h | 2 +- DRAMSys/library/src/controller/CommandMux.cpp | 30 +++++++------ .../library/src/controller/ControllerNew.cpp | 42 +++++-------------- .../library/src/controller/ControllerNew.h | 3 +- .../library/src/controller/ControllerState.h | 1 + 6 files changed, 38 insertions(+), 54 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 54a20c85..d4bb25a2 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -32,7 +32,7 @@ tlm_generic_payload *BankMachine::getNextStateAndResult() return payloadToReturn; } -void BankMachine::startBankMachine(sc_time minDelay) +void BankMachine::startBankMachine() { if (currentPayload == nullptr) { @@ -42,7 +42,7 @@ void BankMachine::startBankMachine(sc_time minDelay) } if (currentState == BmState::Precharged) { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::ACT, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::ACT, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 1"); nextCommand = Command::ACT; timeToSchedule = sc_time_stamp() + delay; @@ -50,18 +50,18 @@ void BankMachine::startBankMachine(sc_time minDelay) else if (currentState == BmState::Activated) { DramExtension extension = DramExtension::getExtension(currentPayload); - if (extension.getRow() == currentRow) + if (extension.getRow() == currentRow) // row hit { if (currentPayload->get_command() == TLM_READ_COMMAND) { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::RD, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::RD, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 2"); nextCommand = Command::RD; timeToSchedule = sc_time_stamp() + delay; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::WR, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::WR, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 3"); nextCommand = Command::WR; timeToSchedule = sc_time_stamp() + delay; @@ -69,9 +69,9 @@ void BankMachine::startBankMachine(sc_time minDelay) else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - else + else // row miss { - sc_time delay = max(minDelay, checker->delayToSatisfyConstraints(Command::PRE, bank)); + sc_time delay = checker->delayToSatisfyConstraints(Command::PRE, bank); controller->triggerEventAfterDelay(delay, "startBankMachine 4"); nextCommand = Command::PRE; timeToSchedule = sc_time_stamp() + delay; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 08e029f8..0d02269f 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -29,7 +29,7 @@ public: BankMachine(ControllerNew *, SchedulerNew *, CheckerDDR3New*, Bank); void setCommandFinishedTime(sc_time); tlm_generic_payload *getNextStateAndResult(); - void startBankMachine(sc_time minDelay); + void startBankMachine(); std::pair getNextCommand(); void updateState(Command); private: diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 65d290a5..7aee2d15 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -17,26 +17,30 @@ void CommandMux::selectCommand() if (result.first != Command::NOP) readyCommands.push_back(result); } - for (auto it : readyCommands) + if (!readyCommands.empty()) { - if (it.first == Command::ACT || it.first == Command::PRE) + for (auto it : readyCommands) { - controller->sendToDram(it.first, it.second); - readyCommands.clear(); - return; - } - } - for (auto it : readyCommands) - { - if (it.first == Command::RD || it.first == Command::WR) - { - if (it.second == payloadOrder.front()) + if (it.first == Command::ACT || it.first == Command::PRE) { - payloadOrder.pop(); controller->sendToDram(it.first, it.second); readyCommands.clear(); return; } } + for (auto it : readyCommands) + { + if (it.first == Command::RD || it.first == Command::WR) + { + if (it.second == payloadOrder.front()) + { + payloadOrder.pop(); + controller->sendToDram(it.first, it.second); + readyCommands.clear(); + return; + } + } + } + readyCommands.clear(); } } diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 3c591783..567f47d4 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -38,19 +38,19 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { recordPhase(trans, phase, delay); - sc_time notDelay = delay; + sc_time notificationDelay = delay; if (phase == BEGIN_REQ) { - notDelay += Configuration::getInstance().memSpec->clk; + notificationDelay += Configuration::getInstance().memSpec->clk; payloadToAcquire = &trans; - timeToAcquire = sc_time_stamp() + notDelay; + timeToAcquire = sc_time_stamp() + notificationDelay; } else if (phase = END_RESP) { // FIXME: synchronization! - notDelay += Configuration::getInstance().memSpec->clk; - timeToRelease = sc_time_stamp() + notDelay; + notificationDelay += Configuration::getInstance().memSpec->clk; + timeToRelease = sc_time_stamp() + notificationDelay; } else { @@ -59,13 +59,13 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, } printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + - notDelay.to_string()); - triggerEventQueueAfterDelay(notDelay, "nb_transport_fw"); + notificationDelay.to_string()); + triggerEventQueueAfterDelay(notificationDelay, "nb_transport_fw"); return TLM_ACCEPTED; } -unsigned int ControllerNew::transport_dbg(tlm_generic_payload &trans) +unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) { SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); return 0; @@ -134,7 +134,7 @@ void ControllerNew::controllerMethod() sendToFrontend(); startBankMachines(); commandMux->selectCommand(); - restartBankMachines(); + startBankMachines(); } } @@ -163,7 +163,7 @@ void ControllerNew::acquirePayload() numberOfPayloads++; // TODO: insert payload ID printDebugMessage("Payload ID entered system."); - payloadToAcquire->set_response_status(tlm::TLM_OK_RESPONSE); + payloadToAcquire->set_response_status(TLM_OK_RESPONSE); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; recordPhase(*payloadToAcquire, tPhase, tDelay); @@ -206,14 +206,7 @@ void ControllerNew::getNextBmStates() void ControllerNew::startBankMachines() { for (auto it : bankMachines) - it.second->startBankMachine(SC_ZERO_TIME); -} - -void ControllerNew::restartBankMachines() -{ - sc_time minDelay = Configuration::getInstance().memSpec->clk; - for (auto it : bankMachines) - it.second->startBankMachine(minDelay); + it.second->startBankMachine(); } void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) @@ -250,16 +243,3 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) iSocket->nb_transport_fw(*payload, phase, delay); } - - -//void CommandMux::compute() -//{ -// // Handling of backpressure from / to arbiter!!! - -// /* END_RESP from arbiter: check for successful transaction, remove payload from response queue, numberOfPayloads-- -// * END_RD / END_WR from DRAM: check for successful transaction, move payload from BM to response queue, send result to arbiter (delay??) -// * BEGIN_REQ from arbiter: check for transaction, move to scheduler map -// * Trigger by BM: get transactions from all BM, choose one, send one, change state on BM, postpone all BM to next point in time -// */ -//} - diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index d24429a1..0e54fd61 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -47,7 +47,7 @@ public: private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); - unsigned int transport_dbg(tlm_generic_payload &trans); + unsigned int transport_dbg(tlm_generic_payload &); tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); void printDebugMessage(string message); @@ -58,7 +58,6 @@ private: void getNextBmStates(); void sendToFrontend(); void startBankMachines(); - void restartBankMachines(); unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index a5d9d609..19cde85b 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -69,6 +69,7 @@ public: //used by the various checkers std::map > lastScheduledByCommandAndBank; + // TODO: remove std::map lastScheduledByCommand; std::map lastScheduledByBank; ScheduledCommand lastScheduled; From e7552f69167e18a9635955bfb0bffeff52007a6e Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 23 Jul 2019 14:30:01 +0200 Subject: [PATCH 032/183] Code cleanup. --- .../library/src/controller/BankMachine.cpp | 8 ++-- .../library/src/controller/ControllerNew.cpp | 46 +++++++++---------- .../library/src/controller/ControllerNew.h | 20 ++++---- 3 files changed, 37 insertions(+), 37 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index d4bb25a2..993ff42d 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -43,7 +43,7 @@ void BankMachine::startBankMachine() if (currentState == BmState::Precharged) { sc_time delay = checker->delayToSatisfyConstraints(Command::ACT, bank); - controller->triggerEventAfterDelay(delay, "startBankMachine 1"); + controller->triggerEventAfterDelay(delay); nextCommand = Command::ACT; timeToSchedule = sc_time_stamp() + delay; } @@ -55,14 +55,14 @@ void BankMachine::startBankMachine() if (currentPayload->get_command() == TLM_READ_COMMAND) { sc_time delay = checker->delayToSatisfyConstraints(Command::RD, bank); - controller->triggerEventAfterDelay(delay, "startBankMachine 2"); + controller->triggerEventAfterDelay(delay); nextCommand = Command::RD; timeToSchedule = sc_time_stamp() + delay; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { sc_time delay = checker->delayToSatisfyConstraints(Command::WR, bank); - controller->triggerEventAfterDelay(delay, "startBankMachine 3"); + controller->triggerEventAfterDelay(delay); nextCommand = Command::WR; timeToSchedule = sc_time_stamp() + delay; } @@ -72,7 +72,7 @@ void BankMachine::startBankMachine() else // row miss { sc_time delay = checker->delayToSatisfyConstraints(Command::PRE, bank); - controller->triggerEventAfterDelay(delay, "startBankMachine 4"); + controller->triggerEventAfterDelay(delay); nextCommand = Command::PRE; timeToSchedule = sc_time_stamp() + delay; currentRow = extension.getRow(); diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 567f47d4..5eee0316 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -60,17 +60,11 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); - triggerEventQueueAfterDelay(notificationDelay, "nb_transport_fw"); + triggerEventQueueAfterDelay(notificationDelay); return TLM_ACCEPTED; } -unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) -{ - SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); - return 0; -} - tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { @@ -79,10 +73,16 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, delay.to_string()); Bank bank = DramExtension::getExtension(trans).getBank(); bankMachines[bank]->setCommandFinishedTime(sc_time_stamp() + delay); - triggerEventQueueAfterDelay(delay, "nb_transport_bw"); + triggerEventQueueAfterDelay(delay); return TLM_ACCEPTED; } +unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) +{ + SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); + return 0; +} + void ControllerNew::printDebugMessage(string message) { debugManager->printDebugMessage(name(), message); @@ -107,7 +107,7 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ tlmRecorder->recordPhase(trans, phase, recTime); } -void ControllerNew::triggerEventAfterDelay(sc_time delay, string sender) +void ControllerNew::triggerEventAfterDelay(sc_time delay) { if (delay != SC_ZERO_TIME) { @@ -115,7 +115,7 @@ void ControllerNew::triggerEventAfterDelay(sc_time delay, string sender) } } -void ControllerNew::triggerEventQueueAfterDelay(sc_time delay, string sender) +void ControllerNew::triggerEventQueueAfterDelay(sc_time delay) { if (delay != SC_ZERO_TIME) { @@ -125,6 +125,7 @@ void ControllerNew::triggerEventQueueAfterDelay(sc_time delay, string sender) void ControllerNew::controllerMethod() { + static sc_time lastTimeCalled = SC_ZERO_TIME; if (lastTimeCalled != sc_time_stamp()) { lastTimeCalled = sc_time_stamp(); @@ -175,6 +176,18 @@ void ControllerNew::acquirePayload() } } +void ControllerNew::getNextBmStates() +{ + for (auto it : bankMachines) + { + tlm_generic_payload *result = it.second->getNextStateAndResult(); + if (result != nullptr) + { + responseQueue.push(result); + } + } +} + void ControllerNew::sendToFrontend() { if (payloadToRelease == nullptr) @@ -190,19 +203,6 @@ void ControllerNew::sendToFrontend() } } -void ControllerNew::getNextBmStates() -{ - for (auto it : bankMachines) - { - tlm_generic_payload *result = it.second->getNextStateAndResult(); - if (result != nullptr) - { - responseQueue.push(result); - } - } - -} - void ControllerNew::startBankMachines() { for (auto it : bankMachines) diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 0e54fd61..ea059eb5 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -33,8 +33,8 @@ public: tlm_utils::simple_target_socket tSocket; tlm_utils::simple_initiator_socket iSocket; - void triggerEventAfterDelay(sc_time, string); - void triggerEventQueueAfterDelay(sc_time, string); + void triggerEventAfterDelay(sc_time); + void triggerEventQueueAfterDelay(sc_time); ControllerState *state; std::map bankMachines; @@ -47,18 +47,13 @@ public: private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); - unsigned int transport_dbg(tlm_generic_payload &); tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); + unsigned int transport_dbg(tlm_generic_payload &); + void printDebugMessage(string message); void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay); - void releasePayload(); - void acquirePayload(); - void getNextBmStates(); - void sendToFrontend(); - void startBankMachines(); - unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; sc_time timeToAcquire = SC_ZERO_TIME; @@ -72,7 +67,12 @@ private: void controllerMethod(); sc_event triggerEvent; sc_event_queue triggerEventQueue; - sc_time lastTimeCalled = SC_ZERO_TIME; + + void releasePayload(); + void acquirePayload(); + void getNextBmStates(); + void sendToFrontend(); + void startBankMachines(); }; #endif // CONTROLLERNEW_H From 1e8b8e37eadd4f7b4bf77cb0f974c7bd4bb6ada5 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 23 Jul 2019 15:10:19 +0200 Subject: [PATCH 033/183] Moved if statements from inner methods to controllerMethod(). --- .../library/src/controller/BankMachine.cpp | 29 ++-- DRAMSys/library/src/controller/BankMachine.h | 1 + .../library/src/controller/ControllerNew.cpp | 124 ++++++++---------- .../library/src/controller/ControllerNew.h | 2 - 4 files changed, 70 insertions(+), 86 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 993ff42d..012c76ed 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -10,25 +10,28 @@ void BankMachine::setCommandFinishedTime(sc_time time) commandFinishedTime = time; } +sc_time BankMachine::getCommandFinishedTime() +{ + return commandFinishedTime; +} + tlm_generic_payload *BankMachine::getNextStateAndResult() { tlm_generic_payload *payloadToReturn = nullptr; - if (commandFinishedTime == sc_time_stamp()) + if (currentState == BmState::Activating) + currentState = BmState::Activated; + else if (currentState == BmState::Precharging) + currentState = BmState::Precharged; + else if (currentState == BmState::Reading || currentState == BmState::Writing) { - if (currentState == BmState::Activating) - currentState = BmState::Activated; - else if (currentState == BmState::Precharging) - currentState = BmState::Precharged; - else if (currentState == BmState::Reading || currentState == BmState::Writing) - { - currentState = BmState::Activated; - payloadToReturn = currentPayload; - currentPayload = nullptr; - } - else - SC_REPORT_FATAL(("BankMachine " + bank.toString()).c_str(), "Wrong command!"); + currentState = BmState::Activated; + payloadToReturn = currentPayload; + currentPayload = nullptr; } + else + SC_REPORT_FATAL(("BankMachine " + bank.toString()).c_str(), "Wrong command!"); + return payloadToReturn; } diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 0d02269f..e699d711 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -28,6 +28,7 @@ class BankMachine public: BankMachine(ControllerNew *, SchedulerNew *, CheckerDDR3New*, Bank); void setCommandFinishedTime(sc_time); + sc_time getCommandFinishedTime(); tlm_generic_payload *getNextStateAndResult(); void startBankMachine(); std::pair getNextCommand(); diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 5eee0316..f58bc9dc 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -48,15 +48,11 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, } else if (phase = END_RESP) { - // FIXME: synchronization! notificationDelay += Configuration::getInstance().memSpec->clk; timeToRelease = sc_time_stamp() + notificationDelay; } else - { - SC_REPORT_FATAL(0, - "Front-end PEQ in controller wrapper was triggered with unknown phase"); - } + SC_REPORT_FATAL(0, "Front-end PEQ in controller wrapper was triggered with unknown phase"); printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); @@ -110,17 +106,13 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ void ControllerNew::triggerEventAfterDelay(sc_time delay) { if (delay != SC_ZERO_TIME) - { triggerEvent.notify(delay); - } } void ControllerNew::triggerEventQueueAfterDelay(sc_time delay) { if (delay != SC_ZERO_TIME) - { triggerEventQueue.notify(delay); - } } void ControllerNew::controllerMethod() @@ -129,84 +121,74 @@ void ControllerNew::controllerMethod() if (lastTimeCalled != sc_time_stamp()) { lastTimeCalled = sc_time_stamp(); - releasePayload(); - acquirePayload(); - getNextBmStates(); - sendToFrontend(); - startBankMachines(); + + if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) + releasePayload(); + + if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + acquirePayload(); + + for (auto it : bankMachines) + { + if (it.second->getCommandFinishedTime() == sc_time_stamp()) + { + tlm_generic_payload *result = it.second->getNextStateAndResult(); + if (result != nullptr) + responseQueue.push(result); + } + } + + if (payloadToRelease == nullptr && !responseQueue.empty()) + sendToFrontend(); + + for (auto it : bankMachines) + it.second->startBankMachine(); + commandMux->selectCommand(); - startBankMachines(); + + for (auto it : bankMachines) + it.second->startBankMachine(); } } void ControllerNew::releasePayload() { - if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) - { - responseQueue.pop(); - payloadToRelease->release(); - payloadToRelease = nullptr; - numberOfPayloads--; - // TODO: insert payload ID - printDebugMessage("Payload ID left system."); - } + responseQueue.pop(); + payloadToRelease->release(); + payloadToRelease = nullptr; + numberOfPayloads--; + // TODO: insert payload ID + printDebugMessage("Payload ID left system."); } void ControllerNew::acquirePayload() { - if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) { - if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) - { - payloadToAcquire->acquire(); - scheduler->storeRequest(payloadToAcquire); - commandMux->insertPayload(payloadToAcquire); - numberOfPayloads++; - // TODO: insert payload ID - printDebugMessage("Payload ID entered system."); - payloadToAcquire->set_response_status(TLM_OK_RESPONSE); - tlm_phase tPhase = END_REQ; - sc_time tDelay = SC_ZERO_TIME; - recordPhase(*payloadToAcquire, tPhase, tDelay); - tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); - payloadToAcquire = nullptr; - } - else - printDebugMessage("Total number of payloads exceeded, backpressure!"); - } -} - -void ControllerNew::getNextBmStates() -{ - for (auto it : bankMachines) - { - tlm_generic_payload *result = it.second->getNextStateAndResult(); - if (result != nullptr) - { - responseQueue.push(result); - } + payloadToAcquire->acquire(); + scheduler->storeRequest(payloadToAcquire); + commandMux->insertPayload(payloadToAcquire); + numberOfPayloads++; + // TODO: insert payload ID + printDebugMessage("Payload ID entered system."); + payloadToAcquire->set_response_status(TLM_OK_RESPONSE); + tlm_phase tPhase = END_REQ; + sc_time tDelay = SC_ZERO_TIME; + recordPhase(*payloadToAcquire, tPhase, tDelay); + tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); + payloadToAcquire = nullptr; } + else + printDebugMessage("Total number of payloads exceeded, backpressure!"); } void ControllerNew::sendToFrontend() { - if (payloadToRelease == nullptr) - { - if (!responseQueue.empty()) - { - payloadToRelease = responseQueue.front(); - tlm_phase tPhase = BEGIN_RESP; - sc_time tDelay = SC_ZERO_TIME; - recordPhase(*payloadToRelease, tPhase, tDelay); - tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay); - } - } -} - -void ControllerNew::startBankMachines() -{ - for (auto it : bankMachines) - it.second->startBankMachine(); + payloadToRelease = responseQueue.front(); + tlm_phase tPhase = BEGIN_RESP; + sc_time tDelay = SC_ZERO_TIME; + recordPhase(*payloadToRelease, tPhase, tDelay); + tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay); } void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index ea059eb5..824978d5 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -70,9 +70,7 @@ private: void releasePayload(); void acquirePayload(); - void getNextBmStates(); void sendToFrontend(); - void startBankMachines(); }; #endif // CONTROLLERNEW_H From e1e53b5c2e1a3633ce8e900524de5cd57157c948 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 23 Jul 2019 16:20:38 +0200 Subject: [PATCH 034/183] Moved parts of logic from CommandMux::selectCommand to controlMethod, moved commandFinishedTime from BMs to Controller. --- .../library/src/controller/BankMachine.cpp | 10 ----- DRAMSys/library/src/controller/BankMachine.h | 3 -- DRAMSys/library/src/controller/CommandMux.cpp | 39 ++++++------------- DRAMSys/library/src/controller/CommandMux.h | 10 +---- .../library/src/controller/ControllerNew.cpp | 25 +++++++++--- .../library/src/controller/ControllerNew.h | 23 +++++------ 6 files changed, 44 insertions(+), 66 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 012c76ed..572e92c0 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -5,16 +5,6 @@ BankMachine::BankMachine(ControllerNew *controller, SchedulerNew *scheduler, CheckerDDR3New *checker, Bank bank) : controller(controller), scheduler(scheduler), checker(checker), bank(bank) {} -void BankMachine::setCommandFinishedTime(sc_time time) -{ - commandFinishedTime = time; -} - -sc_time BankMachine::getCommandFinishedTime() -{ - return commandFinishedTime; -} - tlm_generic_payload *BankMachine::getNextStateAndResult() { tlm_generic_payload *payloadToReturn = nullptr; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index e699d711..8a857d65 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -27,8 +27,6 @@ class BankMachine { public: BankMachine(ControllerNew *, SchedulerNew *, CheckerDDR3New*, Bank); - void setCommandFinishedTime(sc_time); - sc_time getCommandFinishedTime(); tlm_generic_payload *getNextStateAndResult(); void startBankMachine(); std::pair getNextCommand(); @@ -40,7 +38,6 @@ private: Row currentRow = Row(0); Command nextCommand = Command::NOP; sc_time timeToSchedule = SC_ZERO_TIME; - sc_time commandFinishedTime = SC_ZERO_TIME; ControllerNew *controller; SchedulerNew *scheduler; CheckerDDR3New *checker; diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 7aee2d15..3198c3a6 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -1,46 +1,29 @@ #include "CommandMux.h" #include "core/configuration/Configuration.h" -CommandMux::CommandMux(ControllerNew *controller, ControllerState *state, std::map &bankMachines) : - controller(controller), state(state), bankMachines(bankMachines) {} - void CommandMux::insertPayload(tlm_generic_payload *payload) { payloadOrder.push(payload); } -void CommandMux::selectCommand() +std::pair +CommandMux::selectCommand(std::vector> &readyCommands) { - for (auto it : bankMachines) + for (auto it : readyCommands) { - std::pair result = it.second->getNextCommand(); - if (result.first != Command::NOP) - readyCommands.push_back(result); + if (it.first == Command::ACT || it.first == Command::PRE) + return it; } - if (!readyCommands.empty()) + for (auto it : readyCommands) { - for (auto it : readyCommands) + if (it.first == Command::RD || it.first == Command::WR) { - if (it.first == Command::ACT || it.first == Command::PRE) + if (it.second == payloadOrder.front()) { - controller->sendToDram(it.first, it.second); - readyCommands.clear(); - return; + payloadOrder.pop(); + return it; } } - for (auto it : readyCommands) - { - if (it.first == Command::RD || it.first == Command::WR) - { - if (it.second == payloadOrder.front()) - { - payloadOrder.pop(); - controller->sendToDram(it.first, it.second); - readyCommands.clear(); - return; - } - } - } - readyCommands.clear(); } + return std::pair(Command::NOP, nullptr); } diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h index ba74115c..46a6ce33 100644 --- a/DRAMSys/library/src/controller/CommandMux.h +++ b/DRAMSys/library/src/controller/CommandMux.h @@ -10,21 +10,13 @@ using namespace tlm; -class ControllerNew; -class BankMachine; - class CommandMux { public: - CommandMux(ControllerNew *, ControllerState*, std::map &); void insertPayload(tlm_generic_payload *); - void selectCommand(); + std::pair selectCommand(std::vector> &); private: - ControllerState *state; - ControllerNew *controller; std::queue payloadOrder; - std::map &bankMachines; - std::vector> readyCommands; }; #endif // COMMANDMUX_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index f58bc9dc..073a9fa6 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -20,8 +20,11 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : checker = new CheckerDDR3New(Configuration::getInstance(), *state); scheduler = new SchedulerNew(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) + { bankMachines[Bank(bankID)] = new BankMachine(this, scheduler, checker, Bank(bankID)); - commandMux = new CommandMux(this, state, bankMachines); + commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; + } + commandMux = new CommandMux(); } ControllerNew::~ControllerNew() @@ -30,7 +33,6 @@ ControllerNew::~ControllerNew() delete checker; for (auto it : bankMachines) delete it.second; - delete commandMux; delete scheduler; } @@ -68,7 +70,7 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); Bank bank = DramExtension::getExtension(trans).getBank(); - bankMachines[bank]->setCommandFinishedTime(sc_time_stamp() + delay); + commandFinishedTime[bank] = sc_time_stamp() + delay; triggerEventQueueAfterDelay(delay); return TLM_ACCEPTED; } @@ -130,7 +132,7 @@ void ControllerNew::controllerMethod() for (auto it : bankMachines) { - if (it.second->getCommandFinishedTime() == sc_time_stamp()) + if (commandFinishedTime[it.first] == sc_time_stamp()) { tlm_generic_payload *result = it.second->getNextStateAndResult(); if (result != nullptr) @@ -144,7 +146,20 @@ void ControllerNew::controllerMethod() for (auto it : bankMachines) it.second->startBankMachine(); - commandMux->selectCommand(); + std::vector> readyCommands; + std::pair result; + for (auto it : bankMachines) + { + result = it.second->getNextCommand(); + if (result.second != nullptr) + readyCommands.push_back(result); + } + if (!readyCommands.empty()) + { + result = commandMux->selectCommand(readyCommands); + if (result.second != nullptr) + sendToDram(result.first, result.second); + } for (auto it : bankMachines) it.second->startBankMachine(); diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 824978d5..4eea4566 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -36,14 +36,6 @@ public: void triggerEventAfterDelay(sc_time); void triggerEventQueueAfterDelay(sc_time); - ControllerState *state; - std::map bankMachines; - CommandMux *commandMux; - SchedulerNew *scheduler; - CheckerDDR3New *checker; - - void sendToDram(Command, tlm_generic_payload *); - private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); @@ -64,13 +56,22 @@ private: TlmRecorder *tlmRecorder; DebugManager *debugManager; - void controllerMethod(); - sc_event triggerEvent; - sc_event_queue triggerEventQueue; + ControllerState *state; + std::map bankMachines; + CommandMux *commandMux; + SchedulerNew *scheduler; + CheckerDDR3New *checker; void releasePayload(); void acquirePayload(); void sendToFrontend(); + void sendToDram(Command, tlm_generic_payload *); + + void controllerMethod(); + sc_event triggerEvent; + sc_event_queue triggerEventQueue; + + std::map commandFinishedTime; }; #endif // CONTROLLERNEW_H From 7bd0950e1e18e6dd0d3206c91e678abe7fb8d2de Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 23 Jul 2019 21:30:29 +0200 Subject: [PATCH 035/183] Some minor changes. --- DRAMSys/library/src/controller/BankMachine.cpp | 2 -- DRAMSys/library/src/controller/BankMachine.h | 3 +++ DRAMSys/library/src/controller/CommandMux.cpp | 1 - DRAMSys/library/src/controller/CommandMux.h | 8 ++++---- DRAMSys/library/src/controller/ControllerNew.cpp | 15 ++++++++------- DRAMSys/library/src/controller/SchedulerNew.h | 4 ++-- 6 files changed, 17 insertions(+), 16 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 572e92c0..fe6606b0 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -1,6 +1,4 @@ #include "BankMachine.h" -#include "Command.h" -#include "core/scheduling/checker/CheckerDDR3New.h" BankMachine::BankMachine(ControllerNew *controller, SchedulerNew *scheduler, CheckerDDR3New *checker, Bank bank) : controller(controller), scheduler(scheduler), checker(checker), bank(bank) {} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 8a857d65..c03b54ef 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -3,9 +3,12 @@ #include #include +#include #include "../common/dramExtensions.h" +#include "ControllerNew.h" #include "Command.h" #include "SchedulerNew.h" +#include "core/scheduling/checker/CheckerDDR3New.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 3198c3a6..866e38a7 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -1,5 +1,4 @@ #include "CommandMux.h" -#include "core/configuration/Configuration.h" void CommandMux::insertPayload(tlm_generic_payload *payload) { diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h index 46a6ce33..67cb4f79 100644 --- a/DRAMSys/library/src/controller/CommandMux.h +++ b/DRAMSys/library/src/controller/CommandMux.h @@ -1,12 +1,12 @@ #ifndef COMMANDMUX_H #define COMMANDMUX_H -#include #include #include -#include "ControllerState.h" -#include "BankMachine.h" -#include "ControllerNew.h" +#include +#include +#include +#include "Command.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 073a9fa6..1e99b479 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -34,6 +34,7 @@ ControllerNew::~ControllerNew() for (auto it : bankMachines) delete it.second; delete scheduler; + delete commandMux; } tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, @@ -123,13 +124,13 @@ void ControllerNew::controllerMethod() if (lastTimeCalled != sc_time_stamp()) { lastTimeCalled = sc_time_stamp(); - + // Release payload if arbiter has accepted the result if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) releasePayload(); - + // Accept new request from arbiter if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) acquirePayload(); - + // Update states of bank machines and get results if ready for (auto it : bankMachines) { if (commandFinishedTime[it.first] == sc_time_stamp()) @@ -139,13 +140,13 @@ void ControllerNew::controllerMethod() responseQueue.push(result); } } - + // Send result to arbiter if (payloadToRelease == nullptr && !responseQueue.empty()) sendToFrontend(); - + // Start bank machines to issue new requests for (auto it : bankMachines) it.second->startBankMachine(); - + // Choose one request and send it to DRAM std::vector> readyCommands; std::pair result; for (auto it : bankMachines) @@ -160,7 +161,7 @@ void ControllerNew::controllerMethod() if (result.second != nullptr) sendToDram(result.first, result.second); } - + // Restart bank machines to issue new requests for the future for (auto it : bankMachines) it.second->startBankMachine(); } diff --git a/DRAMSys/library/src/controller/SchedulerNew.h b/DRAMSys/library/src/controller/SchedulerNew.h index 1dd17fab..e5dcf6d6 100644 --- a/DRAMSys/library/src/controller/SchedulerNew.h +++ b/DRAMSys/library/src/controller/SchedulerNew.h @@ -3,9 +3,9 @@ #include #include -#include "../common/dramExtensions.h" -#include "ControllerNew.h" +#include #include +#include "../common/dramExtensions.h" using namespace tlm; From f2ab2fe3ee43a276588a9680749c86e3eacdf31e Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 25 Jul 2019 16:40:03 +0200 Subject: [PATCH 036/183] Included first test for CommandMux. --- DRAMSys/unitTests/CommandMuxTests.cpp | 72 +++++++++++++++++++++++++++ DRAMSys/unitTests/Testfile.h | 2 +- DRAMSys/unitTests/unitTests.pro | 4 ++ 3 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 DRAMSys/unitTests/CommandMuxTests.cpp diff --git a/DRAMSys/unitTests/CommandMuxTests.cpp b/DRAMSys/unitTests/CommandMuxTests.cpp new file mode 100644 index 00000000..6fc2736c --- /dev/null +++ b/DRAMSys/unitTests/CommandMuxTests.cpp @@ -0,0 +1,72 @@ +#include +#include +#include +#include +#include "../library/src/controller/CommandMux.h" +#include "../library/src/controller/Command.h" + +class CommandMuxState +{ +public: + Command firstCommand; + Command secondCommand; + Command resultCommand; +}; + +class CommandMuxTestBase : public testing::Test +{ +public: + CommandMux *commandMux; + + tlm_generic_payload *firstPayload; + tlm_generic_payload *secondPayload; + + std::pair firstPair; + std::pair secondPair; + + std::vector> readyCommands; + + std::pair result; + + CommandMuxTestBase() + { + commandMux = new CommandMux(); + firstPayload = new tlm_generic_payload(); + secondPayload = new tlm_generic_payload(); + } + + ~CommandMuxTestBase() + { + delete commandMux; + delete firstPayload; + delete secondPayload; + } +}; + +class CommandMuxTestParam : public CommandMuxTestBase, public testing::WithParamInterface +{ +public: + CommandMuxTestParam() + { + commandMux->insertPayload(firstPayload); + commandMux->insertPayload(secondPayload); + + firstPair.first = GetParam().firstCommand; + firstPair.second = firstPayload; + secondPair.first = GetParam().secondCommand; + secondPair.second = secondPayload; + + readyCommands.push_back(secondPair); + readyCommands.push_back(firstPair); + result = commandMux->selectCommand(readyCommands); + } +}; + +TEST_P(CommandMuxTestParam, satisfiesCommandOrder) +{ + EXPECT_EQ(result.first, GetParam().resultCommand); +} + +INSTANTIATE_TEST_CASE_P(Default, CommandMuxTestParam, testing::Values( + CommandMuxState{Command::RD, Command::WR, Command::RD}, + CommandMuxState{Command::RD, Command::ACT, Command::ACT})); diff --git a/DRAMSys/unitTests/Testfile.h b/DRAMSys/unitTests/Testfile.h index 50726e5c..da025ef2 100644 --- a/DRAMSys/unitTests/Testfile.h +++ b/DRAMSys/unitTests/Testfile.h @@ -3,5 +3,5 @@ TEST(testsuite, test) { - EXPECT_EQ(commandToString(Command::Activate), "ACT"); + EXPECT_EQ(commandToString(Command::ACT), "ACT"); } diff --git a/DRAMSys/unitTests/unitTests.pro b/DRAMSys/unitTests/unitTests.pro index 375411e7..a39ed9a7 100644 --- a/DRAMSys/unitTests/unitTests.pro +++ b/DRAMSys/unitTests/unitTests.pro @@ -64,11 +64,15 @@ SOURCEHOME = ../library/src/ SOURCES += \ main.cpp \ + CommandMuxTests.cpp \ + $${SOURCEHOME}/controller/CommandMux.cpp \ $${SOURCEHOME}/controller/Command.cpp + HEADERS += \ Testfile.h \ + $${SOURCEHOME}/controller/CommandMux.h \ $${SOURCEHOME}/controller/Command.h DISTFILES += ../DRAMSys.astylerc From 3f913b5c16787c79dfb0b3a15e372bcc6b3ca290 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 26 Jul 2019 15:48:58 +0200 Subject: [PATCH 037/183] Arbiter now assigns each payload an ID for transaction order decision in CommandMux. --- DRAMSys/DRAMSys.pro | 4 +-- DRAMSys/library/src/common/dramExtensions.cpp | 33 ++++++++++++------- DRAMSys/library/src/common/dramExtensions.h | 8 +++-- DRAMSys/library/src/common/utils.cpp | 8 ++--- .../library/src/controller/BankMachine.cpp | 2 +- DRAMSys/library/src/controller/CommandMux.cpp | 10 ++---- DRAMSys/library/src/controller/CommandMux.h | 4 +-- .../library/src/controller/ControllerNew.cpp | 14 ++++---- DRAMSys/library/src/simulation/Arbiter.cpp | 9 ++--- DRAMSys/library/src/simulation/Arbiter.h | 1 + DRAMSys/library/src/simulation/IArbiter.h | 2 +- 11 files changed, 53 insertions(+), 42 deletions(-) diff --git a/DRAMSys/DRAMSys.pro b/DRAMSys/DRAMSys.pro index d4a5e29e..6070fb7b 100644 --- a/DRAMSys/DRAMSys.pro +++ b/DRAMSys/DRAMSys.pro @@ -25,12 +25,12 @@ isEmpty(systemc_home) { message(SystemC home is $${systemc_home}) SUBDIRS += library -SUBDIRS += unitTests +#SUBDIRS += unitTests SUBDIRS += simulator SUBDIRS += traceAnalyzer library.subdir = library -unitTests.subdir = unitTests +#unitTests.subdir = unitTests simulator.subdir = simulator traceAnalyzer.subdir = traceAnalyzer diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index ed1d0b0d..18ae9a40 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -44,25 +44,20 @@ using namespace tlm; DramExtension::DramExtension() : - thread(0), channel(0), bank(0), bankgroup(0), row(0), column(0), burstlength(0) -{ -} + thread(0), channel(0), bank(0), bankgroup(0), + row(0), column(0), burstlength(0), payloadID(0) {} DramExtension::DramExtension(const Thread &thread, const Bank &bank, const BankGroup &bankgroup, const Row &row, const Column &column, - unsigned int burstlength) : + unsigned int burstlength, unsigned int payloadID) : thread(thread), channel(0), bank(bank), bankgroup(bankgroup), row(row), - column(column), burstlength(burstlength) -{ -} + column(column), burstlength(burstlength), payloadID(payloadID) {} DramExtension::DramExtension(const Thread &thread, const Channel &channel, const Bank &bank, const BankGroup &bankgroup, const Row &row, - const Column &column, unsigned int burstlength) : + const Column &column, unsigned int burstlength, unsigned int payloadID) : thread(thread), channel(channel), bank(bank), bankgroup(bankgroup), row(row), - column(column), burstlength(burstlength) -{ -} + column(column), burstlength(burstlength), payloadID(payloadID) {} DramExtension &DramExtension::getExtension(const tlm_generic_payload *payload) { @@ -118,10 +113,19 @@ Row DramExtension::getRow(const tlm_generic_payload &payload) return DramExtension::getRow(&payload); } +unsigned int DramExtension::getPayloadID(const tlm_generic_payload *payload) +{ + return DramExtension::getExtension(payload).getPayloadID(); +} + +unsigned int DramExtension::getPayloadID(const tlm_generic_payload &payload) +{ + return DramExtension::getPayloadID(&payload); +} tlm_extension_base *DramExtension::clone() const { - return new DramExtension(thread, bank, bankgroup, row, column, burstlength); + return new DramExtension(thread, bank, bankgroup, row, column, burstlength, payloadID); } void DramExtension::copy_from(const tlm_extension_base &ext) @@ -170,6 +174,11 @@ unsigned int DramExtension::getBurstlength() const return burstlength; } +unsigned int DramExtension::getPayloadID() const +{ + return payloadID; +} + void DramExtension::incrementRow() { ++row; diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 3a4b1a51..4491f3ca 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -151,10 +151,10 @@ public: DramExtension(); DramExtension(const Thread &thread, const Bank &bank, const BankGroup &bankgroup, const Row &row, const Column &column, - unsigned int burstlength = 0); + unsigned int burstlength, unsigned int payloadID); DramExtension(const Thread &thread, const Channel &channel, const Bank &bank, const BankGroup &bankgroup, const Row &row, - const Column &column, unsigned int burstlength = 0); + const Column &column, unsigned int burstlength, unsigned int payloadID); virtual tlm_extension_base *clone() const; virtual void copy_from(const tlm_extension_base &ext); @@ -171,6 +171,8 @@ public: static Thread getThread(const tlm::tlm_generic_payload &payload); static Row getRow(const tlm::tlm_generic_payload *payload); static Row getRow(const tlm::tlm_generic_payload &payload); + static unsigned int getPayloadID(const tlm::tlm_generic_payload *payload); + static unsigned int getPayloadID(const tlm::tlm_generic_payload &payload); Thread getThread() const; Channel getChannel() const; @@ -180,6 +182,7 @@ public: Column getColumn() const; unsigned int getBurstlength() const; + unsigned int getPayloadID() const; void incrementRow(); private: @@ -190,6 +193,7 @@ private: Row row; Column column; unsigned int burstlength; + unsigned int payloadID; }; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 69c6f899..f80d2af9 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -245,10 +245,10 @@ void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank) payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread( - Controller::ControllerThreadId()), bank, BankGroup(0), Row(0), - Column(0))); //payload takes ownership - //TODO .. Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!! + payload.set_extension(new DramExtension(Thread(Controller::ControllerThreadId()), + bank, BankGroup(0), Row(0), Column(0), 0, 0)); + // payload takes ownership + // TODO: Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!! } std::string getFileName(std::string uri) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index fe6606b0..fac96d37 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -23,7 +23,7 @@ tlm_generic_payload *BankMachine::getNextStateAndResult() return payloadToReturn; } -void BankMachine::startBankMachine() +void BankMachine::startBankMachine() // TODO: return delay, do not trigger event inside { if (currentPayload == nullptr) { diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/CommandMux.cpp index 866e38a7..3a075e4c 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/CommandMux.cpp @@ -1,9 +1,5 @@ #include "CommandMux.h" - -void CommandMux::insertPayload(tlm_generic_payload *payload) -{ - payloadOrder.push(payload); -} +#include "../common/dramExtensions.h" std::pair CommandMux::selectCommand(std::vector> &readyCommands) @@ -17,9 +13,9 @@ CommandMux::selectCommand(std::vector> { if (it.first == Command::RD || it.first == Command::WR) { - if (it.second == payloadOrder.front()) + if (DramExtension::getPayloadID(it.second) == nextPayloadID) { - payloadOrder.pop(); + nextPayloadID++; return it; } } diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h index 67cb4f79..9f071a8e 100644 --- a/DRAMSys/library/src/controller/CommandMux.h +++ b/DRAMSys/library/src/controller/CommandMux.h @@ -13,10 +13,10 @@ using namespace tlm; class CommandMux { public: - void insertPayload(tlm_generic_payload *); std::pair selectCommand(std::vector> &); + private: - std::queue payloadOrder; + unsigned nextPayloadID = 0; }; #endif // COMMANDMUX_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 1e99b479..39f5a184 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -97,11 +97,12 @@ void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_ unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); unsigned int row = DramExtension::getExtension(trans).getRow().ID(); unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); + unsigned int id = DramExtension::getExtension(trans).getPayloadID(); printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " at " + recTime.to_string()); + to_string(col) + " id " + to_string(id) + " at " + recTime.to_string()); tlmRecorder->recordPhase(trans, phase, recTime); } @@ -125,7 +126,7 @@ void ControllerNew::controllerMethod() { lastTimeCalled = sc_time_stamp(); // Release payload if arbiter has accepted the result - if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) + if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) releasePayload(); // Accept new request from arbiter if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) @@ -169,24 +170,23 @@ void ControllerNew::controllerMethod() void ControllerNew::releasePayload() { + unsigned id = DramExtension::getPayloadID(payloadToRelease); responseQueue.pop(); payloadToRelease->release(); payloadToRelease = nullptr; numberOfPayloads--; - // TODO: insert payload ID - printDebugMessage("Payload ID left system."); + printDebugMessage("Payload " + std::to_string(id) + " left system."); } void ControllerNew::acquirePayload() { if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) { + unsigned id = DramExtension::getPayloadID(payloadToAcquire); payloadToAcquire->acquire(); scheduler->storeRequest(payloadToAcquire); - commandMux->insertPayload(payloadToAcquire); numberOfPayloads++; - // TODO: insert payload ID - printDebugMessage("Payload ID entered system."); + printDebugMessage("Payload " + std::to_string(id) + " entered system."); payloadToAcquire->set_response_status(TLM_OK_RESPONSE); tlm_phase tPhase = END_REQ; sc_time tDelay = SC_ZERO_TIME; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index c68927f8..1c1074a2 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -51,6 +51,7 @@ Arbiter::Arbiter(sc_module_name /*name*/) : payloadEventQueue(this, &Arbiter::pe { channelIsFree.push_back(true); pendingRequests.push_back(queue()); + nextPayloadID.push_back(0); } // One or more devices can accesss all the memory units through the arbiter. @@ -214,10 +215,10 @@ void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress(payload.get_address()); // Check the valid range of decodedAddress if (addressIsValid(decodedAddress)) { - DramExtension *extension = new DramExtension(Thread(socketId), - Channel(decodedAddress.channel), Bank(decodedAddress.bank), - BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), - Column(decodedAddress.column), burstlength); + DramExtension *extension = new DramExtension(Thread(socketId), Channel(decodedAddress.channel), + Bank(decodedAddress.bank), BankGroup(decodedAddress.bankgroup), + Row(decodedAddress.row), Column(decodedAddress.column), + burstlength, nextPayloadID[decodedAddress.channel]++); payload.set_auto_extension(extension); } else { SC_REPORT_FATAL("Arbiter", "Decoded Address is not inside the valid range"); diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 672862c8..206cd605 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -96,6 +96,7 @@ private: const tlm_phase &phase, const sc_time &delay); void appendDramExtension(int socketId, tlm_generic_payload &payload); + std::vector nextPayloadID; bool addressIsValid(DecodedAddress &decodedAddress); diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 872fd929..a9c5ebd4 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -109,7 +109,7 @@ protected: DramExtension *extension = new DramExtension(Thread(socketId + 1), Channel(decodedAddress.channel), Bank(decodedAddress.bank), BankGroup(decodedAddress.bankgroup), Row(decodedAddress.row), - Column(decodedAddress.column), burstlength); + Column(decodedAddress.column), burstlength, 0); payload.set_auto_extension(extension); } else { SC_REPORT_FATAL("Arbiter", "Decoded Address are not inside the valid range"); From c4c2640594b61df279426d9ba651f8fcc5dec9a9 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 26 Jul 2019 16:28:22 +0200 Subject: [PATCH 038/183] Moved event trigger out of BankMachine. --- .../resources/configs/simulator/ddr3.xml | 2 +- .../library/src/controller/BankMachine.cpp | 22 +++++++++---------- DRAMSys/library/src/controller/BankMachine.h | 4 ++-- .../library/src/controller/ControllerNew.cpp | 12 +++++++--- .../library/src/controller/ControllerNew.h | 5 ++--- 5 files changed, 24 insertions(+), 21 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index 1613737f..f43e4b8c 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,6 +1,6 @@ - + diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index fac96d37..8f3eabd1 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -1,7 +1,7 @@ #include "BankMachine.h" -BankMachine::BankMachine(ControllerNew *controller, SchedulerNew *scheduler, CheckerDDR3New *checker, Bank bank) - : controller(controller), scheduler(scheduler), checker(checker), bank(bank) {} +BankMachine::BankMachine(SchedulerNew *scheduler, CheckerDDR3New *checker, Bank bank) + : scheduler(scheduler), checker(checker), bank(bank) {} tlm_generic_payload *BankMachine::getNextStateAndResult() { @@ -23,18 +23,18 @@ tlm_generic_payload *BankMachine::getNextStateAndResult() return payloadToReturn; } -void BankMachine::startBankMachine() // TODO: return delay, do not trigger event inside +sc_time BankMachine::startBankMachine() // TODO: return delay, do not trigger event inside { if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(bank); if (currentPayload == nullptr) - return; + return SC_ZERO_TIME; } + sc_time delay; if (currentState == BmState::Precharged) { - sc_time delay = checker->delayToSatisfyConstraints(Command::ACT, bank); - controller->triggerEventAfterDelay(delay); + delay = checker->delayToSatisfyConstraints(Command::ACT, bank); nextCommand = Command::ACT; timeToSchedule = sc_time_stamp() + delay; } @@ -45,15 +45,13 @@ void BankMachine::startBankMachine() // TODO: return delay, do not trigger event { if (currentPayload->get_command() == TLM_READ_COMMAND) { - sc_time delay = checker->delayToSatisfyConstraints(Command::RD, bank); - controller->triggerEventAfterDelay(delay); + delay = checker->delayToSatisfyConstraints(Command::RD, bank); nextCommand = Command::RD; timeToSchedule = sc_time_stamp() + delay; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - sc_time delay = checker->delayToSatisfyConstraints(Command::WR, bank); - controller->triggerEventAfterDelay(delay); + delay = checker->delayToSatisfyConstraints(Command::WR, bank); nextCommand = Command::WR; timeToSchedule = sc_time_stamp() + delay; } @@ -62,13 +60,13 @@ void BankMachine::startBankMachine() // TODO: return delay, do not trigger event } else // row miss { - sc_time delay = checker->delayToSatisfyConstraints(Command::PRE, bank); - controller->triggerEventAfterDelay(delay); + delay = checker->delayToSatisfyConstraints(Command::PRE, bank); nextCommand = Command::PRE; timeToSchedule = sc_time_stamp() + delay; currentRow = extension.getRow(); } } + return delay; } std::pair BankMachine::getNextCommand() diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index c03b54ef..b0698bdc 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -29,9 +29,9 @@ enum class BmState class BankMachine { public: - BankMachine(ControllerNew *, SchedulerNew *, CheckerDDR3New*, Bank); + BankMachine(SchedulerNew *, CheckerDDR3New*, Bank); tlm_generic_payload *getNextStateAndResult(); - void startBankMachine(); + sc_time startBankMachine(); std::pair getNextCommand(); void updateState(Command); private: diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 39f5a184..4f5f2262 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -21,7 +21,7 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : scheduler = new SchedulerNew(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - bankMachines[Bank(bankID)] = new BankMachine(this, scheduler, checker, Bank(bankID)); + bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; } commandMux = new CommandMux(); @@ -146,7 +146,10 @@ void ControllerNew::controllerMethod() sendToFrontend(); // Start bank machines to issue new requests for (auto it : bankMachines) - it.second->startBankMachine(); + { + sc_time delay = it.second->startBankMachine(); + triggerEventAfterDelay(delay); + } // Choose one request and send it to DRAM std::vector> readyCommands; std::pair result; @@ -164,7 +167,10 @@ void ControllerNew::controllerMethod() } // Restart bank machines to issue new requests for the future for (auto it : bankMachines) - it.second->startBankMachine(); + { + sc_time delay = it.second->startBankMachine(); + triggerEventAfterDelay(delay); + } } } diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 4eea4566..cad2cbf6 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -33,9 +33,6 @@ public: tlm_utils::simple_target_socket tSocket; tlm_utils::simple_initiator_socket iSocket; - void triggerEventAfterDelay(sc_time); - void triggerEventQueueAfterDelay(sc_time); - private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); @@ -69,7 +66,9 @@ private: void controllerMethod(); sc_event triggerEvent; + void triggerEventAfterDelay(sc_time); sc_event_queue triggerEventQueue; + void triggerEventQueueAfterDelay(sc_time); std::map commandFinishedTime; }; From 215790a931552d19464dd4950a0dd6b64dead241 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 27 Jul 2019 19:24:09 +0200 Subject: [PATCH 039/183] Created different schedulers (Fifo and FrFcfs) and a scheduler interface. --- DRAMSys/library/library.pro | 9 ++- .../library/src/controller/BankMachine.cpp | 2 +- .../library/src/controller/ControllerNew.cpp | 61 +++++++++++-------- .../library/src/controller/SchedulerNew.cpp | 2 +- .../controller/scheduler/SchedulerFifo.cpp | 19 ++++++ .../src/controller/scheduler/SchedulerFifo.h | 22 +++++++ .../controller/scheduler/SchedulerFrFcfs.cpp | 41 +++++++++++++ .../controller/scheduler/SchedulerFrFcfs.h | 22 +++++++ .../src/controller/scheduler/SchedulerIF.h | 24 ++++++++ 9 files changed, 172 insertions(+), 30 deletions(-) create mode 100644 DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp create mode 100644 DRAMSys/library/src/controller/scheduler/SchedulerFifo.h create mode 100644 DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp create mode 100644 DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h create mode 100644 DRAMSys/library/src/controller/scheduler/SchedulerIF.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index adae5930..5d29f14e 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -153,7 +153,9 @@ SOURCES += \ src/controller/BankMachine.cpp \ src/controller/CommandMux.cpp \ src/controller/ControllerNew.cpp \ - src/controller/SchedulerNew.cpp + src/controller/SchedulerNew.cpp \ + src/controller/scheduler/SchedulerFifo.cpp \ + src/controller/scheduler/SchedulerFrFcfs.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -240,7 +242,10 @@ HEADERS += \ src/controller/BankMachine.h \ src/controller/CommandMux.h \ src/controller/ControllerNew.h \ - src/controller/SchedulerNew.h + src/controller/SchedulerNew.h \ + src/controller/scheduler/SchedulerIF.h \ + src/controller/scheduler/SchedulerFifo.h \ + src/controller/scheduler/SchedulerFrFcfs.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 8f3eabd1..cda7bf3f 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -23,7 +23,7 @@ tlm_generic_payload *BankMachine::getNextStateAndResult() return payloadToReturn; } -sc_time BankMachine::startBankMachine() // TODO: return delay, do not trigger event inside +sc_time BankMachine::startBankMachine() { if (currentPayload == nullptr) { diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 4f5f2262..a50d8761 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -125,13 +125,19 @@ void ControllerNew::controllerMethod() if (lastTimeCalled != sc_time_stamp()) { lastTimeCalled = sc_time_stamp(); - // Release payload if arbiter has accepted the result + + // (1) Release payload if arbiter has accepted the result if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) releasePayload(); - // Accept new request from arbiter - if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + + // (2) Accept new request from arbiter + if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr + && numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) acquirePayload(); - // Update states of bank machines and get results if ready + else + printDebugMessage("Total number of payloads exceeded, backpressure!"); + + // (3) Update states of bank machines and get results if ready for (auto it : bankMachines) { if (commandFinishedTime[it.first] == sc_time_stamp()) @@ -141,16 +147,19 @@ void ControllerNew::controllerMethod() responseQueue.push(result); } } - // Send result to arbiter + + // (4) Send result to arbiter if (payloadToRelease == nullptr && !responseQueue.empty()) sendToFrontend(); - // Start bank machines to issue new requests + + // (5) Start bank machines to issue new requests for (auto it : bankMachines) { sc_time delay = it.second->startBankMachine(); triggerEventAfterDelay(delay); } - // Choose one request and send it to DRAM + + // (6) Choose one request and send it to DRAM std::vector> readyCommands; std::pair result; for (auto it : bankMachines) @@ -165,7 +174,8 @@ void ControllerNew::controllerMethod() if (result.second != nullptr) sendToDram(result.first, result.second); } - // Restart bank machines to issue new requests for the future + + // (7) Restart bank machines to issue new requests for the future for (auto it : bankMachines) { sc_time delay = it.second->startBankMachine(); @@ -177,31 +187,30 @@ void ControllerNew::controllerMethod() void ControllerNew::releasePayload() { unsigned id = DramExtension::getPayloadID(payloadToRelease); + printDebugMessage("Payload " + std::to_string(id) + " left system."); + responseQueue.pop(); payloadToRelease->release(); - payloadToRelease = nullptr; numberOfPayloads--; - printDebugMessage("Payload " + std::to_string(id) + " left system."); + payloadToRelease = nullptr; } void ControllerNew::acquirePayload() { - if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) - { - unsigned id = DramExtension::getPayloadID(payloadToAcquire); - payloadToAcquire->acquire(); - scheduler->storeRequest(payloadToAcquire); - numberOfPayloads++; - printDebugMessage("Payload " + std::to_string(id) + " entered system."); - payloadToAcquire->set_response_status(TLM_OK_RESPONSE); - tlm_phase tPhase = END_REQ; - sc_time tDelay = SC_ZERO_TIME; - recordPhase(*payloadToAcquire, tPhase, tDelay); - tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); - payloadToAcquire = nullptr; - } - else - printDebugMessage("Total number of payloads exceeded, backpressure!"); + unsigned id = DramExtension::getPayloadID(payloadToAcquire); + printDebugMessage("Payload " + std::to_string(id) + " entered system."); + + scheduler->storeRequest(payloadToAcquire); + payloadToAcquire->acquire(); + numberOfPayloads++; + + payloadToAcquire->set_response_status(TLM_OK_RESPONSE); + tlm_phase tPhase = END_REQ; + sc_time tDelay = SC_ZERO_TIME; + recordPhase(*payloadToAcquire, tPhase, tDelay); + tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); + + payloadToAcquire = nullptr; } void ControllerNew::sendToFrontend() diff --git a/DRAMSys/library/src/controller/SchedulerNew.cpp b/DRAMSys/library/src/controller/SchedulerNew.cpp index 7f3d5df3..bef8b8b9 100644 --- a/DRAMSys/library/src/controller/SchedulerNew.cpp +++ b/DRAMSys/library/src/controller/SchedulerNew.cpp @@ -3,7 +3,7 @@ void SchedulerNew::storeRequest(tlm_generic_payload *payload) { - Bank bank = DramExtension::getExtension(payload).getBank(); + Bank bank = DramExtension::getBank(payload); buffer[bank].emplace_back(payload); } diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp new file mode 100644 index 00000000..1e459590 --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -0,0 +1,19 @@ +#include "SchedulerFifo.h" + +void SchedulerFifo::storeRequest(tlm_generic_payload *payload) +{ + Bank bank = DramExtension::getBank(payload); + buffer[bank].push(payload); +} + +tlm_generic_payload *SchedulerFifo::getNextRequest(Bank bank, BmState, Row) +{ + if (!buffer[bank].empty()) + { + tlm_generic_payload *result = buffer[bank].front(); + buffer[bank].pop(); + return result; + } + else + return nullptr; +} diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h new file mode 100644 index 00000000..372f9eaf --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -0,0 +1,22 @@ +#ifndef SCHEDULERFIFO_H +#define SCHEDULERFIFO_H + +#include +#include +#include +#include "SchedulerIF.h" +#include "../../common/dramExtensions.h" +#include "../BankMachine.h" + +using namespace tlm; + +class SchedulerFifo : public SchedulerIF +{ +public: + void storeRequest(tlm_generic_payload *); + tlm_generic_payload *getNextRequest(Bank, BmState, Row); +private: + std::map> buffer; +}; + +#endif // SCHEDULERFIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp new file mode 100644 index 00000000..5f3cd411 --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -0,0 +1,41 @@ +#include "SchedulerFrFcfs.h" +#include + +void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) +{ + Bank bank = DramExtension::getBank(payload); + buffer[bank].push_back(payload); +} + +tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BmState state, Row openRow) +{ + if (!buffer[bank].empty()) + { + if (state == BmState::Precharged) + { + tlm_generic_payload *result = buffer[bank].front(); + buffer[bank].erase(buffer[bank].begin()); + return result; + } + else if (state == BmState::Activated) + { + // Search for row hit + for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) + { + if (DramExtension::getRow(*it) == openRow) + { + tlm_generic_payload *result = *it; + buffer[bank].erase(it); + return result; + } + } + // No row hit found + tlm_generic_payload *result = buffer[bank].front(); + buffer[bank].erase(buffer[bank].begin()); + return result; + } + else + SC_REPORT_FATAL("SchedulerFrFcfs", "Wrong BM state!"); + } + return nullptr; +} diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h new file mode 100644 index 00000000..27db26cb --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -0,0 +1,22 @@ +#ifndef SCHEDULERFRFCFS_H +#define SCHEDULERFRFCFS_H + +#include +#include +#include +#include "SchedulerIF.h" +#include "../../common/dramExtensions.h" +#include "../BankMachine.h" + +using namespace tlm; + +class SchedulerFrFcfs : public SchedulerIF +{ +public: + void storeRequest(tlm_generic_payload *); + tlm_generic_payload *getNextRequest(Bank, BmState, Row); +private: + std::map> buffer; +}; + +#endif // SCHEDULERFRFCFS_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h new file mode 100644 index 00000000..da72118e --- /dev/null +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -0,0 +1,24 @@ +#ifndef SCHEDULERIF_H +#define SCHEDULERIF_H + +#include +#include "../../common/dramExtensions.h" +#include "../../common/DebugManager.h" +#include "../BankMachine.h" + +using namespace tlm; + +class SchedulerIF +{ +public: + virtual ~SchedulerIF() {} + virtual void storeRequest(tlm_generic_payload *) = 0; + virtual tlm_generic_payload *getNextRequest(Bank, BmState, Row) = 0; +protected: + void printDebugMessage(std::string message) + { + DebugManager::getInstance().printDebugMessage("Scheduler", message); + } +}; + +#endif // SCHEDULERIF_H From 733525e787219022b4094c88bbfedc00975fcca6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 27 Jul 2019 21:12:22 +0200 Subject: [PATCH 040/183] Included command mux which selects the oldest payload and a command mux interface. --- DRAMSys/library/library.pro | 13 +++++----- .../library/src/controller/BankMachine.cpp | 4 +-- DRAMSys/library/src/controller/BankMachine.h | 10 +++----- DRAMSys/library/src/controller/CommandMux.h | 22 ---------------- .../library/src/controller/ControllerNew.cpp | 9 ++++--- .../library/src/controller/ControllerNew.h | 11 ++++---- .../library/src/controller/SchedulerNew.cpp | 25 ------------------- DRAMSys/library/src/controller/SchedulerNew.h | 22 ---------------- .../library/src/controller/cmdmux/CmdMuxIF.h | 19 ++++++++++++++ .../src/controller/cmdmux/CmdMuxOldest.cpp | 23 +++++++++++++++++ .../src/controller/cmdmux/CmdMuxOldest.h | 13 ++++++++++ .../CmdMuxStrict.cpp} | 6 ++--- .../src/controller/cmdmux/CmdMuxStrict.h | 16 ++++++++++++ .../src/controller/scheduler/SchedulerIF.h | 2 ++ 14 files changed, 100 insertions(+), 95 deletions(-) delete mode 100644 DRAMSys/library/src/controller/CommandMux.h delete mode 100644 DRAMSys/library/src/controller/SchedulerNew.cpp delete mode 100644 DRAMSys/library/src/controller/SchedulerNew.h create mode 100644 DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h create mode 100644 DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp create mode 100644 DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h rename DRAMSys/library/src/controller/{CommandMux.cpp => cmdmux/CmdMuxStrict.cpp} (76%) create mode 100644 DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 5d29f14e..8f8d6e9f 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -151,11 +151,11 @@ SOURCES += \ src/controller/core/configuration/MemSpec.cpp \ src/controller/core/scheduling/checker/CheckerDDR3New.cpp \ src/controller/BankMachine.cpp \ - src/controller/CommandMux.cpp \ src/controller/ControllerNew.cpp \ - src/controller/SchedulerNew.cpp \ src/controller/scheduler/SchedulerFifo.cpp \ - src/controller/scheduler/SchedulerFrFcfs.cpp + src/controller/scheduler/SchedulerFrFcfs.cpp \ + src/controller/cmdmux/CmdMuxStrict.cpp \ + src/controller/cmdmux/CmdMuxOldest.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -240,12 +240,13 @@ HEADERS += \ src/controller/GenericController.h \ src/controller/core/scheduling/checker/CheckerDDR3New.h \ src/controller/BankMachine.h \ - src/controller/CommandMux.h \ src/controller/ControllerNew.h \ - src/controller/SchedulerNew.h \ src/controller/scheduler/SchedulerIF.h \ src/controller/scheduler/SchedulerFifo.h \ - src/controller/scheduler/SchedulerFrFcfs.h + src/controller/scheduler/SchedulerFrFcfs.h \ + src/controller/cmdmux/CmdMuxIF.h \ + src/controller/cmdmux/CmdMuxStrict.h \ + src/controller/cmdmux/CmdMuxOldest.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index cda7bf3f..2a2e09e0 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -1,6 +1,6 @@ #include "BankMachine.h" -BankMachine::BankMachine(SchedulerNew *scheduler, CheckerDDR3New *checker, Bank bank) +BankMachine::BankMachine(SchedulerIF *scheduler, CheckerDDR3New *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) {} tlm_generic_payload *BankMachine::getNextStateAndResult() @@ -27,7 +27,7 @@ sc_time BankMachine::startBankMachine() { if (currentPayload == nullptr) { - currentPayload = scheduler->getNextRequest(bank); + currentPayload = scheduler->getNextRequest(bank, currentState, currentRow); if (currentPayload == nullptr) return SC_ZERO_TIME; } diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index b0698bdc..535b1296 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -7,13 +7,12 @@ #include "../common/dramExtensions.h" #include "ControllerNew.h" #include "Command.h" -#include "SchedulerNew.h" +#include "scheduler/SchedulerIF.h" #include "core/scheduling/checker/CheckerDDR3New.h" using namespace tlm; -class ControllerNew; -class SchedulerNew; +class SchedulerIF; class CheckerDDR3New; enum class BmState @@ -29,7 +28,7 @@ enum class BmState class BankMachine { public: - BankMachine(SchedulerNew *, CheckerDDR3New*, Bank); + BankMachine(SchedulerIF *, CheckerDDR3New*, Bank); tlm_generic_payload *getNextStateAndResult(); sc_time startBankMachine(); std::pair getNextCommand(); @@ -41,8 +40,7 @@ private: Row currentRow = Row(0); Command nextCommand = Command::NOP; sc_time timeToSchedule = SC_ZERO_TIME; - ControllerNew *controller; - SchedulerNew *scheduler; + SchedulerIF *scheduler; CheckerDDR3New *checker; }; diff --git a/DRAMSys/library/src/controller/CommandMux.h b/DRAMSys/library/src/controller/CommandMux.h deleted file mode 100644 index 9f071a8e..00000000 --- a/DRAMSys/library/src/controller/CommandMux.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef COMMANDMUX_H -#define COMMANDMUX_H - -#include -#include -#include -#include -#include -#include "Command.h" - -using namespace tlm; - -class CommandMux -{ -public: - std::pair selectCommand(std::vector> &); - -private: - unsigned nextPayloadID = 0; -}; - -#endif // COMMANDMUX_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index a50d8761..72ee2b2d 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -1,6 +1,9 @@ #include "ControllerNew.h" #include "core/configuration/Configuration.h" -#include "scheduler/FifoStrict.h" +#include "scheduler/SchedulerFifo.h" +#include "scheduler/SchedulerFrFcfs.h" +#include "cmdmux/CmdMuxStrict.h" +#include "cmdmux/CmdMuxOldest.h" #include "../common/dramExtensions.h" #include "../common/protocol.h" #include "core/scheduling/ScheduledCommand.h" @@ -18,13 +21,13 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : state = new ControllerState("Controller", &Configuration::getInstance()); checker = new CheckerDDR3New(Configuration::getInstance(), *state); - scheduler = new SchedulerNew(); + scheduler = new SchedulerFrFcfs(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; } - commandMux = new CommandMux(); + commandMux = new CmdMuxOldest(); } ControllerNew::~ControllerNew() diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index cad2cbf6..7fa4ab94 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -10,8 +10,8 @@ #include #include "../common/dramExtensions.h" #include "BankMachine.h" -#include "CommandMux.h" -#include "SchedulerNew.h" +#include "cmdmux/CmdMuxIF.h" +#include "scheduler/SchedulerIF.h" #include "../common/TlmRecorder.h" #include "../common/DebugManager.h" #include "core/scheduling/checker/CheckerDDR3New.h" @@ -19,9 +19,8 @@ using namespace tlm; -class SchedulerNew; class BankMachine; -class CommandMux; +class SchedulerIF; class ControllerNew : public sc_module { @@ -55,8 +54,8 @@ private: ControllerState *state; std::map bankMachines; - CommandMux *commandMux; - SchedulerNew *scheduler; + CmdMuxIF *commandMux; + SchedulerIF *scheduler; CheckerDDR3New *checker; void releasePayload(); diff --git a/DRAMSys/library/src/controller/SchedulerNew.cpp b/DRAMSys/library/src/controller/SchedulerNew.cpp deleted file mode 100644 index bef8b8b9..00000000 --- a/DRAMSys/library/src/controller/SchedulerNew.cpp +++ /dev/null @@ -1,25 +0,0 @@ -#include "SchedulerNew.h" -#include "../common/DebugManager.h" - -void SchedulerNew::storeRequest(tlm_generic_payload *payload) -{ - Bank bank = DramExtension::getBank(payload); - buffer[bank].emplace_back(payload); -} - -tlm_generic_payload *SchedulerNew::getNextRequest(Bank bank) -{ - if (!buffer[bank].empty()) - { - tlm_generic_payload *payload = buffer[bank].front(); - buffer[bank].pop_front(); - return payload; - } - else - return nullptr; -} - -void SchedulerNew::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage("Scheduler", message); -} diff --git a/DRAMSys/library/src/controller/SchedulerNew.h b/DRAMSys/library/src/controller/SchedulerNew.h deleted file mode 100644 index e5dcf6d6..00000000 --- a/DRAMSys/library/src/controller/SchedulerNew.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef SCHEDULERNEW_H -#define SCHEDULERNEW_H - -#include -#include -#include -#include -#include "../common/dramExtensions.h" - -using namespace tlm; - -class SchedulerNew -{ -public: - void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(Bank bank); -private: - void printDebugMessage(std::string message); - std::map> buffer; -}; - -#endif // SCHEDULERNEW_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h new file mode 100644 index 00000000..7e700862 --- /dev/null +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h @@ -0,0 +1,19 @@ +#ifndef CMDMUXIF_H +#define CMDMUXIF_H + +#include +#include +#include +#include "../Command.h" + +using namespace tlm; + +class CmdMuxIF +{ +public: + virtual ~CmdMuxIF() {} + virtual std::pair + selectCommand(std::vector> &) = 0; +}; + +#endif // CMDMUXIF_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp new file mode 100644 index 00000000..d912e4de --- /dev/null +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -0,0 +1,23 @@ +#include "CmdMuxOldest.h" +#include "../../common/dramExtensions.h" + +std::pair +CmdMuxOldest::selectCommand(std::vector> &readyCommands) +{ + auto it = readyCommands.begin(); + auto result = it; + unsigned lastPayloadID = DramExtension::getPayloadID(it->second); + it++; + + while (it != readyCommands.end()) + { + unsigned newPayloadID = DramExtension::getPayloadID(it->second); + if (newPayloadID < lastPayloadID) + { + lastPayloadID = newPayloadID; + result = it; + } + it++; + } + return *result; +} diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h new file mode 100644 index 00000000..cb3c1d1d --- /dev/null +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h @@ -0,0 +1,13 @@ +#ifndef CMDMUXOLDEST_H +#define CMDMUXOLDEST_H + +#include "CmdMuxIF.h" + +class CmdMuxOldest : public CmdMuxIF +{ +public: + std::pair + selectCommand(std::vector> &); +}; + +#endif // CMDMUXOLDEST_H diff --git a/DRAMSys/library/src/controller/CommandMux.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp similarity index 76% rename from DRAMSys/library/src/controller/CommandMux.cpp rename to DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index 3a075e4c..0b39329e 100644 --- a/DRAMSys/library/src/controller/CommandMux.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -1,8 +1,8 @@ -#include "CommandMux.h" -#include "../common/dramExtensions.h" +#include "CmdMuxStrict.h" +#include "../../common/dramExtensions.h" std::pair -CommandMux::selectCommand(std::vector> &readyCommands) +CmdMuxStrict::selectCommand(std::vector> &readyCommands) { for (auto it : readyCommands) { diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h new file mode 100644 index 00000000..1b70b695 --- /dev/null +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h @@ -0,0 +1,16 @@ +#ifndef CMDMUXSTRICT_H +#define CMDMUXSTRICT_H + +#include "CmdMuxIF.h" + +class CmdMuxStrict : public CmdMuxIF +{ +public: + std::pair + selectCommand(std::vector> &); + +private: + unsigned nextPayloadID = 0; +}; + +#endif // CMDMUXSTRICT_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index da72118e..7170591c 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -8,6 +8,8 @@ using namespace tlm; +enum class BmState; + class SchedulerIF { public: From e0743b71d63ff0c76aecf136d013985fb82d5f3a Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 28 Jul 2019 20:45:03 +0200 Subject: [PATCH 041/183] Small improvement in ControllerNew (redundant event triggers), renaming in ControllerState. --- .../library/src/controller/ControllerNew.cpp | 15 ++-- .../src/controller/ControllerState.cpp | 4 +- .../library/src/controller/ControllerState.h | 18 +++-- .../src/controller/RecordableController.cpp | 2 +- .../core/scheduling/checker/ActBChecker.cpp | 4 +- .../scheduling/checker/ActivateChecker.cpp | 4 +- .../core/scheduling/checker/CheckerDDR3.cpp | 68 +++++++++---------- .../scheduling/checker/CheckerDDR3New.cpp | 48 ++++++------- .../scheduling/checker/PowerDownChecker.cpp | 6 +- .../core/scheduling/checker/PreBChecker.cpp | 4 +- .../checker/PrechargeAllChecker.cpp | 2 +- .../scheduling/checker/PrechargeChecker.cpp | 2 +- .../core/scheduling/checker/ReadChecker.cpp | 2 +- 13 files changed, 90 insertions(+), 89 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 72ee2b2d..9ec6afb7 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -21,13 +21,13 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : state = new ControllerState("Controller", &Configuration::getInstance()); checker = new CheckerDDR3New(Configuration::getInstance(), *state); - scheduler = new SchedulerFrFcfs(); + scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; } - commandMux = new CmdMuxOldest(); + commandMux = new CmdMuxStrict(); } ControllerNew::~ControllerNew() @@ -155,12 +155,9 @@ void ControllerNew::controllerMethod() if (payloadToRelease == nullptr && !responseQueue.empty()) sendToFrontend(); - // (5) Start bank machines to issue new requests + // (5) Start bank machines to issue new requests for current time for (auto it : bankMachines) - { - sc_time delay = it.second->startBankMachine(); - triggerEventAfterDelay(delay); - } + it.second->startBankMachine(); // (6) Choose one request and send it to DRAM std::vector> readyCommands; @@ -243,14 +240,14 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::RD) { phase = BEGIN_RD; - ScheduledCommand scheduledCommand = state->getLastCommand(command, bank); + ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } else if (command == Command::WR) { phase = BEGIN_WR; - ScheduledCommand scheduledCommand = state->getLastCommand(command, bank); + ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index fc56c269..494d5ab3 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -41,7 +41,7 @@ using namespace std; -const ScheduledCommand ControllerState::getLastCommand(Command command, +const ScheduledCommand ControllerState::getLastCommandOnBank(Command command, Bank bank) //TODO const reference? and make const { return lastScheduledByCommandAndBank[command][bank]; @@ -52,7 +52,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command) ScheduledCommand max; for (unsigned int i = 0; i < config->memSpec->NumberOfBanks; ++i) { - ScheduledCommand current = getLastCommand(command, Bank(i)); + ScheduledCommand current = getLastCommandOnBank(command, Bank(i)); if (current.getStart() > max.getStart()) max = current; } diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 19cde85b..58bdcd8c 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -48,15 +48,19 @@ class ControllerState { public: - ControllerState(std::string ownerName, - Configuration *config) : bus(config->memSpec->clk), ownerName(ownerName), + ControllerState(std::string ownerName, Configuration *config) + : bus(config->memSpec->clk), ownerName(ownerName), config(config) { rowBufferStates = new RowBufferState(ownerName); } - virtual ~ControllerState() {} - const ScheduledCommand getLastCommand(Command command, Bank bank); + virtual ~ControllerState() + { + delete rowBufferStates; + } + + const ScheduledCommand getLastCommandOnBank(Command command, Bank bank); const ScheduledCommand getLastCommand(Command command); const ScheduledCommand getLastScheduledCommand(Bank bank); const ScheduledCommand getLastScheduledCommand(); @@ -70,9 +74,9 @@ public: std::map > lastScheduledByCommandAndBank; // TODO: remove - std::map lastScheduledByCommand; - std::map lastScheduledByBank; - ScheduledCommand lastScheduled; + //std::map lastScheduledByCommand; + //std::map lastScheduledByBank; + //ScheduledCommand lastScheduled; Slots bus; std::vector lastDataStrobeCommands; diff --git a/DRAMSys/library/src/controller/RecordableController.cpp b/DRAMSys/library/src/controller/RecordableController.cpp index 9fd2d70d..4b762fa2 100644 --- a/DRAMSys/library/src/controller/RecordableController.cpp +++ b/DRAMSys/library/src/controller/RecordableController.cpp @@ -84,7 +84,7 @@ void RecordableController::schedule(Command command, gp &payload) { Controller::schedule(command, payload); if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) { - ScheduledCommand scheduledCommand = controllerCore->state->getLastCommand( + ScheduledCommand scheduledCommand = controllerCore->state->getLastCommandOnBank( command, DramExtension::getBank(payload)); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, payload); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 31c33d15..6f6bb260 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -88,12 +88,12 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const void ActBChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand &cmd) const { - ScheduledCommand lastActOnBank = state.getLastCommand(Command::ACT, + ScheduledCommand lastActOnBank = state.getLastCommandOnBank(Command::ACT, cmd.getBank()); if (lastActOnBank.isValidCommand()) { cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec->tRC); } - ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ACTB, + ScheduledCommand lastActBOnBank = state.getLastCommandOnBank(Command::ACTB, cmd.getBank()); if (lastActBOnBank.isValidCommand()) { cmd.establishMinDistanceFromStart(lastActBOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index db6e0b86..6b64d156 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -92,14 +92,14 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand &command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, + ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivateOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), config.memSpec->tRC); } - ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ACTB, + ScheduledCommand lastActBOnBank = state.getLastCommandOnBank(Command::ACTB, command.getBank()); if (lastActBOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 068a57a9..58cc1437 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -14,14 +14,14 @@ using namespace std; void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const { ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); - Command LastCmd = lastCommandOnBank.getCommand(); - Command NextCmd = command.getCommand(); + Command lastCmd = lastCommandOnBank.getCommand(); + Command nextCmd = command.getCommand(); - if (NextCmd == Command::ACT) + if (nextCmd == Command::ACT) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: case Command::PREA: @@ -52,7 +52,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Activate can not follow " + commandToString(LastCmd)); + "Activate can not follow " + commandToString(lastCmd)); } } @@ -64,12 +64,12 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const command.delayStart(memSpec->clk); } } - else if (NextCmd == Command::RD || NextCmd == Command::RDA) + else if (nextCmd == Command::RD || nextCmd == Command::RDA) { delayToSatisfyDLL(command); if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -90,17 +90,17 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Read can not follow " + commandToString(LastCmd) + "First: Activate!"); + "Read can not follow " + commandToString(lastCmd) + "First: Activate!"); } } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) command.delayStart(memSpec->clk); } - else if (NextCmd == Command::WR || NextCmd == Command::WRA) + else if (nextCmd == Command::WR || nextCmd == Command::WRA) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -120,17 +120,17 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const memSpec->tXP); break; default: - reportFatal("Checker DDR3", "Write can not follow " + commandToString(LastCmd)); + reportFatal("Checker DDR3", "Write can not follow " + commandToString(lastCmd)); } } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) command.delayStart(memSpec->clk); } - else if (NextCmd == Command::PRE) + else if (nextCmd == Command::PRE) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -155,16 +155,16 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Precharge can not follow " + commandToString(LastCmd)); + "Precharge can not follow " + commandToString(lastCmd)); } } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) command.establishMinDistanceFromStart(lastActivate.getStart(), memSpec->tRAS); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PREA) + else if (nextCmd == Command::PREA) { for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) { @@ -214,21 +214,21 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker_DDR3", - "Precharge All can not follow " + commandToString(LastCmd)); + "Precharge All can not follow " + commandToString(lastCmd)); } } } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) command.establishMinDistanceFromStart(lastActivate.getStart(), memSpec->tRAS); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDEA || NextCmd == Command::PDEP || NextCmd == Command::SREFEN ) + else if (nextCmd == Command::PDEA || nextCmd == Command::PDEP || nextCmd == Command::SREFEN ) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: case Command::PREA: @@ -265,39 +265,39 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const memSpec->tXS); break; default: - reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow " - + commandToString(LastCmd) + ".First: Precharge!"); + reportFatal("Checker DDR3", commandToString(nextCmd) + " can not follow " + + commandToString(lastCmd) + ".First: Precharge!"); } } state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDXA) + else if (nextCmd == Command::PDXA) { // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, command.getBank()).getStart(), memSpec->tCKE); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDXP) + else if (nextCmd == Command::PDXP) { // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, command.getBank()).getStart(), memSpec->tCKE); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::SREFEX) + else if (nextCmd == Command::SREFEX) { // Leaving Self Refresh - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, command.getBank()).getStart(), memSpec->tCKESR); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::REFA) + else if (nextCmd == Command::REFA) { if (config.BankwiseLogic) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: case Command::PREA: @@ -328,7 +328,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(LastCmd)); + "Refresh can not follow " + commandToString(lastCmd)); } } } @@ -375,7 +375,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(LastCmd)); + "Refresh can not follow " + commandToString(lastCmd)); } } } @@ -390,7 +390,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); + ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivateOnBank.isValidCommand()) command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); } @@ -477,7 +477,7 @@ bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const { - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, read.getBank()); + ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 696f7b02..42988069 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -19,45 +19,45 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (command == Command::ACT) { - lastCommand = state.getLastCommand(Command::RDA, bank); + lastCommand = state.getLastCommandOnBank(Command::RDA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - lastCommand = state.getLastCommand(Command::WRA, bank); + lastCommand = state.getLastCommandOnBank(Command::WRA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PRE, bank); + lastCommand = state.getLastCommandOnBank(Command::PRE, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PREA, bank); + lastCommand = state.getLastCommandOnBank(Command::PREA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::PDXP, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXP, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::REFA, bank); + lastCommand = state.getLastCommandOnBank(Command::REFA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); - lastCommand = state.getLastCommand(Command::SREFEX, bank); + lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::ACT, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::ACT, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); } @@ -67,7 +67,7 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::RD || command == Command::RDA) { - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); //if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); @@ -79,11 +79,11 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) // if (lastCommand.isValidCommand()) // minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::SREFEX, bank); + lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); @@ -92,18 +92,18 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::RD, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - lastCommand = state.getLastCommand(Command::WR, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); } } else if (command == Command::WR || command == Command::WRA) { - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); //if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); @@ -115,11 +115,11 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) // if (lastCommand.isValidCommand()) // minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::SREFEX, bank); + lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); @@ -128,30 +128,30 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::RD, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = state.getLastCommand(Command::WR, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); } } else if (command == Command::PRE) { - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); //if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); - lastCommand = state.getLastCommand(Command::RD, bank); + lastCommand = state.getLastCommandOnBank(Command::RD, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); - lastCommand = state.getLastCommand(Command::WR, bank); + lastCommand = state.getLastCommandOnBank(Command::WR, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 48c35d9e..16ace13e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -81,17 +81,17 @@ const } else if (pdnCmd == Command::PDXA) { // Leaving Active Power Down timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, bank).getStart(), timeConstraint); } else if (pdnCmd == Command::PDXP) { // Leaving Precharge Power Down timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, bank).getStart(), timeConstraint); } else if (pdnCmd == Command::SREFEX) { // Leaving Self Refresh timeConstraint = config.memSpec->tCKESR; - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, bank).getStart(), timeConstraint); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 907dcb73..5a0f7229 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -71,11 +71,11 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } // ------------ - if ((lc = state.getLastCommand(Command::ACT, + if ((lc = state.getLastCommandOnBank(Command::ACT, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); } - if ((lc = state.getLastCommand(Command::ACTB, + if ((lc = state.getLastCommandOnBank(Command::ACTB, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), Configuration::getInstance().getTrasb()); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index aede0f2d..45380a72 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -90,7 +90,7 @@ const } } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); // TODO: Why do we only check the ACT of one bank? (always bank 0) if (lastActivate.isValidCommand()) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index 50c67c43..3666f5f3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -75,7 +75,7 @@ const "PRE can not follow " + commandToString(lastCommand.getCommand())); } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 1683a30b..769624cc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -108,7 +108,7 @@ bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand &read, void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const { - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, + ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), From a05b0ed610fdd83b61db2968a6856e2678efeab9 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 28 Jul 2019 20:57:48 +0200 Subject: [PATCH 042/183] Removed RowBufferState in ControllerState. --- .../src/controller/ControllerState.cpp | 23 +- .../library/src/controller/ControllerState.h | 13 +- .../src/controller/core/ControllerCore.h | 7 +- .../src/controller/scheduler/FrFcfs.cpp | 148 ++++----- .../src/controller/scheduler/FrFcfsGrp.cpp | 280 +++++++++--------- .../src/controller/scheduler/FrFcfsRp.cpp | 178 +++++------ .../library/src/controller/scheduler/Grp.cpp | 258 ++++++++-------- .../src/controller/scheduler/IScheduler.cpp | 104 +++---- 8 files changed, 489 insertions(+), 522 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index 494d5ab3..8c299037 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -104,45 +104,26 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) lastScheduledByCommandAndBank[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand; - switch (scheduledCommand.getCommand()) { + switch (scheduledCommand.getCommand()) + { case Command::RD: lastDataStrobeCommands.emplace_back(scheduledCommand); break; case Command::RDA: - rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); lastDataStrobeCommands.emplace_back(scheduledCommand); break; case Command::WR: lastDataStrobeCommands.emplace_back(scheduledCommand); break; case Command::WRA: - rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); lastDataStrobeCommands.emplace_back(scheduledCommand); break; - case Command::REFA: - break; case Command::ACTB: - rowBufferStates->openRowInRowBuffer(scheduledCommand.getBank(), - scheduledCommand.getRow()); lastActivatesB.emplace(scheduledCommand.getStart(), scheduledCommand); break; case Command::ACT: - rowBufferStates->openRowInRowBuffer(scheduledCommand.getBank(), - scheduledCommand.getRow()); lastActivates.emplace(scheduledCommand.getStart(), scheduledCommand); break; - case Command::PREB: - rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); - break; - case Command::PRE: - rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); - break; - case Command::PREA: - rowBufferStates->closeAllRowBuffers(); - break; - case Command::SREFEN: - rowBufferStates->closeRowBuffer(scheduledCommand.getBank()); - break; default: break; } diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 58bdcd8c..ea7c0e22 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -38,7 +38,6 @@ #define CONTROLLERSTATE_H #include -#include "RowBufferStates.h" #include "core/Slots.h" #include "core/configuration/Configuration.h" #include @@ -50,15 +49,7 @@ class ControllerState public: ControllerState(std::string ownerName, Configuration *config) : bus(config->memSpec->clk), ownerName(ownerName), - config(config) - { - rowBufferStates = new RowBufferState(ownerName); - } - - virtual ~ControllerState() - { - delete rowBufferStates; - } + config(config) {} const ScheduledCommand getLastCommandOnBank(Command command, Bank bank); const ScheduledCommand getLastCommand(Command command); @@ -68,8 +59,6 @@ public: void change(const ScheduledCommand &scheduledCommand); void cleanUp(sc_time time); - RowBufferState *rowBufferStates; - //used by the various checkers std::map > lastScheduledByCommandAndBank; diff --git a/DRAMSys/library/src/controller/core/ControllerCore.h b/DRAMSys/library/src/controller/core/ControllerCore.h index 424998f3..c3d94f02 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.h +++ b/DRAMSys/library/src/controller/core/ControllerCore.h @@ -46,7 +46,7 @@ #include "powerdown/PowerDownManager.h" #include "refresh/IRefreshManager.h" #include "scheduling/checker/ICommandChecker.h" -#include "../RowBufferStates.h" +//#include "../RowBufferStates.h" #include "../ControllerState.h" using namespace std; @@ -63,10 +63,7 @@ public: const std::vector &getBanks(); std::vector getFreeBanks(); - const RowBufferState &getRowBufferStates() - { - return *(state->rowBufferStates); - } + bool hasPendingRequests(); bool hasPendingRequests(Bank bank); bool bankIsBusy(Bank bank); diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp index c0d742af..daec88c0 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp @@ -35,88 +35,88 @@ * Matthias Jung */ -#include "FrFcfs.h" -#include "../../common/dramExtensions.h" -#include "../core/configuration/Configuration.h" -#include +//#include "FrFcfs.h" +//#include "../../common/dramExtensions.h" +//#include "../core/configuration/Configuration.h" +//#include -using namespace std; +//using namespace std; -// The FrFcfs (First Ready First Come First Served) is descibed in a 2000 paper from Rixner et al.: -// Memory Access Scheduling -// -// The FrFcfs scheduler features for each bank in the DRAM a specific -// scheduling buffer for example: -// -// Bank0: OOOOOOOO -// Bank1: OOXXXXXX -// ... ^ ^ -// ... | | -// ... back | -// ... front -// ... -// Bank6: OOOOO0XX -// Bank7: XXXXXXXX +//// The FrFcfs (First Ready First Come First Served) is descibed in a 2000 paper from Rixner et al.: +//// Memory Access Scheduling +//// +//// The FrFcfs scheduler features for each bank in the DRAM a specific +//// scheduling buffer for example: +//// +//// Bank0: OOOOOOOO +//// Bank1: OOXXXXXX +//// ... ^ ^ +//// ... | | +//// ... back | +//// ... front +//// ... +//// Bank6: OOOOO0XX +//// Bank7: XXXXXXXX -void FrFcfs::storeRequest(gp *payload) -{ - // FIXME: Question: what if the buffer is full? IMHO the schedule function - // should provide a true or false when the placement into the buffer worked - // out or not (?). - buffer[DramExtension::getExtension(payload).getBank()] - .emplace_back(payload); -} +//void FrFcfs::storeRequest(gp *payload) +//{ +// // FIXME: Question: what if the buffer is full? IMHO the schedule function +// // should provide a true or false when the placement into the buffer worked +// // out or not (?). +// buffer[DramExtension::getExtension(payload).getBank()] +// .emplace_back(payload); +//} -std::pair FrFcfs::getNextRequest(Bank bank) -{ - // If the bank is empty like Bank0 in the example we do nothing - if (buffer[bank].empty()) - return std::pair(Command::NOP, NULL); +//std::pair FrFcfs::getNextRequest(Bank bank) +//{ +// // If the bank is empty like Bank0 in the example we do nothing +// if (buffer[bank].empty()) +// return std::pair(Command::NOP, NULL); - // In FrFcfs row hits have always the highest priority, therefore we search - // for row hits. If we find a row hit, we remove the transaction from the - // queue and send it to the DRAM. - std::deque::iterator it = findRowHit(bank); - if (it != buffer[bank].end()) - { - gp *payload = *it; - buffer[bank].erase(it); - return std::pair(getReadWriteCommand(payload), payload); - } +// // In FrFcfs row hits have always the highest priority, therefore we search +// // for row hits. If we find a row hit, we remove the transaction from the +// // queue and send it to the DRAM. +// std::deque::iterator it = findRowHit(bank); +// if (it != buffer[bank].end()) +// { +// gp *payload = *it; +// buffer[bank].erase(it); +// return std::pair(getReadWriteCommand(payload), payload); +// } - // If there is no row hit, the FrFcfs takes always the oldest transaction - // in the buffer, i.e. the transaction in the front. - return std::pair(getNextCommand(buffer[bank].front()), - buffer[bank].front()); -} +// // If there is no row hit, the FrFcfs takes always the oldest transaction +// // in the buffer, i.e. the transaction in the front. +// return std::pair(getNextCommand(buffer[bank].front()), +// buffer[bank].front()); +//} -// This function searches for a row hit in the scheduling queue of the specific -// bank. If no row hit is found the end of the queue is returned. -// -// Note: end() Returns an iterator referring to the past-the-end element in the -// deque container. The past-the-end element is the theoretical element that -// would follow the last element in the deque container. It does not point to -// any element, and thus shall not be dereferenced. -std::deque::iterator FrFcfs::findRowHit(Bank bank) -{ - std::deque &queue = buffer[bank]; - Row activeRow = controllerCore.getRowBufferStates().getRowInRowBuffer(bank); +//// This function searches for a row hit in the scheduling queue of the specific +//// bank. If no row hit is found the end of the queue is returned. +//// +//// Note: end() Returns an iterator referring to the past-the-end element in the +//// deque container. The past-the-end element is the theoretical element that +//// would follow the last element in the deque container. It does not point to +//// any element, and thus shall not be dereferenced. +//std::deque::iterator FrFcfs::findRowHit(Bank bank) +//{ +// std::deque &queue = buffer[bank]; +// Row activeRow = controllerCore.getRowBufferStates().getRowInRowBuffer(bank); - if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) - return queue.end(); +// if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) +// return queue.end(); - // Traverse the scheduling queue of the specific bank: - for (auto it = queue.begin(); it != queue.end(); it++) - { - //Found row-hit and return the according iterator - if (DramExtension::getRow(*it) == activeRow) - return it; - } +// // Traverse the scheduling queue of the specific bank: +// for (auto it = queue.begin(); it != queue.end(); it++) +// { +// //Found row-hit and return the according iterator +// if (DramExtension::getRow(*it) == activeRow) +// return it; +// } - return queue.end(); -} +// return queue.end(); +//} -gp *FrFcfs::getPendingRequest(Bank /*bank*/) -{ - return NULL; -} +//gp *FrFcfs::getPendingRequest(Bank /*bank*/) +//{ +// return NULL; +//} diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp index 3b41fd43..29da4399 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp @@ -33,162 +33,162 @@ * Matthias Jung */ -#include "FrFcfsGrp.h" +//#include "FrFcfsGrp.h" -// The FrFcfsGrp (First Ready First Come First Served Grouper) works exactly -// like the FrFcfsRp (First Ready First Come First Served Read Priority). -// However writes are grouped! For detailed documentation look into the FrFcfs. -// TODO: what is missed is a check if the buffers are full. This will only work -// if we have buffers with a fixed size (Prado's future patch). +//// The FrFcfsGrp (First Ready First Come First Served Grouper) works exactly +//// like the FrFcfsRp (First Ready First Come First Served Read Priority). +//// However writes are grouped! For detailed documentation look into the FrFcfs. +//// TODO: what is missed is a check if the buffers are full. This will only work +//// if we have buffers with a fixed size (Prado's future patch). -std::pair FrFcfsGrp::getNextRequest(Bank bank) -{ - // If the bank is empty we do nothing: - if (buffer[bank].empty()) { - return pair(Command::NOP, NULL); - } +//std::pair FrFcfsGrp::getNextRequest(Bank bank) +//{ +// // If the bank is empty we do nothing: +// if (buffer[bank].empty()) { +// return pair(Command::NOP, NULL); +// } - // If we are in write mode we should check if we should switch to read mode - // because there are no writes anymore in the buffer. - if (readMode == false) { - if (getNumberOfRequest(tlm::TLM_WRITE_COMMAND) == 0) { - readMode = true; - } - } else { // If we are in read mode but all reads are served we switch to write - if (getNumberOfRequest(tlm::TLM_READ_COMMAND) == 0) { - readMode = false; - } - } +// // If we are in write mode we should check if we should switch to read mode +// // because there are no writes anymore in the buffer. +// if (readMode == false) { +// if (getNumberOfRequest(tlm::TLM_WRITE_COMMAND) == 0) { +// readMode = true; +// } +// } else { // If we are in read mode but all reads are served we switch to write +// if (getNumberOfRequest(tlm::TLM_READ_COMMAND) == 0) { +// readMode = false; +// } +// } - // Now lets search for read and write commands. However keep in mind that - // readMode is a shared variable for all the banks! - if (readMode == true) { - // 1. Seach for read hit: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *read = *it; +// // Now lets search for read and write commands. However keep in mind that +// // readMode is a shared variable for all the banks! +// if (readMode == true) { +// // 1. Seach for read hit: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *read = *it; - if (read->get_command() == tlm::TLM_READ_COMMAND) { - // If there is a row hit: - if (DramExtension::getRow(read) - == controllerCore.getRowBufferStates() - .getRowInRowBuffer(bank)) { - if (hazardDetection(bank, it) == false) { - buffer[bank].erase(it); - printDebugMessage("Read Hit found"); - return pair(getReadWriteCommand(read), - read); - } else { - // If there was a hazard, switch the mode and try again: - readMode = false; - return getNextRequest(bank); - } - } - } - } +// if (read->get_command() == tlm::TLM_READ_COMMAND) { +// // If there is a row hit: +// if (DramExtension::getRow(read) +// == controllerCore.getRowBufferStates() +// .getRowInRowBuffer(bank)) { +// if (hazardDetection(bank, it) == false) { +// buffer[bank].erase(it); +// printDebugMessage("Read Hit found"); +// return pair(getReadWriteCommand(read), +// read); +// } else { +// // If there was a hazard, switch the mode and try again: +// readMode = false; +// return getNextRequest(bank); +// } +// } +// } +// } - // 2. Search for read miss: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *read = *it; +// // 2. Search for read miss: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *read = *it; - if (read->get_command() == tlm::TLM_READ_COMMAND) { - if (hazardDetection(bank, it) == false) { - printDebugMessage("Read miss found"); - return pair(getNextCommand(read), read); - } else { - // If there was a hazard, switch the mode and try again: - readMode = false; - return getNextRequest(bank); - } - } - } - } else { // write mode: - // 3. Search for write hit: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *write = *it; +// if (read->get_command() == tlm::TLM_READ_COMMAND) { +// if (hazardDetection(bank, it) == false) { +// printDebugMessage("Read miss found"); +// return pair(getNextCommand(read), read); +// } else { +// // If there was a hazard, switch the mode and try again: +// readMode = false; +// return getNextRequest(bank); +// } +// } +// } +// } else { // write mode: +// // 3. Search for write hit: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - // If there is a row hit: - if (DramExtension::getRow(write) - == controllerCore.getRowBufferStates() - .getRowInRowBuffer(bank)) { - buffer[bank].erase(it); - printDebugMessage("Write Hit found"); - return pair(getReadWriteCommand(write), - write); - } - } - } +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// // If there is a row hit: +// if (DramExtension::getRow(write) +// == controllerCore.getRowBufferStates() +// .getRowInRowBuffer(bank)) { +// buffer[bank].erase(it); +// printDebugMessage("Write Hit found"); +// return pair(getReadWriteCommand(write), +// write); +// } +// } +// } - // 4. Search for write miss: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *write = *it; +// // 4. Search for write miss: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - printDebugMessage("Write miss found"); - return pair(getNextCommand(write), write); - } - } - } +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// printDebugMessage("Write miss found"); +// return pair(getNextCommand(write), write); +// } +// } +// } - // If nothing was found we check the other banks before we switch the mode: - pair other(Command::NOP, NULL); - unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; +// // If nothing was found we check the other banks before we switch the mode: +// pair other(Command::NOP, NULL); +// unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; - for (unsigned int i = 1; i < B; i++) { - Bank nextBank((bank.ID() + i) % B); - ctrl->scheduleNextFromScheduler(nextBank); - } +// for (unsigned int i = 1; i < B; i++) { +// Bank nextBank((bank.ID() + i) % B); +// ctrl->scheduleNextFromScheduler(nextBank); +// } - // If nothing was found in the current mode, switch the mode and try again: - // FIXME: this is in my opinion not so clever yet, because we switch maybe - // even though there are still reads/writes request on other banks ... - readMode = !readMode; - return getNextRequest(bank); +// // If nothing was found in the current mode, switch the mode and try again: +// // FIXME: this is in my opinion not so clever yet, because we switch maybe +// // even though there are still reads/writes request on other banks ... +// readMode = !readMode; +// return getNextRequest(bank); - reportFatal("FrFcfsGrp", "Never should go here ..."); -} +// reportFatal("FrFcfsGrp", "Never should go here ..."); +//} -// There is a hazard if a read is found which will be scheduled before a write -// to the same column and the same row of the same bank: -bool FrFcfsGrp::hazardDetection(Bank bank, std::deque::iterator ext) -{ - gp *read = *ext; +//// There is a hazard if a read is found which will be scheduled before a write +//// to the same column and the same row of the same bank: +//bool FrFcfsGrp::hazardDetection(Bank bank, std::deque::iterator ext) +//{ +// gp *read = *ext; - //for(unsigned long i=0; i < id; i++) - for (auto it = buffer[bank].begin(); it != ext; it++) { - gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - if ((DramExtension::getExtension(read).getColumn() - == DramExtension::getExtension(write).getColumn()) - && (DramExtension::getExtension(read).getRow() - == DramExtension::getExtension(write).getRow())) { - printDebugMessage("Hazard Detected"); - return true; - } - } - } - return false; -} +// //for(unsigned long i=0; i < id; i++) +// for (auto it = buffer[bank].begin(); it != ext; it++) { +// gp *write = *it; +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// if ((DramExtension::getExtension(read).getColumn() +// == DramExtension::getExtension(write).getColumn()) +// && (DramExtension::getExtension(read).getRow() +// == DramExtension::getExtension(write).getRow())) { +// printDebugMessage("Hazard Detected"); +// return true; +// } +// } +// } +// return false; +//} -// Estimate the number of writes/reads in all bank buffers: -unsigned int FrFcfsGrp::getNumberOfRequest(tlm::tlm_command cmd) -{ - unsigned int numberOfRequests = 0; - for (unsigned int i = 0; - i < Configuration::getInstance().memSpec->NumberOfBanks; - i++) { - for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { - gp *trans = *it; - if (trans->get_command() == cmd) { - numberOfRequests++; - } - } - } +//// Estimate the number of writes/reads in all bank buffers: +//unsigned int FrFcfsGrp::getNumberOfRequest(tlm::tlm_command cmd) +//{ +// unsigned int numberOfRequests = 0; +// for (unsigned int i = 0; +// i < Configuration::getInstance().memSpec->NumberOfBanks; +// i++) { +// for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { +// gp *trans = *it; +// if (trans->get_command() == cmd) { +// numberOfRequests++; +// } +// } +// } - return numberOfRequests; -} +// return numberOfRequests; +//} -void FrFcfsGrp::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); -} +//void FrFcfsGrp::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); +//} diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp index 250510c0..cdfa5fee 100644 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp +++ b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp @@ -33,108 +33,108 @@ * Matthias Jung */ -#include "FrFcfsRp.h" +//#include "FrFcfsRp.h" -// The FrFcfsRp (First Ready First Come First Served Read Priority) works -// exactly like the FrFcfs but reads are prioratized over writes. -// For detailed documentation look into the FrFcfs. +//// The FrFcfsRp (First Ready First Come First Served Read Priority) works +//// exactly like the FrFcfs but reads are prioratized over writes. +//// For detailed documentation look into the FrFcfs. -std::pair FrFcfsRp::getNextRequest(Bank bank) -{ - // If the bank is empty like Bank0 in the example we do nothing: - if (buffer[bank].empty()) { - return pair(Command::NOP, NULL); - } +//std::pair FrFcfsRp::getNextRequest(Bank bank) +//{ +// // If the bank is empty like Bank0 in the example we do nothing: +// if (buffer[bank].empty()) { +// return pair(Command::NOP, NULL); +// } - // Order of Priority: - // 1. Read Hits (Hazard Check) - // 2. Write Hits - // 3. Read Miss (Hazard Check) - // 4. Write Miss +// // Order of Priority: +// // 1. Read Hits (Hazard Check) +// // 2. Write Hits +// // 3. Read Miss (Hazard Check) +// // 4. Write Miss - // 1. Seach for read hit: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *read = *it; +// // 1. Seach for read hit: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *read = *it; - if (read->get_command() == tlm::TLM_READ_COMMAND) { - // If there is a row hit: - if (DramExtension::getRow(read) - == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { - if (hazardDetection(bank, it) == false) { - buffer[bank].erase(it); - printDebugMessage("Read Hit found"); - return pair(getReadWriteCommand(read), read); - } - } - } - } +// if (read->get_command() == tlm::TLM_READ_COMMAND) { +// // If there is a row hit: +// if (DramExtension::getRow(read) +// == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { +// if (hazardDetection(bank, it) == false) { +// buffer[bank].erase(it); +// printDebugMessage("Read Hit found"); +// return pair(getReadWriteCommand(read), read); +// } +// } +// } +// } - // 2. Search for write hit: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *write = *it; +// // 2. Search for write hit: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - // If there is a row hit: - if (DramExtension::getRow(write) - == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { - buffer[bank].erase(it); - printDebugMessage("Write Hit found"); - return pair(getReadWriteCommand(write), write); - } - } - } +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// // If there is a row hit: +// if (DramExtension::getRow(write) +// == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { +// buffer[bank].erase(it); +// printDebugMessage("Write Hit found"); +// return pair(getReadWriteCommand(write), write); +// } +// } +// } - // For now return the oldest request but prefere also reads before writes: +// // For now return the oldest request but prefere also reads before writes: - // 3. Search for read miss: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *read = *it; +// // 3. Search for read miss: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *read = *it; - if (read->get_command() == tlm::TLM_READ_COMMAND) { - if (hazardDetection(bank, it) == false) { - printDebugMessage("Read miss found"); - return pair(getNextCommand(read), read); - } - } - } +// if (read->get_command() == tlm::TLM_READ_COMMAND) { +// if (hazardDetection(bank, it) == false) { +// printDebugMessage("Read miss found"); +// return pair(getNextCommand(read), read); +// } +// } +// } - // 3. Search for write miss: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *write = *it; +// // 3. Search for write miss: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - printDebugMessage("Write miss found"); - return pair(getNextCommand(write), write); - } - } +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// printDebugMessage("Write miss found"); +// return pair(getNextCommand(write), write); +// } +// } - reportFatal("FrFcfsRp", "Never should go here ..."); - return pair(Command::NOP, NULL); -} +// reportFatal("FrFcfsRp", "Never should go here ..."); +// return pair(Command::NOP, NULL); +//} -// There is a hazard if a read is found which will be scheduled before a write -// to the same column and the same row of the same bank: -bool FrFcfsRp::hazardDetection(Bank bank, std::deque::iterator ext) -{ - gp *read = *ext; +//// There is a hazard if a read is found which will be scheduled before a write +//// to the same column and the same row of the same bank: +//bool FrFcfsRp::hazardDetection(Bank bank, std::deque::iterator ext) +//{ +// gp *read = *ext; - //for(unsigned long i=0; i < id; i++) - for (auto it = buffer[bank].begin(); it != ext; it++) { - gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - if ((DramExtension::getExtension(read).getColumn() - == DramExtension::getExtension(write).getColumn()) - && (DramExtension::getExtension(read).getRow() - == DramExtension::getExtension(write).getRow())) { - printDebugMessage("Hazard Detected"); - return true; - } - } - } - return false; -} +// //for(unsigned long i=0; i < id; i++) +// for (auto it = buffer[bank].begin(); it != ext; it++) { +// gp *write = *it; +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// if ((DramExtension::getExtension(read).getColumn() +// == DramExtension::getExtension(write).getColumn()) +// && (DramExtension::getExtension(read).getRow() +// == DramExtension::getExtension(write).getRow())) { +// printDebugMessage("Hazard Detected"); +// return true; +// } +// } +// } +// return false; +//} -void FrFcfsRp::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage("FrFcfsRp", message); -} +//void FrFcfsRp::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage("FrFcfsRp", message); +//} diff --git a/DRAMSys/library/src/controller/scheduler/Grp.cpp b/DRAMSys/library/src/controller/scheduler/Grp.cpp index cf4dffe2..9a920ae7 100644 --- a/DRAMSys/library/src/controller/scheduler/Grp.cpp +++ b/DRAMSys/library/src/controller/scheduler/Grp.cpp @@ -33,148 +33,148 @@ * Matthias Jung */ -#include "Grp.h" +//#include "Grp.h" -// Grp (Grouper) just reorders w.r.t. read write grouping, however is not aware of the -// row buffer. For a row buffer aware grouper refer to FrFcfsGrp. -// TODO: what is missed is a check if the buffers are full. This will only work -// if we have buffers with a fixed size (Prado's future patch). +//// Grp (Grouper) just reorders w.r.t. read write grouping, however is not aware of the +//// row buffer. For a row buffer aware grouper refer to FrFcfsGrp. +//// TODO: what is missed is a check if the buffers are full. This will only work +//// if we have buffers with a fixed size (Prado's future patch). -std::pair Grp::getNextRequest(Bank bank) -{ - // If the bank is empty we do nothing: - if (buffer[bank].empty()) { - return pair(Command::NOP, NULL); - } +//std::pair Grp::getNextRequest(Bank bank) +//{ +// // If the bank is empty we do nothing: +// if (buffer[bank].empty()) { +// return pair(Command::NOP, NULL); +// } - // If we are in write mode we should check if we should switch to read mode - // because there are no writes anymore in the buffer. - if (readMode == false) { - if (getNumberOfRequest(tlm::TLM_WRITE_COMMAND) == 0) { - readMode = true; - } - } else { // If we are in read mode but all reads are served we switch to write - if (getNumberOfRequest(tlm::TLM_READ_COMMAND) == 0) { - readMode = false; - } - } +// // If we are in write mode we should check if we should switch to read mode +// // because there are no writes anymore in the buffer. +// if (readMode == false) { +// if (getNumberOfRequest(tlm::TLM_WRITE_COMMAND) == 0) { +// readMode = true; +// } +// } else { // If we are in read mode but all reads are served we switch to write +// if (getNumberOfRequest(tlm::TLM_READ_COMMAND) == 0) { +// readMode = false; +// } +// } - // Now lets search for read and write commands. However keep in mind that - // readMode is a shared variable for all the banks! - if (readMode == true) { - // 1. Seach for read hit: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *read = *it; +// // Now lets search for read and write commands. However keep in mind that +// // readMode is a shared variable for all the banks! +// if (readMode == true) { +// // 1. Seach for read hit: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *read = *it; - if (read->get_command() == tlm::TLM_READ_COMMAND) { - // If there is a row hit: - if (DramExtension::getRow(read) - == controllerCore.getRowBufferStates() - .getRowInRowBuffer(bank)) { - if (hazardDetection(bank, it) == false) { - buffer[bank].erase(it); - printDebugMessage("Read Hit found"); - return pair(getReadWriteCommand(read), - read); - } else { - // If there was a hazard, switch the mode and try again: - readMode = false; - return getNextRequest(bank); - } - } else { // if there is a row miss: - if (hazardDetection(bank, it) == false) { - printDebugMessage("Read miss found"); - return pair(getNextCommand(read), read); - } else { - // If there was a hazard, switch the mode and try again: - readMode = false; - return getNextRequest(bank); - } - } - } - } +// if (read->get_command() == tlm::TLM_READ_COMMAND) { +// // If there is a row hit: +// if (DramExtension::getRow(read) +// == controllerCore.getRowBufferStates() +// .getRowInRowBuffer(bank)) { +// if (hazardDetection(bank, it) == false) { +// buffer[bank].erase(it); +// printDebugMessage("Read Hit found"); +// return pair(getReadWriteCommand(read), +// read); +// } else { +// // If there was a hazard, switch the mode and try again: +// readMode = false; +// return getNextRequest(bank); +// } +// } else { // if there is a row miss: +// if (hazardDetection(bank, it) == false) { +// printDebugMessage("Read miss found"); +// return pair(getNextCommand(read), read); +// } else { +// // If there was a hazard, switch the mode and try again: +// readMode = false; +// return getNextRequest(bank); +// } +// } +// } +// } - } else { // write mode: - // 3. Search for write hit: - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { - gp *write = *it; +// } else { // write mode: +// // 3. Search for write hit: +// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { +// gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - // If there is a row hit: - if (DramExtension::getRow(write) - == controllerCore.getRowBufferStates() - .getRowInRowBuffer(bank)) { - buffer[bank].erase(it); - printDebugMessage("Write Hit found"); - return pair(getReadWriteCommand(write), - write); - } else { - printDebugMessage("Write miss found"); - return pair(getNextCommand(write), write); - } - } - } - } +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// // If there is a row hit: +// if (DramExtension::getRow(write) +// == controllerCore.getRowBufferStates() +// .getRowInRowBuffer(bank)) { +// buffer[bank].erase(it); +// printDebugMessage("Write Hit found"); +// return pair(getReadWriteCommand(write), +// write); +// } else { +// printDebugMessage("Write miss found"); +// return pair(getNextCommand(write), write); +// } +// } +// } +// } - // If nothing was found we check the other banks before we switch the mode: - pair other(Command::NOP, NULL); - unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; +// // If nothing was found we check the other banks before we switch the mode: +// pair other(Command::NOP, NULL); +// unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; - for (unsigned int i = 1; i < B; i++) { - Bank nextBank((bank.ID() + i) % B); - ctrl->scheduleNextFromScheduler(nextBank); - } +// for (unsigned int i = 1; i < B; i++) { +// Bank nextBank((bank.ID() + i) % B); +// ctrl->scheduleNextFromScheduler(nextBank); +// } - // If nothing was found in the current mode, switch the mode and try again: - // FIXME: this is in my opinion not so clever yet, because we switch maybe - // even though there are still reads/writes request on other banks ... - readMode = !readMode; - return getNextRequest(bank); +// // If nothing was found in the current mode, switch the mode and try again: +// // FIXME: this is in my opinion not so clever yet, because we switch maybe +// // even though there are still reads/writes request on other banks ... +// readMode = !readMode; +// return getNextRequest(bank); - reportFatal("Grp", "Never should go here ..."); -} +// reportFatal("Grp", "Never should go here ..."); +//} -// There is a hazard if a read is found which will be scheduled before a write -// to the same column and the same row of the same bank: -bool Grp::hazardDetection(Bank bank, std::deque::iterator ext) -{ - gp *read = *ext; +//// There is a hazard if a read is found which will be scheduled before a write +//// to the same column and the same row of the same bank: +//bool Grp::hazardDetection(Bank bank, std::deque::iterator ext) +//{ +// gp *read = *ext; - //for(unsigned long i=0; i < id; i++) - for (auto it = buffer[bank].begin(); it != ext; it++) { - gp *write = *it; - if (write->get_command() == tlm::TLM_WRITE_COMMAND) { - if ((DramExtension::getExtension(read).getColumn() - == DramExtension::getExtension(write).getColumn()) - && (DramExtension::getExtension(read).getRow() - == DramExtension::getExtension(write).getRow())) { - printDebugMessage("Hazard Detected"); - return true; - } - } - } - return false; -} +// //for(unsigned long i=0; i < id; i++) +// for (auto it = buffer[bank].begin(); it != ext; it++) { +// gp *write = *it; +// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { +// if ((DramExtension::getExtension(read).getColumn() +// == DramExtension::getExtension(write).getColumn()) +// && (DramExtension::getExtension(read).getRow() +// == DramExtension::getExtension(write).getRow())) { +// printDebugMessage("Hazard Detected"); +// return true; +// } +// } +// } +// return false; +//} -// Estimate the number of writes/reads in all bank buffers: -unsigned int Grp::getNumberOfRequest(tlm::tlm_command cmd) -{ - unsigned int numberOfRequests = 0; - for (unsigned int i = 0; - i < Configuration::getInstance().memSpec->NumberOfBanks; - i++) { - for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { - gp *trans = *it; - if (trans->get_command() == cmd) { - numberOfRequests++; - } - } - } +//// Estimate the number of writes/reads in all bank buffers: +//unsigned int Grp::getNumberOfRequest(tlm::tlm_command cmd) +//{ +// unsigned int numberOfRequests = 0; +// for (unsigned int i = 0; +// i < Configuration::getInstance().memSpec->NumberOfBanks; +// i++) { +// for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { +// gp *trans = *it; +// if (trans->get_command() == cmd) { +// numberOfRequests++; +// } +// } +// } - return numberOfRequests; -} +// return numberOfRequests; +//} -void Grp::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); -} +//void Grp::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); +//} diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp index 7e1aa462..47f3ccdc 100644 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp +++ b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp @@ -35,62 +35,62 @@ * Matthias Jung */ -#include "IScheduler.h" -#include "../../common/DebugManager.h" -#include "../core/configuration/Configuration.h" +//#include "IScheduler.h" +//#include "../../common/DebugManager.h" +//#include "../core/configuration/Configuration.h" -std::string IScheduler::sendername = "scheduler"; +//std::string IScheduler::sendername = "scheduler"; -void IScheduler::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(IScheduler::sendername, message); -} +//void IScheduler::printDebugMessage(std::string message) +//{ +// DebugManager::getInstance().printDebugMessage(IScheduler::sendername, message); +//} -// Get the next command that is necessary to process the request representend by the payload -Command IScheduler::getNextCommand(gp &payload) -{ - Bank bank = DramExtension::getBank(payload); - if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) - { - return Command::ACT; - } - else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && - controllerCore.getRowBufferStates().getRowInRowBuffer(bank) != - DramExtension::getRow(payload)) - { - return Command::PRE; - } - else - { - return getReadWriteCommand(payload); - } -} +//// Get the next command that is necessary to process the request representend by the payload +//Command IScheduler::getNextCommand(gp &payload) +//{ +// Bank bank = DramExtension::getBank(payload); +// if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) +// { +// return Command::ACT; +// } +// else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && +// controllerCore.getRowBufferStates().getRowInRowBuffer(bank) != +// DramExtension::getRow(payload)) +// { +// return Command::PRE; +// } +// else +// { +// return getReadWriteCommand(payload); +// } +//} -Command IScheduler::getNextCommand(gp *payload) -{ - return getNextCommand(*payload); -} +//Command IScheduler::getNextCommand(gp *payload) +//{ +// return getNextCommand(*payload); +//} -Command IScheduler::getReadWriteCommand(gp &payload) -{ - if (payload.get_command() == tlm::TLM_READ_COMMAND) - { - if (Configuration::getInstance().OpenPagePolicy) - return Command::RD; - else - return Command::RDA; - } - else - { - if (Configuration::getInstance().OpenPagePolicy) - return Command::WR; - else - return Command::WRA; - } -} +//Command IScheduler::getReadWriteCommand(gp &payload) +//{ +// if (payload.get_command() == tlm::TLM_READ_COMMAND) +// { +// if (Configuration::getInstance().OpenPagePolicy) +// return Command::RD; +// else +// return Command::RDA; +// } +// else +// { +// if (Configuration::getInstance().OpenPagePolicy) +// return Command::WR; +// else +// return Command::WRA; +// } +//} -Command IScheduler::getReadWriteCommand(gp *payload) -{ - return getReadWriteCommand(*payload); -} +//Command IScheduler::getReadWriteCommand(gp *payload) +//{ +// return getReadWriteCommand(*payload); +//} From 42344ce87fe9e5ebabb6483efd7448f69be763d8 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 28 Jul 2019 21:50:28 +0200 Subject: [PATCH 043/183] Removed lastDataStrobeCommands in ControllerState, removed unused methods in timing checker. --- .../src/controller/ControllerState.cpp | 20 +-- .../library/src/controller/ControllerState.h | 4 +- .../core/scheduling/checker/CheckerDDR3.cpp | 20 +-- .../scheduling/checker/CheckerDDR3New.cpp | 132 ------------------ .../core/scheduling/checker/CheckerDDR3New.h | 24 +--- .../core/scheduling/checker/ReadChecker.cpp | 8 +- .../core/scheduling/checker/WriteChecker.cpp | 8 +- 7 files changed, 22 insertions(+), 194 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index 8c299037..fb0f7af6 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -106,18 +106,6 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) switch (scheduledCommand.getCommand()) { - case Command::RD: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; - case Command::RDA: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; - case Command::WR: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; - case Command::WRA: - lastDataStrobeCommands.emplace_back(scheduledCommand); - break; case Command::ACTB: lastActivatesB.emplace(scheduledCommand.getStart(), scheduledCommand); break; @@ -132,13 +120,7 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) void ControllerState::cleanUp(sc_time time) { bus.cleanUpSlots(time); - vector tmp; - for (ScheduledCommand &command : lastDataStrobeCommands) { - if (command.getEnd() >= time - || getDistance(command.getEnd(), time) <= config->memSpec->tDataStrobeHistory()) - tmp.push_back(command); - } - lastDataStrobeCommands = tmp; + if (time >= config->memSpec->tActHistory()) lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->memSpec->tActHistory())); diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index ea7c0e22..5406386f 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -60,15 +60,13 @@ public: void cleanUp(sc_time time); //used by the various checkers - std::map > - lastScheduledByCommandAndBank; + std::map> lastScheduledByCommandAndBank; // TODO: remove //std::map lastScheduledByCommand; //std::map lastScheduledByBank; //ScheduledCommand lastScheduled; Slots bus; - std::vector lastDataStrobeCommands; std::map lastActivates; std::map lastActivatesB; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 58cc1437..8f1722fc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -441,11 +441,11 @@ bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_RD(read, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) +// { +// if (collidesWithStrobeCommand_RD(read, strobeCommand)) +// return true; +// } return false; } @@ -515,11 +515,11 @@ sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &seco bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_WR(write, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) +// { +// if (collidesWithStrobeCommand_WR(write, strobeCommand)) +// return true; +// } return false; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 42988069..6f4c62f3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -165,22 +165,6 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) return (minTimeToWait - sc_time_stamp()); } -/* -* ActivateChecker -*/ -bool CheckerDDR3New::satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const -{ - for (auto act : state.lastActivates) - { - sc_time time = act.first; - if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) - || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) - return false; - } - return true; - -} - bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const { /* @@ -206,119 +190,3 @@ bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const } return true; } - - -/* - * Read-Checker -*/ - -bool CheckerDDR3New::collidesOnDataStrobe_RD(ScheduledCommand &read) const -{ - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_RD(read, strobeCommand)) - return true; - } - return false; -} - -bool CheckerDDR3New::collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - return getDistance(read.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, read); - } - else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - if (strobeCommand.getStart() >= read.getStart()) - return getDistance(read.getStart(), - strobeCommand.getStart()) < readToWrite(read, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - read.getStart()) < writeToRead(strobeCommand, read); - } else { - reportFatal("CheckerDDR3New", - "Invalid strobeCommand in data strobe commands " + commandToString( - strobeCommand.getCommand())); - return true; - } - return false; -} - -sc_time CheckerDDR3New::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const -{ - sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA); - - return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; -} - -/* CAS-CAS */ - -sc_time CheckerDDR3New::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const -{ - if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA) - { - if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA) - return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); - } - else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA) - { - if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA) - return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); - } - SC_REPORT_FATAL("CasToCas", "Exception reached"); - return SC_ZERO_TIME; -} - -/* -* Write-Checker -*/ - -bool CheckerDDR3New::collidesOnDataStrobe_WR(ScheduledCommand &write) const -{ - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) - { - if (collidesWithStrobeCommand_WR(write, strobeCommand)) - return true; - } - return false; -} - -bool CheckerDDR3New::collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - return getDistance(write.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, write); - } - else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - if (strobeCommand.getStart() >= write.getStart()) - return getDistance(write.getStart(), - strobeCommand.getStart()) < writeToRead(write, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - write.getStart()) < readToWrite(strobeCommand, write); - } - else - { - reportFatal("CheckerDDR3New", "Invalid strobeCommand in data strobe commands " - + commandToString(strobeCommand.getCommand())); - return true; - } -} - - -sc_time CheckerDDR3New::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const -{ - sc_assert(read.getCommand() == Command::RD - || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR - || write.getCommand() == Command::WRA); - - return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 349b250d..a658da60 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -24,30 +24,10 @@ private: MemSpecDDR3 *memSpec; //Activate - bool satsfiesACTtoACTdifferentBank(ScheduledCommand &command) const; bool satisfiesNActivateWindow(ScheduledCommand &command) const; - //PowerDown - sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; - - //used for Read - bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; - bool collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const; - - //Write - bool collidesOnDataStrobe_WR(ScheduledCommand &write) const; - bool collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const; - - //handles WR->RD - sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const; - - //RD->WR - sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const; - - //CasToCas Commands (WR->WR)(RD->RD) - sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const; + //PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; const Configuration &config; ControllerState &state;//TODO make const diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 769624cc..d47dee54 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -75,10 +75,10 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const bool ReadChecker::collidesOnDataStrobe(ScheduledCommand &read) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { - if (collidesWithStrobeCommand(read, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { +// if (collidesWithStrobeCommand(read, strobeCommand)) +// return true; +// } return false; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp index e9136ef7..df8fc8ed 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp @@ -75,10 +75,10 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const bool WriteChecker::collidesOnDataStrobe(ScheduledCommand &write) const { - for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { - if (collidesWithStrobeCommand(write, strobeCommand)) - return true; - } +// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { +// if (collidesWithStrobeCommand(write, strobeCommand)) +// return true; +// } return false; } From dbcdf3f61d6b0021f0a5028911a6fae0780878be Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 28 Jul 2019 22:53:27 +0200 Subject: [PATCH 044/183] Included FAW check. --- .../src/controller/ControllerState.cpp | 26 +++-------- .../library/src/controller/ControllerState.h | 3 +- .../core/scheduling/checker/ActBChecker.cpp | 16 +++---- .../scheduling/checker/ActivateChecker.cpp | 42 +++++++++--------- .../core/scheduling/checker/CheckerDDR3.cpp | 44 +++++++++---------- .../scheduling/checker/CheckerDDR3New.cpp | 32 +++++--------- .../core/scheduling/checker/CheckerDDR3New.h | 2 +- 7 files changed, 72 insertions(+), 93 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index fb0f7af6..ad896cdf 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -96,38 +96,26 @@ const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank) void ControllerState::change(const ScheduledCommand &scheduledCommand) { - bus.blockSlot(scheduledCommand.getStart()); - printDebugMessage("Changing state on bank " + to_string( scheduledCommand.getBank().ID()) + " command is " + commandToString( scheduledCommand.getCommand())); + + bus.blockSlot(scheduledCommand.getStart()); lastScheduledByCommandAndBank[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand; - switch (scheduledCommand.getCommand()) + // TODO: implement FAW for ACTB + if (scheduledCommand.getCommand() == Command::ACT) { - case Command::ACTB: - lastActivatesB.emplace(scheduledCommand.getStart(), scheduledCommand); - break; - case Command::ACT: - lastActivates.emplace(scheduledCommand.getStart(), scheduledCommand); - break; - default: - break; + if (lastActivates.size() == 4) + lastActivates.pop(); + lastActivates.push(scheduledCommand.getStart()); } } void ControllerState::cleanUp(sc_time time) { bus.cleanUpSlots(time); - - if (time >= config->memSpec->tActHistory()) - lastActivates.erase(lastActivates.begin(), - lastActivates.lower_bound(time - config->memSpec->tActHistory())); - - if (time >= config->memSpec->tActBHistory()) - lastActivatesB.erase(lastActivatesB.begin(), - lastActivatesB.lower_bound(time - config->memSpec->tActBHistory())); } void ControllerState::printDebugMessage(std::string message) diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 5406386f..8c9afa21 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -41,6 +41,7 @@ #include "core/Slots.h" #include "core/configuration/Configuration.h" #include +#include #include #include @@ -67,7 +68,7 @@ public: //ScheduledCommand lastScheduled; Slots bus; - std::map lastActivates; + std::queue lastActivates; std::map lastActivatesB; private: diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 6f6bb260..0c119726 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -113,14 +113,14 @@ bool ActBChecker::satsfies_activateToActivate_differentBank( return false; } } - for (auto act : state.lastActivates) { - sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ? - config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old); - if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t - && t - cmd.getStart() < tRRD)) { - return false; - } - } +// for (auto act : state.lastActivates) { +// sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ? +// config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old); +// if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t +// && t - cmd.getStart() < tRRD)) { +// return false; +// } +// } return true; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index 6b64d156..8e3b6a65 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -110,15 +110,15 @@ void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank( bool ActivateChecker::satsfies_activateToActivate_differentBank( ScheduledCommand &command) const { - for (auto act : state.lastActivates) { - sc_time time = act.first; - sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? - config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old; +// for (auto act : state.lastActivates) { +// sc_time time = act.first; +// sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? +// config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old; - if ((time < command.getStart() && command.getStart() - time < tRRD) - || (command.getStart() <= time && time - command.getStart() < tRRD)) - return false; - } +// if ((time < command.getStart() && command.getStart() - time < tRRD) +// || (command.getStart() <= time && time - command.getStart() < tRRD)) +// return false; +// } return true; } @@ -129,20 +129,20 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand &command) const * command in a copied set (not necessarily the last in time), * and check if the n-act constraint holds for the whole set. */ - if (state.lastActivates.size() >= config.memSpec->nActivate) { - map lastActivates = state.lastActivates; - lastActivates.emplace(command.getStart(), command); - auto upper = lastActivates.begin(); - advance(upper, config.memSpec->nActivate); - auto lower = lastActivates.begin(); +// if (state.lastActivates.size() >= config.memSpec->nActivate) { +// map lastActivates = state.lastActivates; +// lastActivates.emplace(command.getStart(), command); +// auto upper = lastActivates.begin(); +// advance(upper, config.memSpec->nActivate); +// auto lower = lastActivates.begin(); - while (upper != lastActivates.end()) { - if (upper->first - lower->first < config.memSpec->tNAW_old) - return false; - ++upper; - ++lower; - } - } +// while (upper != lastActivates.end()) { +// if (upper->first - lower->first < config.memSpec->tNAW_old) +// return false; +// ++upper; +// ++lower; +// } +// } return true; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 8f1722fc..94ac3ffb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -397,13 +397,13 @@ void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand bool CheckerDDR3::satsfies_activateToActivate_differentBank(ScheduledCommand &command) const { - for (auto act : state.lastActivates) - { - sc_time time = act.first; - if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) - || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) - return false; - } +// for (auto act : state.lastActivates) +// { +// sc_time time = act.first; +// if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) +// || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) +// return false; +// } return true; } @@ -415,22 +415,22 @@ bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const * command in a copied set (not necessarily the last in time), * and check if the n-act constraint holds for the whole set. */ - if (state.lastActivates.size() >= memSpec->nActivate) - { - std::map lastActivates = state.lastActivates; - lastActivates.emplace(command.getStart(), command); - auto upper = lastActivates.begin(); - std::advance(upper, memSpec->nActivate); - auto lower = lastActivates.begin(); +// if (state.lastActivates.size() >= memSpec->nActivate) +// { +// std::map lastActivates = state.lastActivates; +// lastActivates.emplace(command.getStart(), command); +// auto upper = lastActivates.begin(); +// std::advance(upper, memSpec->nActivate); +// auto lower = lastActivates.begin(); - while (upper != lastActivates.end()) - { - if (upper->first - lower->first < memSpec->tNAW_old) - return false; - upper++; - lower++; - } - } +// while (upper != lastActivates.end()) +// { +// if (upper->first - lower->first < memSpec->tNAW_old) +// return false; +// upper++; +// lower++; +// } +// } return true; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 6f4c62f3..ecac9380 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -64,6 +64,8 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (!state.bus.isFree(sc_time_stamp())) minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); + + minTimeToWait = max(minTimeToWait, timeToSatisfyFAW()); } else if (command == Command::RD || command == Command::RDA) { @@ -165,28 +167,16 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) return (minTimeToWait - sc_time_stamp()); } -bool CheckerDDR3New::satisfiesNActivateWindow(ScheduledCommand &command) const +sc_time CheckerDDR3New::timeToSatisfyFAW() { - /* - * there may be activates scheduled in the future, so emplace - * command in a copied set (not necessarily the last in time), - * and check if the n-act constraint holds for the whole set. - */ - if (state.lastActivates.size() >= memSpec->nActivate) + if (state.lastActivates.size() < 4) + return sc_time_stamp(); + else { - std::map lastActivates = state.lastActivates; - lastActivates.emplace(command.getStart(), command); - auto upper = lastActivates.begin(); - std::advance(upper, memSpec->nActivate); - auto lower = lastActivates.begin(); - - while (upper != lastActivates.end()) - { - if (upper->first - lower->first < memSpec->tNAW_old) - return false; - upper++; - lower++; - } + sc_time earliestTime = state.lastActivates.front() + memSpec->tFAW; + if (earliestTime > sc_time_stamp()) + return earliestTime; + else + return sc_time_stamp(); } - return true; } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index a658da60..08c55fe7 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -24,7 +24,7 @@ private: MemSpecDDR3 *memSpec; //Activate - bool satisfiesNActivateWindow(ScheduledCommand &command) const; + sc_time timeToSatisfyFAW(); //PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; From de650810dd96c1187a19ae80eca89cec6b92ba05 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 29 Jul 2019 11:05:03 +0200 Subject: [PATCH 045/183] Changed interface of scheduler, small bugfix (wrong debug message in Controller). --- DRAMSys/library/src/common/DebugManager.cpp | 2 +- DRAMSys/library/src/controller/BankMachine.cpp | 12 +++++++++++- DRAMSys/library/src/controller/BankMachine.h | 4 ++++ DRAMSys/library/src/controller/ControllerNew.cpp | 16 +++++++++------- .../src/controller/scheduler/SchedulerFifo.cpp | 2 +- .../src/controller/scheduler/SchedulerFifo.h | 2 +- .../src/controller/scheduler/SchedulerFrFcfs.cpp | 8 +++++--- .../src/controller/scheduler/SchedulerFrFcfs.h | 2 +- .../src/controller/scheduler/SchedulerIF.h | 3 ++- 9 files changed, 35 insertions(+), 16 deletions(-) diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp index 51e2380e..e58ec8f5 100644 --- a/DRAMSys/library/src/common/DebugManager.cpp +++ b/DRAMSys/library/src/common/DebugManager.cpp @@ -65,7 +65,7 @@ void DebugManager::openDebugFile(string filename) } DebugManager::DebugManager() : - writeToConsole(true), writeToFile(true) + writeToConsole(false), writeToFile(false) { } diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 2a2e09e0..65f51c20 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -27,7 +27,7 @@ sc_time BankMachine::startBankMachine() { if (currentPayload == nullptr) { - currentPayload = scheduler->getNextRequest(bank, currentState, currentRow); + currentPayload = scheduler->getNextRequest(bank, this); if (currentPayload == nullptr) return SC_ZERO_TIME; } @@ -90,3 +90,13 @@ void BankMachine::updateState(Command command) else SC_REPORT_FATAL("BankMachine", "Unknown phase"); } + +Row BankMachine::getOpenRow() +{ + return currentRow; +} + +BmState BankMachine::getState() +{ + return currentState; +} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 535b1296..383a7e4c 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -33,6 +33,10 @@ public: sc_time startBankMachine(); std::pair getNextCommand(); void updateState(Command); + + Row getOpenRow(); + BmState getState(); + private: tlm_generic_payload *currentPayload = nullptr; BmState currentState = BmState::Precharged; diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 9ec6afb7..49c9adaf 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -21,13 +21,13 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : state = new ControllerState("Controller", &Configuration::getInstance()); checker = new CheckerDDR3New(Configuration::getInstance(), *state); - scheduler = new SchedulerFifo(); + scheduler = new SchedulerFrFcfs(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; } - commandMux = new CmdMuxStrict(); + commandMux = new CmdMuxOldest(); } ControllerNew::~ControllerNew() @@ -134,11 +134,13 @@ void ControllerNew::controllerMethod() releasePayload(); // (2) Accept new request from arbiter - if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr - && numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) - acquirePayload(); - else - printDebugMessage("Total number of payloads exceeded, backpressure!"); + if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + { + if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) + acquirePayload(); + else + printDebugMessage("Total number of payloads exceeded, backpressure!"); + } // (3) Update states of bank machines and get results if ready for (auto it : bankMachines) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 1e459590..00055677 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -6,7 +6,7 @@ void SchedulerFifo::storeRequest(tlm_generic_payload *payload) buffer[bank].push(payload); } -tlm_generic_payload *SchedulerFifo::getNextRequest(Bank bank, BmState, Row) +tlm_generic_payload *SchedulerFifo::getNextRequest(Bank bank, BankMachine *) { if (!buffer[bank].empty()) { diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index 372f9eaf..24d25b09 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -14,7 +14,7 @@ class SchedulerFifo : public SchedulerIF { public: void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(Bank, BmState, Row); + tlm_generic_payload *getNextRequest(Bank, BankMachine *); private: std::map> buffer; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 5f3cd411..128a5893 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -7,19 +7,21 @@ void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) buffer[bank].push_back(payload); } -tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BmState state, Row openRow) +tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BankMachine *bankMachine) { if (!buffer[bank].empty()) { - if (state == BmState::Precharged) + BmState currentState = bankMachine->getState(); + if (currentState == BmState::Precharged) { tlm_generic_payload *result = buffer[bank].front(); buffer[bank].erase(buffer[bank].begin()); return result; } - else if (state == BmState::Activated) + else if (currentState == BmState::Activated) { // Search for row hit + Row openRow = bankMachine->getOpenRow(); for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { if (DramExtension::getRow(*it) == openRow) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 27db26cb..23869455 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -14,7 +14,7 @@ class SchedulerFrFcfs : public SchedulerIF { public: void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(Bank, BmState, Row); + tlm_generic_payload *getNextRequest(Bank, BankMachine *); private: std::map> buffer; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index 7170591c..a4025f6d 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -9,13 +9,14 @@ using namespace tlm; enum class BmState; +class BankMachine; class SchedulerIF { public: virtual ~SchedulerIF() {} virtual void storeRequest(tlm_generic_payload *) = 0; - virtual tlm_generic_payload *getNextRequest(Bank, BmState, Row) = 0; + virtual tlm_generic_payload *getNextRequest(Bank, BankMachine *) = 0; protected: void printDebugMessage(std::string message) { From 91755962a2b2f7053c59ce661abadfc603670bc8 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 29 Jul 2019 14:17:03 +0200 Subject: [PATCH 046/183] Improvement in timing checker: additional map instead of for loops. --- .../src/controller/ControllerState.cpp | 18 ++--- .../library/src/controller/ControllerState.h | 2 +- .../scheduling/checker/CheckerDDR3New.cpp | 68 ++++++++----------- 3 files changed, 37 insertions(+), 51 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index ad896cdf..bc95cfb7 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -49,15 +49,7 @@ const ScheduledCommand ControllerState::getLastCommandOnBank(Command command, const ScheduledCommand ControllerState::getLastCommand(Command command) { - ScheduledCommand max; - - for (unsigned int i = 0; i < config->memSpec->NumberOfBanks; ++i) { - ScheduledCommand current = getLastCommandOnBank(command, Bank(i)); - if (current.getStart() > max.getStart()) - max = current; - } - - return max; + return lastScheduledByCommand[command]; } const ScheduledCommand ControllerState::getLastScheduledCommand() @@ -96,16 +88,18 @@ const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank) void ControllerState::change(const ScheduledCommand &scheduledCommand) { + Command command = scheduledCommand.getCommand(); printDebugMessage("Changing state on bank " + to_string( scheduledCommand.getBank().ID()) + " command is " + commandToString( - scheduledCommand.getCommand())); + command)); bus.blockSlot(scheduledCommand.getStart()); - lastScheduledByCommandAndBank[scheduledCommand.getCommand()][scheduledCommand.getBank()] + lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] = scheduledCommand; + lastScheduledByCommand[command] = scheduledCommand; // TODO: implement FAW for ACTB - if (scheduledCommand.getCommand() == Command::ACT) + if (command == Command::ACT) { if (lastActivates.size() == 4) lastActivates.pop(); diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 8c9afa21..2e02c693 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -63,7 +63,7 @@ public: //used by the various checkers std::map> lastScheduledByCommandAndBank; // TODO: remove - //std::map lastScheduledByCommand; + std::map lastScheduledByCommand; //std::map lastScheduledByBank; //ScheduledCommand lastScheduled; diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index ecac9380..29ed9c19 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -55,12 +55,9 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); - for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - { - lastCommand = state.getLastCommandOnBank(Command::ACT, Bank(bankID)); - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); - } + lastCommand = state.getLastCommand(Command::ACT); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); if (!state.bus.isFree(sc_time_stamp())) minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); @@ -70,16 +67,7 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) else if (command == Command::RD || command == Command::RDA) { lastCommand = state.getLastCommandOnBank(Command::ACT, bank); - //if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); - -// lastCommand = state.getLastCommand(Command::RD, bank); -// if (lastCommand.isValidCommand()) -// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - -// lastCommand = state.getLastCommand(Command::WR, bank); -// if (lastCommand.isValidCommand()) -// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) @@ -89,25 +77,21 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + lastCommand = state.getLastCommand(Command::RD); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + + lastCommand = state.getLastCommand(Command::WR); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + if (!state.bus.isFree(sc_time_stamp())) minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); - - for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - { - lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - - lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - } } else if (command == Command::WR || command == Command::WRA) { lastCommand = state.getLastCommandOnBank(Command::ACT, bank); - //if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); // lastCommand = state.getLastCommand(Command::RD, bank); // if (lastCommand.isValidCommand()) @@ -128,16 +112,24 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (!state.bus.isFree(sc_time_stamp())) minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); - for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - { - lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); +// for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) +// { +// lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); +// if (lastCommand.isValidCommand()) +// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - } +// lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); +// if (lastCommand.isValidCommand()) +// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); +// } + + lastCommand = state.getLastCommand(Command::RD); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + + lastCommand = state.getLastCommand(Command::WR); + if (lastCommand.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); } else if (command == Command::PRE) { From 4fa59c24103a9d617d742fc67cc6c2de0616af41 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 29 Jul 2019 16:44:14 +0200 Subject: [PATCH 047/183] Included ControllerRecordable for disabling of trace recording. --- DRAMSys/library/library.pro | 6 +- .../library/src/controller/ControllerNew.cpp | 51 +++--------- .../library/src/controller/ControllerNew.h | 21 +++-- .../src/controller/ControllerRecordable.cpp | 78 +++++++++++++++++++ .../src/controller/ControllerRecordable.h | 27 +++++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 14 ++-- 6 files changed, 135 insertions(+), 62 deletions(-) create mode 100644 DRAMSys/library/src/controller/ControllerRecordable.cpp create mode 100644 DRAMSys/library/src/controller/ControllerRecordable.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 8f8d6e9f..c7ddd020 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -155,7 +155,8 @@ SOURCES += \ src/controller/scheduler/SchedulerFifo.cpp \ src/controller/scheduler/SchedulerFrFcfs.cpp \ src/controller/cmdmux/CmdMuxStrict.cpp \ - src/controller/cmdmux/CmdMuxOldest.cpp + src/controller/cmdmux/CmdMuxOldest.cpp \ + src/controller/ControllerRecordable.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -246,7 +247,8 @@ HEADERS += \ src/controller/scheduler/SchedulerFrFcfs.h \ src/controller/cmdmux/CmdMuxIF.h \ src/controller/cmdmux/CmdMuxStrict.h \ - src/controller/cmdmux/CmdMuxOldest.h + src/controller/cmdmux/CmdMuxOldest.h \ + src/controller/ControllerRecordable.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 49c9adaf..48239bb6 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -8,8 +8,8 @@ #include "../common/protocol.h" #include "core/scheduling/ScheduledCommand.h" -ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : - sc_module(name), tlmRecorder(tlmRecorder), debugManager(&DebugManager::getInstance()) +ControllerNew::ControllerNew(sc_module_name name) : + sc_module(name), debugManager(&DebugManager::getInstance()) { SC_METHOD(controllerMethod); sensitive << triggerEvent << triggerEventQueue; @@ -43,7 +43,6 @@ ControllerNew::~ControllerNew() tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - recordPhase(trans, phase, delay); sc_time notificationDelay = delay; if (phase == BEGIN_REQ) @@ -70,7 +69,6 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - recordPhase(trans, phase, delay); printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); Bank bank = DramExtension::getExtension(trans).getBank(); @@ -90,26 +88,6 @@ void ControllerNew::printDebugMessage(string message) debugManager->printDebugMessage(name(), message); } -void ControllerNew::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) -{ - sc_time recTime = delay + sc_time_stamp(); - - unsigned int thr = DramExtension::getExtension(trans).getThread().ID(); - unsigned int ch = DramExtension::getExtension(trans).getChannel().ID(); - unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID(); - unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); - unsigned int row = DramExtension::getExtension(trans).getRow().ID(); - unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); - unsigned int id = DramExtension::getExtension(trans).getPayloadID(); - - printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + - to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( - bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " id " + to_string(id) + " at " + recTime.to_string()); - - tlmRecorder->recordPhase(trans, phase, recTime); -} - void ControllerNew::triggerEventAfterDelay(sc_time delay) { if (delay != SC_ZERO_TIME) @@ -155,7 +133,10 @@ void ControllerNew::controllerMethod() // (4) Send result to arbiter if (payloadToRelease == nullptr && !responseQueue.empty()) - sendToFrontend(); + { + payloadToRelease = responseQueue.front(); + sendToFrontend(payloadToRelease, BEGIN_RESP); + } // (5) Start bank machines to issue new requests for current time for (auto it : bankMachines) @@ -207,21 +188,15 @@ void ControllerNew::acquirePayload() numberOfPayloads++; payloadToAcquire->set_response_status(TLM_OK_RESPONSE); - tlm_phase tPhase = END_REQ; - sc_time tDelay = SC_ZERO_TIME; - recordPhase(*payloadToAcquire, tPhase, tDelay); - tSocket->nb_transport_bw(*payloadToAcquire, tPhase, tDelay); + sendToFrontend(payloadToAcquire, END_REQ); payloadToAcquire = nullptr; } -void ControllerNew::sendToFrontend() +void ControllerNew::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) { - payloadToRelease = responseQueue.front(); - tlm_phase tPhase = BEGIN_RESP; - sc_time tDelay = SC_ZERO_TIME; - recordPhase(*payloadToRelease, tPhase, tDelay); - tSocket->nb_transport_bw(*payloadToRelease, tPhase, tDelay); + sc_time delay = SC_ZERO_TIME; + tSocket->nb_transport_bw(*payload, phase, delay); } void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) @@ -242,16 +217,10 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::RD) { phase = BEGIN_RD; - ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); - TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); - tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } else if (command == Command::WR) { phase = BEGIN_WR; - ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); - TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); - tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } else SC_REPORT_FATAL("ControllerNew", "Unknown phase"); diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 7fa4ab94..48874d3b 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -12,7 +12,6 @@ #include "BankMachine.h" #include "cmdmux/CmdMuxIF.h" #include "scheduler/SchedulerIF.h" -#include "../common/TlmRecorder.h" #include "../common/DebugManager.h" #include "core/scheduling/checker/CheckerDDR3New.h" #include "ControllerState.h" @@ -25,23 +24,26 @@ class SchedulerIF; class ControllerNew : public sc_module { public: - ControllerNew(sc_module_name, TlmRecorder *); + ControllerNew(sc_module_name); SC_HAS_PROCESS(ControllerNew); - ~ControllerNew(); + virtual ~ControllerNew(); tlm_utils::simple_target_socket tSocket; tlm_utils::simple_initiator_socket iSocket; -private: - tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, +protected: + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); - tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, + virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay); - unsigned int transport_dbg(tlm_generic_payload &); + virtual unsigned int transport_dbg(tlm_generic_payload &); + + virtual void sendToFrontend(tlm_generic_payload *, tlm_phase); + virtual void sendToDram(Command, tlm_generic_payload *); void printDebugMessage(string message); - void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay); +//private: unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; sc_time timeToAcquire = SC_ZERO_TIME; @@ -49,7 +51,6 @@ private: sc_time timeToRelease = SC_ZERO_TIME; std::queue responseQueue; - TlmRecorder *tlmRecorder; DebugManager *debugManager; ControllerState *state; @@ -60,8 +61,6 @@ private: void releasePayload(); void acquirePayload(); - void sendToFrontend(); - void sendToDram(Command, tlm_generic_payload *); void controllerMethod(); sc_event triggerEvent; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp new file mode 100644 index 00000000..4a424a9a --- /dev/null +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -0,0 +1,78 @@ +#include "ControllerRecordable.h" +#include "../common/protocol.h" + +tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) +{ + recordPhase(trans, phase, delay); + return ControllerNew::nb_transport_fw(trans, phase, delay); +} + +tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) +{ + recordPhase(trans, phase, delay); + return ControllerNew::nb_transport_bw(trans, phase, delay); +} + +void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) +{ + sc_time delay = SC_ZERO_TIME; + recordPhase(*payload, phase, delay); + tSocket->nb_transport_bw(*payload, phase, delay); +} +// TODO: call ControllerNew::sendToDram +void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload) +{ + sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); + ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); + state->cleanUp(sc_time_stamp()); + state->change(scheduledCommand); + Bank bank = scheduledCommand.getBank(); + bankMachines[bank]->updateState(command); + + sc_time delay = SC_ZERO_TIME; + tlm_phase phase; + if (command == Command::ACT) + phase = BEGIN_ACT; + else if (command == Command::PRE) + phase = BEGIN_PRE; + else if (command == Command::RD) + { + phase = BEGIN_RD; + ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); + TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); + tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); + } + else if (command == Command::WR) + { + phase = BEGIN_WR; + ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); + TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); + tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); + } + else + SC_REPORT_FATAL("ControllerNew", "Unknown phase"); + + iSocket->nb_transport_fw(*payload, phase, delay); +} + +void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) +{ + sc_time recTime = delay + sc_time_stamp(); + + unsigned int thr = DramExtension::getExtension(trans).getThread().ID(); + unsigned int ch = DramExtension::getExtension(trans).getChannel().ID(); + unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID(); + unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); + unsigned int row = DramExtension::getExtension(trans).getRow().ID(); + unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); + unsigned int id = DramExtension::getExtension(trans).getPayloadID(); + + printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( + bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + + to_string(col) + " id " + to_string(id) + " at " + recTime.to_string()); + + tlmRecorder->recordPhase(trans, phase, recTime); +} diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h new file mode 100644 index 00000000..0540bd78 --- /dev/null +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -0,0 +1,27 @@ +#ifndef CONTROLLERRECORDABLE_H +#define CONTROLLERRECORDABLE_H + +#include "ControllerNew.h" +#include "../common/TlmRecorder.h" + +class ControllerRecordable final : public ControllerNew +{ +public: + ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) : + ControllerNew(name), tlmRecorder(tlmRecorder) {} + +private: + tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) override; + tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, + tlm_phase &phase, sc_time &delay) override; + + void sendToFrontend(tlm_generic_payload *, tlm_phase) override; + void sendToDram(Command, tlm_generic_payload *) override; + + void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay); + + TlmRecorder *tlmRecorder; +}; + +#endif // CONTROLLERRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index d4482924..21be54a1 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -59,6 +59,7 @@ #include "DramDDR4.h" #include "DramWideIO.h" #include "../controller/ControllerNew.h" +#include "../controller/ControllerRecordable.h" using namespace std; @@ -252,14 +253,11 @@ void DRAMSys::instantiateModules(const string &traceName, { std::string str = "controller" + std::to_string(i); -// GenericController *controller; -// if (recordingEnabled) -// controller = new RecordableController(str.c_str(), tlmRecorders[i]); -// else -// controller = new Controller(str.c_str()); -// controllers.push_back(controller); - - ControllerNew *controller = new ControllerNew(str.c_str(), tlmRecorders[i]); + ControllerNew *controller; + if (recordingEnabled) + controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]); + else + controller = new ControllerNew(str.c_str()); newControllers.push_back(controller); str = "dram" + std::to_string(i); From fb9abb9cee887294d16067c53feae02609442466 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 29 Jul 2019 20:55:40 +0200 Subject: [PATCH 048/183] Changed type of payloadID to uint64_t for overflow prevention. --- DRAMSys/library/src/common/dramExtensions.cpp | 10 +++++----- DRAMSys/library/src/common/dramExtensions.h | 12 ++++++------ DRAMSys/library/src/controller/ControllerNew.cpp | 4 ++-- .../library/src/controller/ControllerRecordable.cpp | 2 +- DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h | 2 +- DRAMSys/library/src/simulation/Arbiter.h | 2 +- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 18ae9a40..cce8f853 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -49,13 +49,13 @@ DramExtension::DramExtension() : DramExtension::DramExtension(const Thread &thread, const Bank &bank, const BankGroup &bankgroup, const Row &row, const Column &column, - unsigned int burstlength, unsigned int payloadID) : + unsigned int burstlength, uint64_t payloadID) : thread(thread), channel(0), bank(bank), bankgroup(bankgroup), row(row), column(column), burstlength(burstlength), payloadID(payloadID) {} DramExtension::DramExtension(const Thread &thread, const Channel &channel, const Bank &bank, const BankGroup &bankgroup, const Row &row, - const Column &column, unsigned int burstlength, unsigned int payloadID) : + const Column &column, unsigned int burstlength, uint64_t payloadID) : thread(thread), channel(channel), bank(bank), bankgroup(bankgroup), row(row), column(column), burstlength(burstlength), payloadID(payloadID) {} @@ -113,12 +113,12 @@ Row DramExtension::getRow(const tlm_generic_payload &payload) return DramExtension::getRow(&payload); } -unsigned int DramExtension::getPayloadID(const tlm_generic_payload *payload) +uint64_t DramExtension::getPayloadID(const tlm_generic_payload *payload) { return DramExtension::getExtension(payload).getPayloadID(); } -unsigned int DramExtension::getPayloadID(const tlm_generic_payload &payload) +uint64_t DramExtension::getPayloadID(const tlm_generic_payload &payload) { return DramExtension::getPayloadID(&payload); } @@ -174,7 +174,7 @@ unsigned int DramExtension::getBurstlength() const return burstlength; } -unsigned int DramExtension::getPayloadID() const +uint64_t DramExtension::getPayloadID() const { return payloadID; } diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 4491f3ca..aa3a176b 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -151,10 +151,10 @@ public: DramExtension(); DramExtension(const Thread &thread, const Bank &bank, const BankGroup &bankgroup, const Row &row, const Column &column, - unsigned int burstlength, unsigned int payloadID); + unsigned int burstlength, uint64_t payloadID); DramExtension(const Thread &thread, const Channel &channel, const Bank &bank, const BankGroup &bankgroup, const Row &row, - const Column &column, unsigned int burstlength, unsigned int payloadID); + const Column &column, unsigned int burstlength, uint64_t payloadID); virtual tlm_extension_base *clone() const; virtual void copy_from(const tlm_extension_base &ext); @@ -171,8 +171,8 @@ public: static Thread getThread(const tlm::tlm_generic_payload &payload); static Row getRow(const tlm::tlm_generic_payload *payload); static Row getRow(const tlm::tlm_generic_payload &payload); - static unsigned int getPayloadID(const tlm::tlm_generic_payload *payload); - static unsigned int getPayloadID(const tlm::tlm_generic_payload &payload); + static uint64_t getPayloadID(const tlm::tlm_generic_payload *payload); + static uint64_t getPayloadID(const tlm::tlm_generic_payload &payload); Thread getThread() const; Channel getChannel() const; @@ -182,7 +182,7 @@ public: Column getColumn() const; unsigned int getBurstlength() const; - unsigned int getPayloadID() const; + uint64_t getPayloadID() const; void incrementRow(); private: @@ -193,7 +193,7 @@ private: Row row; Column column; unsigned int burstlength; - unsigned int payloadID; + uint64_t payloadID; }; diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 48239bb6..ea047f85 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -169,7 +169,7 @@ void ControllerNew::controllerMethod() void ControllerNew::releasePayload() { - unsigned id = DramExtension::getPayloadID(payloadToRelease); + uint64_t id = DramExtension::getPayloadID(payloadToRelease); printDebugMessage("Payload " + std::to_string(id) + " left system."); responseQueue.pop(); @@ -180,7 +180,7 @@ void ControllerNew::releasePayload() void ControllerNew::acquirePayload() { - unsigned id = DramExtension::getPayloadID(payloadToAcquire); + uint64_t id = DramExtension::getPayloadID(payloadToAcquire); printDebugMessage("Payload " + std::to_string(id) + " entered system."); scheduler->storeRequest(payloadToAcquire); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 4a424a9a..d6d6480b 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -67,7 +67,7 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); unsigned int row = DramExtension::getExtension(trans).getRow().ID(); unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); - unsigned int id = DramExtension::getExtension(trans).getPayloadID(); + uint64_t id = DramExtension::getExtension(trans).getPayloadID(); printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h index 1b70b695..e5228e99 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h @@ -10,7 +10,7 @@ public: selectCommand(std::vector> &); private: - unsigned nextPayloadID = 0; + uint64_t nextPayloadID = 0; }; #endif // CMDMUXSTRICT_H diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 206cd605..cb2bc27a 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -96,7 +96,7 @@ private: const tlm_phase &phase, const sc_time &delay); void appendDramExtension(int socketId, tlm_generic_payload &payload); - std::vector nextPayloadID; + std::vector nextPayloadID; bool addressIsValid(DecodedAddress &decodedAddress); From b477424a98d22f80b4e44f2ec66208f503fb594a Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 30 Jul 2019 13:30:59 +0200 Subject: [PATCH 049/183] Bugfix: Commands on one bank can overlap now. --- .../library/src/controller/BankMachine.cpp | 30 ++---------- DRAMSys/library/src/controller/BankMachine.h | 7 +-- .../library/src/controller/ControllerNew.cpp | 49 ++++++++----------- .../library/src/controller/ControllerNew.h | 3 +- .../src/controller/ControllerRecordable.cpp | 1 - 5 files changed, 28 insertions(+), 62 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 65f51c20..ab17ed03 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -3,26 +3,6 @@ BankMachine::BankMachine(SchedulerIF *scheduler, CheckerDDR3New *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) {} -tlm_generic_payload *BankMachine::getNextStateAndResult() -{ - tlm_generic_payload *payloadToReturn = nullptr; - - if (currentState == BmState::Activating) - currentState = BmState::Activated; - else if (currentState == BmState::Precharging) - currentState = BmState::Precharged; - else if (currentState == BmState::Reading || currentState == BmState::Writing) - { - currentState = BmState::Activated; - payloadToReturn = currentPayload; - currentPayload = nullptr; - } - else - SC_REPORT_FATAL(("BankMachine " + bank.toString()).c_str(), "Wrong command!"); - - return payloadToReturn; -} - sc_time BankMachine::startBankMachine() { if (currentPayload == nullptr) @@ -80,13 +60,11 @@ std::pair BankMachine::getNextCommand() void BankMachine::updateState(Command command) { if (command == Command::ACT) - currentState = BmState::Activating; + currentState = BmState::Activated; else if (command == Command::PRE) - currentState = BmState::Precharging; - else if (command == Command::RD) - currentState = BmState::Reading; - else if (command == Command::WR) - currentState = BmState::Writing; + currentState = BmState::Precharged; + else if (command == Command::RD || command == Command::WR) + currentPayload = nullptr; else SC_REPORT_FATAL("BankMachine", "Unknown phase"); } diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 383a7e4c..33750f44 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -18,18 +18,13 @@ class CheckerDDR3New; enum class BmState { Precharged, - Activated, - Precharging, - Activating, - Reading, - Writing + Activated }; class BankMachine { public: BankMachine(SchedulerIF *, CheckerDDR3New*, Bank); - tlm_generic_payload *getNextStateAndResult(); sc_time startBankMachine(); std::pair getNextCommand(); void updateState(Command); diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index ea047f85..27f19437 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -21,13 +21,10 @@ ControllerNew::ControllerNew(sc_module_name name) : state = new ControllerState("Controller", &Configuration::getInstance()); checker = new CheckerDDR3New(Configuration::getInstance(), *state); - scheduler = new SchedulerFrFcfs(); + scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - { bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); - commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; - } - commandMux = new CmdMuxOldest(); + commandMux = new CmdMuxStrict(); } ControllerNew::~ControllerNew() @@ -71,9 +68,12 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, { printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); - Bank bank = DramExtension::getExtension(trans).getBank(); - commandFinishedTime[bank] = sc_time_stamp() + delay; triggerEventQueueAfterDelay(delay); + if (phase == END_RD || phase == END_WR) + { + std::pair element((sc_time_stamp() + delay), &trans); + responseQueue.push(element); + } return TLM_ACCEPTED; } @@ -120,29 +120,23 @@ void ControllerNew::controllerMethod() printDebugMessage("Total number of payloads exceeded, backpressure!"); } - // (3) Update states of bank machines and get results if ready - for (auto it : bankMachines) + // (3) Send result to arbiter + if (payloadToRelease == nullptr && !responseQueue.empty()) { - if (commandFinishedTime[it.first] == sc_time_stamp()) + std::pair element = responseQueue.front(); + if (sc_time_stamp() >= element.first) { - tlm_generic_payload *result = it.second->getNextStateAndResult(); - if (result != nullptr) - responseQueue.push(result); + payloadToRelease = element.second; + responseQueue.pop(); + sendToFrontend(payloadToRelease, BEGIN_RESP); } } - // (4) Send result to arbiter - if (payloadToRelease == nullptr && !responseQueue.empty()) - { - payloadToRelease = responseQueue.front(); - sendToFrontend(payloadToRelease, BEGIN_RESP); - } - - // (5) Start bank machines to issue new requests for current time + // (4) Start bank machines to issue new requests for current time for (auto it : bankMachines) it.second->startBankMachine(); - // (6) Choose one request and send it to DRAM + // (5) Choose one request and send it to DRAM std::vector> readyCommands; std::pair result; for (auto it : bankMachines) @@ -155,10 +149,14 @@ void ControllerNew::controllerMethod() { result = commandMux->selectCommand(readyCommands); if (result.second != nullptr) + { + Bank bank = DramExtension::getBank(result.second); + bankMachines[bank]->updateState(result.first); sendToDram(result.first, result.second); + } } - // (7) Restart bank machines to issue new requests for the future + // (6) Restart bank machines to issue new requests for the future for (auto it : bankMachines) { sc_time delay = it.second->startBankMachine(); @@ -172,7 +170,6 @@ void ControllerNew::releasePayload() uint64_t id = DramExtension::getPayloadID(payloadToRelease); printDebugMessage("Payload " + std::to_string(id) + " left system."); - responseQueue.pop(); payloadToRelease->release(); numberOfPayloads--; payloadToRelease = nullptr; @@ -186,10 +183,8 @@ void ControllerNew::acquirePayload() scheduler->storeRequest(payloadToAcquire); payloadToAcquire->acquire(); numberOfPayloads++; - payloadToAcquire->set_response_status(TLM_OK_RESPONSE); sendToFrontend(payloadToAcquire, END_REQ); - payloadToAcquire = nullptr; } @@ -205,8 +200,6 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); state->cleanUp(sc_time_stamp()); state->change(scheduledCommand); - Bank bank = scheduledCommand.getBank(); - bankMachines[bank]->updateState(command); sc_time delay = SC_ZERO_TIME; tlm_phase phase; diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 48874d3b..aae06319 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -49,7 +50,7 @@ protected: sc_time timeToAcquire = SC_ZERO_TIME; tlm_generic_payload *payloadToRelease = nullptr; sc_time timeToRelease = SC_ZERO_TIME; - std::queue responseQueue; + std::queue> responseQueue; DebugManager *debugManager; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index d6d6480b..30a54c7b 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -29,7 +29,6 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl state->cleanUp(sc_time_stamp()); state->change(scheduledCommand); Bank bank = scheduledCommand.getBank(); - bankMachines[bank]->updateState(command); sc_time delay = SC_ZERO_TIME; tlm_phase phase; From b9f0c31ddfed18da00f5189fe4e50043f26550e0 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 30 Jul 2019 15:14:24 +0200 Subject: [PATCH 050/183] Moved controller state into timing checker. Inserted preambles. --- .../library/src/controller/BankMachine.cpp | 34 ++++ DRAMSys/library/src/controller/BankMachine.h | 34 ++++ .../library/src/controller/ControllerNew.cpp | 46 ++++-- .../library/src/controller/ControllerNew.h | 38 ++++- .../src/controller/ControllerRecordable.cpp | 67 ++++---- .../src/controller/ControllerRecordable.h | 34 ++++ .../src/controller/ControllerState.cpp | 18 +-- .../library/src/controller/ControllerState.h | 2 +- .../library/src/controller/cmdmux/CmdMuxIF.h | 34 ++++ .../src/controller/cmdmux/CmdMuxOldest.cpp | 35 ++++ .../src/controller/cmdmux/CmdMuxOldest.h | 34 ++++ .../src/controller/cmdmux/CmdMuxStrict.cpp | 35 ++++ .../src/controller/cmdmux/CmdMuxStrict.h | 34 ++++ .../scheduling/checker/CheckerDDR3New.cpp | 149 +++++++++++------- .../core/scheduling/checker/CheckerDDR3New.h | 59 ++++++- .../controller/scheduler/SchedulerFifo.cpp | 34 ++++ .../src/controller/scheduler/SchedulerFifo.h | 34 ++++ .../controller/scheduler/SchedulerFrFcfs.cpp | 35 ++++ .../controller/scheduler/SchedulerFrFcfs.h | 34 ++++ .../src/controller/scheduler/SchedulerIF.h | 34 ++++ 20 files changed, 702 insertions(+), 122 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index ab17ed03..36ea5414 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "BankMachine.h" BankMachine::BankMachine(SchedulerIF *scheduler, CheckerDDR3New *checker, Bank bank) diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 33750f44..dc561680 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef BANKMACHINE_H #define BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 27f19437..f0ace2e7 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -1,4 +1,39 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "ControllerNew.h" + #include "core/configuration/Configuration.h" #include "scheduler/SchedulerFifo.h" #include "scheduler/SchedulerFrFcfs.h" @@ -19,8 +54,7 @@ ControllerNew::ControllerNew(sc_module_name name) : tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg); iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw); - state = new ControllerState("Controller", &Configuration::getInstance()); - checker = new CheckerDDR3New(Configuration::getInstance(), *state); + checker = new CheckerDDR3New(); scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); @@ -29,7 +63,6 @@ ControllerNew::ControllerNew(sc_module_name name) : ControllerNew::~ControllerNew() { - delete state; delete checker; for (auto it : bankMachines) delete it.second; @@ -198,8 +231,7 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) { sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); - state->cleanUp(sc_time_stamp()); - state->change(scheduledCommand); + checker->insert(scheduledCommand); sc_time delay = SC_ZERO_TIME; tlm_phase phase; @@ -208,13 +240,9 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::PRE) phase = BEGIN_PRE; else if (command == Command::RD) - { phase = BEGIN_RD; - } else if (command == Command::WR) - { phase = BEGIN_WR; - } else SC_REPORT_FATAL("ControllerNew", "Unknown phase"); diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index aae06319..e1dd1c0f 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef CONTROLLERNEW_H #define CONTROLLERNEW_H @@ -15,7 +49,6 @@ #include "scheduler/SchedulerIF.h" #include "../common/DebugManager.h" #include "core/scheduling/checker/CheckerDDR3New.h" -#include "ControllerState.h" using namespace tlm; @@ -44,7 +77,7 @@ protected: void printDebugMessage(string message); -//private: +private: unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; sc_time timeToAcquire = SC_ZERO_TIME; @@ -54,7 +87,6 @@ protected: DebugManager *debugManager; - ControllerState *state; std::map bankMachines; CmdMuxIF *commandMux; SchedulerIF *scheduler; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 30a54c7b..95f101a1 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -1,4 +1,39 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "ControllerRecordable.h" + #include "../common/protocol.h" tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, @@ -21,39 +56,17 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phas recordPhase(*payload, phase, delay); tSocket->nb_transport_bw(*payload, phase, delay); } -// TODO: call ControllerNew::sendToDram + void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload) { - sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); - ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); - state->cleanUp(sc_time_stamp()); - state->change(scheduledCommand); - Bank bank = scheduledCommand.getBank(); - - sc_time delay = SC_ZERO_TIME; - tlm_phase phase; - if (command == Command::ACT) - phase = BEGIN_ACT; - else if (command == Command::PRE) - phase = BEGIN_PRE; - else if (command == Command::RD) + if (command == Command::RD || command == Command::WR) { - phase = BEGIN_RD; - ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); + sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); + ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } - else if (command == Command::WR) - { - phase = BEGIN_WR; - ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); - TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); - tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); - } - else - SC_REPORT_FATAL("ControllerNew", "Unknown phase"); - - iSocket->nb_transport_fw(*payload, phase, delay); + ControllerNew::sendToDram(command, payload); } void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index 0540bd78..17459b7d 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef CONTROLLERRECORDABLE_H #define CONTROLLERRECORDABLE_H diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index bc95cfb7..9f3b9a2d 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -54,20 +54,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command) const ScheduledCommand ControllerState::getLastScheduledCommand() { - ScheduledCommand lastCommand; - - for (Command cmd : getAllCommands()) { - for (Bank bank : Configuration::getInstance().memSpec->getBanks()) { - ScheduledCommand ¤t = lastScheduledByCommandAndBank[cmd][bank]; - if (current.getStart() > lastCommand.getStart()) - lastCommand = current; - } - } - - printDebugMessage("Last scheduled command was " + commandToString( - lastCommand.getCommand())); - - return lastCommand; + return lastScheduled; } const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank) @@ -93,10 +80,11 @@ void ControllerState::change(const ScheduledCommand &scheduledCommand) scheduledCommand.getBank().ID()) + " command is " + commandToString( command)); - bus.blockSlot(scheduledCommand.getStart()); + //bus.blockSlot(scheduledCommand.getStart()); lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] = scheduledCommand; lastScheduledByCommand[command] = scheduledCommand; + lastScheduled = scheduledCommand; // TODO: implement FAW for ACTB if (command == Command::ACT) diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 2e02c693..6430c5ba 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -65,7 +65,7 @@ public: // TODO: remove std::map lastScheduledByCommand; //std::map lastScheduledByBank; - //ScheduledCommand lastScheduled; + ScheduledCommand lastScheduled; Slots bus; std::queue lastActivates; diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h index 7e700862..2e599656 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef CMDMUXIF_H #define CMDMUXIF_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index d912e4de..6414c3ce 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -1,4 +1,39 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "CmdMuxOldest.h" + #include "../../common/dramExtensions.h" std::pair diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h index cb3c1d1d..124d056c 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef CMDMUXOLDEST_H #define CMDMUXOLDEST_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index 0b39329e..024beaf3 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -1,4 +1,39 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "CmdMuxStrict.h" + #include "../../common/dramExtensions.h" std::pair diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h index e5228e99..8c98b8c6 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef CMDMUXSTRICT_H #define CMDMUXSTRICT_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 29ed9c19..c4f8f007 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "CheckerDDR3New.h" #include @@ -19,156 +53,153 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (command == Command::ACT) { - lastCommand = state.getLastCommandOnBank(Command::RDA, bank); + lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - lastCommand = state.getLastCommandOnBank(Command::WRA, bank); + lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = state.getLastCommandOnBank(Command::PRE, bank); + lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommandOnBank(Command::PREA, bank); + lastCommand = lastScheduledByCommand[Command::PREA]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); + lastCommand = lastScheduledByCommand[Command::PDXA]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommandOnBank(Command::PDXP, bank); + lastCommand = lastScheduledByCommand[Command::PDXP]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommandOnBank(Command::REFA, bank); + lastCommand = lastScheduledByCommand[Command::REFA]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); - lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); + lastCommand = lastScheduledByCommand[Command::SREFEX]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); - lastCommand = state.getLastCommandOnBank(Command::ACT, bank); + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); - lastCommand = state.getLastCommand(Command::ACT); + lastCommand = lastScheduledByCommand[Command::ACT]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); - if (!state.bus.isFree(sc_time_stamp())) - minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); - minTimeToWait = max(minTimeToWait, timeToSatisfyFAW()); } else if (command == Command::RD || command == Command::RDA) { - lastCommand = state.getLastCommandOnBank(Command::ACT, bank); + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); - lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); + lastCommand = lastScheduledByCommand[Command::PDXA]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); + lastCommand = lastScheduledByCommand[Command::SREFEX]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); - lastCommand = state.getLastCommand(Command::RD); + lastCommand = lastScheduledByCommand[Command::RD]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - lastCommand = state.getLastCommand(Command::WR); + lastCommand = lastScheduledByCommand[Command::WR]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - - if (!state.bus.isFree(sc_time_stamp())) - minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); } else if (command == Command::WR || command == Command::WRA) { - lastCommand = state.getLastCommandOnBank(Command::ACT, bank); + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); -// lastCommand = state.getLastCommand(Command::RD, bank); -// if (lastCommand.isValidCommand()) -// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - -// lastCommand = state.getLastCommand(Command::WR, bank); -// if (lastCommand.isValidCommand()) -// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - - lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); + lastCommand = lastScheduledByCommand[Command::PDXA]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); + lastCommand = lastScheduledByCommand[Command::SREFEX]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); - if (!state.bus.isFree(sc_time_stamp())) - minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); - -// for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) -// { -// lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); -// if (lastCommand.isValidCommand()) -// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - -// lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); -// if (lastCommand.isValidCommand()) -// minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); -// } - - lastCommand = state.getLastCommand(Command::RD); + lastCommand = lastScheduledByCommand[Command::RD]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = state.getLastCommand(Command::WR); + lastCommand = lastScheduledByCommand[Command::WR]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); } else if (command == Command::PRE) { - lastCommand = state.getLastCommandOnBank(Command::ACT, bank); - //if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); - lastCommand = state.getLastCommandOnBank(Command::RD, bank); + lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); - lastCommand = state.getLastCommandOnBank(Command::WR, bank); + lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); + lastCommand = lastScheduledByCommand[Command::PDXA]; if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - if (!state.bus.isFree(sc_time_stamp())) - minTimeToWait = max(minTimeToWait, sc_time_stamp() + memSpec->clk); } else { reportFatal("CheckerDDR3New", "Unknown command!"); } + // Check if bus is free + if (lastScheduled.isValidCommand()) + minTimeToWait = max(minTimeToWait, lastScheduled.getStart() + memSpec->clk); + return (minTimeToWait - sc_time_stamp()); } sc_time CheckerDDR3New::timeToSatisfyFAW() { - if (state.lastActivates.size() < 4) + if (lastActivates.size() < 4) return sc_time_stamp(); else { - sc_time earliestTime = state.lastActivates.front() + memSpec->tFAW; + sc_time earliestTime = lastActivates.front() + memSpec->tFAW; if (earliestTime > sc_time_stamp()) return earliestTime; else return sc_time_stamp(); } } + +void CheckerDDR3New::insert(const ScheduledCommand &scheduledCommand) +{ + Command command = scheduledCommand.getCommand(); + printDebugMessage("Changing state on bank " + + to_string(scheduledCommand.getBank().ID()) + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] = scheduledCommand; + lastScheduledByCommand[command] = scheduledCommand; + lastScheduled = scheduledCommand; + + // TODO: implement FAW for ACTB + if (command == Command::ACT) + { + if (lastActivates.size() == 4) + lastActivates.pop(); + lastActivates.push(scheduledCommand.getStart()); + } +} + +void CheckerDDR3New::printDebugMessage(std::string message) +{ + DebugManager::getInstance().printDebugMessage("Checker", message); +} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 08c55fe7..81b50295 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -1,16 +1,54 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef CHECKERDDR3NEW_H #define CHECKERDDR3NEW_H -#include "ICommandChecker.h" +#include +#include +#include +#include "../ScheduledCommand.h" #include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" +#include "../../configuration/MemSpec.h" +#include "../../../Command.h" +#include "../../../../common/dramExtensions.h" //Activate class CheckerDDR3New { public: - CheckerDDR3New(const Configuration &config, - ControllerState &state) : config(config), state(state) + CheckerDDR3New() { memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) @@ -19,18 +57,23 @@ public: ~CheckerDDR3New() {} sc_time delayToSatisfyConstraints(Command command, Bank bank); + void insert(const ScheduledCommand &scheduledCommand); private: - MemSpecDDR3 *memSpec; + const MemSpecDDR3 *memSpec; - //Activate + std::map> lastScheduledByCommandAndBank; + std::map lastScheduledByCommand; + ScheduledCommand lastScheduled; + + // Four activate window + std::queue lastActivates; sc_time timeToSatisfyFAW(); //PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; - const Configuration &config; - ControllerState &state;//TODO make const + void printDebugMessage(std::string message); }; #endif // CHECKERDDR3NEW_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 00055677..626a3541 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "SchedulerFifo.h" void SchedulerFifo::storeRequest(tlm_generic_payload *payload) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index 24d25b09..f6640d74 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef SCHEDULERFIFO_H #define SCHEDULERFIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 128a5893..c6cb27ae 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -1,4 +1,39 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "SchedulerFrFcfs.h" + #include void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 23869455..819d7b50 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef SCHEDULERFRFCFS_H #define SCHEDULERFRFCFS_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index a4025f6d..d608db9b 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef SCHEDULERIF_H #define SCHEDULERIF_H From 1053f7c1b7bac823ab5afec1fdeb1716ddab2f4c Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 30 Jul 2019 16:03:49 +0200 Subject: [PATCH 051/183] Created CheckerIF, removed old CheckerDDR3. --- DRAMSys/library/library.pro | 8 +- .../src/controller/checker/CheckerIF.cpp | 2 + .../src/controller/checker/CheckerIF.h | 64 ++ .../src/controller/core/ControllerCore.cpp | 1 - .../core/scheduling/checker/CheckerDDR3.cpp | 561 ------------------ .../core/scheduling/checker/CheckerDDR3.h | 58 -- .../core/scheduling/checker/CheckerDDR3New.h | 1 - 7 files changed, 70 insertions(+), 625 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerIF.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerIF.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index c7ddd020..386605e1 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -147,7 +147,6 @@ SOURCES += \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ - src/controller/core/scheduling/checker/CheckerDDR3.cpp \ src/controller/core/configuration/MemSpec.cpp \ src/controller/core/scheduling/checker/CheckerDDR3New.cpp \ src/controller/BankMachine.cpp \ @@ -156,7 +155,8 @@ SOURCES += \ src/controller/scheduler/SchedulerFrFcfs.cpp \ src/controller/cmdmux/CmdMuxStrict.cpp \ src/controller/cmdmux/CmdMuxOldest.cpp \ - src/controller/ControllerRecordable.cpp + src/controller/ControllerRecordable.cpp \ + src/controller/checker/CheckerIF.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -237,7 +237,6 @@ HEADERS += \ src/simulation/DramDDR4.h \ src/simulation/DramRecordable.h \ src/simulation/DramWideIO.h \ - src/controller/core/scheduling/checker/CheckerDDR3.h \ src/controller/GenericController.h \ src/controller/core/scheduling/checker/CheckerDDR3New.h \ src/controller/BankMachine.h \ @@ -248,7 +247,8 @@ HEADERS += \ src/controller/cmdmux/CmdMuxIF.h \ src/controller/cmdmux/CmdMuxStrict.h \ src/controller/cmdmux/CmdMuxOldest.h \ - src/controller/ControllerRecordable.h + src/controller/ControllerRecordable.h \ + src/controller/checker/CheckerIF.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.cpp b/DRAMSys/library/src/controller/checker/CheckerIF.cpp new file mode 100644 index 00000000..fd5f6059 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerIF.cpp @@ -0,0 +1,2 @@ +#include "CheckerIF.h" + diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h new file mode 100644 index 00000000..015a1cd8 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERIF_H +#define CHECKERIF_H + +#include +#include +#include "../core/scheduling/ScheduledCommand.h" +#include "../Command.h" +#include "../../common/dramExtensions.h" +#include "../../common/DebugManager.h" + +class CheckerIF +{ +public: + virtual ~CheckerIF() {} + + virtual sc_time delayToSatisfyConstraints(Command, Bank) = 0; + virtual void insert(const ScheduledCommand &) = 0; + +protected: + std::map> lastScheduledByCommandAndBank; + std::map lastScheduledByCommand; + ScheduledCommand lastScheduled; + + void printDebugMessage(std::string message) + { + DebugManager::getInstance().printDebugMessage("Checker", message); + } +}; + +#endif // CHECKERIF_H diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp index 8b5c87ab..c9d46587 100644 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ b/DRAMSys/library/src/controller/core/ControllerCore.cpp @@ -52,7 +52,6 @@ #include "../../common/dramExtensions.h" #include "../../common/utils.h" #include "timingCalculations.h" -#include "scheduling/checker/CheckerDDR3.h" #include "scheduling/checker/CheckerDDR3New.h" #include "powerdown/PowerDownManager.h" diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp deleted file mode 100644 index 94ac3ffb..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ /dev/null @@ -1,561 +0,0 @@ -#include "CheckerDDR3.h" - -#include -#include -#include -#include -#include "../../timingCalculations.h" -#include "../../../../common/DebugManager.h" -#include "../../../Command.h" -#include "../../../../common/utils.h" - -using namespace std; - -void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const -{ - ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); - Command lastCmd = lastCommandOnBank.getCommand(); - Command nextCmd = command.getCommand(); - - if (nextCmd == Command::ACT) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - default: - reportFatal("Checker DDR3", - "Activate can not follow " + commandToString(lastCmd)); - } - } - - delay_to_satisfy_activateToActivate_sameBank(command); - - while (!(state.bus.isFree(command.getStart()) && - satsfies_activateToActivate_differentBank(command) && satisfies_nActivateWindow(command))) - { - command.delayStart(memSpec->clk); - } - } - else if (nextCmd == Command::RD || nextCmd == Command::RDA) - { - delayToSatisfyDLL(command); - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - CasToCas(lastCommandOnBank, command)); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - writeToRead(lastCommandOnBank, command)); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("Checker DDR3", - "Read can not follow " + commandToString(lastCmd) + "First: Activate!"); - } - } - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::WR || nextCmd == Command::WRA) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - readToWrite(lastCommandOnBank, command)); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - CasToCas(lastCommandOnBank, command)); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("Checker DDR3", "Write can not follow " + commandToString(lastCmd)); - } - } - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) - command.delayStart(memSpec->clk); - } - else if (nextCmd == Command::PRE) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->tWR - + memSpec->getWriteAccessTime()); - break; - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - default: - reportFatal("Checker DDR3", - "Precharge can not follow " + commandToString(lastCmd)); - } - } - ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); - if (lastActivate.isValidCommand()) - command.establishMinDistanceFromStart(lastActivate.getStart(), - memSpec->tRAS); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PREA) - { - for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) - { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - if (lastCommand.isValidCommand()) - { - switch (lastCommand.getCommand()) - { - case Command::PRE: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRCD); - break; - case Command::RD: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::PDXA: - case Command::PDXP: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC_old); - break; - default: - reportFatal("Checker_DDR3", - "Precharge All can not follow " + commandToString(lastCmd)); - } - } - } - ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); - if (lastActivate.isValidCommand()) - command.establishMinDistanceFromStart(lastActivate.getStart(), - memSpec->tRAS); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDEA || nextCmd == Command::PDEP || nextCmd == Command::SREFEN ) - { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RD: - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRL + memSpec->getReadAccessTime() - + memSpec->clk); - break; - case Command::WR: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->clk); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXA: - case Command::PDXP: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - default: - reportFatal("Checker DDR3", commandToString(nextCmd) + " can not follow " - + commandToString(lastCmd) + ".First: Precharge!"); - } - } - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDXA) - { - // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, - command.getBank()).getStart(), memSpec->tCKE); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::PDXP) - { - // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, - command.getBank()).getStart(), memSpec->tCKE); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::SREFEX) - { - // Leaving Self Refresh - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, - command.getBank()).getStart(), memSpec->tCKESR); - state.bus.moveCommandToNextFreeSlot(command); - } - else if (nextCmd == Command::REFA) - { - if (config.BankwiseLogic) { - if (lastCommandOnBank.isValidCommand()) - { - switch (lastCmd) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRP_old); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - memSpec->tXS); - break; - default: - reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(lastCmd)); - } - } - } - else - { - for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) - { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - - if (lastCommand.isValidCommand()) - { - switch (lastCommand.getCommand()) - { - case Command::PRE: - case Command::PREA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRP_old); - break; - case Command::ACT: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRCD); - break; - case Command::RDA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRTP + memSpec->tRP_old); - break; - case Command::WRA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tWL + memSpec->getWriteAccessTime() - + memSpec->tWR + memSpec->tRP_old); - break; - case Command::REFA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tRFC_old); - break; - case Command::PDXP: - case Command::PDXA: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXP); - break; - case Command::SREFEX: - command.establishMinDistanceFromStart(lastCommand.getStart(), - memSpec->tXS); - break; - default: - reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(lastCmd)); - } - } - } - } - state.bus.moveCommandToNextFreeSlot(command); - } -} - -/* -* ActivateChecker -*/ - -void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const -{ - ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, command.getBank()); - if (lastActivateOnBank.isValidCommand()) - command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); -} - -bool CheckerDDR3::satsfies_activateToActivate_differentBank(ScheduledCommand &command) const -{ -// for (auto act : state.lastActivates) -// { -// sc_time time = act.first; -// if ((time < command.getStart() && command.getStart() - time < memSpec->tRRD) -// || (command.getStart() <= time && time - command.getStart() < memSpec->tRRD)) -// return false; -// } - return true; - -} - -bool CheckerDDR3::satisfies_nActivateWindow(ScheduledCommand &command) const -{ - /* - * there may be activates scheduled in the future, so emplace - * command in a copied set (not necessarily the last in time), - * and check if the n-act constraint holds for the whole set. - */ -// if (state.lastActivates.size() >= memSpec->nActivate) -// { -// std::map lastActivates = state.lastActivates; -// lastActivates.emplace(command.getStart(), command); -// auto upper = lastActivates.begin(); -// std::advance(upper, memSpec->nActivate); -// auto lower = lastActivates.begin(); - -// while (upper != lastActivates.end()) -// { -// if (upper->first - lower->first < memSpec->tNAW_old) -// return false; -// upper++; -// lower++; -// } -// } - return true; -} - - -/* - * Read-Checker -*/ - -bool CheckerDDR3::collidesOnDataStrobe_RD(ScheduledCommand &read) const -{ -// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) -// { -// if (collidesWithStrobeCommand_RD(read, strobeCommand)) -// return true; -// } - return false; -} - -bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - return getDistance(read.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, read); - } - else if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - if (strobeCommand.getStart() >= read.getStart()) - return getDistance(read.getStart(), - strobeCommand.getStart()) < readToWrite(read, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - read.getStart()) < writeToRead(strobeCommand, read); - } else { - reportFatal("Checker DDR3", - "Invalid strobeCommand in data strobe commands " + commandToString( - strobeCommand.getCommand())); - return true; - } - return false; -} - - -void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const -{ - ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, read.getBank()); - if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); -} - - -sc_time CheckerDDR3::writeToRead(ScheduledCommand &write, ScheduledCommand &read) const -{ - sc_assert(read.getCommand() == Command::RD || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR || write.getCommand() == Command::WRA); - - return memSpec->tWL + memSpec->getWriteAccessTime() + memSpec->tWTR; -} - -/* CAS-CAS */ - -sc_time CheckerDDR3::CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const -{ - if (firstCAS.getCommand() == Command::RD || firstCAS.getCommand() == Command::RDA) - { - if (secondCAS.getCommand() == Command::RD || secondCAS.getCommand() == Command::RDA) - return std::max(memSpec->tCCD, memSpec->getReadAccessTime()); - } - else if (firstCAS.getCommand() == Command::WR || firstCAS.getCommand() == Command::WRA) - { - if (secondCAS.getCommand() == Command::WR || secondCAS.getCommand() == Command::WRA) - return std::max(memSpec->tCCD, memSpec->getWriteAccessTime()); - } - SC_REPORT_FATAL("CasToCas", "Exception reached"); - return SC_ZERO_TIME; -} - -/* -* Write-Checker -*/ - -bool CheckerDDR3::collidesOnDataStrobe_WR(ScheduledCommand &write) const -{ -// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) -// { -// if (collidesWithStrobeCommand_WR(write, strobeCommand)) -// return true; -// } - return false; -} - -bool CheckerDDR3::collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::WR || strobeCommand.getCommand() == Command::WRA) - { - // TODO: Cast from sc_time to bool? - return getDistance(write.getStart(), - strobeCommand.getStart()) < CasToCas(strobeCommand, write); - } - else if (strobeCommand.getCommand() == Command::RD || strobeCommand.getCommand() == Command::RDA) - { - if (strobeCommand.getStart() >= write.getStart()) - return getDistance(write.getStart(), - strobeCommand.getStart()) < writeToRead(write, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - write.getStart()) < readToWrite(strobeCommand, write); - } - else - { - reportFatal("CheckerDDR3", "Invalid strobeCommand in data strobe commands " - + commandToString(strobeCommand.getCommand())); - return true; - } -} - - -sc_time CheckerDDR3::readToWrite(ScheduledCommand &read, ScheduledCommand &write) const -{ - sc_assert(read.getCommand() == Command::RD - || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR - || write.getCommand() == Command::WRA); - - return memSpec->tRL + memSpec->getReadAccessTime() - memSpec->tWL + memSpec->clk * 2; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h deleted file mode 100644 index 28baca01..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef CHECKERDDR3_H -#define CHECKERDDR3_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -//Activate -class CheckerDDR3 : public ICommandChecker -{ -public: - CheckerDDR3(const Configuration &config, - ControllerState &state) : config(config), state(state) - { - memSpec = dynamic_cast(Configuration::getInstance().memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - } - virtual ~CheckerDDR3() {} - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const override; - -private: - MemSpecDDR3 *memSpec; - - //Activate - void delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const; - bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const; - bool satisfies_nActivateWindow(ScheduledCommand &command) const; - - //PowerDown - sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; - - //used for Read - void delayToSatisfyDLL(ScheduledCommand &read) const; - bool collidesOnDataStrobe_RD(ScheduledCommand &read) const; - bool collidesWithStrobeCommand_RD(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const; - - //Write - bool collidesOnDataStrobe_WR(ScheduledCommand &write) const; - bool collidesWithStrobeCommand_WR(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const; - - //handles WR->RD - sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read) const; - - //RD->WR - sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write) const; - - //CasToCas Commands (WR->WR)(RD->RD) - sc_time CasToCas(ScheduledCommand &firstCAS, ScheduledCommand &secondCAS) const; - - const Configuration &config; - ControllerState &state;//TODO make const -}; - -#endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h index 81b50295..085104e6 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h @@ -44,7 +44,6 @@ #include "../../../Command.h" #include "../../../../common/dramExtensions.h" -//Activate class CheckerDDR3New { public: From ed96f9fb54de7911075ab2657373407ca0ace940 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 30 Jul 2019 16:25:05 +0200 Subject: [PATCH 052/183] Added new CheckerDDR3, changed checker type in controller to CheckerIF for polymorphism. --- DRAMSys/library/library.pro | 5 +- .../library/src/controller/BankMachine.cpp | 2 +- DRAMSys/library/src/controller/BankMachine.h | 8 +- .../library/src/controller/ControllerNew.cpp | 5 +- .../library/src/controller/ControllerNew.h | 6 +- .../src/controller/ControllerRecordable.cpp | 1 + .../src/controller/checker/CheckerDDR3.cpp | 189 ++++++++++++++++++ .../src/controller/checker/CheckerDDR3.h | 67 +++++++ .../src/controller/checker/CheckerIF.cpp | 2 - .../src/controller/checker/CheckerIF.h | 3 + 10 files changed, 274 insertions(+), 14 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerDDR3.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerDDR3.h delete mode 100644 DRAMSys/library/src/controller/checker/CheckerIF.cpp diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 386605e1..605871bb 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -156,7 +156,7 @@ SOURCES += \ src/controller/cmdmux/CmdMuxStrict.cpp \ src/controller/cmdmux/CmdMuxOldest.cpp \ src/controller/ControllerRecordable.cpp \ - src/controller/checker/CheckerIF.cpp + src/controller/checker/CheckerDDR3.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -248,7 +248,8 @@ HEADERS += \ src/controller/cmdmux/CmdMuxStrict.h \ src/controller/cmdmux/CmdMuxOldest.h \ src/controller/ControllerRecordable.h \ - src/controller/checker/CheckerIF.h + src/controller/checker/CheckerIF.h \ + src/controller/checker/CheckerDDR3.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 36ea5414..e29200c0 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -34,7 +34,7 @@ #include "BankMachine.h" -BankMachine::BankMachine(SchedulerIF *scheduler, CheckerDDR3New *checker, Bank bank) +BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) {} sc_time BankMachine::startBankMachine() diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index dc561680..77eeec72 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -42,12 +42,12 @@ #include "ControllerNew.h" #include "Command.h" #include "scheduler/SchedulerIF.h" -#include "core/scheduling/checker/CheckerDDR3New.h" +#include "checker/CheckerIF.h" using namespace tlm; class SchedulerIF; -class CheckerDDR3New; +class CheckerIF; enum class BmState { @@ -58,7 +58,7 @@ enum class BmState class BankMachine { public: - BankMachine(SchedulerIF *, CheckerDDR3New*, Bank); + BankMachine(SchedulerIF *, CheckerIF*, Bank); sc_time startBankMachine(); std::pair getNextCommand(); void updateState(Command); @@ -74,7 +74,7 @@ private: Command nextCommand = Command::NOP; sc_time timeToSchedule = SC_ZERO_TIME; SchedulerIF *scheduler; - CheckerDDR3New *checker; + CheckerIF *checker; }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index f0ace2e7..79b5104f 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -42,6 +42,7 @@ #include "../common/dramExtensions.h" #include "../common/protocol.h" #include "core/scheduling/ScheduledCommand.h" +#include "checker/CheckerDDR3.h" ControllerNew::ControllerNew(sc_module_name name) : sc_module(name), debugManager(&DebugManager::getInstance()) @@ -54,7 +55,7 @@ ControllerNew::ControllerNew(sc_module_name name) : tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg); iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw); - checker = new CheckerDDR3New(); + checker = new CheckerDDR3(); scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); @@ -116,7 +117,7 @@ unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) return 0; } -void ControllerNew::printDebugMessage(string message) +void ControllerNew::printDebugMessage(std::string message) { debugManager->printDebugMessage(name(), message); } diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index e1dd1c0f..0b852661 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -48,7 +48,7 @@ #include "cmdmux/CmdMuxIF.h" #include "scheduler/SchedulerIF.h" #include "../common/DebugManager.h" -#include "core/scheduling/checker/CheckerDDR3New.h" +#include "checker/CheckerIF.h" using namespace tlm; @@ -75,7 +75,7 @@ protected: virtual void sendToFrontend(tlm_generic_payload *, tlm_phase); virtual void sendToDram(Command, tlm_generic_payload *); - void printDebugMessage(string message); + void printDebugMessage(std::string message); private: unsigned numberOfPayloads = 0; @@ -90,7 +90,7 @@ private: std::map bankMachines; CmdMuxIF *commandMux; SchedulerIF *scheduler; - CheckerDDR3New *checker; + CheckerIF *checker; void releasePayload(); void acquirePayload(); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 95f101a1..8457f5e7 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -35,6 +35,7 @@ #include "ControllerRecordable.h" #include "../common/protocol.h" +#include "core/configuration/Configuration.h" tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp new file mode 100644 index 00000000..6dc57d5d --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerDDR3.h" + +sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) +{ + ScheduledCommand lastCommand; + + sc_time minTimeToWait = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); + + lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + + lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); + + lastCommand = lastScheduledByCommand[Command::PREA]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); + + lastCommand = lastScheduledByCommand[Command::PDXA]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + lastCommand = lastScheduledByCommand[Command::PDXP]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + lastCommand = lastScheduledByCommand[Command::REFA]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); + + lastCommand = lastScheduledByCommand[Command::SREFEX]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); + + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); + + lastCommand = lastScheduledByCommand[Command::ACT]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); + + minTimeToWait = std::max(minTimeToWait, timeToSatisfyFAW()); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); + + lastCommand = lastScheduledByCommand[Command::PDXA]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + lastCommand = lastScheduledByCommand[Command::SREFEX]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + + lastCommand = lastScheduledByCommand[Command::RD]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + + lastCommand = lastScheduledByCommand[Command::WR]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); + + lastCommand = lastScheduledByCommand[Command::PDXA]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + + lastCommand = lastScheduledByCommand[Command::SREFEX]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + + lastCommand = lastScheduledByCommand[Command::RD]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + + lastCommand = lastScheduledByCommand[Command::WR]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + } + else if (command == Command::PRE) + { + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); + + lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); + + lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + + lastCommand = lastScheduledByCommand[Command::PDXA]; + if (lastCommand.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + } + else + { + reportFatal("CheckerDDR3", "Unknown command!"); + } + // Check if bus is free + if (lastScheduled.isValidCommand()) + minTimeToWait = std::max(minTimeToWait, lastScheduled.getStart() + memSpec->clk); + + return (minTimeToWait - sc_time_stamp()); +} + +sc_time CheckerDDR3::timeToSatisfyFAW() +{ + if (lastActivates.size() < 4) + return sc_time_stamp(); + else + { + sc_time earliestTime = lastActivates.front() + memSpec->tFAW; + if (earliestTime > sc_time_stamp()) + return earliestTime; + else + return sc_time_stamp(); + } +} + +void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) +{ + Command command = scheduledCommand.getCommand(); + printDebugMessage("Changing state on bank " + + to_string(scheduledCommand.getBank().ID()) + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] = scheduledCommand; + lastScheduledByCommand[command] = scheduledCommand; + lastScheduled = scheduledCommand; + + // TODO: implement FAW for ACTB + if (command == Command::ACT) + { + if (lastActivates.size() == 4) + lastActivates.pop(); + lastActivates.push(scheduledCommand.getStart()); + } +} diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h new file mode 100644 index 00000000..e17750b2 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERDDR3_H +#define CHECKERDDR3_H + +#include "CheckerIF.h" +#include +#include "../core/configuration/MemSpec.h" +#include "../core/configuration/Configuration.h" + +class CheckerDDR3 final : public CheckerIF +{ +public: + CheckerDDR3() + { + memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + } + + sc_time delayToSatisfyConstraints(Command, Bank); + void insert(const ScheduledCommand &); + +private: + const MemSpecDDR3 *memSpec; + + // Four activate window + std::queue lastActivates; + sc_time timeToSatisfyFAW(); + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; +}; + +#endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.cpp b/DRAMSys/library/src/controller/checker/CheckerIF.cpp deleted file mode 100644 index fd5f6059..00000000 --- a/DRAMSys/library/src/controller/checker/CheckerIF.cpp +++ /dev/null @@ -1,2 +0,0 @@ -#include "CheckerIF.h" - diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 015a1cd8..1d0c6b70 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -59,6 +59,9 @@ protected: { DebugManager::getInstance().printDebugMessage("Checker", message); } + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERIF_H From 36373c9ccec2750a3237975ce89eaa7f79013b63 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 31 Jul 2019 15:20:13 +0200 Subject: [PATCH 053/183] Gave all sc_modules names. Added missing virtual destructors in different DRAMs. --- DRAMSys/library/src/common/TlmRecorder.cpp | 6 +++--- DRAMSys/library/src/common/TlmRecorder.h | 2 +- .../library/src/controller/checker/CheckerDDR3.cpp | 2 +- DRAMSys/library/src/error/errormodel.cpp | 4 ++-- DRAMSys/library/src/error/errormodel.h | 4 ++-- DRAMSys/library/src/simulation/Arbiter.cpp | 3 ++- DRAMSys/library/src/simulation/DRAMSys.cpp | 5 +++-- DRAMSys/library/src/simulation/Dram.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR3.h | 1 + DRAMSys/library/src/simulation/DramDDR4.h | 1 + DRAMSys/library/src/simulation/DramRecordable.h | 12 +++++------- DRAMSys/library/src/simulation/StlPlayer.h | 4 ++-- DRAMSys/library/src/simulation/TraceGenerator.h | 4 ++-- DRAMSys/library/src/simulation/TracePlayer.cpp | 3 ++- DRAMSys/library/src/simulation/TracePlayer.h | 2 +- 15 files changed, 29 insertions(+), 26 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 8619e3ca..e470cf27 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -49,9 +49,9 @@ using namespace std; -TlmRecorder::TlmRecorder(sc_module_name /*name*/, string uri, - string dbname) : sqlScriptURI(uri), dbName(dbname), totalNumTransactions(1), - simulationTimeCoveredByRecording(SC_ZERO_TIME) +TlmRecorder::TlmRecorder(sc_module_name name, string uri, string dbname) : + sc_module(name), sqlScriptURI(uri), dbName(dbname), + totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME) { recordedData.reserve(transactionCommitRate); setUpTransactionTerminatingPhases(); diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index c69ad4f6..bfd4ae9f 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -61,7 +61,7 @@ public: std::string sqlScriptURI; std::string dbName; - TlmRecorder(sc_module_name /*name*/, string uri, string dbname); + TlmRecorder(sc_module_name name, string uri, string dbname); ~TlmRecorder(); void recordMCconfig(string mcconfig) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 6dc57d5d..affd8195 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -147,7 +147,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) { reportFatal("CheckerDDR3", "Unknown command!"); } - // Check if bus is free + // Check if command bus is free if (lastScheduled.isValidCommand()) minTimeToWait = std::max(minTimeToWait, lastScheduled.getStart() + memSpec->clk); diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index 861df60a..e2329750 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -112,13 +112,13 @@ void errorModel::init() markBitFlips(); } -errorModel::errorModel(sc_module_name /*name*/, libDRAMPower *dp) +errorModel::errorModel(sc_module_name name, libDRAMPower *dp) : sc_module(name) { this->DRAMPower = dp; init(); } -errorModel::errorModel(sc_module_name /*name*/) +errorModel::errorModel(sc_module_name name) : sc_module(name) { init(); } diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index e562401c..1f4e3b71 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -46,8 +46,8 @@ class errorModel : public sc_module { public: - errorModel(sc_module_name /*name*/, libDRAMPower *dp); - errorModel(sc_module_name /*name*/); + errorModel(sc_module_name, libDRAMPower *); + errorModel(sc_module_name); ~errorModel(); // Access Methods: diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 1c1074a2..3b7e8217 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -40,7 +40,8 @@ using namespace std; using namespace tlm; -Arbiter::Arbiter(sc_module_name /*name*/) : payloadEventQueue(this, &Arbiter::peqCallback) +Arbiter::Arbiter(sc_module_name name) : + sc_module(name), payloadEventQueue(this, &Arbiter::peqCallback) { // The arbiter communicates with one or more memory unity through one or more sockets (one or more memory channels). // Each of the arbiter's initiator sockets is bound to a memory controller's target socket. diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 21be54a1..db9796d4 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -63,9 +63,9 @@ using namespace std; -DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name, +DRAMSys::DRAMSys(sc_module_name name, string simulationToRun, - string pathToResources) : tSocket("DRAMSys_tSocket") + string pathToResources) : sc_module(name), tSocket("DRAMSys_tSocket") { // Initialize ecc pointer ecc = nullptr; @@ -79,6 +79,7 @@ DRAMSys::DRAMSys(sc_module_name __attribute__((unused)) name, string simconfig; string thermalconfig; + // TODO: Setup never used? Setup setup(simulationToRun, memspec, mcconfig, diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 2d0eb8d2..76a3717f 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -61,7 +61,7 @@ using namespace std; using namespace tlm; using namespace Data; -Dram::Dram(sc_module_name) : tSocket("socket") +Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") { // Adjust number of bytes per burst dynamically to the selected ecc controller bytesPerBurst = Configuration::getInstance() diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/DramDDR3.h index 1db185df..fef6c7fa 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/DramDDR3.h @@ -45,6 +45,7 @@ class DramDDR3 : public Dram public: DramDDR3(sc_module_name); SC_HAS_PROCESS(DramDDR3); + virtual ~DramDDR3() {} }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/DramDDR4.h index 358ec454..3979c950 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/DramDDR4.h @@ -45,6 +45,7 @@ class DramDDR4 : public Dram public: DramDDR4(sc_module_name); SC_HAS_PROCESS(DramDDR4); + virtual ~DramDDR4() {} }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index 2859b749..aa09e778 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -45,19 +45,17 @@ using namespace tlm; template -class DramRecordable : public BaseDram +class DramRecordable final : public BaseDram { public: - DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder); + DramRecordable(sc_module_name, TlmRecorder *); SC_HAS_PROCESS(DramRecordable); - virtual ~DramRecordable(); - -protected: - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay); + ~DramRecordable(); private: + tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay); TlmRecorder *tlmRecorder; sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * Configuration::getInstance().WindowSize; diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index cace8884..30f774ef 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -50,11 +50,11 @@ template class StlPlayer : public TracePlayer { public: - StlPlayer(sc_module_name /*name*/, + StlPlayer(sc_module_name name, string pathToTrace, sc_time playerClk, TracePlayerListener *listener) : - TracePlayer(listener), + TracePlayer(name, listener), file(pathToTrace) { if (!file.is_open()) diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index c6e5cd12..b96b5456 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -46,8 +46,8 @@ using namespace tlm; struct TraceGenerator : public TracePlayer { public: - TraceGenerator(sc_module_name /*name*/, unsigned int clkMhz, - TracePlayerListener *listener) : TracePlayer(listener), transCounter(0) + TraceGenerator(sc_module_name name, unsigned int clkMhz, TracePlayerListener *listener) + : TracePlayer(name, listener), transCounter(0) { if (clkMhz == 0) clk = Configuration::getInstance().memSpec->clk; diff --git a/DRAMSys/library/src/simulation/TracePlayer.cpp b/DRAMSys/library/src/simulation/TracePlayer.cpp index 793dd904..889124b3 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.cpp +++ b/DRAMSys/library/src/simulation/TracePlayer.cpp @@ -38,7 +38,8 @@ #include "TracePlayer.h" -TracePlayer::TracePlayer(TracePlayerListener *listener) : +TracePlayer::TracePlayer(sc_module_name name, TracePlayerListener *listener) : + sc_module(name), payloadEventQueue(this, &TracePlayer::peqCallback), numberOfTransactions(0), transactionsSent(0), diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index fbc2e004..a62ff00a 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -60,7 +60,7 @@ struct TracePlayer : public sc_module { public: tlm_utils::simple_initiator_socket iSocket; - TracePlayer(TracePlayerListener *listener); + TracePlayer(sc_module_name name, TracePlayerListener *listener); virtual void nextPayload() = 0; unsigned int getNumberOfLines(string pathToTrace); From 6a66c89130ba3284f92cc8ef133ffa5385475480 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 1 Aug 2019 11:00:31 +0200 Subject: [PATCH 054/183] Included GenericController for verilator compatibility. --- .../library/src/controller/ControllerNew.cpp | 8 ++------ .../library/src/controller/ControllerNew.h | 14 +++++--------- .../src/controller/GenericController.h | 19 +++++++++---------- 3 files changed, 16 insertions(+), 25 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 79b5104f..5d8d95ec 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -45,16 +45,12 @@ #include "checker/CheckerDDR3.h" ControllerNew::ControllerNew(sc_module_name name) : - sc_module(name), debugManager(&DebugManager::getInstance()) + GenericController(name), debugManager(&DebugManager::getInstance()) { SC_METHOD(controllerMethod); sensitive << triggerEvent << triggerEventQueue; dont_initialize(); - tSocket.register_nb_transport_fw(this, &ControllerNew::nb_transport_fw); - tSocket.register_transport_dbg(this, &ControllerNew::transport_dbg); - iSocket.register_nb_transport_bw(this, &ControllerNew::nb_transport_bw); - checker = new CheckerDDR3(); scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) @@ -88,7 +84,7 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, timeToRelease = sc_time_stamp() + notificationDelay; } else - SC_REPORT_FATAL(0, "Front-end PEQ in controller wrapper was triggered with unknown phase"); + SC_REPORT_FATAL(0, "nb_transport_fw in controller was triggered with unknown phase"); printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 0b852661..75e61fee 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -43,6 +43,7 @@ #include #include #include +#include "GenericController.h" #include "../common/dramExtensions.h" #include "BankMachine.h" #include "cmdmux/CmdMuxIF.h" @@ -55,27 +56,22 @@ using namespace tlm; class BankMachine; class SchedulerIF; -class ControllerNew : public sc_module +class ControllerNew : public GenericController { public: ControllerNew(sc_module_name); SC_HAS_PROCESS(ControllerNew); virtual ~ControllerNew(); - tlm_utils::simple_target_socket tSocket; - tlm_utils::simple_initiator_socket iSocket; - protected: - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay); - virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, - tlm_phase &phase, sc_time &delay); + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &); + virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &); virtual unsigned int transport_dbg(tlm_generic_payload &); virtual void sendToFrontend(tlm_generic_payload *, tlm_phase); virtual void sendToDram(Command, tlm_generic_payload *); - void printDebugMessage(std::string message); + void printDebugMessage(std::string); private: unsigned numberOfPayloads = 0; diff --git a/DRAMSys/library/src/controller/GenericController.h b/DRAMSys/library/src/controller/GenericController.h index 165963aa..08d016b0 100644 --- a/DRAMSys/library/src/controller/GenericController.h +++ b/DRAMSys/library/src/controller/GenericController.h @@ -1,11 +1,13 @@ #ifndef GENERICCONTROLLER_H #define GENERICCONTROLLER_H -#include -#include +#include +#include #include #include +using namespace tlm; + // Utiliy class to pass around the DRAMSys, without having to propagate the template defintions // throughout all classes class GenericController : public sc_module @@ -16,7 +18,6 @@ public: tlm_utils::simple_initiator_socket iSocket; // DRAM side // Bind sockets with virtual functions - SC_HAS_PROCESS(GenericController); GenericController(sc_module_name name) : sc_module(name), tSocket("tSocket"), iSocket("iSocket") { @@ -24,18 +25,16 @@ public: tSocket.register_transport_dbg(this, &GenericController::transport_dbg); iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw); } + SC_HAS_PROCESS(GenericController); // Destructor virtual ~GenericController() {} +protected: // Virtual transport functions - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, - sc_time &delay) = 0; - virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans) = 0; - virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, - tlm::tlm_phase &phase, - sc_time &delay) = 0; + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; + virtual unsigned int transport_dbg(tlm_generic_payload &) = 0; + virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; }; From 85e9fc6930198df96d6c173f70ba06837c3df8d7 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 1 Aug 2019 16:26:57 +0200 Subject: [PATCH 055/183] Included bandwidth calculation. Fixed bug (RD/WR from wrong row). --- .../library/src/controller/BankMachine.cpp | 8 ++- DRAMSys/library/src/controller/BankMachine.h | 5 +- .../library/src/controller/ControllerNew.cpp | 67 +++++++++++++++++++ .../library/src/controller/ControllerNew.h | 9 +++ 4 files changed, 85 insertions(+), 4 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index e29200c0..c2c9fcaa 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -46,15 +46,16 @@ sc_time BankMachine::startBankMachine() return SC_ZERO_TIME; } sc_time delay; + DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) { delay = checker->delayToSatisfyConstraints(Command::ACT, bank); nextCommand = Command::ACT; + nextRow = extension.getRow(); timeToSchedule = sc_time_stamp() + delay; } else if (currentState == BmState::Activated) { - DramExtension extension = DramExtension::getExtension(currentPayload); if (extension.getRow() == currentRow) // row hit { if (currentPayload->get_command() == TLM_READ_COMMAND) @@ -76,8 +77,8 @@ sc_time BankMachine::startBankMachine() { delay = checker->delayToSatisfyConstraints(Command::PRE, bank); nextCommand = Command::PRE; + nextRow = extension.getRow(); timeToSchedule = sc_time_stamp() + delay; - currentRow = extension.getRow(); } } return delay; @@ -94,7 +95,10 @@ std::pair BankMachine::getNextCommand() void BankMachine::updateState(Command command) { if (command == Command::ACT) + { currentState = BmState::Activated; + currentRow = nextRow; + } else if (command == Command::PRE) currentState = BmState::Precharged; else if (command == Command::RD || command == Command::WR) diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 77eeec72..4574bfa2 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -70,8 +70,9 @@ private: tlm_generic_payload *currentPayload = nullptr; BmState currentState = BmState::Precharged; Bank bank; - Row currentRow = Row(0); - Command nextCommand = Command::NOP; + Row currentRow; + Row nextRow; + Command nextCommand; sc_time timeToSchedule = SC_ZERO_TIME; SchedulerIF *scheduler; CheckerIF *checker; diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 5d8d95ec..2a4562f4 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -56,10 +56,50 @@ ControllerNew::ControllerNew(sc_module_name name) : for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); commandMux = new CmdMuxStrict(); + + startBandwidthIdleCollector(); } ControllerNew::~ControllerNew() { + endBandwithIdleCollector(); + + sc_time activeTime = numberOfTransactionsServed + * Configuration::getInstance().memSpec->BurstLength + / Configuration::getInstance().memSpec->DataRate + * Configuration::getInstance().memSpec->clk; + + double bandwidth = (activeTime / sc_time_stamp() * 100); + double bandwidth_IDLE = ((activeTime) / (sc_time_stamp() - idleTime) * 100); + + double maxBandwidth = ( + // clk in Mhz e.g. 800 [MHz]: + (1000000 / Configuration::getInstance().memSpec->clk.to_double()) + // DataRate e.g. 2 + * Configuration::getInstance().memSpec->DataRate + // BusWidth e.g. 8 or 64 + * Configuration::getInstance().memSpec->bitWidth + // Number of devices on a DIMM e.g. 8 + * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); + + std::cout << name() << string(" Total Time: ") + << sc_time_stamp().to_string() + << std::endl; + std::cout << name() << string(" AVG BW: ") + << std::fixed << std::setprecision(2) + << ((bandwidth / 100) * maxBandwidth) + << " Gibit/s (" << bandwidth << " %)" + << std::endl; + std::cout << name() << string(" AVG BW\\IDLE: ") + << std::fixed << std::setprecision(2) + << ((bandwidth_IDLE / 100) * maxBandwidth) + << " Gibit/s (" << bandwidth_IDLE << " %)" + << endl; + std::cout << name() << string(" MAX BW: ") + << std::fixed << std::setprecision(2) + << maxBandwidth << " Gibit/s" + << std::endl; + delete checker; for (auto it : bankMachines) delete it.second; @@ -203,6 +243,10 @@ void ControllerNew::releasePayload() payloadToRelease->release(); numberOfPayloads--; payloadToRelease = nullptr; + + numberOfTransactionsServed++; + if (numberOfPayloads == 0) + startBandwidthIdleCollector(); } void ControllerNew::acquirePayload() @@ -210,6 +254,9 @@ void ControllerNew::acquirePayload() uint64_t id = DramExtension::getPayloadID(payloadToAcquire); printDebugMessage("Payload " + std::to_string(id) + " entered system."); + if (numberOfPayloads == 0) + endBandwithIdleCollector(); + scheduler->storeRequest(payloadToAcquire); payloadToAcquire->acquire(); numberOfPayloads++; @@ -245,3 +292,23 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) iSocket->nb_transport_fw(*payload, phase, delay); } + +void ControllerNew::startBandwidthIdleCollector() +{ + if (!isIdle) + { + printDebugMessage("IDLE start"); + idleStart = sc_time_stamp(); + isIdle = true; + } +} + +void ControllerNew::endBandwithIdleCollector() +{ + if (isIdle) + { + printDebugMessage("IDLE end"); + idleTime += sc_time_stamp() - idleStart; + isIdle = false; + } +} diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 75e61fee..71f9b532 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -98,6 +98,15 @@ private: void triggerEventQueueAfterDelay(sc_time); std::map commandFinishedTime; + + // Bandwidth related: + sc_time idleStart; + sc_time idleTime = SC_ZERO_TIME; + bool isIdle = false; + void startBandwidthIdleCollector(); + void endBandwithIdleCollector(); + + uint64_t numberOfTransactionsServed = 0; }; #endif // CONTROLLERNEW_H From c93a11fbf53b6a817fdebfac85e5509a10eb9e10 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 2 Aug 2019 10:44:49 +0200 Subject: [PATCH 056/183] Code formatting. --- DRAMSys/library/resources/configs/simulator/ddr3.xml | 2 +- DRAMSys/library/src/controller/BankMachine.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index f43e4b8c..1613737f 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -1,6 +1,6 @@ - + diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index c2c9fcaa..022acc9f 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -47,7 +47,7 @@ sc_time BankMachine::startBankMachine() } sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); - if (currentState == BmState::Precharged) + if (currentState == BmState::Precharged) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, bank); nextCommand = Command::ACT; From ca36faa40342ad7d520e3d734055ef0e4a519ccd Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 8 Aug 2019 09:45:22 +0200 Subject: [PATCH 057/183] Changed printDebugMessage into macro to turn it off completely for speedup. --- DRAMSys/library/src/common/DebugManager.h | 8 +++++ DRAMSys/library/src/common/TlmRecorder.cpp | 29 +++++++------------ DRAMSys/library/src/common/TlmRecorder.h | 2 -- .../library/src/controller/ControllerNew.cpp | 21 +++++--------- .../library/src/controller/ControllerNew.h | 4 --- .../src/controller/ControllerRecordable.cpp | 2 +- .../src/controller/checker/CheckerDDR3.cpp | 2 +- .../src/controller/checker/CheckerIF.h | 5 ---- .../src/controller/scheduler/SchedulerIF.h | 5 ---- DRAMSys/library/src/simulation/Arbiter.cpp | 9 ++---- DRAMSys/library/src/simulation/Arbiter.h | 2 -- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 7 +---- DRAMSys/library/src/simulation/Dram.h | 2 -- .../library/src/simulation/DramRecordable.cpp | 7 ++--- .../library/src/simulation/MemoryManager.cpp | 4 +-- .../library/src/simulation/TracePlayer.cpp | 8 +---- DRAMSys/library/src/simulation/TracePlayer.h | 1 - 18 files changed, 39 insertions(+), 81 deletions(-) diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index dd35b796..0d61f33a 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -37,6 +37,14 @@ #ifndef DEBUGMANAGER_H #define DEBUGMANAGER_H +//#define DEBUGGING + +#ifdef DEBUGGING +#define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) +#else +#define PRINTDEBUGMESSAGE(sender, message) +#endif + #include #include #include diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index e470cf27..6a208bb4 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -66,7 +66,7 @@ TlmRecorder::TlmRecorder(sc_module_name name, string uri, string dbname) : createTables(TlmRecorder::sqlScriptURI); prepareSqlStatements(); - printDebugMessage("Starting new database transaction"); + PRINTDEBUGMESSAGE(this->name(), "Starting new database transaction"); } TlmRecorder::~TlmRecorder() @@ -153,13 +153,12 @@ void TlmRecorder::introduceTransactionSystem(tlm::tlm_generic_payload &trans) currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getExtension(&trans).TimeOfGeneration(); - printDebugMessage("New transaction #" + to_string(id) + " generation time " + + PRINTDEBUGMESSAGE(name(), "New transaction #" + to_string(id) + " generation time " + currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); if (id % transactionCommitRate == 0) { - printDebugMessage( - "Committing transactions " + to_string(id - transactionCommitRate + 1) + " - " - + to_string(id)); + PRINTDEBUGMESSAGE(name(), "Committing transactions " + + to_string(id - transactionCommitRate + 1) + " - " + to_string(id)); commitRecordedDataToDB(); } } @@ -168,8 +167,8 @@ void TlmRecorder::removeTransactionFromSystem(tlm::tlm_generic_payload &trans) { assert(currentTransactionsInSystem.count(&trans) != 0); - printDebugMessage("Removing transaction #" + to_string( - currentTransactionsInSystem[&trans].id)); + PRINTDEBUGMESSAGE(name(), "Removing transaction #" + + to_string(currentTransactionsInSystem[&trans].id)); Transaction &recordingData = currentTransactionsInSystem[&trans]; recordedData.push_back(recordingData); @@ -415,7 +414,7 @@ void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement) void TlmRecorder::executeSqlCommand(string command) { - printDebugMessage("Creating database by running provided sql script"); + PRINTDEBUGMESSAGE(name(), "Creating database by running provided sql script"); char *errMsg = 0; int rc = sqlite3_exec(db, command.c_str(), NULL, 0, &errMsg); @@ -424,22 +423,16 @@ void TlmRecorder::executeSqlCommand(string command) sqlite3_free(errMsg); } - printDebugMessage("Database created successfully"); -} - -void TlmRecorder::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); + PRINTDEBUGMESSAGE(name(), "Database created successfully"); } void TlmRecorder::closeConnection() { commitRecordedDataToDB(); insertGeneralInfo(); - printDebugMessage( - "Number of transactions written to DB: " + std::to_string( - totalNumTransactions - 1)); - printDebugMessage("tlmPhaseRecorder:\tEnd Recording"); + PRINTDEBUGMESSAGE(name(), "Number of transactions written to DB: " + + std::to_string(totalNumTransactions - 1)); + PRINTDEBUGMESSAGE(name(), "tlmPhaseRecorder:\tEnd Recording"); sqlite3_close(db); db = NULL; } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index bfd4ae9f..ea016dff 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -130,8 +130,6 @@ private: unsigned int transactionID); void insertDebugMessageInDB(string message, const sc_time &time); - void printDebugMessage(std::string message); - static const int transactionCommitRate = 1000; vector recordedData; map currentTransactionsInSystem; diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 2a4562f4..8113e83d 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -45,7 +45,7 @@ #include "checker/CheckerDDR3.h" ControllerNew::ControllerNew(sc_module_name name) : - GenericController(name), debugManager(&DebugManager::getInstance()) + GenericController(name) { SC_METHOD(controllerMethod); sensitive << triggerEvent << triggerEventQueue; @@ -126,7 +126,7 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, else SC_REPORT_FATAL(0, "nb_transport_fw in controller was triggered with unknown phase"); - printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); triggerEventQueueAfterDelay(notificationDelay); @@ -136,7 +136,7 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { - printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); triggerEventQueueAfterDelay(delay); if (phase == END_RD || phase == END_WR) @@ -153,11 +153,6 @@ unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) return 0; } -void ControllerNew::printDebugMessage(std::string message) -{ - debugManager->printDebugMessage(name(), message); -} - void ControllerNew::triggerEventAfterDelay(sc_time delay) { if (delay != SC_ZERO_TIME) @@ -187,7 +182,7 @@ void ControllerNew::controllerMethod() if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) acquirePayload(); else - printDebugMessage("Total number of payloads exceeded, backpressure!"); + PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); } // (3) Send result to arbiter @@ -238,7 +233,7 @@ void ControllerNew::controllerMethod() void ControllerNew::releasePayload() { uint64_t id = DramExtension::getPayloadID(payloadToRelease); - printDebugMessage("Payload " + std::to_string(id) + " left system."); + PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); payloadToRelease->release(); numberOfPayloads--; @@ -252,7 +247,7 @@ void ControllerNew::releasePayload() void ControllerNew::acquirePayload() { uint64_t id = DramExtension::getPayloadID(payloadToAcquire); - printDebugMessage("Payload " + std::to_string(id) + " entered system."); + PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); if (numberOfPayloads == 0) endBandwithIdleCollector(); @@ -297,7 +292,7 @@ void ControllerNew::startBandwidthIdleCollector() { if (!isIdle) { - printDebugMessage("IDLE start"); + PRINTDEBUGMESSAGE(name(), "IDLE start"); idleStart = sc_time_stamp(); isIdle = true; } @@ -307,7 +302,7 @@ void ControllerNew::endBandwithIdleCollector() { if (isIdle) { - printDebugMessage("IDLE end"); + PRINTDEBUGMESSAGE(name(), "IDLE end"); idleTime += sc_time_stamp() - idleStart; isIdle = false; } diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 71f9b532..6bf2cf8d 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -71,8 +71,6 @@ protected: virtual void sendToFrontend(tlm_generic_payload *, tlm_phase); virtual void sendToDram(Command, tlm_generic_payload *); - void printDebugMessage(std::string); - private: unsigned numberOfPayloads = 0; tlm_generic_payload *payloadToAcquire = nullptr; @@ -81,8 +79,6 @@ private: sc_time timeToRelease = SC_ZERO_TIME; std::queue> responseQueue; - DebugManager *debugManager; - std::map bankMachines; CmdMuxIF *commandMux; SchedulerIF *scheduler; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 8457f5e7..218d221a 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -82,7 +82,7 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); uint64_t id = DramExtension::getExtension(trans).getPayloadID(); - printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + PRINTDEBUGMESSAGE(name(), "Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + to_string(col) + " id " + to_string(id) + " at " + recTime.to_string()); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index affd8195..f60103a0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -171,7 +171,7 @@ sc_time CheckerDDR3::timeToSatisfyFAW() void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) { Command command = scheduledCommand.getCommand(); - printDebugMessage("Changing state on bank " + + PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + to_string(scheduledCommand.getBank().ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 1d0c6b70..9a7c4e0a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -55,11 +55,6 @@ protected: std::map lastScheduledByCommand; ScheduledCommand lastScheduled; - void printDebugMessage(std::string message) - { - DebugManager::getInstance().printDebugMessage("Checker", message); - } - // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index d608db9b..e07f3d03 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -51,11 +51,6 @@ public: virtual ~SchedulerIF() {} virtual void storeRequest(tlm_generic_payload *) = 0; virtual tlm_generic_payload *getNextRequest(Bank, BankMachine *) = 0; -protected: - void printDebugMessage(std::string message) - { - DebugManager::getInstance().printDebugMessage("Scheduler", message); - } }; #endif // SCHEDULERIF_H diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 3b7e8217..a5543332 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -87,7 +87,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, payload.release(); } - printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " + notDelay.to_string()); payloadEventQueue.notify(payload, phase, notDelay); return TLM_ACCEPTED; @@ -102,7 +102,7 @@ tlm_sync_enum Arbiter::nb_transport_bw(int channelId, tlm_generic_payload &paylo if ((unsigned int)channelId != DramExtension::getExtension(payload).getChannel().ID()) SC_REPORT_FATAL("Arbiter", "Payload extension was corrupted"); - printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + + PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + bwDelay.to_string()); payloadEventQueue.notify(payload, phase, bwDelay); return TLM_ACCEPTED; @@ -246,8 +246,3 @@ bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) } return true; } - -void Arbiter::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index cb2bc27a..1be19fe8 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -99,8 +99,6 @@ private: std::vector nextPayloadID; bool addressIsValid(DecodedAddress &decodedAddress); - - void printDebugMessage(std::string message); }; #endif // ARBITER_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index db9796d4..51c7a978 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -360,6 +360,6 @@ DRAMSys::~DRAMSys() void DRAMSys::report(string message) { - DebugManager::getInstance().printDebugMessage(this->name(), message); + PRINTDEBUGMESSAGE(name(), message); cout << message << endl; } diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 76a3717f..a8f08083 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -345,7 +345,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned int Dram::transport_dbg(tlm_generic_payload &trans) { - printDebugMessage("transport_dgb"); + PRINTDEBUGMESSAGE(name(), "transport_dgb"); // TODO: This part is not tested yet, neither with traceplayers nor with GEM5 coupling if (StoreMode == StorageMode::NoStorage) @@ -401,8 +401,3 @@ void Dram::sendToController(tlm_generic_payload &payload, const tlm_phase &phase sc_time TDelay = delay; tSocket->nb_transport_bw(payload, TPhase, TDelay); } - -void Dram::printDebugMessage(string message) -{ - DebugManager::getInstance().printDebugMessage(name(), message); -} diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 6b551f4d..4ae01c33 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -74,8 +74,6 @@ protected: void sendToController(tlm_generic_payload &payload, const tlm_phase &phase, const sc_time &delay); - void printDebugMessage(string message); - public: tlm_utils::simple_target_socket tSocket; diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 0ed6f553..c54e255d 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -85,8 +85,7 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay unsigned int row = DramExtension::getExtension(payload).getRow().ID(); unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); - // TODO: printDebugMessage not inherited - this->printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + + PRINTDEBUGMESSAGE(this->name(), "Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + to_string(col) + " at " + recTime.to_string()); @@ -119,10 +118,10 @@ void DramRecordable::powerWindow() recordPower(); // Here considering that DRAMPower provides the energy in pJ and the power in mW - this->printDebugMessage(string("\tWindow Energy: \t") + to_string( + PRINTDEBUGMESSAGE(this->name(), string("\tWindow Energy: \t") + to_string( this->DRAMPower->getEnergy().window_energy * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); - this->printDebugMessage(string("\tWindow Average Power: \t") + to_string( + PRINTDEBUGMESSAGE(this->name(), string("\tWindow Average Power: \t") + to_string( this->DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); diff --git a/DRAMSys/library/src/simulation/MemoryManager.cpp b/DRAMSys/library/src/simulation/MemoryManager.cpp index 6f456272..08792b1e 100644 --- a/DRAMSys/library/src/simulation/MemoryManager.cpp +++ b/DRAMSys/library/src/simulation/MemoryManager.cpp @@ -53,8 +53,8 @@ MemoryManager::~MemoryManager() } //Comment in if you are suspecting a memory leak in the manager - //DebugManager::getInstance().printDebugMessage("MemoryManager","Number of allocated payloads: " + to_string(numberOfAllocations)); - //DebugManager::getInstance().printDebugMessage("MemoryManager","Number of freed payloads: " + to_string(numberOfFrees)); + //PRINTDEBUGMESSAGE("MemoryManager","Number of allocated payloads: " + to_string(numberOfAllocations)); + //PRINTDEBUGMESSAGE("MemoryManager","Number of freed payloads: " + to_string(numberOfFrees)); } gp *MemoryManager::allocate() diff --git a/DRAMSys/library/src/simulation/TracePlayer.cpp b/DRAMSys/library/src/simulation/TracePlayer.cpp index 889124b3..ad727568 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.cpp +++ b/DRAMSys/library/src/simulation/TracePlayer.cpp @@ -66,11 +66,6 @@ void TracePlayer::terminate() listener->tracePlayerTerminates(); } -void TracePlayer::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} - tlm_sync_enum TracePlayer::nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay) { @@ -86,8 +81,7 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, sendToTarget(payload, phase, SC_ZERO_TIME); transactionsSent++; - DebugManager::getInstance().printDebugMessage(name(), - "Performing request #" + std::to_string(transactionsSent)); + PRINTDEBUGMESSAGE(name(), "Performing request #" + std::to_string(transactionsSent)); } else if (phase == END_REQ) { nextPayload(); } else if (phase == BEGIN_RESP) { diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index a62ff00a..9adbcb51 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -69,7 +69,6 @@ protected: tlm_utils::peq_with_cb_and_phase payloadEventQueue; void finish(); void terminate(); - void printDebugMessage(std::string message); void setNumberOfTransactions(unsigned int n); unsigned int numberOfTransactions; From 88f57dd88f8117d01c9a443697227fe36886a8c4 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 8 Aug 2019 16:22:33 +0200 Subject: [PATCH 058/183] Included refresh. --- DRAMSys/library/library.pro | 6 +- .../resources/configs/simulator/ddr3.xml | 4 +- DRAMSys/library/src/common/DebugManager.h | 2 +- .../library/src/controller/BankMachine.cpp | 7 +- DRAMSys/library/src/controller/BankMachine.h | 1 + .../library/src/controller/ControllerNew.cpp | 50 +++++++--- .../library/src/controller/ControllerNew.h | 2 + .../library/src/controller/RefreshManager.cpp | 49 ++++++++++ .../library/src/controller/RefreshManager.h | 38 ++++++++ .../src/controller/checker/CheckerDDR3.cpp | 95 ++++++++----------- .../src/controller/checker/CheckerDDR3.h | 6 ++ 11 files changed, 183 insertions(+), 77 deletions(-) create mode 100644 DRAMSys/library/src/controller/RefreshManager.cpp create mode 100644 DRAMSys/library/src/controller/RefreshManager.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 605871bb..21ee97ad 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -156,7 +156,8 @@ SOURCES += \ src/controller/cmdmux/CmdMuxStrict.cpp \ src/controller/cmdmux/CmdMuxOldest.cpp \ src/controller/ControllerRecordable.cpp \ - src/controller/checker/CheckerDDR3.cpp + src/controller/checker/CheckerDDR3.cpp \ + src/controller/RefreshManager.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -249,7 +250,8 @@ HEADERS += \ src/controller/cmdmux/CmdMuxOldest.h \ src/controller/ControllerRecordable.h \ src/controller/checker/CheckerIF.h \ - src/controller/checker/CheckerDDR3.h + src/controller/checker/CheckerDDR3.h \ + src/controller/RefreshManager.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml index 1613737f..276dde8e 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.xml +++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml @@ -2,8 +2,8 @@ - - + + diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index 0d61f33a..86306a46 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -42,7 +42,7 @@ #ifdef DEBUGGING #define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) #else -#define PRINTDEBUGMESSAGE(sender, message) +#define PRINTDEBUGMESSAGE(sender, message) {} #endif #include diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 022acc9f..229d32e9 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -86,7 +86,7 @@ sc_time BankMachine::startBankMachine() std::pair BankMachine::getNextCommand() { - if (timeToSchedule == sc_time_stamp()) + if (sc_time_stamp() == timeToSchedule) return std::pair(nextCommand, currentPayload); else return std::pair(Command::NOP, nullptr); @@ -107,6 +107,11 @@ void BankMachine::updateState(Command command) SC_REPORT_FATAL("BankMachine", "Unknown phase"); } +void BankMachine::forcePrecharge() +{ + currentState = BmState::Precharged; +} + Row BankMachine::getOpenRow() { return currentRow; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 4574bfa2..faa50fc0 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -62,6 +62,7 @@ public: sc_time startBankMachine(); std::pair getNextCommand(); void updateState(Command); + void forcePrecharge(); Row getOpenRow(); BmState getState(); diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 8113e83d..0f657741 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -43,6 +43,7 @@ #include "../common/protocol.h" #include "core/scheduling/ScheduledCommand.h" #include "checker/CheckerDDR3.h" +#include "RefreshManager.h" ControllerNew::ControllerNew(sc_module_name name) : GenericController(name) @@ -52,6 +53,8 @@ ControllerNew::ControllerNew(sc_module_name name) : dont_initialize(); checker = new CheckerDDR3(); + refreshManager = new RefreshManager(); + triggerEventQueue.notify(refreshManager->getInitialDelay()); scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); @@ -138,7 +141,7 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, { PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); - triggerEventQueueAfterDelay(delay); + triggerEventQueueAfterDelay(delay); // TODO: Why do we always trigger the queue? if (phase == END_RD || phase == END_WR) { std::pair element((sc_time_stamp() + delay), &trans); @@ -202,22 +205,37 @@ void ControllerNew::controllerMethod() it.second->startBankMachine(); // (5) Choose one request and send it to DRAM - std::vector> readyCommands; std::pair result; - for (auto it : bankMachines) + result = refreshManager->getNextCommand(); + if (result.second != nullptr) // do PREA or REFA { - result = it.second->getNextCommand(); - if (result.second != nullptr) - readyCommands.push_back(result); - } - if (!readyCommands.empty()) - { - result = commandMux->selectCommand(readyCommands); - if (result.second != nullptr) + sc_time delay = refreshManager->updateState(); + triggerEventQueueAfterDelay(delay); + if (result.first == Command::PREA) { - Bank bank = DramExtension::getBank(result.second); - bankMachines[bank]->updateState(result.first); - sendToDram(result.first, result.second); + for (auto it : bankMachines) + it.second->forcePrecharge(); + } + sendToDram(result.first, result.second); + } + else + { + std::vector> readyCommands; + for (auto it : bankMachines) + { + result = it.second->getNextCommand(); + if (result.second != nullptr) + readyCommands.push_back(result); + } + if (!readyCommands.empty()) + { + result = commandMux->selectCommand(readyCommands); + if (result.second != nullptr) + { + Bank bank = DramExtension::getBank(result.second); + bankMachines[bank]->updateState(result.first); + sendToDram(result.first, result.second); + } } } @@ -282,6 +300,10 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) phase = BEGIN_RD; else if (command == Command::WR) phase = BEGIN_WR; + else if (command == Command::PREA) + phase = BEGIN_PRE_ALL; + else if (command == Command::REFA) + phase = BEGIN_REFA; else SC_REPORT_FATAL("ControllerNew", "Unknown phase"); diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 6bf2cf8d..c8d7c3ca 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -50,6 +50,7 @@ #include "scheduler/SchedulerIF.h" #include "../common/DebugManager.h" #include "checker/CheckerIF.h" +#include "RefreshManager.h" using namespace tlm; @@ -83,6 +84,7 @@ private: CmdMuxIF *commandMux; SchedulerIF *scheduler; CheckerIF *checker; + RefreshManager *refreshManager; void releasePayload(); void acquirePayload(); diff --git a/DRAMSys/library/src/controller/RefreshManager.cpp b/DRAMSys/library/src/controller/RefreshManager.cpp new file mode 100644 index 00000000..5c7a79ec --- /dev/null +++ b/DRAMSys/library/src/controller/RefreshManager.cpp @@ -0,0 +1,49 @@ +#include "RefreshManager.h" +#include "../common/dramExtensions.h" +#include "core/configuration/Configuration.h" + +RefreshManager::RefreshManager() +{ + // TODO: Change time of generation? + refreshPayload.set_extension(new GenerationExtension(SC_ZERO_TIME)); + refreshPayload.set_extension(new DramExtension()); + memSpec = static_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + + timeForNextREFA = memSpec->tREFI; + timeForNextPREA = timeForNextREFA - memSpec->tRP; +} + +std::pair RefreshManager::getNextCommand() +{ + if (sc_time_stamp() == timeForNextPREA) + return std::pair(Command::PREA, &refreshPayload); + else if (sc_time_stamp() == timeForNextREFA) + return std::pair(Command::REFA, &refreshPayload); + else + return std::pair(Command::NOP, nullptr); +} + +sc_time RefreshManager::updateState() +{ + if (state == RmState::IDLE) + { + state = RmState::REFRESHING; + timeForNextPREA += memSpec->tREFI; + return memSpec->tRP; + } + else + { + state = RmState::IDLE; + timeForNextREFA += memSpec->tREFI; + return (memSpec->tREFI - memSpec->tRP); + } +} + +sc_time RefreshManager::getInitialDelay() +{ + return timeForNextPREA; +} + + diff --git a/DRAMSys/library/src/controller/RefreshManager.h b/DRAMSys/library/src/controller/RefreshManager.h new file mode 100644 index 00000000..2246b4e5 --- /dev/null +++ b/DRAMSys/library/src/controller/RefreshManager.h @@ -0,0 +1,38 @@ +#ifndef REFRESHMANAGER_H +#define REFRESHMANAGER_H + +#include +#include +#include +#include "Command.h" +#include "core/configuration/MemSpec.h" + +using namespace tlm; + +enum class RmState +{ + IDLE, + REFRESHING +}; + +class RefreshManager +{ +public: + RefreshManager(); + + std::pair getNextCommand(); + sc_time updateState(); + sc_time getInitialDelay(); + +private: + RmState state = RmState::IDLE; + + const MemSpecDDR3 *memSpec; + + tlm_generic_payload refreshPayload; + + sc_time timeForNextREFA; + sc_time timeForNextPREA; +}; + +#endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index f60103a0..1bb36603 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -38,110 +38,86 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) { ScheduledCommand lastCommand; - sc_time minTimeToWait = sc_time_stamp(); + sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::ACT) { lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - - lastCommand = lastScheduledByCommand[Command::PREA]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::PDXP]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::REFA]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); - - lastCommand = lastScheduledByCommand[Command::SREFEX]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRP); lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); lastCommand = lastScheduledByCommand[Command::ACT]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRRD); - minTimeToWait = std::max(minTimeToWait, timeToSatisfyFAW()); + lastCommand = lastScheduledByCommand[Command::REFA]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + + earliestTimeToStart = std::max(earliestTimeToStart, timeToSatisfyFAW()); + + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } else if (command == Command::RD || command == Command::RDA) { lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::SREFEX]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); lastCommand = lastScheduledByCommand[Command::RD]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); lastCommand = lastScheduledByCommand[Command::WR]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } else if (command == Command::WR || command == Command::WRA) { lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::SREFEX]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); lastCommand = lastScheduledByCommand[Command::RD]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); lastCommand = lastScheduledByCommand[Command::WR]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } else if (command == Command::PRE) { lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRAS); lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP); lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); + if (earliestTimeToStart >= timeForNextPREA) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } else { @@ -149,9 +125,9 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) } // Check if command bus is free if (lastScheduled.isValidCommand()) - minTimeToWait = std::max(minTimeToWait, lastScheduled.getStart() + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled.getStart() + memSpec->clk); - return (minTimeToWait - sc_time_stamp()); + return (earliestTimeToStart - sc_time_stamp()); } sc_time CheckerDDR3::timeToSatisfyFAW() @@ -186,4 +162,9 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) lastActivates.pop(); lastActivates.push(scheduledCommand.getStart()); } + else if (command == Command::REFA) + { + timeForNextREFA += memSpec->tREFI; + timeForNextPREA = timeForNextREFA - memSpec->tRP; + } } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index e17750b2..f4acd019 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -48,6 +48,9 @@ public: memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + + timeForNextREFA = memSpec->tREFI; + timeForNextPREA = timeForNextREFA - memSpec->tRP; } sc_time delayToSatisfyConstraints(Command, Bank); @@ -60,6 +63,9 @@ private: std::queue lastActivates; sc_time timeToSatisfyFAW(); + sc_time timeForNextREFA; + sc_time timeForNextPREA; + // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; From 1bd322e576d909954bed29b2e5d8746e85ef2969 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 9 Aug 2019 10:35:17 +0200 Subject: [PATCH 059/183] Fixed "PREA if all banks are precharged" issue. --- .../library/src/controller/BankMachine.cpp | 10 ++++-- DRAMSys/library/src/controller/BankMachine.h | 2 +- .../library/src/controller/ControllerNew.cpp | 16 ++++++--- .../library/src/controller/RefreshManager.cpp | 34 +++++++++++++++++++ .../library/src/controller/RefreshManager.h | 34 +++++++++++++++++++ 5 files changed, 89 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 229d32e9..0264d2b0 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -107,9 +107,15 @@ void BankMachine::updateState(Command command) SC_REPORT_FATAL("BankMachine", "Unknown phase"); } -void BankMachine::forcePrecharge() +bool BankMachine::forcePrecharge() { - currentState = BmState::Precharged; + if (currentState != BmState::Precharged) + { + currentState = BmState::Precharged; + return true; + } + else + return false; } Row BankMachine::getOpenRow() diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index faa50fc0..57e7aa5b 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -62,7 +62,7 @@ public: sc_time startBankMachine(); std::pair getNextCommand(); void updateState(Command); - void forcePrecharge(); + bool forcePrecharge(); Row getOpenRow(); BmState getState(); diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 0f657741..d6e9bba1 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -141,11 +141,12 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, { PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); - triggerEventQueueAfterDelay(delay); // TODO: Why do we always trigger the queue? + //triggerEventQueueAfterDelay(delay); // TODO: Why do we always trigger the queue? if (phase == END_RD || phase == END_WR) { std::pair element((sc_time_stamp() + delay), &trans); responseQueue.push(element); + triggerEventQueueAfterDelay(delay); } return TLM_ACCEPTED; } @@ -206,18 +207,25 @@ void ControllerNew::controllerMethod() // (5) Choose one request and send it to DRAM std::pair result; + // (5.1) Check for refresh command (PREA or REFA) result = refreshManager->getNextCommand(); - if (result.second != nullptr) // do PREA or REFA + if (result.second != nullptr) { sc_time delay = refreshManager->updateState(); triggerEventQueueAfterDelay(delay); if (result.first == Command::PREA) { + bool forcedPrecharges = false; for (auto it : bankMachines) - it.second->forcePrecharge(); + forcedPrecharges |= it.second->forcePrecharge(); + // Send the PREA only if at least one bank was precharged + if (forcedPrecharges) + sendToDram(result.first, result.second); } - sendToDram(result.first, result.second); + else + sendToDram(result.first, result.second); } + // (5.2) Check for other commands (PRE, ACT, RD or WR) else { std::vector> readyCommands; diff --git a/DRAMSys/library/src/controller/RefreshManager.cpp b/DRAMSys/library/src/controller/RefreshManager.cpp index 5c7a79ec..6e616556 100644 --- a/DRAMSys/library/src/controller/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/RefreshManager.cpp @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "RefreshManager.h" #include "../common/dramExtensions.h" #include "core/configuration/Configuration.h" diff --git a/DRAMSys/library/src/controller/RefreshManager.h b/DRAMSys/library/src/controller/RefreshManager.h index 2246b4e5..dc150e80 100644 --- a/DRAMSys/library/src/controller/RefreshManager.h +++ b/DRAMSys/library/src/controller/RefreshManager.h @@ -1,3 +1,37 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef REFRESHMANAGER_H #define REFRESHMANAGER_H From 2e40894097fe26ef1b9dab397e9aba26ef8940c4 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 9 Aug 2019 13:39:02 +0200 Subject: [PATCH 060/183] Included RefreshManagerIF and RefreshManagerDummy to disable refresh. --- DRAMSys/library/library.pro | 7 ++- .../library/src/controller/ControllerNew.cpp | 28 ++++++++-- .../library/src/controller/ControllerNew.h | 4 +- .../src/controller/checker/CheckerDDR3.cpp | 19 +++++++ .../src/controller/checker/CheckerDDR3.h | 11 +--- .../{ => refresh}/RefreshManager.cpp | 6 +- .../controller/{ => refresh}/RefreshManager.h | 7 ++- .../refresh/RefreshManagerDummy.cpp | 50 +++++++++++++++++ .../controller/refresh/RefreshManagerDummy.h | 54 ++++++++++++++++++ .../src/controller/refresh/RefreshManagerIF.h | 55 +++++++++++++++++++ 10 files changed, 215 insertions(+), 26 deletions(-) rename DRAMSys/library/src/controller/{ => refresh}/RefreshManager.cpp (97%) rename DRAMSys/library/src/controller/{ => refresh}/RefreshManager.h (93%) create mode 100644 DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp create mode 100644 DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h create mode 100644 DRAMSys/library/src/controller/refresh/RefreshManagerIF.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 21ee97ad..acf9a8af 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -157,7 +157,8 @@ SOURCES += \ src/controller/cmdmux/CmdMuxOldest.cpp \ src/controller/ControllerRecordable.cpp \ src/controller/checker/CheckerDDR3.cpp \ - src/controller/RefreshManager.cpp + src/controller/refresh/RefreshManager.cpp \ + src/controller/refresh/RefreshManagerDummy.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -251,7 +252,9 @@ HEADERS += \ src/controller/ControllerRecordable.h \ src/controller/checker/CheckerIF.h \ src/controller/checker/CheckerDDR3.h \ - src/controller/RefreshManager.h + src/controller/refresh/RefreshManagerIF.h \ + src/controller/refresh/RefreshManager.h \ + src/controller/refresh/RefreshManagerDummy.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index d6e9bba1..99316ec5 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -43,7 +43,8 @@ #include "../common/protocol.h" #include "core/scheduling/ScheduledCommand.h" #include "checker/CheckerDDR3.h" -#include "RefreshManager.h" +#include "refresh/RefreshManager.h" +#include "refresh/RefreshManagerDummy.h" ControllerNew::ControllerNew(sc_module_name name) : GenericController(name) @@ -52,13 +53,30 @@ ControllerNew::ControllerNew(sc_module_name name) : sensitive << triggerEvent << triggerEventQueue; dont_initialize(); + Configuration config = Configuration::getInstance(); + checker = new CheckerDDR3(); - refreshManager = new RefreshManager(); - triggerEventQueue.notify(refreshManager->getInitialDelay()); - scheduler = new SchedulerFifo(); + if (config.ControllerCoreRefDisable) + refreshManager = new RefreshManagerDummy(); + else + { + refreshManager = new RefreshManager(); + triggerEventQueue.notify(refreshManager->getInitialDelay()); + } + if (config.Scheduler == "FifoStrict") + { + scheduler = new SchedulerFifo(); + commandMux = new CmdMuxStrict(); + } + else if (config.Scheduler == "FrFcfs") + { + scheduler = new SchedulerFrFcfs(); + commandMux = new CmdMuxOldest(); + } + else + SC_REPORT_FATAL("ControllerNew", "Selected scheduler not supported"); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); - commandMux = new CmdMuxStrict(); startBandwidthIdleCollector(); } diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index c8d7c3ca..0ed2e785 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -50,7 +50,7 @@ #include "scheduler/SchedulerIF.h" #include "../common/DebugManager.h" #include "checker/CheckerIF.h" -#include "RefreshManager.h" +#include "refresh/RefreshManagerIF.h" using namespace tlm; @@ -84,7 +84,7 @@ private: CmdMuxIF *commandMux; SchedulerIF *scheduler; CheckerIF *checker; - RefreshManager *refreshManager; + RefreshManagerIF *refreshManager; void releasePayload(); void acquirePayload(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 1bb36603..fe8a8391 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -34,6 +34,25 @@ #include "CheckerDDR3.h" +CheckerDDR3::CheckerDDR3() +{ + Configuration config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + + if (config.ControllerCoreRefDisable) + { + timeForNextREFA = sc_max_time(); + timeForNextPREA = sc_max_time(); + } + else + { + timeForNextREFA = memSpec->tREFI; + timeForNextPREA = timeForNextREFA - memSpec->tRP; + } +} + sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) { ScheduledCommand lastCommand; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index f4acd019..1deeb7fa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -43,16 +43,7 @@ class CheckerDDR3 final : public CheckerIF { public: - CheckerDDR3() - { - memSpec = dynamic_cast(Configuration::getInstance().memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - - timeForNextREFA = memSpec->tREFI; - timeForNextPREA = timeForNextREFA - memSpec->tRP; - } - + CheckerDDR3(); sc_time delayToSatisfyConstraints(Command, Bank); void insert(const ScheduledCommand &); diff --git a/DRAMSys/library/src/controller/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp similarity index 97% rename from DRAMSys/library/src/controller/RefreshManager.cpp rename to DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 6e616556..9ae16379 100644 --- a/DRAMSys/library/src/controller/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -33,8 +33,8 @@ */ #include "RefreshManager.h" -#include "../common/dramExtensions.h" -#include "core/configuration/Configuration.h" +#include "../../common/dramExtensions.h" +#include "../core/configuration/Configuration.h" RefreshManager::RefreshManager() { @@ -79,5 +79,3 @@ sc_time RefreshManager::getInitialDelay() { return timeForNextPREA; } - - diff --git a/DRAMSys/library/src/controller/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h similarity index 93% rename from DRAMSys/library/src/controller/RefreshManager.h rename to DRAMSys/library/src/controller/refresh/RefreshManager.h index dc150e80..2882d342 100644 --- a/DRAMSys/library/src/controller/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -38,8 +38,9 @@ #include #include #include -#include "Command.h" -#include "core/configuration/MemSpec.h" +#include "RefreshManagerIF.h" +#include "../Command.h" +#include "../core/configuration/MemSpec.h" using namespace tlm; @@ -49,7 +50,7 @@ enum class RmState REFRESHING }; -class RefreshManager +class RefreshManager final : public RefreshManagerIF { public: RefreshManager(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp new file mode 100644 index 00000000..8a1fa224 --- /dev/null +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "RefreshManagerDummy.h" + +std::pair RefreshManagerDummy::getNextCommand() +{ + return std::pair(Command::NOP, nullptr); +} + +sc_time RefreshManagerDummy::updateState() +{ + return SC_ZERO_TIME; +} + +sc_time RefreshManagerDummy::getInitialDelay() +{ + return SC_ZERO_TIME; +} diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h new file mode 100644 index 00000000..8031d82c --- /dev/null +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef REFRESHMANAGERDUMMY_H +#define REFRESHMANAGERDUMMY_H + +#include +#include +#include +#include "RefreshManagerIF.h" +#include "../Command.h" + +using namespace tlm; + +class RefreshManagerDummy final : public RefreshManagerIF +{ +public: + std::pair getNextCommand(); + sc_time updateState(); + sc_time getInitialDelay(); +}; + +#endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h new file mode 100644 index 00000000..94999460 --- /dev/null +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef REFRESHMANAGERIF_H +#define REFRESHMANAGERIF_H + +#include +#include +#include +#include "../Command.h" + +using namespace tlm; + +class RefreshManagerIF +{ +public: + virtual ~RefreshManagerIF() {} + + virtual std::pair getNextCommand() = 0; + virtual sc_time updateState() = 0; + virtual sc_time getInitialDelay() = 0; +}; + +#endif // REFRESHMANAGERIF_H From 1dea807da31a7dcaefa59c3e6c3353ab9b8bd322 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 9 Aug 2019 19:38:49 +0200 Subject: [PATCH 061/183] Included various events to avoid multiple triggers of controllerMethod at the same time. --- .../library/src/controller/ControllerNew.cpp | 34 ++++++++----------- .../library/src/controller/ControllerNew.h | 9 ++--- .../src/controller/refresh/RefreshManager.cpp | 2 +- 3 files changed, 21 insertions(+), 24 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 99316ec5..2a1963e1 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -50,7 +50,8 @@ ControllerNew::ControllerNew(sc_module_name name) : GenericController(name) { SC_METHOD(controllerMethod); - sensitive << triggerEvent << triggerEventQueue; + sensitive << beginReqEvent << endRespEvent << bankMachineEvent + << refreshEvent << dataResponseEventQueue; dont_initialize(); Configuration config = Configuration::getInstance(); @@ -61,7 +62,7 @@ ControllerNew::ControllerNew(sc_module_name name) : else { refreshManager = new RefreshManager(); - triggerEventQueue.notify(refreshManager->getInitialDelay()); + refreshEvent.notify(refreshManager->getInitialDelay()); } if (config.Scheduler == "FifoStrict") { @@ -126,6 +127,8 @@ ControllerNew::~ControllerNew() delete it.second; delete scheduler; delete commandMux; + + std::cout << "Total method calls: " << methodCalls << ", false triggered: " << falseTriggered << std::endl; } tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, @@ -138,18 +141,19 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, notificationDelay += Configuration::getInstance().memSpec->clk; payloadToAcquire = &trans; timeToAcquire = sc_time_stamp() + notificationDelay; + beginReqEvent.notify(notificationDelay); } else if (phase = END_RESP) { notificationDelay += Configuration::getInstance().memSpec->clk; timeToRelease = sc_time_stamp() + notificationDelay; + endRespEvent.notify(notificationDelay); } else SC_REPORT_FATAL(0, "nb_transport_fw in controller was triggered with unknown phase"); PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " + notificationDelay.to_string()); - triggerEventQueueAfterDelay(notificationDelay); return TLM_ACCEPTED; } @@ -159,12 +163,12 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, { PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); - //triggerEventQueueAfterDelay(delay); // TODO: Why do we always trigger the queue? + if (phase == END_RD || phase == END_WR) { std::pair element((sc_time_stamp() + delay), &trans); responseQueue.push(element); - triggerEventQueueAfterDelay(delay); + dataResponseEventQueue.notify(delay); } return TLM_ACCEPTED; } @@ -175,20 +179,9 @@ unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) return 0; } -void ControllerNew::triggerEventAfterDelay(sc_time delay) -{ - if (delay != SC_ZERO_TIME) - triggerEvent.notify(delay); -} - -void ControllerNew::triggerEventQueueAfterDelay(sc_time delay) -{ - if (delay != SC_ZERO_TIME) - triggerEventQueue.notify(delay); -} - void ControllerNew::controllerMethod() { + methodCalls++; static sc_time lastTimeCalled = SC_ZERO_TIME; if (lastTimeCalled != sc_time_stamp()) { @@ -230,7 +223,7 @@ void ControllerNew::controllerMethod() if (result.second != nullptr) { sc_time delay = refreshManager->updateState(); - triggerEventQueueAfterDelay(delay); + refreshEvent.notify(delay); if (result.first == Command::PREA) { bool forcedPrecharges = false; @@ -269,9 +262,12 @@ void ControllerNew::controllerMethod() for (auto it : bankMachines) { sc_time delay = it.second->startBankMachine(); - triggerEventAfterDelay(delay); + if (delay != SC_ZERO_TIME) // must be checked to avoid + bankMachineEvent.notify(delay); } } + else + falseTriggered++; } void ControllerNew::releasePayload() diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 0ed2e785..31b26d0c 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -90,10 +90,8 @@ private: void acquirePayload(); void controllerMethod(); - sc_event triggerEvent; - void triggerEventAfterDelay(sc_time); - sc_event_queue triggerEventQueue; - void triggerEventQueueAfterDelay(sc_time); + sc_event beginReqEvent, endRespEvent, bankMachineEvent, refreshEvent; + sc_event_queue dataResponseEventQueue; std::map commandFinishedTime; @@ -105,6 +103,9 @@ private: void endBandwithIdleCollector(); uint64_t numberOfTransactionsServed = 0; + + unsigned methodCalls = 0; + unsigned falseTriggered = 0; }; #endif // CONTROLLERNEW_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 9ae16379..e2890c02 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -41,7 +41,7 @@ RefreshManager::RefreshManager() // TODO: Change time of generation? refreshPayload.set_extension(new GenerationExtension(SC_ZERO_TIME)); refreshPayload.set_extension(new DramExtension()); - memSpec = static_cast(Configuration::getInstance().memSpec); + memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); From 08dc5e811acdf64fbb6ab87b273764cd6eb045ae Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 9 Aug 2019 23:45:17 +0200 Subject: [PATCH 062/183] Removed redundant check in controllerMethod. --- DRAMSys/library/src/controller/ControllerNew.cpp | 11 ----------- DRAMSys/library/src/controller/ControllerNew.h | 3 --- 2 files changed, 14 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 2a1963e1..8ef3bdec 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -127,8 +127,6 @@ ControllerNew::~ControllerNew() delete it.second; delete scheduler; delete commandMux; - - std::cout << "Total method calls: " << methodCalls << ", false triggered: " << falseTriggered << std::endl; } tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, @@ -181,12 +179,6 @@ unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) void ControllerNew::controllerMethod() { - methodCalls++; - static sc_time lastTimeCalled = SC_ZERO_TIME; - if (lastTimeCalled != sc_time_stamp()) - { - lastTimeCalled = sc_time_stamp(); - // (1) Release payload if arbiter has accepted the result if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) releasePayload(); @@ -265,9 +257,6 @@ void ControllerNew::controllerMethod() if (delay != SC_ZERO_TIME) // must be checked to avoid bankMachineEvent.notify(delay); } - } - else - falseTriggered++; } void ControllerNew::releasePayload() diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 31b26d0c..2fafba4e 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -103,9 +103,6 @@ private: void endBandwithIdleCollector(); uint64_t numberOfTransactionsServed = 0; - - unsigned methodCalls = 0; - unsigned falseTriggered = 0; }; #endif // CONTROLLERNEW_H From dc194781f7e1cbf2f4f83ca098286564ed28e6fb Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 9 Aug 2019 23:46:49 +0200 Subject: [PATCH 063/183] Code formatting. --- .../library/src/controller/ControllerNew.cpp | 164 +++++++++--------- 1 file changed, 82 insertions(+), 82 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 8ef3bdec..9b9d8efe 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -129,6 +129,88 @@ ControllerNew::~ControllerNew() delete commandMux; } +void ControllerNew::controllerMethod() +{ + // (1) Release payload if arbiter has accepted the result + if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) + releasePayload(); + + // (2) Accept new request from arbiter + if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + { + if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) + acquirePayload(); + else + PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); + } + + // (3) Send result to arbiter + if (payloadToRelease == nullptr && !responseQueue.empty()) + { + std::pair element = responseQueue.front(); + if (sc_time_stamp() >= element.first) + { + payloadToRelease = element.second; + responseQueue.pop(); + sendToFrontend(payloadToRelease, BEGIN_RESP); + } + } + + // (4) Start bank machines to issue new requests for current time + for (auto it : bankMachines) + it.second->startBankMachine(); + + // (5) Choose one request and send it to DRAM + std::pair result; + // (5.1) Check for refresh command (PREA or REFA) + result = refreshManager->getNextCommand(); + if (result.second != nullptr) + { + sc_time delay = refreshManager->updateState(); + refreshEvent.notify(delay); + if (result.first == Command::PREA) + { + bool forcedPrecharges = false; + for (auto it : bankMachines) + forcedPrecharges |= it.second->forcePrecharge(); + // Send the PREA only if at least one bank was precharged + if (forcedPrecharges) + sendToDram(result.first, result.second); + } + else + sendToDram(result.first, result.second); + } + // (5.2) Check for other commands (PRE, ACT, RD or WR) + else + { + std::vector> readyCommands; + for (auto it : bankMachines) + { + result = it.second->getNextCommand(); + if (result.second != nullptr) + readyCommands.push_back(result); + } + if (!readyCommands.empty()) + { + result = commandMux->selectCommand(readyCommands); + if (result.second != nullptr) + { + Bank bank = DramExtension::getBank(result.second); + bankMachines[bank]->updateState(result.first); + sendToDram(result.first, result.second); + } + } + } + + // (6) Restart bank machines to issue new requests for the future + for (auto it : bankMachines) + { + sc_time delay = it.second->startBankMachine(); + if (delay != SC_ZERO_TIME) // must be checked to avoid + bankMachineEvent.notify(delay); + } +} + tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { @@ -177,88 +259,6 @@ unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) return 0; } -void ControllerNew::controllerMethod() -{ - // (1) Release payload if arbiter has accepted the result - if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) - releasePayload(); - - // (2) Accept new request from arbiter - if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) - { - if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) - acquirePayload(); - else - PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); - } - - // (3) Send result to arbiter - if (payloadToRelease == nullptr && !responseQueue.empty()) - { - std::pair element = responseQueue.front(); - if (sc_time_stamp() >= element.first) - { - payloadToRelease = element.second; - responseQueue.pop(); - sendToFrontend(payloadToRelease, BEGIN_RESP); - } - } - - // (4) Start bank machines to issue new requests for current time - for (auto it : bankMachines) - it.second->startBankMachine(); - - // (5) Choose one request and send it to DRAM - std::pair result; - // (5.1) Check for refresh command (PREA or REFA) - result = refreshManager->getNextCommand(); - if (result.second != nullptr) - { - sc_time delay = refreshManager->updateState(); - refreshEvent.notify(delay); - if (result.first == Command::PREA) - { - bool forcedPrecharges = false; - for (auto it : bankMachines) - forcedPrecharges |= it.second->forcePrecharge(); - // Send the PREA only if at least one bank was precharged - if (forcedPrecharges) - sendToDram(result.first, result.second); - } - else - sendToDram(result.first, result.second); - } - // (5.2) Check for other commands (PRE, ACT, RD or WR) - else - { - std::vector> readyCommands; - for (auto it : bankMachines) - { - result = it.second->getNextCommand(); - if (result.second != nullptr) - readyCommands.push_back(result); - } - if (!readyCommands.empty()) - { - result = commandMux->selectCommand(readyCommands); - if (result.second != nullptr) - { - Bank bank = DramExtension::getBank(result.second); - bankMachines[bank]->updateState(result.first); - sendToDram(result.first, result.second); - } - } - } - - // (6) Restart bank machines to issue new requests for the future - for (auto it : bankMachines) - { - sc_time delay = it.second->startBankMachine(); - if (delay != SC_ZERO_TIME) // must be checked to avoid - bankMachineEvent.notify(delay); - } -} - void ControllerNew::releasePayload() { uint64_t id = DramExtension::getPayloadID(payloadToRelease); From 05a8272ee6bbcf6a41268b8d858fa45096a40484 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 10 Aug 2019 01:01:52 +0200 Subject: [PATCH 064/183] Moved bandwidth calculation to GenericController. --- .../library/src/controller/ControllerNew.cpp | 36 -------------- .../library/src/controller/ControllerNew.h | 5 +- .../src/controller/GenericController.h | 48 +++++++++++++++++-- 3 files changed, 46 insertions(+), 43 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 9b9d8efe..3f25d984 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -86,42 +86,6 @@ ControllerNew::~ControllerNew() { endBandwithIdleCollector(); - sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec->BurstLength - / Configuration::getInstance().memSpec->DataRate - * Configuration::getInstance().memSpec->clk; - - double bandwidth = (activeTime / sc_time_stamp() * 100); - double bandwidth_IDLE = ((activeTime) / (sc_time_stamp() - idleTime) * 100); - - double maxBandwidth = ( - // clk in Mhz e.g. 800 [MHz]: - (1000000 / Configuration::getInstance().memSpec->clk.to_double()) - // DataRate e.g. 2 - * Configuration::getInstance().memSpec->DataRate - // BusWidth e.g. 8 or 64 - * Configuration::getInstance().memSpec->bitWidth - // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); - - std::cout << name() << string(" Total Time: ") - << sc_time_stamp().to_string() - << std::endl; - std::cout << name() << string(" AVG BW: ") - << std::fixed << std::setprecision(2) - << ((bandwidth / 100) * maxBandwidth) - << " Gibit/s (" << bandwidth << " %)" - << std::endl; - std::cout << name() << string(" AVG BW\\IDLE: ") - << std::fixed << std::setprecision(2) - << ((bandwidth_IDLE / 100) * maxBandwidth) - << " Gibit/s (" << bandwidth_IDLE << " %)" - << endl; - std::cout << name() << string(" MAX BW: ") - << std::fixed << std::setprecision(2) - << maxBandwidth << " Gibit/s" - << std::endl; - delete checker; for (auto it : bankMachines) delete it.second; diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/ControllerNew.h index 2fafba4e..31bfc7ab 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/ControllerNew.h @@ -95,14 +95,11 @@ private: std::map commandFinishedTime; - // Bandwidth related: + // Bandwidth related sc_time idleStart; - sc_time idleTime = SC_ZERO_TIME; bool isIdle = false; void startBandwidthIdleCollector(); void endBandwithIdleCollector(); - - uint64_t numberOfTransactionsServed = 0; }; #endif // CONTROLLERNEW_H diff --git a/DRAMSys/library/src/controller/GenericController.h b/DRAMSys/library/src/controller/GenericController.h index 08d016b0..3dbffffd 100644 --- a/DRAMSys/library/src/controller/GenericController.h +++ b/DRAMSys/library/src/controller/GenericController.h @@ -5,6 +5,7 @@ #include #include #include +#include "core/configuration/Configuration.h" using namespace tlm; @@ -14,9 +15,10 @@ class GenericController : public sc_module { public: // Already create and bind sockets to the virtual functions - tlm_utils::simple_target_socket tSocket; // DRAMSys side + tlm_utils::simple_target_socket tSocket; // Arbiter side tlm_utils::simple_initiator_socket iSocket; // DRAM side +protected: // Bind sockets with virtual functions GenericController(sc_module_name name) : sc_module(name), tSocket("tSocket"), iSocket("iSocket") @@ -28,13 +30,53 @@ public: SC_HAS_PROCESS(GenericController); // Destructor - virtual ~GenericController() {} + virtual ~GenericController() + { + sc_time activeTime = numberOfTransactionsServed + * Configuration::getInstance().memSpec->BurstLength + / Configuration::getInstance().memSpec->DataRate + * Configuration::getInstance().memSpec->clk; + + double bandwidth = (activeTime / sc_time_stamp() * 100); + double bandwidth_IDLE = ((activeTime) / (sc_time_stamp() - idleTime) * 100); + + double maxBandwidth = ( + // clk in Mhz e.g. 800 [MHz]: + (1000000 / Configuration::getInstance().memSpec->clk.to_double()) + // DataRate e.g. 2 + * Configuration::getInstance().memSpec->DataRate + // BusWidth e.g. 8 or 64 + * Configuration::getInstance().memSpec->bitWidth + // Number of devices on a DIMM e.g. 8 + * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); + + std::cout << name() << std::string(" Total Time: ") + << sc_time_stamp().to_string() + << std::endl; + std::cout << name() << std::string(" AVG BW: ") + << std::fixed << std::setprecision(2) + << ((bandwidth / 100) * maxBandwidth) + << " Gibit/s (" << bandwidth << " %)" + << std::endl; + std::cout << name() << std::string(" AVG BW\\IDLE: ") + << std::fixed << std::setprecision(2) + << ((bandwidth_IDLE / 100) * maxBandwidth) + << " Gibit/s (" << bandwidth_IDLE << " %)" + << endl; + std::cout << name() << std::string(" MAX BW: ") + << std::fixed << std::setprecision(2) + << maxBandwidth << " Gibit/s" + << std::endl; + } -protected: // Virtual transport functions virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; virtual unsigned int transport_dbg(tlm_generic_payload &) = 0; virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; + + // Bandwidth related + sc_time idleTime = SC_ZERO_TIME; + uint64_t numberOfTransactionsServed = 0; }; From e6dc4e7c75493a904ed8e3404ccf43646d86bf25 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 12 Aug 2019 14:19:22 +0200 Subject: [PATCH 065/183] Removed unused files of old controller. --- DRAMSys/library/library.pro | 57 -- DRAMSys/library/src/common/TlmRecorder.cpp | 7 +- DRAMSys/library/src/common/utils.cpp | 7 +- DRAMSys/library/src/common/utils.h | 2 +- DRAMSys/library/src/controller/Command.h | 1 + DRAMSys/library/src/controller/Controller.cpp | 648 ------------------ DRAMSys/library/src/controller/Controller.h | 169 ----- .../src/controller/ControllerState.cpp | 107 --- .../library/src/controller/ControllerState.h | 81 --- DRAMSys/library/src/controller/IController.h | 64 -- .../src/controller/RecordableController.cpp | 92 --- .../src/controller/RecordableController.h | 64 -- .../src/controller/RowBufferStates.cpp | 99 --- .../library/src/controller/RowBufferStates.h | 64 -- .../src/controller/core/ControllerCore.cpp | 284 -------- .../src/controller/core/ControllerCore.h | 90 --- DRAMSys/library/src/controller/core/Slots.cpp | 87 --- DRAMSys/library/src/controller/core/Slots.h | 63 -- .../controller/core/refresh/IRefreshManager.h | 66 -- .../src/controller/core/refresh/RGR.cpp | 275 -------- .../library/src/controller/core/refresh/RGR.h | 81 --- .../core/refresh/RefreshManager.cpp | 275 -------- .../controller/core/refresh/RefreshManager.h | 82 --- .../core/refresh/RefreshManagerBankwise.cpp | 265 ------- .../core/refresh/RefreshManagerBankwise.h | 83 --- .../core/scheduling/checker/ActBChecker.cpp | 144 ---- .../core/scheduling/checker/ActBChecker.h | 60 -- .../scheduling/checker/ActivateChecker.cpp | 148 ---- .../core/scheduling/checker/ActivateChecker.h | 64 -- .../scheduling/checker/CheckerDDR3New.cpp | 205 ------ .../core/scheduling/checker/CheckerDDR3New.h | 78 --- .../core/scheduling/checker/ICommandChecker.h | 53 -- .../scheduling/checker/PowerDownChecker.cpp | 134 ---- .../scheduling/checker/PowerDownChecker.h | 64 -- .../core/scheduling/checker/PreBChecker.cpp | 84 --- .../core/scheduling/checker/PreBChecker.h | 55 -- .../checker/PrechargeAllChecker.cpp | 103 --- .../scheduling/checker/PrechargeAllChecker.h | 64 -- .../scheduling/checker/PrechargeChecker.cpp | 87 --- .../scheduling/checker/PrechargeChecker.h | 59 -- .../core/scheduling/checker/ReadChecker.cpp | 146 ---- .../core/scheduling/checker/ReadChecker.h | 69 -- .../scheduling/checker/RefreshChecker.cpp | 113 --- .../core/scheduling/checker/RefreshChecker.h | 66 -- .../core/scheduling/checker/WriteChecker.cpp | 135 ---- .../core/scheduling/checker/WriteChecker.h | 66 -- .../controller/core/timingCalculations.cpp | 3 - .../src/controller/refresh/RefreshManager.cpp | 5 +- .../library/src/controller/scheduler/Fifo.cpp | 70 -- .../library/src/controller/scheduler/Fifo.h | 63 -- .../src/controller/scheduler/FifoStrict.cpp | 136 ---- .../src/controller/scheduler/FifoStrict.h | 69 -- .../src/controller/scheduler/FrFcfs.cpp | 122 ---- .../library/src/controller/scheduler/FrFcfs.h | 66 -- .../src/controller/scheduler/FrFcfsGrp.cpp | 194 ------ .../src/controller/scheduler/FrFcfsGrp.h | 61 -- .../src/controller/scheduler/FrFcfsRp.cpp | 140 ---- .../src/controller/scheduler/FrFcfsRp.h | 53 -- .../library/src/controller/scheduler/Grp.cpp | 180 ----- .../library/src/controller/scheduler/Grp.h | 61 -- .../src/controller/scheduler/IScheduler.cpp | 96 --- .../src/controller/scheduler/IScheduler.h | 70 -- .../library/src/controller/scheduler/SMS.cpp | 358 ---------- .../library/src/controller/scheduler/SMS.h | 88 --- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 - DRAMSys/library/src/simulation/DRAMSys.h | 1 - DRAMSys/library/src/simulation/Dram.cpp | 1 - 67 files changed, 9 insertions(+), 6940 deletions(-) delete mode 100644 DRAMSys/library/src/controller/Controller.cpp delete mode 100644 DRAMSys/library/src/controller/Controller.h delete mode 100644 DRAMSys/library/src/controller/ControllerState.cpp delete mode 100644 DRAMSys/library/src/controller/ControllerState.h delete mode 100644 DRAMSys/library/src/controller/IController.h delete mode 100644 DRAMSys/library/src/controller/RecordableController.cpp delete mode 100644 DRAMSys/library/src/controller/RecordableController.h delete mode 100644 DRAMSys/library/src/controller/RowBufferStates.cpp delete mode 100644 DRAMSys/library/src/controller/RowBufferStates.h delete mode 100644 DRAMSys/library/src/controller/core/ControllerCore.cpp delete mode 100644 DRAMSys/library/src/controller/core/ControllerCore.h delete mode 100644 DRAMSys/library/src/controller/core/Slots.cpp delete mode 100644 DRAMSys/library/src/controller/core/Slots.h delete mode 100644 DRAMSys/library/src/controller/core/refresh/IRefreshManager.h delete mode 100644 DRAMSys/library/src/controller/core/refresh/RGR.cpp delete mode 100644 DRAMSys/library/src/controller/core/refresh/RGR.h delete mode 100644 DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp delete mode 100644 DRAMSys/library/src/controller/core/refresh/RefreshManager.h delete mode 100644 DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp delete mode 100644 DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h delete mode 100644 DRAMSys/library/src/controller/scheduler/Fifo.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/Fifo.h delete mode 100644 DRAMSys/library/src/controller/scheduler/FifoStrict.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/FifoStrict.h delete mode 100644 DRAMSys/library/src/controller/scheduler/FrFcfs.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/FrFcfs.h delete mode 100644 DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h delete mode 100644 DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/FrFcfsRp.h delete mode 100644 DRAMSys/library/src/controller/scheduler/Grp.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/Grp.h delete mode 100644 DRAMSys/library/src/controller/scheduler/IScheduler.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/IScheduler.h delete mode 100644 DRAMSys/library/src/controller/scheduler/SMS.cpp delete mode 100644 DRAMSys/library/src/controller/scheduler/SMS.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index acf9a8af..ff3d9cc4 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -92,35 +92,13 @@ SOURCES += \ src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ src/controller/core/powerdown/PowerDownManagerBankwise.cpp \ src/controller/core/powerdown/PowerDownManager.cpp \ - src/controller/scheduler/FrFcfs.cpp \ - src/controller/scheduler/Fifo.cpp \ - src/controller/scheduler/SMS.cpp \ - src/controller/core/refresh/RefreshManagerBankwise.cpp \ - src/controller/core/refresh/RefreshManager.cpp \ - src/controller/core/refresh/RGR.cpp \ - src/controller/core/scheduling/checker/WriteChecker.cpp \ - src/controller/core/scheduling/checker/RefreshChecker.cpp \ - src/controller/core/scheduling/checker/ReadChecker.cpp \ - src/controller/core/scheduling/checker/PrechargeChecker.cpp \ - src/controller/core/scheduling/checker/PrechargeAllChecker.cpp \ - src/controller/core/scheduling/checker/PowerDownChecker.cpp \ - src/controller/core/scheduling/checker/ActivateChecker.cpp \ - src/controller/core/scheduling/checker/PreBChecker.cpp \ - src/controller/core/scheduling/checker/ActBChecker.cpp \ src/controller/core/scheduling/ScheduledCommand.cpp \ - src/controller/core/Slots.cpp \ - src/controller/core/ControllerCore.cpp \ src/simulation/MemoryManager.cpp \ src/simulation/TemperatureController.cpp \ src/controller/core/configuration/ConfigurationLoader.cpp \ src/controller/core/powerdown/NoPowerDown.cpp \ src/controller/Command.cpp \ - src/controller/ControllerState.cpp \ - src/controller/RowBufferStates.cpp \ - src/controller/scheduler/IScheduler.cpp \ - src/controller/scheduler/FifoStrict.cpp \ src/error/errormodel.cpp \ - src/controller/Controller.cpp \ src/simulation/TracePlayer.cpp \ src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp \ src/simulation/TraceSetup.cpp \ @@ -131,10 +109,6 @@ SOURCES += \ src/error/ECC/Word.cpp \ src/error/eccbaseclass.cpp \ src/error/ecchamming.cpp \ - src/controller/scheduler/FrFcfsRp.cpp \ - src/controller/scheduler/FrFcfsGrp.cpp \ - src/controller/scheduler/Grp.cpp \ - src/controller/RecordableController.cpp \ src/common/AddressDecoder.cpp \ src/simulation/Dram.cpp \ src/simulation/Arbiter.cpp \ @@ -148,7 +122,6 @@ SOURCES += \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ src/controller/core/configuration/MemSpec.cpp \ - src/controller/core/scheduling/checker/CheckerDDR3New.cpp \ src/controller/BankMachine.cpp \ src/controller/ControllerNew.cpp \ src/controller/scheduler/SchedulerFifo.cpp \ @@ -170,27 +143,7 @@ HEADERS += \ src/controller/core/powerdown/PowerDownManagerTimeout.h \ src/controller/core/powerdown/PowerDownManagerBankwise.h \ src/controller/core/powerdown/PowerDownManager.h \ - src/controller/scheduler/FrFcfs.h \ - src/controller/scheduler/Fifo.h \ - src/controller/scheduler/SMS.h \ - src/controller/Controller.h \ - src/controller/core/refresh/RefreshManagerBankwise.h \ - src/controller/core/refresh/RefreshManager.h \ - src/controller/core/refresh/IRefreshManager.h \ - src/controller/core/refresh/RGR.h \ - src/controller/core/scheduling/checker/WriteChecker.h \ - src/controller/core/scheduling/checker/RefreshChecker.h \ - src/controller/core/scheduling/checker/ReadChecker.h \ - src/controller/core/scheduling/checker/PrechargeChecker.h \ - src/controller/core/scheduling/checker/PrechargeAllChecker.h \ - src/controller/core/scheduling/checker/PowerDownChecker.h \ - src/controller/core/scheduling/checker/ICommandChecker.h \ - src/controller/core/scheduling/checker/ActivateChecker.h \ - src/controller/core/scheduling/checker/PreBChecker.h \ - src/controller/core/scheduling/checker/ActBChecker.h \ src/controller/core/scheduling/ScheduledCommand.h \ - src/controller/core/Slots.h \ - src/controller/core/ControllerCore.h \ src/simulation/TracePlayer.h \ src/simulation/MemoryManager.h \ src/simulation/Dram.h \ @@ -204,12 +157,7 @@ HEADERS += \ src/simulation/TemperatureController.h \ src/controller/core/powerdown/NoPowerDown.h \ src/controller/Command.h \ - src/controller/RowBufferStates.h \ - src/controller/ControllerState.h \ src/controller/core/powerdown/IPowerDownManager.h \ - src/controller/scheduler/IScheduler.h \ - src/controller/scheduler/FifoStrict.h \ - src/controller/IController.h \ src/controller/core/configuration/ConfigurationLoader.h \ src/error/errormodel.h \ src/simulation/ExampleInitiator.h \ @@ -222,12 +170,8 @@ HEADERS += \ src/error/ECC/Word.h \ src/error/eccbaseclass.h \ src/error/ecchamming.h \ - src/controller/scheduler/FrFcfsRp.h \ - src/controller/scheduler/FrFcfsGrp.h \ - src/controller/scheduler/Grp.h \ src/simulation/IArbiter.h \ src/simulation/SimpleArbiter.h \ - src/controller/RecordableController.h \ src/common/AddressDecoder.h \ src/common/CongenAddressDecoder.h \ src/common/XmlAddressDecoder.h \ @@ -240,7 +184,6 @@ HEADERS += \ src/simulation/DramRecordable.h \ src/simulation/DramWideIO.h \ src/controller/GenericController.h \ - src/controller/core/scheduling/checker/CheckerDDR3New.h \ src/controller/BankMachine.h \ src/controller/ControllerNew.h \ src/controller/scheduler/SchedulerIF.h \ diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 6a208bb4..fe9b056e 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -44,7 +44,6 @@ #include "dramExtensions.h" #include "XmlAddressDecoder.h" #include "../controller/core/configuration/Configuration.h" -#include "../controller/Controller.h" using namespace std; @@ -146,8 +145,7 @@ void TlmRecorder::introduceTransactionSystem(tlm::tlm_generic_payload &trans) currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension( trans); - if (DramExtension::getExtension(trans).getThread().ID() == - Controller::ControllerThreadId()) + if (DramExtension::getExtension(trans).getThread().ID() == UINT_MAX) currentTransactionsInSystem[&trans].timeOfGeneration = SC_ZERO_TIME; else currentTransactionsInSystem[&trans].timeOfGeneration = @@ -348,8 +346,7 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int(insertGeneralInfoStatement, 10, 0); sqlite3_bind_int(insertGeneralInfoStatement, 11, 0); } - sqlite3_bind_int(insertGeneralInfoStatement, 12, - Controller::ControllerThreadId()); ; + sqlite3_bind_int(insertGeneralInfoStatement, 12, UINT_MAX); executeSqlStatement(insertGeneralInfoStatement); } diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index f80d2af9..4f7c1489 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -40,7 +40,6 @@ #include #include #include "dramExtensions.h" -#include "../controller/Controller.h" using namespace std; using namespace tinyxml2; @@ -236,7 +235,7 @@ string loadTextFileContents(string filename) } } -void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank) +void setUpDummy(tlm::tlm_generic_payload &payload, Bank bank) { payload.set_address(bank.getStartAddress()); payload.set_command(tlm::TLM_READ_COMMAND); @@ -245,8 +244,8 @@ void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank) payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread(Controller::ControllerThreadId()), - bank, BankGroup(0), Row(0), Column(0), 0, 0)); + payload.set_extension(new DramExtension(Thread(UINT_MAX), bank, BankGroup(0), + Row(0), Column(0), 0, 0)); // payload takes ownership // TODO: Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!! } diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index 79bf1c5b..d856c96e 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -146,7 +146,7 @@ std::string queryStringParameter(tinyxml2::XMLElement *node, std::string name); bool queryBoolParameter(tinyxml2::XMLElement *node, std::string name); double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name); -void setUpDummy(tlm::tlm_generic_payload &payload, Bank &bank); +void setUpDummy(tlm::tlm_generic_payload &payload, Bank bank = Bank(0)); #endif // UTILS_H diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 08d51d17..c51c2a67 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -51,6 +51,7 @@ enum class Command { RDA, WRA, REFA, + REFB, PDEA, PDXA, PDEP, diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp deleted file mode 100644 index aa79c3d2..00000000 --- a/DRAMSys/library/src/controller/Controller.cpp +++ /dev/null @@ -1,648 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - */ - -#include "Controller.h" - -#include -#include "core/configuration/Configuration.h" - -Controller::Controller(sc_module_name name) : - GenericController(name), - frontendPEQ(this, &Controller::frontendPEQCallback), - dramPEQ(this, &Controller::dramPEQCallback), - controllerCorePEQ(this, &Controller::controllerCorePEQCallback), - debugManager(DebugManager::getInstance()) -{ - controllerCore = new ControllerCore("core", *this, numberOfPayloadsInSystem); - buildScheduler(); -} - -Controller::~Controller() -{ - // Bandwidth: - sc_time activeTime = numberOfTransactionsServed - * Configuration::getInstance().memSpec->BurstLength - / Configuration::getInstance().memSpec->DataRate - * Configuration::getInstance().memSpec->clk; - - sc_time idleTime = getIdleTime(); - sc_time endTime = getEndTime(); - sc_time startTime = getStartTime(); - - double bandwidth = (activeTime / (endTime - startTime) * 100); - double bandwidth_IDLE = ((activeTime) / (endTime - startTime - idleTime) * 100); - - double maxBandwidth = ( - // clk in Mhz e.g. 800 [MHz]: - (1000000 / Configuration::getInstance().memSpec->clk.to_double()) - // DataRate e.g. 2 - * Configuration::getInstance().memSpec->DataRate - // BusWidth e.g. 8 or 64 - * Configuration::getInstance().memSpec->bitWidth - // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().NumberOfDevicesOnDIMM ) / ( 1024 ); - - cout << name() << string(" Total Time: ") - << (endTime - startTime).to_string() - << endl; - cout << name() << string(" AVG BW: ") - << std::fixed << std::setprecision(2) - << ((bandwidth / 100)*maxBandwidth) - << " Gibit/s (" << bandwidth << " %)" - << endl; - cout << name() << string(" AVG BW/IDLE: ") - << std::fixed << std::setprecision(2) - << ((bandwidth_IDLE / 100)*maxBandwidth) - << " Gibit/s (" << (bandwidth_IDLE) << " %)" - << endl; - cout << name() << string(" MAX BW: ") - << std::fixed << std::setprecision(2) - << maxBandwidth << " Gibit/s" - << endl; - - delete controllerCore; - delete scheduler; -} - -void Controller::buildScheduler() -{ - string selectedScheduler = Configuration::getInstance().Scheduler; - - if (selectedScheduler == "Fifo") { - scheduler = new Fifo(*controllerCore); - } else if (selectedScheduler == "FifoStrict") { - scheduler = new FifoStrict(*this, *controllerCore); - } else if (selectedScheduler == "FrFcfs") { - scheduler = new FrFcfs(*controllerCore); - } else if (selectedScheduler == "FrFcfsRp") { - scheduler = new FrFcfsRp(*controllerCore); - } else if (selectedScheduler == "FrFcfsGrp") { - scheduler = new FrFcfsGrp(*controllerCore, this); - } else if (selectedScheduler == "Grp") { - scheduler = new Grp(*controllerCore, this); - } else if (selectedScheduler == "SMS") { - scheduler = new SMS("SMS", *controllerCore, - Configuration::getInstance().SJFProbability); - } - //else if (selectedScheduler == "PAR_BS") - //{ - // scheduler = new PAR_BS(*controllerCore,Configuration::getInstance().RefreshAwareScheduling, - // Configuration::getInstance().Capsize); - //} - // else if (selectedScheduler == "Grouper") - // { - // scheduler = new ReadWriteGrouper(*controllerCore); - // } - else - reportFatal(name(), "unsupported scheduler: " + selectedScheduler); -} - -//Send the next scheduled command to the DRAM -void Controller::send(const ScheduledCommand &command, - tlm_generic_payload &payload) -{ - sc_assert(command.getStart() >= sc_time_stamp()); - - tlm_phase phase; - - switch (command.getCommand()) - { - //TODO: refactor tlm recorder - case Command::RD: - phase = BEGIN_RD; - break; - case Command::RDA: - phase = BEGIN_RDA; - break; - case Command::WR: - phase = BEGIN_WR; - break; - case Command::WRA: - phase = BEGIN_WRA; - break; - case Command::REFA: - if (!Configuration::getInstance().BankwiseLogic) - phase = BEGIN_REFA; - else - phase = BEGIN_REFB; - break; - case Command::ACT: - phase = BEGIN_ACT; - break; - case Command::ACTB: - phase = BEGIN_ACTB; - break; - case Command::PRE: - phase = BEGIN_PRE; - break; - case Command::PREB: - phase = BEGIN_PREB; - break; - case Command::PREA: - phase = BEGIN_PRE_ALL; - break; - case Command::PDEA: - if (!Configuration::getInstance().BankwiseLogic) - phase = BEGIN_PDNA; - else - phase = BEGIN_PDNAB; - break; - case Command::PDXA: - if (!Configuration::getInstance().BankwiseLogic) - phase = END_PDNA; - else - phase = END_PDNAB; - break; - case Command::PDEP: - if (!Configuration::getInstance().BankwiseLogic) - phase = BEGIN_PDNP; - else - phase = BEGIN_PDNPB; - break; - case Command::PDXP: - if (!Configuration::getInstance().BankwiseLogic) - phase = END_PDNP; - else - phase = END_PDNPB; - break; - case Command::SREFEN: - if (!Configuration::getInstance().BankwiseLogic) - phase = BEGIN_SREF; - else - phase = BEGIN_SREFB; - break; - case Command::SREFEX: - if (!Configuration::getInstance().BankwiseLogic) - phase = END_SREF; - else - phase = END_SREFB; - break; - default: - SC_REPORT_FATAL(0, "unsupported command was sent by controller"); - break; - } - - sc_time notDelay = command.getStart() - sc_time_stamp(); - printDebugMessage(phaseNameToString(phase) + " notification in " + - notDelay.to_string()); - controllerCorePEQ.notify(payload, phase, notDelay); -} - -//Trigger the next planned refresh or the power down mode on the DRAM -void Controller::send(Trigger trigger, sc_time time, - tlm_generic_payload &payload) -{ - sc_assert(time >= sc_time_stamp()); - - tlm_phase phase; - - if (trigger == Trigger::REFTrigger) { - phase = REF_TRIGGER; - } else if (trigger == Trigger::PDNTrigger) { - phase = PDN_TRIGGER; - } else { - SC_REPORT_FATAL("controller wrapper", "unknown trigger"); - } - - sc_time delay = time - sc_time_stamp(); - printDebugMessage(phaseNameToString(phase) + " notification in " + - delay.to_string()); - controllerCorePEQ.notify(payload, phase, delay); -} - -void Controller::controllerCorePEQCallback(tlm_generic_payload &payload, - const tlm_phase &phase) -{ - if (phase == REF_TRIGGER) - { - //controllerCore->triggerRefresh(payload); - } - else if (phase == PDN_TRIGGER) - { - //controllerCore->powerDownManager->sleep(DramExtension::getExtension( - // payload).getBank(), sc_time_stamp()); - } - else - { - Bank bank = DramExtension::getBank(payload); - sendToDram(payload, phase, SC_ZERO_TIME); - - if (phase == BEGIN_RD || phase == BEGIN_WR) - scheduleNextFromScheduler(DramExtension::getBank(payload)); - else if (phase == BEGIN_REFB) - printDebugMessage("Entering REFB on bank " + to_string(bank.ID())); - else if (phase == BEGIN_REFA) - printDebugMessage("Entering REFA"); - else if (containsPhase(phase, { BEGIN_PDNAB, BEGIN_PDNPB, BEGIN_SREFB })) - printDebugMessage("Entering PowerDown " + phaseNameToString( - phase) + " on bank " + to_string(bank.ID())); - else if (containsPhase(phase, { END_PDNAB, END_PDNPB, END_SREFB })) - printDebugMessage("Leaving PowerDown " + phaseNameToString( - phase) + " on bank " + to_string(bank.ID())); - else if (containsPhase(phase, { BEGIN_PDNA, BEGIN_PDNP, BEGIN_SREF })) - printDebugMessage("Entering PowerDown " + phaseNameToString( - phase) + " on all banks"); - else if (containsPhase(phase, { END_PDNA, END_PDNP, END_SREF })) - printDebugMessage("Leaving PowerDown " + phaseNameToString( - phase) + " on all banks" ); - else if (containsPhase(phase, { BEGIN_RD, BEGIN_WR, BEGIN_ACTB, BEGIN_ACT, BEGIN_PREB, BEGIN_PRE, BEGIN_PRE_ALL, BEGIN_RDA, BEGIN_WRA })) { - printDebugMessage("Controller has sent to DRAM this: " + phaseNameToString( - phase) + " bank " + to_string(bank.ID())); - } - else - SC_REPORT_FATAL(0, - "Controller Core PEQ in controller wrapper was triggered with unsupported phase"); - } -} - -tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay) -{ - sc_time notDelay = fwDelay; - - if (phase == BEGIN_REQ) - { - notDelay += Configuration::getInstance().memSpec->clk; - - // Bandwidth IDLE - if ((getTotalNumberOfPayloadsInSystem() == 0) && idleState) - endBandwidthIdleCollector(); - } - else if (phase == END_RESP) - { - // Bandwidth IDLE - if (getTotalNumberOfPayloadsInSystem() == 1) - startBandwidthIdleCollector(); - } - - printDebugMessage("[fw] " + phaseNameToString(phase) + " notification in " + - notDelay.to_string()); - frontendPEQ.notify(payload, phase, notDelay); - - return TLM_ACCEPTED; -} - -unsigned int Controller::transport_dbg(tlm::tlm_generic_payload &trans) -{ - return iSocket->transport_dbg(trans); -} - -void Controller::frontendPEQCallback(tlm_generic_payload &payload, - const tlm_phase &phase) -{ - if (phase == BEGIN_REQ) - { - printDebugMessage(string("Payloads in system: ") + - to_string(getTotalNumberOfPayloadsInSystem())); - payload.acquire(); - payloadEntersSystem(payload); - - if (getTotalNumberOfPayloadsInSystem() > - controllerCore->config.MaxNrOfTransactions) - { - printDebugMessage("##Backpressure: Max number of transactions in system reached"); - backpressure = &payload; - } - else - { - payload.set_response_status(tlm::TLM_OK_RESPONSE); - sendToFrontend(payload, END_REQ, SC_ZERO_TIME); - - scheduler->storeRequest(&payload); - // TODO: remove this - scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); - } - } - else if (phase == PendingRequest) - { - // Schedule a pending request. - scheduleNextFromScheduler(DramExtension::getExtension(payload).getBank()); - } - else if (phase == END_RESP) - { - if (backpressure != NULL) - { - printDebugMessage("##Backpressure released"); - backpressure->set_response_status(tlm::TLM_OK_RESPONSE); - sendToFrontend(*backpressure, END_REQ, SC_ZERO_TIME); - - scheduler->storeRequest(backpressure); - scheduleNextFromScheduler(DramExtension::getExtension(backpressure).getBank()); - backpressure = NULL; - } - - payloadLeavesSystem(payload); - responseQueue.pop(); - payload.release(); - - if(!responseQueue.empty()) - sendToFrontend(*(responseQueue.front()), BEGIN_RESP, SC_ZERO_TIME); - } - else - { - SC_REPORT_FATAL(0, - "Front-end PEQ in controller wrapper was triggered with unknown phase"); - } -} - -void Controller::payloadEntersSystem(tlm_generic_payload &payload) -{ - Bank bank = DramExtension::getExtension(payload).getBank(); - numberOfPayloadsInSystem[bank]++; - printDebugMessage( - "Payload enters system on bank " + to_string(bank.ID()) + - ". Total number of payloads in Controller: " - + to_string(getTotalNumberOfPayloadsInSystem())); - // Set Start Time for Simulation - if (!startTimeSet) - { - printDebugMessage("Simulation Timer Start"); - startTime = sc_time_stamp() - Configuration::getInstance().memSpec->clk; - startTimeSet = true; - } -} - -void Controller::payloadLeavesSystem(tlm_generic_payload &payload) -{ - Bank bank = DramExtension::getExtension(payload).getBank(); - numberOfPayloadsInSystem[bank]--; - printDebugMessage( - "Payload left system on bank " + to_string(bank.ID()) + - ". Total number of payloads in Controller: " - + to_string(getTotalNumberOfPayloadsInSystem())); - //controllerCore->powerDownManager->triggerSleep(bank, sc_time_stamp()); -} - -unsigned int Controller::getTotalNumberOfPayloadsInSystem() -{ - unsigned int sum = 0; - for (Bank bank : controllerCore->getBanks()) - sum += numberOfPayloadsInSystem[bank]; - return sum; -} - -void Controller::scheduleNextFromScheduler(Bank bank) -{ - if (controllerCore->bankIsBusy(bank)) - return; - - // TODO: rescheduled always true? - bool rescheduled = true; - pair nextRequest = - scheduler->getNextRequest(bank); - if (nextRequest.second != NULL) - { - schedule(nextRequest.first, *nextRequest.second); - } - else - { - gp *pendingRequest = scheduler->getPendingRequest(bank); - // TODO: if path (pendingRequest != NULL) is only used by SMS scheduler - if (pendingRequest != NULL) - { - rescheduled = true; - frontendPEQ.notify(*(pendingRequest), PendingRequest, - Configuration::getInstance().memSpec->clk); - } - } - - // TODO: only used with FifoStrict scheduler - queue blocked; - while (!blockedRequests.empty()) - { - bank = blockedRequests.front(); - blockedRequests.pop(); - - pair nextRequest = - scheduler->getNextRequest(bank); - if (nextRequest.second != NULL) - { - schedule(nextRequest.first, *nextRequest.second); - } - else - { - gp *pendingRequest = scheduler->getPendingRequest(bank); - if (pendingRequest != NULL) - { - //Pending request - if (!rescheduled) - { - // TODO: never reached, rescheduled is always true - rescheduled = true; - frontendPEQ.notify(*(pendingRequest), PendingRequest, - Configuration::getInstance().memSpec->clk); - } - else - { - blocked.push(bank); - } - } - } - } - blockedRequests = blocked; -} - -void Controller::schedule(Command command, gp &payload) -{ - //controllerCore->powerDownManager->wakeUp(DramExtension::getBank(payload), - // sc_time_stamp()); - if (controllerCore->scheduleRequest(command, payload)) - { - printDebugMessage("\t-> Next payload was scheduled by core [" + commandToString( - command) + "] (unblocked)"); - } -} - -void Controller::sendToFrontend(tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay) -{ - tlm_phase TPhase = phase; - sc_time TDelay = delay; - tSocket->nb_transport_bw(payload, TPhase, TDelay); -} - -tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay) -{ - printDebugMessage("[bw] " + phaseNameToString(phase) + " notification in " + - bwDelay.to_string()); - dramPEQ.notify(payload, phase, bwDelay); - return TLM_ACCEPTED; -} - -void Controller::dramPEQCallback(tlm_generic_payload &payload, - const tlm_phase &phase) -{ - Bank bank = DramExtension::getExtension(payload).getBank(); - printDebugMessage("Received " + phaseNameToString(phase) + " on bank " + - to_string(bank.ID()) + " from DRAM"); - - if (phase == END_RD || phase == END_WR) - { - if(responseQueue.empty()) - sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); - - responseQueue.push(&payload); - } - else if (phase == END_RDA || phase == END_WRA) - { - if(responseQueue.empty()) - sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); - - responseQueue.push(&payload); - scheduleNextFromScheduler(bank); - } - else if (phase == END_REFA) - { - printDebugMessage("Finished auto refresh on all banks "); - - bool sleepy = true; - for (Bank bank : controllerCore->getBanks()) - { - if (numberOfPayloadsInSystem[bank] != 0) - { - sleepy = false; - scheduleNextFromScheduler(bank); - } - } - //if (sleepy == true) - //controllerCore->powerDownManager->sleep(0, sc_time_stamp()); - } - else if (phase == END_REFB) - { - printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID())); - - if (numberOfPayloadsInSystem[bank] == 0) {} - //controllerCore->powerDownManager->sleep(bank, sc_time_stamp()); - else - scheduleNextFromScheduler(bank); - - scheduleNextFromScheduler(bank); - } - else if (containsPhase(phase, {END_PREB, END_PRE, END_ACTB, END_ACT})) - { - scheduleNextFromScheduler(bank); - } - else if (phase == END_PRE_ALL) - { - // No need to trigger anything for a END_PRE_ALL. It is followed by a AUTO_REFRESH anyway (in our current - // scheduler implementation) - } - else - { - string str = - string("DRAM PEQ in controller wrapper was triggered with unsupported phase ") - + phaseNameToString(phase); - SC_REPORT_FATAL(0, str.c_str()); - } -} - -void Controller::sendToDram(tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay) -{ - tlm_phase TPhase = phase; - sc_time TDelay = delay; - if (phase == BEGIN_WR || phase == BEGIN_RD || phase == BEGIN_WRA || phase == BEGIN_RDA) - numberOfTransactionsServed++; - iSocket->nb_transport_fw(payload, TPhase, TDelay); -} - -void Controller::printDebugMessage(string message) -{ - debugManager.printDebugMessage(name(), message); -} - -bool Controller::containsPhase(tlm_phase phase, std::vector phases) -{ - for (tlm_phase p : phases) { - if (p == phase) - return true; - } - return false; -} - -void Controller::end_of_simulation() -{ - terminateSimulation(); -} - -void Controller::terminateSimulation() -{ - if (Configuration::getInstance().BankwiseLogic) { - for (Bank bank : controllerCore->getBanks()) { - //controllerCore->powerDownManager->wakeUp(bank, clkAlign(sc_time_stamp())); - } - } else { - //controllerCore->powerDownManager->wakeUp(0, clkAlign(sc_time_stamp())); - } - - endTime = sc_time_stamp(); -} - -void Controller::startBandwidthIdleCollector() -{ - printDebugMessage("IDLE Start"); - idleStart = sc_time_stamp(); - endTime = sc_time_stamp(); - idleState = true; -} - -void Controller::endBandwidthIdleCollector() -{ - printDebugMessage("IDLE End"); - idleTime += sc_time_stamp() - idleStart + - Configuration::getInstance().memSpec->clk; - idleState = false; -} - -sc_time Controller::getIdleTime() -{ - printDebugMessage("IDLE Time: " + idleTime.to_string()); - return idleTime; -} - -sc_time Controller::getEndTime() -{ - printDebugMessage("End Time: " + endTime.to_string()); - return endTime; -} - -sc_time Controller::getStartTime() -{ - printDebugMessage("Start Time: " + startTime.to_string()); - return startTime; -} diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h deleted file mode 100644 index 479d71d8..00000000 --- a/DRAMSys/library/src/controller/Controller.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - * Eder F. Zulian - */ - -#ifndef CONTROLLER_H -#define CONTROLLER_H - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "../common/dramExtensions.h" -#include "../common/DebugManager.h" -#include "../common/protocol.h" -#include "../common/TlmRecorder.h" -#include "../common/utils.h" -#include "core/configuration/Configuration.h" -#include "core/configuration/MemSpec.h" -#include "Command.h" -#include "core/ControllerCore.h" -#include "ControllerState.h" -#include "IController.h" -#include "core/powerdown/IPowerDownManager.h" -#include "core/scheduling/ScheduledCommand.h" -#include "core/timingCalculations.h" -#include "scheduler/Fifo.h" -#include "scheduler/Grp.h" -#include "scheduler/FifoStrict.h" -#include "scheduler/FrFcfs.h" -#include "scheduler/FrFcfsRp.h" -#include "scheduler/FrFcfsGrp.h" -#include "scheduler/SMS.h" -#include "scheduler/IScheduler.h" -#include "GenericController.h" - -using namespace std; -using namespace tlm; - -DECLARE_EXTENDED_PHASE(PendingRequest); - -class Controller : public GenericController, public IController -{ -public: - Controller(sc_module_name); - - virtual ~Controller(); - - void terminateSimulation(); - - sc_time getIdleTime(); - sc_time getEndTime(); - sc_time getStartTime(); - - // ------- CONTROLLER CORE --------- - virtual void send(const ScheduledCommand &command, - tlm_generic_payload &payload) override; - virtual void send(Trigger trigger, sc_time time, - tlm_generic_payload &payload) override; - - unsigned int getTotalNumberOfPayloadsInSystem(); - void scheduleNextFromScheduler(Bank bank) override; - - static unsigned int ControllerThreadId() - { - return controllerThreadId; - } - -protected: - void buildScheduler(); - void payloadEntersSystem(tlm_generic_payload &payload); - void payloadLeavesSystem(tlm_generic_payload &payload); - - // --- FRONTEND ------ - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay); - virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans); - void frontendPEQCallback(tlm_generic_payload &payload, const tlm_phase &phase); - virtual void sendToFrontend(tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay); - - // --- DRAM ------ - virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay); - void dramPEQCallback(tlm_generic_payload &payload, const tlm_phase &phase); - void sendToDram(tlm_generic_payload &payload, const tlm_phase &phase, - const sc_time &delay); - - // ------- CONTROLLER CORE --------- - virtual void schedule(Command command, gp &payload); - void controllerCorePEQCallback(tlm_generic_payload &payload, - const tlm_phase &phase); - - // Helpers TODO move them - void printDebugMessage(string message); - bool containsPhase(tlm_phase phase, std::vector phases); - - ControllerCore *controllerCore; - //Scheduler* scheduler; - IScheduler *scheduler; - std::map numberOfPayloadsInSystem; - std::vector refreshCollisionRequets; - tlm_generic_payload *backpressure = NULL; - std::queue responseQueue; - - tlm_utils::peq_with_cb_and_phase frontendPEQ; - tlm_utils::peq_with_cb_and_phase dramPEQ; - tlm_utils::peq_with_cb_and_phase controllerCorePEQ; - - DebugManager &debugManager; - - // Bandwidth realted: - sc_time idleStart; - bool idleState = false; - sc_time idleTime; - sc_time endTime; - sc_time startTime; - bool startTimeSet = false; - unsigned long long int numberOfTransactionsServed = 0; - void startBandwidthIdleCollector(); - void endBandwidthIdleCollector(); - - // SystemC related: - virtual void end_of_simulation() override; - - static const unsigned int controllerThreadId = INT_MAX; -}; - -#endif // CONTROLLER_H - diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp deleted file mode 100644 index 9f3b9a2d..00000000 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Felipe S. Prado - */ - -#include "ControllerState.h" -#include -#include "core/timingCalculations.h" - -using namespace std; - -const ScheduledCommand ControllerState::getLastCommandOnBank(Command command, - Bank bank) //TODO const reference? and make const -{ - return lastScheduledByCommandAndBank[command][bank]; -} - -const ScheduledCommand ControllerState::getLastCommand(Command command) -{ - return lastScheduledByCommand[command]; -} - -const ScheduledCommand ControllerState::getLastScheduledCommand() -{ - return lastScheduled; -} - -const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank) -{ - ScheduledCommand lastCommand; - - for (Command cmd : getAllCommands()) { - ScheduledCommand ¤t = lastScheduledByCommandAndBank[cmd][bank]; - if (current.getStart() > lastCommand.getStart()) - lastCommand = current; - } - - printDebugMessage("Last scheduled command on bank " + to_string( - bank.ID()) + " was " + commandToString(lastCommand.getCommand())); - - return lastCommand; -} - -void ControllerState::change(const ScheduledCommand &scheduledCommand) -{ - Command command = scheduledCommand.getCommand(); - printDebugMessage("Changing state on bank " + to_string( - scheduledCommand.getBank().ID()) + " command is " + commandToString( - command)); - - //bus.blockSlot(scheduledCommand.getStart()); - lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] - = scheduledCommand; - lastScheduledByCommand[command] = scheduledCommand; - lastScheduled = scheduledCommand; - - // TODO: implement FAW for ACTB - if (command == Command::ACT) - { - if (lastActivates.size() == 4) - lastActivates.pop(); - lastActivates.push(scheduledCommand.getStart()); - } -} - -void ControllerState::cleanUp(sc_time time) -{ - bus.cleanUpSlots(time); -} - -void ControllerState::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(ownerName, message); -} - diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h deleted file mode 100644 index 6430c5ba..00000000 --- a/DRAMSys/library/src/controller/ControllerState.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef CONTROLLERSTATE_H -#define CONTROLLERSTATE_H - -#include -#include "core/Slots.h" -#include "core/configuration/Configuration.h" -#include -#include -#include -#include - -class ControllerState -{ -public: - ControllerState(std::string ownerName, Configuration *config) - : bus(config->memSpec->clk), ownerName(ownerName), - config(config) {} - - const ScheduledCommand getLastCommandOnBank(Command command, Bank bank); - const ScheduledCommand getLastCommand(Command command); - const ScheduledCommand getLastScheduledCommand(Bank bank); - const ScheduledCommand getLastScheduledCommand(); - - void change(const ScheduledCommand &scheduledCommand); - void cleanUp(sc_time time); - - //used by the various checkers - std::map> lastScheduledByCommandAndBank; - // TODO: remove - std::map lastScheduledByCommand; - //std::map lastScheduledByBank; - ScheduledCommand lastScheduled; - - Slots bus; - std::queue lastActivates; - std::map lastActivatesB; - -private: - std::string ownerName; - Configuration *config; - void printDebugMessage(std::string message); -}; - -#endif // CONTROLLERSTATE_H - diff --git a/DRAMSys/library/src/controller/IController.h b/DRAMSys/library/src/controller/IController.h deleted file mode 100644 index b61fc0d7..00000000 --- a/DRAMSys/library/src/controller/IController.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef ICONTROLLER_H -#define ICONTROLLER_H - -#include -#include -#include "core/scheduling/ScheduledCommand.h" -#include "../common/dramExtensions.h" - -enum Trigger {REFTrigger, PDNTrigger}; - -// Utiliy class to pass around the Controller class to the controller Core and various schedulers, without having to propagate the template defintions -// throughout all classes -class IController -{ -public: - virtual ~IController() {} - virtual void send(const ScheduledCommand &command, - tlm::tlm_generic_payload &payload) = 0; - virtual void send(Trigger trigger, sc_time time, - tlm::tlm_generic_payload &payload) = 0; - virtual void scheduleNextFromScheduler(Bank bank) = 0; - - std::queue blockedRequests; -}; - - -#endif // ICONTROLLER_H diff --git a/DRAMSys/library/src/controller/RecordableController.cpp b/DRAMSys/library/src/controller/RecordableController.cpp deleted file mode 100644 index 4b762fa2..00000000 --- a/DRAMSys/library/src/controller/RecordableController.cpp +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2018, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Felipe S. Prado - * Matthias Jung - */ - -#include "RecordableController.h" - -tlm_sync_enum RecordableController::nb_transport_fw(tlm_generic_payload - &payload, tlm_phase &phase, sc_time &fwDelay) -{ - recordPhase(payload, phase, fwDelay); - - return Controller::nb_transport_fw(payload, phase, fwDelay); -} - -void RecordableController::sendToFrontend(tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay) -{ - recordPhase(payload, phase, delay); - - Controller::sendToFrontend(payload, phase, delay); -} - -tlm_sync_enum RecordableController::nb_transport_bw(tlm_generic_payload - &payload, tlm_phase &phase, sc_time &bwDelay) -{ - recordPhase(payload, phase, bwDelay); - - return Controller::nb_transport_bw(payload, phase, bwDelay); -} - -void RecordableController::recordPhase(tlm::tlm_generic_payload &trans, - tlm::tlm_phase phase, sc_time delay) -{ - sc_time recTime = delay + sc_time_stamp(); - - unsigned int thr = DramExtension::getExtension(trans).getThread().ID(); - unsigned int ch = DramExtension::getExtension(trans).getChannel().ID(); - unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID(); - unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); - unsigned int row = DramExtension::getExtension(trans).getRow().ID(); - unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); - - printDebugMessage("Recording " + phaseNameToString(phase) + " thread " + - to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( - bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " + - to_string(col) + " at " + recTime.to_string()); - - tlmRecorder->recordPhase(trans, phase, recTime); -} - -void RecordableController::schedule(Command command, gp &payload) -{ - Controller::schedule(command, payload); - if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) { - ScheduledCommand scheduledCommand = controllerCore->state->getLastCommandOnBank( - command, DramExtension::getBank(payload)); - TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); - tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, payload); - } -} diff --git a/DRAMSys/library/src/controller/RecordableController.h b/DRAMSys/library/src/controller/RecordableController.h deleted file mode 100644 index 3f37870c..00000000 --- a/DRAMSys/library/src/controller/RecordableController.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2018, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Felipe S. Prado - * Matthias Jung - */ - -#ifndef RECORDABLECONTROLLER_H -#define RECORDABLECONTROLLER_H - -#include "Controller.h" - -struct RecordableController: public Controller { -public: - RecordableController(sc_module_name name, TlmRecorder *rec) : - Controller(name), tlmRecorder(rec) - { - } - -protected: - TlmRecorder *tlmRecorder; - - virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &fwDelay) override; - virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &bwDelay) override; - virtual void sendToFrontend(tlm_generic_payload &payload, - const tlm_phase &phase, const sc_time &delay) override; - virtual void schedule(Command command, tlm_generic_payload &payload) override; - - void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, - sc_time delay); -}; - -#endif // RECORDABLECONTROLLER_H diff --git a/DRAMSys/library/src/controller/RowBufferStates.cpp b/DRAMSys/library/src/controller/RowBufferStates.cpp deleted file mode 100644 index 4db36b8a..00000000 --- a/DRAMSys/library/src/controller/RowBufferStates.cpp +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#include "RowBufferStates.h" -#include "core/ControllerCore.h" -#include "../common/DebugManager.h" -#include "../common/utils.h" - -using namespace std; - -RowBufferState::RowBufferState(std::string ownerName) : ownerName(ownerName) -{ - closeAllRowBuffers(); -} - -RowBufferState::~RowBufferState() -{ -} - -bool RowBufferState::rowBufferIsOpen(Bank bank) const -{ - return getElementFromMap(rowsInRowBuffers, bank) != Row::NO_ROW; -} - -Row RowBufferState::getRowInRowBuffer(Bank bank) const -{ - return getElementFromMap(rowsInRowBuffers, bank); -} - -void RowBufferState::openRowInRowBuffer(Bank bank, Row row) -{ - printDebugMessage("Row buffer for bank " + to_string(bank.ID()) + - " is now open"); - rowsInRowBuffers[bank] = row; -} - -void RowBufferState::closeRowBuffer(Bank bank) -{ - printDebugMessage("Row buffer for bank " + to_string(bank.ID()) + - " is now closed"); - rowsInRowBuffers[bank] = Row::NO_ROW; -} - -bool RowBufferState::allRowBuffersAreClosed() const -{ - for (unsigned int i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; - ++i) { - if (rowBufferIsOpen(Bank(i))) - return false; - } - return true; -} - -void RowBufferState::closeAllRowBuffers() -{ - for (unsigned int i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; - ++i) { - rowsInRowBuffers[Bank(i)] = Row::NO_ROW; - } -} - -void RowBufferState::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(ownerName, message); -} - diff --git a/DRAMSys/library/src/controller/RowBufferStates.h b/DRAMSys/library/src/controller/RowBufferStates.h deleted file mode 100644 index f2670dec..00000000 --- a/DRAMSys/library/src/controller/RowBufferStates.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef ROWBUFFERSTATES_H -#define ROWBUFFERSTATES_H - -#include -#include "../common/dramExtensions.h" - -class RowBufferState -{ -public: - RowBufferState(std::string ownerName); - virtual ~RowBufferState(); - - bool rowBufferIsOpen(Bank bank) const; - bool allRowBuffersAreClosed() const; - Row getRowInRowBuffer(Bank bank) const; - - void openRowInRowBuffer(Bank bank, Row row); - void closeRowBuffer(Bank bank); - void closeAllRowBuffers(); - -private: - std::string ownerName; - std::map rowsInRowBuffers; - void printDebugMessage(std::string message); -}; - -#endif // ROWBUFFERSTATES_H - diff --git a/DRAMSys/library/src/controller/core/ControllerCore.cpp b/DRAMSys/library/src/controller/core/ControllerCore.cpp deleted file mode 100644 index c9d46587..00000000 --- a/DRAMSys/library/src/controller/core/ControllerCore.cpp +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Felipe S. Prado - */ - -#include -#include "ControllerCore.h" -#include "scheduling/checker/ActBChecker.h" -#include "scheduling/checker/ActivateChecker.h" -#include "scheduling/checker/PreBChecker.h" -#include "scheduling/checker/PrechargeChecker.h" -#include "scheduling/checker/PrechargeAllChecker.h" -#include "scheduling/checker/ReadChecker.h" -#include "scheduling/checker/WriteChecker.h" -#include "scheduling/checker/RefreshChecker.h" -#include "scheduling/checker/PowerDownChecker.h" -#include "refresh/RefreshManagerBankwise.h" -#include "refresh/RefreshManager.h" -#include "refresh/RGR.h" -#include "../../common/dramExtensions.h" -#include "../../common/utils.h" -#include "timingCalculations.h" -#include "scheduling/checker/CheckerDDR3New.h" - -#include "powerdown/PowerDownManager.h" -#include "powerdown/PowerDownManagerTimeout.h" -#include "powerdown/PowerDownManagerBankwise.h" -#include "powerdown/PowerDownManagerTimeoutBankwise.h" -#include "powerdown/NoPowerDown.h" -#include "../../common/DebugManager.h" - -ControllerCore::ControllerCore(sc_module_name /*name*/, - IController &wrapperConnector, std::map &numberOfPayloads) : - config(Configuration::getInstance()), controller(wrapperConnector), - numberOfPayloads(numberOfPayloads), commandChecker() -{ - state = new ControllerState(name(), &config); - - commandChecker[Command::ACTB] = new ActBChecker(config, *state); - commandChecker[Command::ACT] = new ActivateChecker(config, *state); - commandChecker[Command::PREB] = new PreBChecker(config, *state); - commandChecker[Command::PRE] = new PrechargeChecker(config, *state); - commandChecker[Command::PREA] = new PrechargeAllChecker(config, *state); - commandChecker[Command::RD] = new ReadChecker(config, *state); - commandChecker[Command::RDA] = commandChecker[Command::RD]; - commandChecker[Command::WR] = new WriteChecker(config, *state); - commandChecker[Command::WRA] = commandChecker[Command::WR]; - - commandChecker[Command::REFA] = new RefreshChecker(config, *state); - commandChecker[Command::PDEA] = new PowerDownChecker(config, *state); - commandChecker[Command::PDEP] = commandChecker[Command::PDEA]; - commandChecker[Command::SREFEN] = commandChecker[Command::PDEA]; - commandChecker[Command::PDXA] = commandChecker[Command::PDEA]; - commandChecker[Command::PDXP] = commandChecker[Command::PDEA]; - commandChecker[Command::SREFEX] = commandChecker[Command::PDEA]; - - //timingChecker = new CheckerDDR3New(config, *state); - -// if (config.RowGranularRef) { -// refreshManager = new RGR("RGR", *this); -// } else { -// if (config.BankwiseLogic) { -// refreshManager = new RefreshManagerBankwise("refManagerBw", *this); -// } else { -// refreshManager = new RefreshManager("refManager", *this); -// } -// } - -// if (config.PowerDownMode == EPowerDownMode::Staggered) { -// if (config.BankwiseLogic) -// powerDownManager = new PowerDownManagerBankwise("pdnManagerBw", *this); -// else -// powerDownManager = new PowerDownManager("pdnManager", *this); -// } else if (config.PowerDownMode == EPowerDownMode::TimeoutPDN -// || config.PowerDownMode == EPowerDownMode::TimeoutSREF) { -// if (config.BankwiseLogic) -// powerDownManager = new PowerDownManagerTimeoutBankwise("pdnManagerBw", *this); -// else -// powerDownManager = new PowerDownManagerTimeout("pdnManager", *this); -// } else if (config.PowerDownMode == EPowerDownMode::NoPowerDown) { -// powerDownManager = new NoPowerDown(); -// } else { -// SC_REPORT_FATAL(0, -// "Unsupported powerdown mode in constructor of controller core"); -// } -} - -ControllerCore::~ControllerCore() -{ - delete commandChecker[Command::ACT]; - delete commandChecker[Command::PRE]; - delete commandChecker[Command::PREA]; - delete commandChecker[Command::RD]; - delete commandChecker[Command::WR]; - delete commandChecker[Command::REFA]; - delete commandChecker[Command::PDEA]; - //delete timingChecker; - //delete refreshManager; - //delete powerDownManager; - delete state; -} - -//void ControllerCore::triggerRefresh(tlm::tlm_generic_payload &payload) -//{ -// /* Refresh can be disabled for tests purpose */ -// if (config.ControllerCoreRefDisable == false) -// { -// sc_time time = sc_time_stamp(); -// Bank bank = DramExtension::getExtension(payload).getBank(); - -// state->cleanUp(time); - -// if (!refreshManager->isInvalidated(payload, time) -// && !powerDownManager->isInSelfRefresh(bank)) -// { -// printDebugMessage("Triggering refresh on bank " + to_string(bank.ID())); -// powerDownManager->wakeUpForRefresh(bank, -// time); //expects PDNA and PDNP to exit without delay -// bool pdnpToSrefTransition = false; -// if (config.PowerDownMode == EPowerDownMode::Staggered) -// pdnpToSrefTransition = (state->getLastCommand(Command::PDXP, -// bank).getStart() >= time); -// if (pdnpToSrefTransition) -// powerDownManager->sleep(bank, time); -// else -// refreshManager->scheduleRefresh(payload, time); -// } -// } -//} - -bool ControllerCore::scheduleRequest(Command command, - tlm::tlm_generic_payload &payload) -{ - sc_time start = clkAlign(sc_time_stamp()); - state->cleanUp(start); - ScheduledCommand scheduledCommand = schedule(command, start, payload); - //if (config.ControllerCoreRefDisable) - //{ - state->change(scheduledCommand); - controller.send(scheduledCommand, payload); - return true; -// } -// else -// { -// if (!((command == Command::PRE || command == Command::ACT) -// && refreshManager->hasCollision(scheduledCommand))) -// { -// state->change(scheduledCommand); -// controller.send(scheduledCommand, payload); -// return true; -// } -// } -// return false; -} - -ScheduledCommand ControllerCore::schedule(Command command, sc_time start, - tlm::tlm_generic_payload &payload) -{ - ControllerCore::printDebugMessage("Scheduling command " + commandToString( - command) + " on " + DramExtension::getBank(payload).toString()); - sc_time executionTime = Configuration::getInstance().memSpec->getExecutionTime(command, payload); - ScheduledCommand scheduledCommand(command, start, executionTime, - DramExtension::getExtension(payload)); - getCommandChecker(command).delayToSatisfyConstraints(scheduledCommand); - return scheduledCommand; -} - -bool ControllerCore::hasPendingRequests() -{ - for (Bank bank : getBanks()) - { - if (numberOfPayloads[bank] != 0) - return true; - } - return false; -} - -bool ControllerCore::hasPendingRequests(Bank bank) -{ - return (numberOfPayloads[bank] != 0) ? true : false; -} - -bool ControllerCore::bankIsBusy(Bank bank) -{ - sc_time time = sc_time_stamp(); - ScheduledCommand lastScheduledCommand = state->getLastScheduledCommand(bank); - - if (lastScheduledCommand.isNoCommand()) - { - return false; - } - else if (lastScheduledCommand.commandIsIn({Command::WR, Command::RD})) - { - // Read and writes can overlap, so the bank should not be busy during a rd/wr - return (time < lastScheduledCommand.getStart()); - } - else if (lastScheduledCommand.commandIsIn({Command::WRA, Command::RDA, Command::PREB, - Command::PRE, Command::PREA, - Command::ACTB, Command::ACT})) - { - return (time < lastScheduledCommand.getEnd()); - } - else if (lastScheduledCommand.getCommand() == Command::REFA) - { - return (time < lastScheduledCommand.getEnd()); - } - else if (lastScheduledCommand.commandIsIn({Command::SREFEX, Command::PDXP, Command::PDXA, - Command::SREFEN, Command::PDEP, Command::PDEA})) - { - return false; - } - else - { - SC_REPORT_FATAL("Core", "Last command unkown"); - return false; - } -} - -const std::vector &ControllerCore::getBanks() -{ - static std::vector banks; - - if (banks.size() == 0) { - for (unsigned int i = 0; i < config.memSpec->NumberOfBanks; i++) { - banks.push_back(Bank(i)); - } - } - - return banks; -} - -std::vector ControllerCore::getFreeBanks() -{ - std::vector freeBanks; - for (Bank bank : getBanks()) { - if (!bankIsBusy(bank)) - freeBanks.push_back(bank); - } - return freeBanks; -} - -ICommandChecker &ControllerCore::getCommandChecker(Command command) -{ - return *getElementFromMap(commandChecker, command); - //return *timingChecker; -} - -void ControllerCore::printDebugMessage(string message) -{ - DebugManager::getInstance().printDebugMessage(this->name(), message); -} - diff --git a/DRAMSys/library/src/controller/core/ControllerCore.h b/DRAMSys/library/src/controller/core/ControllerCore.h deleted file mode 100644 index c3d94f02..00000000 --- a/DRAMSys/library/src/controller/core/ControllerCore.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef CONTROLLERCORE_H -#define CONTROLLERCORE_H - -#include -#include -#include -#include -#include "../IController.h" -#include "configuration/Configuration.h" -#include "powerdown/PowerDownManager.h" -#include "refresh/IRefreshManager.h" -#include "scheduling/checker/ICommandChecker.h" -//#include "../RowBufferStates.h" -#include "../ControllerState.h" - -using namespace std; - -class ControllerCore : public sc_module -{ -public: - ControllerCore(sc_module_name /*name*/, IController &controller, - std::map &numberOfPayloads); - virtual ~ControllerCore(); - - bool scheduleRequest(Command command, tlm::tlm_generic_payload &payload); - //void triggerRefresh(tlm::tlm_generic_payload &payload); - - const std::vector &getBanks(); - std::vector getFreeBanks(); - - bool hasPendingRequests(); - bool hasPendingRequests(Bank bank); - bool bankIsBusy(Bank bank); - - ICommandChecker &getCommandChecker(Command command); - - Configuration config; - ControllerState *state; - IController &controller; - //IPowerDownManager *powerDownManager; - //IRefreshManager *refreshManager; - std::map &numberOfPayloads; - -private: - - ScheduledCommand schedule(Command command, sc_time start, - tlm::tlm_generic_payload &payload); - std::map commandChecker; - //ICommandChecker *timingChecker; - void printDebugMessage(string message); -}; - -#endif // CONTROLLERCORE_H - diff --git a/DRAMSys/library/src/controller/core/Slots.cpp b/DRAMSys/library/src/controller/core/Slots.cpp deleted file mode 100644 index d74ce9e9..00000000 --- a/DRAMSys/library/src/controller/core/Slots.cpp +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#include "Slots.h" -#include "timingCalculations.h" - - -Slots::Slots(sc_time clk) : - clk(clk) -{ - -} - -Slots::~Slots() -{ -} - -void Slots::moveCommandToNextFreeSlot(ScheduledCommand &command) -{ - while (!isFree(command.getStart())) - command.delayStart(clk); -} - -void Slots::cleanUpSlots(sc_time time) -{ - slotSet.erase(slotSet.begin(), slotSet.lower_bound(time)); -} - -void Slots::blockSlot(sc_time time) -{ - sc_assert(isClkAligned(time, clk)); - slotSet.insert(time); -} - -bool Slots::isFree(sc_time time) -{ - return (slotSet.count(time) == 0); -} - -void Slots::blockSlots(sc_time begin, sc_time end, bool excludeBorders) -{ - sc_assert(isClkAligned(begin, clk)); - sc_assert(isClkAligned(end, clk)); - - if (excludeBorders) { - begin += clk; - end -= clk; - } - - for (sc_time time = begin; time <= end; time += clk) { - blockSlot(time); - } -} - diff --git a/DRAMSys/library/src/controller/core/Slots.h b/DRAMSys/library/src/controller/core/Slots.h deleted file mode 100644 index 61663568..00000000 --- a/DRAMSys/library/src/controller/core/Slots.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef SLOTS_H -#define SLOTS_H - -#include -#include -#include "scheduling/ScheduledCommand.h" - -class Slots -{ -public: - Slots(sc_time clk); - virtual ~Slots(); - - void moveCommandToNextFreeSlot(ScheduledCommand &command); - void cleanUpSlots(sc_time time); - void blockSlot(sc_time time); - bool isFree(sc_time); - -private: - sc_time clk; - std::set slotSet; - void blockSlots(sc_time begin, sc_time end, bool excludeBorders); - -}; - - -#endif // SLOTS_H diff --git a/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h b/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h deleted file mode 100644 index 54d535dc..00000000 --- a/DRAMSys/library/src/controller/core/refresh/IRefreshManager.h +++ /dev/null @@ -1,66 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// */ - -//#ifndef IREFRESHMANAGER_H -//#define IREFRESHMANAGER_H - -//#include -//#include "../scheduling/ScheduledCommand.h" - -//// Flex. refresh (pull-in, postpone) -//typedef enum { -// ST_REFRESH = 0, -// ST_PULLIN, -// ST_POSTPONE, -// ST_SKIP, -// ST_BURST, -// ST_ALIGN -//} ref_fsm_state_t; - -//class IRefreshManager -//{ -//public: -// virtual ~IRefreshManager() {}; -// virtual bool hasCollision(const ScheduledCommand &command) = 0; -// virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, -// sc_time time) = 0; -// virtual void reInitialize(Bank bank, sc_time time) = 0; -// virtual bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) = 0; -//}; - -//#endif // IREFRESHMANAGER_H - diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.cpp b/DRAMSys/library/src/controller/core/refresh/RGR.cpp deleted file mode 100644 index ed8fee75..00000000 --- a/DRAMSys/library/src/controller/core/refresh/RGR.cpp +++ /dev/null @@ -1,275 +0,0 @@ -///* -// * Copyright (c) 2017, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Author: Éder F. Zulian -// */ - -//#include - -//#include "RGR.h" -//#include "../ControllerCore.h" -//#include "../timingCalculations.h" -//#include "../../../common/utils.h" - -//#define TRUE 1 -//#define FALSE !(TRUE) -//#define INITIAL_DISPLACEMENT FALSE - -//using namespace std; - -//RGR::RGR(sc_module_name, ControllerCore &ctrlcore) : ccore(ctrlcore), -// timing(ctrlcore.config.memSpec->refreshTimings[ccore.getBanks()[0]]) -//{ -// fmb = ccore.config.ControllerCoreRefForceMaxPostponeBurst; -// bwl = ccore.config.BankwiseLogic; -// ri = ccore.config.getRowInc(); -// auto nr = ccore.config.memSpec->NumberOfRows; -// auto nar = ccore.config.getNumAR(); -// auto m = ccore.config.getRefMode(); -// rpr = (nr / m) / nar; -// assert(rpr > 0); -// tREFIx = timing.tREFI / m; -// trp = ccore.config.getTrpb(); -// trcd = ccore.config.memSpec->tRCD; -// postponeEnabled = ccore.config.ControllerCoreRefEnablePostpone; -// pullInEnabled = ccore.config.ControllerCoreRefEnablePullIn; -// maxpostpone = ccore.config.ControllerCoreRefMaxPostponed * m; -// maxpullin = ccore.config.ControllerCoreRefMaxPulledIn * m; -// for (Bank b : ccore.getBanks()) { -// pulledin[b] = 0; -// postponed[b] = 0; -// currentState[b] = ST_REFRESH; -// previousState[b] = ST_REFRESH; -// nextState[b] = ST_REFRESH; -// setUpDummy(rps[b], b); -// } -//#if INITIAL_DISPLACEMENT == TRUE -// if (bwl) { -// auto nbs = ccore.config.memSpec->NumberOfBanks; -// for (Bank b : ccore.getBanks()) { -// nextPlannedRefreshs[b] = b.ID() * tREFIx / nbs; -// } -// } -//#else -// for (Bank b : ccore.getBanks()) { -// nextPlannedRefreshs[b] = SC_ZERO_TIME; -// } -//#endif -// if (bwl) { -// for (Bank b : ccore.getBanks()) { -// planNextRefresh(b, tREFIx, false); -// } -// } else { -// planNextRefresh(ccore.getBanks()[0], tREFIx, false); -// } -//} - -//RGR::~RGR() -//{ -//} - -//bool RGR::hasCollision(const ScheduledCommand &cmd) -//{ -// Bank b = cmd.getBank(); -// if (currentState[b] == ST_BURST) { -// // A burst due to postponed refreshes shall not be interrupted. -// return true; -// } -// return false; -//} - -//sc_time RGR::doRefresh(tlm::tlm_generic_payload &p, sc_time t) -//{ -// sc_assert(!isInvalidated(p, t)); -// Bank b = DramExtension::getExtension(p).getBank(); -// bool openBank = ccore.state->rowBufferStates->rowBufferIsOpen(b); -// bool allClosed = ccore.state->rowBufferStates->allRowBuffersAreClosed(); -// bool pre = bwl ? openBank : !allClosed; -// sc_time trfcx = SC_ZERO_TIME; - -// if (!bwl) { -// for (Bank b : ccore.getBanks()) { -// currentRefresh[b] = t; -// } -// } else { -// currentRefresh[b] = t; -// } - -// if (pre) { -// trfcx += trp; -// if (bwl) { -// if (ccore.config.getRGRBank(b.ID())) { -// ccore.scheduleRequest(Command::PREB, rps[b]); -// } -// } else { -// for (Bank b : ccore.getBanks()) { -// auto rgrb = ccore.config.getRGRBank(b.ID()); -// if (ccore.state->rowBufferStates->rowBufferIsOpen(b) && rgrb) { -// ccore.scheduleRequest(Command::PREB, rps[Bank(b)]); -// } -// } -// } -// } - -// for (unsigned r = 0; r < rpr; r += ri) { -// trfcx += trcd + trp; -// if (bwl) { -// if (ccore.config.getRGRBank(b.ID())) { -// ccore.scheduleRequest(Command::ACTB, rps[b]); -// ccore.scheduleRequest(Command::PREB, rps[b]); -// } -// DramExtension::getExtension(p).incrementRow(); -// } else { -// for (Bank b : ccore.getBanks()) { -// if (ccore.config.getRGRBank(b.ID())) { -// ccore.scheduleRequest(Command::ACTB, rps[b]); -// ccore.scheduleRequest(Command::PREB, rps[b]); -// } -// DramExtension::getExtension(rps[b]).incrementRow(); -// } -// } -// } - -// return trfcx; -//} - -//void RGR::scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t) -//{ -// sc_time nrt; -// sc_time trfcx; -// Bank b = DramExtension::getExtension(p).getBank(); -// bool preq = bwl ? ccore.hasPendingRequests(b) : ccore.hasPendingRequests(); -// bool postpone = postponeEnabled && preq && (postponed[b] < maxpostpone); -// bool pullIn = pullInEnabled && !preq && (pulledin[b] < maxpullin); -// previousState[b] = currentState[b]; -// currentState[b] = nextState[b]; -// bool align = false; - -// switch (currentState[b]) { -// case ST_REFRESH: -// assert(pulledin[b] == 0 && postponed[b] == 0); -// if (postpone) { -// nrt = SC_ZERO_TIME; -// nextState[b] = ST_POSTPONE; -// } else if (pullIn) { -// trfcx = doRefresh(p, t); -// nrt = trfcx; -// nextState[b] = ST_PULLIN; -// } else { -// doRefresh(p, t); -// nrt = tREFIx; -// nextState[b] = ST_REFRESH; -// } -// break; -// case ST_PULLIN: -// if (pullIn) { -// trfcx = doRefresh(p, t); -// pulledin[b]++; -// nrt = trfcx; -// nextState[b] = ST_PULLIN; -// } else { -// nrt = SC_ZERO_TIME; -// nextState[b] = ST_ALIGN; -// } -// break; -// case ST_SKIP: -// if (pulledin[b] == 0) { -// nrt = SC_ZERO_TIME; -// nextState[b] = ST_REFRESH; -// } else { -// pulledin[b]--; -// nrt = tREFIx; -// nextState[b] = ST_SKIP; -// } -// break; -// case ST_POSTPONE: -// postponed[b]++; -// if ((postponed[b] > maxpostpone) || (!preq && !fmb)) { -// // Burst triggered by inactivity or max postpone value reached. -// nrt = SC_ZERO_TIME; -// nextState[b] = ST_BURST; -// } else { -// nrt = tREFIx; -// nextState[b] = ST_POSTPONE; -// } -// break; -// case ST_BURST: -// doRefresh(p, t); -// postponed[b]--; -// if (postponed[b] == 0) { -// nrt = SC_ZERO_TIME; -// nextState[b] = ST_ALIGN; -// } else { -// nrt = SC_ZERO_TIME; -// nextState[b] = ST_BURST; -// } -// break; -// case ST_ALIGN: -// nrt = tREFIx; -// align = true; -// if (previousState[b] == ST_PULLIN) { -// nextState[b] = ST_SKIP; -// } else { -// nextState[b] = ST_REFRESH; -// } -// break; -// default: -// SC_REPORT_FATAL(this->name(), "RGR flex FSM invalid state."); -// break; -// } -// planNextRefresh(bwl ? b : ccore.getBanks()[0], nrt, align); -//} - -//void RGR::planNextRefresh(Bank b, sc_time t, bool align) -//{ -// if (align) { -// nextPlannedRefreshs[b] = trunc(nextPlannedRefreshs[b].to_double() / -// tREFIx.to_double()) * tREFIx; -// } -// nextPlannedRefreshs[b] += t; -// ccore.controller.send(REFTrigger, nextPlannedRefreshs[b], rps[b]); -//} - -//void RGR::reInitialize(Bank b, sc_time t) -//{ -// nextPlannedRefreshs[b] = clkAlign(t, Alignment::DOWN); -// planNextRefresh(b, tREFIx, true); -//} - -//bool RGR::isInvalidated(tlm::tlm_generic_payload &p, sc_time t) -//{ -// return nextPlannedRefreshs[DramExtension::getExtension(p).getBank()] > t; -//} - -//void RGR::printDebugMessage(std::string msg) -//{ -// DebugManager::getInstance().printDebugMessage(this->name(), msg); -//} diff --git a/DRAMSys/library/src/controller/core/refresh/RGR.h b/DRAMSys/library/src/controller/core/refresh/RGR.h deleted file mode 100644 index 00524a29..00000000 --- a/DRAMSys/library/src/controller/core/refresh/RGR.h +++ /dev/null @@ -1,81 +0,0 @@ -///* -// * Copyright (c) 2017, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Author: Éder F. Zulian -// */ - -//#ifndef RGR_H -//#define RGR_H - -//#include "../../../common/dramExtensions.h" -//#include "../configuration/MemSpec.h" -//#include "IRefreshManager.h" - -//class ControllerCore; - -//class RGR : public IRefreshManager, public sc_module -//{ -//public: -// RGR(sc_module_name, ControllerCore &ctrlcore); -// virtual ~RGR(); -// virtual bool hasCollision(const ScheduledCommand &cmd) override; -// virtual void scheduleRefresh(tlm::tlm_generic_payload &p, sc_time t) override; -// void reInitialize(Bank bank, sc_time time) override; -// bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override; -//private: -// bool fmb; -// bool bwl; -// unsigned int ri; -// unsigned int rpr; -// sc_time trp; -// sc_time trcd; -// sc_time tREFIx; -// ControllerCore &ccore; -// RefreshTiming &timing; -// std::map rps; -// std::map nextPlannedRefreshs; -// std::map currentRefresh; -// bool postponeEnabled; -// bool pullInEnabled; -// unsigned int maxpostpone; -// unsigned int maxpullin; -// std::map pulledin; -// std::map postponed; -// std::map currentState; -// std::map previousState; -// std::map nextState; -// sc_time doRefresh(tlm::tlm_generic_payload &p, sc_time t); -// void planNextRefresh(Bank b, sc_time t, bool align); -// void printDebugMessage(std::string message); -//}; - -//#endif // RGR_H - diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp deleted file mode 100644 index f229cb80..00000000 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.cpp +++ /dev/null @@ -1,275 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Robert Gernhardt -// * Matthias Jung -// * Felipe S. Prado -// * Ana Mativi -// * Éder F. Zulian -// */ - -//#include "RefreshManager.h" -//#include "../ControllerCore.h" -//#include "../timingCalculations.h" -//#include "../../../common/utils.h" - -//using namespace tlm; - -//RefreshManager::RefreshManager(sc_module_name, -// ControllerCore &controller) : controllerCore(controller), -// timing(controller.config.memSpec->refreshTimings[Bank(0)]) -//{ -// auto m = controllerCore.config.getRefMode(); -// tREFIx = timing.tREFI / m; -// tRFCx = timing.tRFC; -// postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; -// pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; -// maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; -// maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; -// pulledin = 0; -// postponed = 0; -// currentState = ST_REFRESH; -// previousState = ST_REFRESH; -// nextState = ST_REFRESH; -// nextPlannedRefresh = SC_ZERO_TIME; -// for (Bank bank : controller.getBanks()) { -// setUpDummy(refreshPayloads[bank], bank); -// } -// planNextRefresh(tREFIx, false); -//} - -//RefreshManager::~RefreshManager() -//{ -//} - -////Check if a command will be scheduled during the next refresh period -//bool RefreshManager::hasCollision(const ScheduledCommand &command) -//{ -// bool collisionWithPreviousRefEnd = command.getStart() < -// controllerCore.state->getLastCommand(Command::REFA).getEnd(); -// bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefresh; -// if (controllerCore.config.ControllerCoreRefEnablePostpone -// && (postponed < maxpostpone)) { -// // Flexible refresh is on and have "credits" to postpone. -// // Then there will not be a collision with next refresh because -// // nextPlannedRefresh will be updated. -// collisionWithNextRefStart = false; -// } -// if (currentState == ST_BURST) { -// // A burst due to postponed refreshes shall not be interrupted. -// collisionWithNextRefStart = true; -// } -// return collisionWithPreviousRefEnd || collisionWithNextRefStart; -//} - -//bool RefreshManager::doRefresh(tlm::tlm_generic_payload &payload, sc_time time) -//{ -// sc_assert(!isInvalidated(payload, time)); -// bool pre = false; -// // If any row is open, precharge all. -// if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { -// pre = true; -// ScheduledCommand prechargeAllMaster(Command::PREA, time, -// Configuration::getInstance().memSpec->getExecutionTime( -// Command::PREA, refreshPayloads[Bank(0)]), -// refreshPayloads[Bank(0)]); -// controllerCore.getCommandChecker( -// Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); - -// for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { -// ScheduledCommand prechargeAll(Command::PREA, -// prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), -// refreshPayloads[Bank(i)]); -// controllerCore.state->change(prechargeAll); -// } -// controllerCore.state->change(prechargeAllMaster); -// controllerCore.controller.send(prechargeAllMaster, refreshPayloads[Bank(0)]); -// } - -// //Otherwise just the AutoRefresh command is scheduled. -// ScheduledCommand refreshAllMaster(Command::REFA, time, -// Configuration::getInstance().memSpec->getExecutionTime( -// Command::REFA, refreshPayloads[Bank(0)]), -// DramExtension::getExtension(refreshPayloads[Bank(0)])); -// controllerCore.getCommandChecker( -// Command::REFA).delayToSatisfyConstraints(refreshAllMaster); - -// for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { -// ScheduledCommand refresh(Command::REFA, refreshAllMaster.getStart(), -// refreshAllMaster.getExecutionTime(), refreshPayloads[Bank(i)]); -// controllerCore.state->change(refresh); -// DramExtension::getExtension(refreshPayloads[Bank(i)]).incrementRow(); -// } -// controllerCore.state->change(refreshAllMaster); -// DramExtension::getExtension(refreshPayloads[Bank(0)]).incrementRow(); -// controllerCore.controller.send(refreshAllMaster, refreshPayloads[Bank(0)]); -// return pre; -//} - - -//void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload &payload, -// sc_time time) -//{ -// sc_time nextRefTiming; -// bool pendingReq = controllerCore.hasPendingRequests(); -// bool canPostpone = postponeEnabled && pendingReq && (postponed < maxpostpone); -// bool canPullIn = pullInEnabled && !pendingReq && (pulledin < maxpullin); -// previousState = currentState; -// currentState = nextState; -// bool align = false; -// sc_time nrt; -// bool pre; - -// switch (currentState) { -// case ST_REFRESH: -// // Regular Refresh. It's possible to migrate from this to the flexible -// // refresh states -// assert(pulledin == 0 && postponed == 0); -// if (canPostpone) { -// nextRefTiming = SC_ZERO_TIME; -// nextState = ST_POSTPONE; -// } else if (canPullIn) { -// pre = doRefresh(payload, time); -// nrt = tRFCx; -// if (pre) -// nrt += controllerCore.config.memSpec->tRP_old; -// nextRefTiming = nrt; -// nextState = ST_PULLIN; -// } else { -// doRefresh(payload, time); -// nextRefTiming = tREFIx; -// nextState = ST_REFRESH; -// } -// break; -// case ST_PULLIN: -// // Pull-in a refresh. Try to pull-in refreshes as long it is possible. -// if (canPullIn) { -// pulledin++; -// pre = doRefresh(payload, time); -// nrt = tRFCx; -// if (pre) -// nrt += controllerCore.config.memSpec->tRP_old; -// nextRefTiming = nrt; -// nextState = ST_PULLIN; -// } else { -// nextRefTiming = SC_ZERO_TIME; -// nextState = ST_ALIGN; -// } -// break; -// case ST_SKIP: -// // Skip the pulled-in refreshes. -// if (pulledin == 0) { -// nextRefTiming = SC_ZERO_TIME; -// nextState = ST_REFRESH; -// } else { -// pulledin--; -// nextRefTiming = tREFIx; -// nextState = ST_SKIP; -// } -// break; -// case ST_POSTPONE: -// // Postpone Refresh. Delaying refreshes as long as there are pending -// // requests and credits to postpone. Should be followed by a burst -// // refresh. -// postponed++; -// if ((postponed > maxpostpone) || (!pendingReq -// && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { -// // Burst triggered by inactivity or max postpone value reached. -// nextRefTiming = SC_ZERO_TIME; -// nextState = ST_BURST; -// } else { -// nextRefTiming = tREFIx; -// nextState = ST_POSTPONE; -// } -// break; -// case ST_BURST: -// // Burst postponed refreshes. -// pre = doRefresh(payload, time); -// postponed--; -// if (postponed == 0) { -// // All refreshes issued, next state will align to tREFIx -// nextRefTiming = SC_ZERO_TIME; -// nextState = ST_ALIGN; -// } else { -// nrt = tRFCx; -// if (pre) -// nrt += controllerCore.config.memSpec->tRP_old; -// nextRefTiming = nrt; -// nextState = ST_BURST; -// } -// break; -// case ST_ALIGN: -// // Align Refresh. Adjusting the timing so the next REF timing will be -// // a in a time multiple of tREFIx -// nextRefTiming = tREFIx; -// align = true; -// if (previousState == ST_PULLIN) { -// nextState = ST_SKIP; -// } else { -// nextState = ST_REFRESH; -// } -// break; -// default: -// SC_REPORT_FATAL(this->name(), "Invalid state in flexible refresh FSM."); -// break; -// } -// planNextRefresh(nextRefTiming, align); -//} - -//void RefreshManager::planNextRefresh(sc_time nextRefTiming, bool align) -//{ -// if (align) { -// nextPlannedRefresh = trunc(nextPlannedRefresh.to_double() / tREFIx.to_double()) -// * tREFIx; -// } -// nextPlannedRefresh += nextRefTiming; -// controllerCore.controller.send(REFTrigger, nextPlannedRefresh, -// refreshPayloads[Bank(0)]); -//} - -//void RefreshManager::reInitialize(Bank, sc_time time) -//{ -// nextPlannedRefresh = clkAlign(time, Alignment::DOWN); -// planNextRefresh(tREFIx, true); -//} - -//bool RefreshManager::isInvalidated(tlm::tlm_generic_payload &payload -// __attribute__((unused)), sc_time time) -//{ -// return nextPlannedRefresh > time; -//} - -//void RefreshManager::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage(this->name(), message); -//} - diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h b/DRAMSys/library/src/controller/core/refresh/RefreshManager.h deleted file mode 100644 index b4f5c0fc..00000000 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManager.h +++ /dev/null @@ -1,82 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Robert Gernhardt -// * Matthias Jung -// * Éder F. Zulian -// */ - -//#ifndef REFRESHMANAGER_H -//#define REFRESHMANAGER_H - -//#include "IRefreshManager.h" -//#include "../configuration/MemSpec.h" - -//class ControllerCore; - -//class RefreshManager : public IRefreshManager, public sc_module -//{ -//public: -// RefreshManager(sc_module_name /*name*/, ControllerCore &controllerCore); -// virtual ~RefreshManager(); - -// virtual bool hasCollision(const ScheduledCommand &command) override; -// virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, -// sc_time time) override; -// void reInitialize(Bank bank, sc_time time) override; -// virtual bool isInvalidated(tlm::tlm_generic_payload &payload, -// sc_time time) override; - -//private: -// ControllerCore &controllerCore; -// RefreshTiming &timing; -// sc_time nextPlannedRefresh; -// sc_time tREFIx; -// sc_time tRFCx; -// std::map refreshPayloads; -// bool postponeEnabled; -// bool pullInEnabled; -// unsigned int maxpostpone; -// unsigned int maxpullin; -// unsigned int pulledin; -// unsigned int postponed; -// ref_fsm_state_t currentState; -// ref_fsm_state_t previousState; -// ref_fsm_state_t nextState; - -// bool doRefresh(tlm::tlm_generic_payload &payload, sc_time time); -// void planNextRefresh(sc_time time, bool align); -// void printDebugMessage(std::string message); -//}; - -//#endif // REFRESHMANAGER_H - diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp deleted file mode 100644 index 373204c2..00000000 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.cpp +++ /dev/null @@ -1,265 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// * Éder F. Zulian -// */ - -//#include "RefreshManagerBankwise.h" -//#include "../ControllerCore.h" -//#include "../timingCalculations.h" -//#include "../../../common/utils.h" - -//using namespace std; - -//RefreshManagerBankwise::RefreshManagerBankwise(sc_module_name, -// ControllerCore &controller) : controllerCore(controller), -// timing(controller.config.memSpec->refreshTimings[Bank(0)]) -//{ -// auto m = controllerCore.config.getRefMode(); -// tREFIx = timing.tREFI / m; -// tRFCx = timing.tRFC; -// postponeEnabled = controllerCore.config.ControllerCoreRefEnablePostpone; -// pullInEnabled = controllerCore.config.ControllerCoreRefEnablePullIn; -// maxpostpone = controllerCore.config.ControllerCoreRefMaxPostponed * m; -// maxpullin = controllerCore.config.ControllerCoreRefMaxPulledIn * m; -// for (Bank bank : controller.getBanks()) { -// nextPlannedRefreshs[bank] = SC_ZERO_TIME; -// pulledin[bank] = 0; -// postponed[bank] = 0; -// currentState[bank] = ST_REFRESH; -// previousState[bank] = ST_REFRESH; -// nextState[bank] = ST_REFRESH; -// setUpDummy(refreshPayloads[bank], bank); -// planNextRefresh(bank, tREFIx, false); -// } -//} - -//RefreshManagerBankwise::~RefreshManagerBankwise() -//{ -//} - -//bool RefreshManagerBankwise::hasCollision(const ScheduledCommand &command) -//{ -// Bank bank = command.getBank(); -// bool collisionWithPreviousRefEnd = command.getStart() < -// controllerCore.state->getLastCommand(Command::REFA, bank).getEnd(); -// bool collisionWithNextRefStart = command.getEnd() >= nextPlannedRefreshs[bank]; -// if (controllerCore.config.ControllerCoreRefEnablePostpone -// && (postponed[bank] < maxpostpone)) { -// // Flexible refresh is on and have "credits" to postpone. -// // Then there will not be a collision with next refresh because -// // nextPlannedRefresh will be updated. -// collisionWithNextRefStart = false; -// } -// if (currentState[bank] == ST_BURST) { -// // A burst due to postponed refreshes shall not be interrupted. -// collisionWithNextRefStart = true; -// } -// return collisionWithPreviousRefEnd || collisionWithNextRefStart; -//} - -//bool RefreshManagerBankwise::doRefresh(tlm::tlm_generic_payload &payload, -// sc_time time) -//{ -// sc_assert(!isInvalidated(payload, time)); -// bool pre = false; -// tlm::tlm_generic_payload &refreshPayload = -// refreshPayloads[DramExtension::getExtension(payload).getBank()]; -// DramExtension &extension = DramExtension::getExtension(refreshPayload); - -// if (controllerCore.state->rowBufferStates->rowBufferIsOpen( -// extension.getBank())) { -// pre = true; -// ScheduledCommand precharge(Command::PRE, time, -// Configuration::getInstance().memSpec->getExecutionTime( -// Command::PRE, refreshPayload), extension); -// controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( -// precharge); -// controllerCore.state->change(precharge); -// controllerCore.controller.send(precharge, refreshPayload); -// } - -// ScheduledCommand refresh(Command::REFA, time, -// Configuration::getInstance().memSpec->getExecutionTime( -// Command::REFA, refreshPayload), extension); -// controllerCore.getCommandChecker( -// Command::REFA).delayToSatisfyConstraints(refresh); -// controllerCore.state->change(refresh); -// extension.incrementRow(); -// controllerCore.controller.send(refresh, refreshPayload); -// return pre; -//} - -//void RefreshManagerBankwise::scheduleRefresh(tlm::tlm_generic_payload &payload, -// sc_time time) -//{ -// sc_time nextRefTiming; -// Bank bank = DramExtension::getExtension(payload).getBank(); -// bool pendingReq = controllerCore.hasPendingRequests(bank); -// bool canPostpone = postponeEnabled && pendingReq -// && (postponed[bank] < maxpostpone); -// bool canPullIn = pullInEnabled && !pendingReq && (pulledin[bank] < maxpullin); -// previousState[bank] = currentState[bank]; -// currentState[bank] = nextState[bank]; -// bool align = false; -// sc_time nrt; -// bool pre; - -// switch (currentState[bank]) { -// case ST_REFRESH: -// // Regular Refresh. It's possible to migrate from this to the flexible -// // refresh states -// assert(pulledin[bank] == 0 && postponed[bank] == 0); -// if (canPostpone) { -// nextRefTiming = SC_ZERO_TIME; -// nextState[bank] = ST_POSTPONE; -// } else if (canPullIn) { -// pre = doRefresh(payload, time); -// nrt = tRFCx; -// if (pre) -// nrt += controllerCore.config.memSpec->tRP_old; -// nextRefTiming = nrt; -// nextState[bank] = ST_PULLIN; -// } else { -// doRefresh(payload, time); -// nextRefTiming = tREFIx; -// nextState[bank] = ST_REFRESH; -// } -// break; -// case ST_PULLIN: -// // Pull-in a refresh. Try to pull-in refreshes as long it is possible. -// if (canPullIn) { -// pulledin[bank]++; -// pre = doRefresh(payload, time); -// nrt = tRFCx; -// if (pre) -// nrt += controllerCore.config.memSpec->tRP_old; -// nextRefTiming = nrt; -// nextState[bank] = ST_PULLIN; -// } else { -// nextRefTiming = SC_ZERO_TIME; -// nextState[bank] = ST_ALIGN; -// } -// break; -// case ST_SKIP: -// // Skip the pulled-in refreshes. -// if (pulledin[bank] == 0) { -// nextRefTiming = SC_ZERO_TIME; -// nextState[bank] = ST_REFRESH; -// } else { -// pulledin[bank]--; -// nextRefTiming = tREFIx; -// nextState[bank] = ST_SKIP; -// } -// break; -// case ST_POSTPONE: -// // Postpone Refresh. Delaying refreshes as long as there are pending -// // requests and credits to postpone. Should be followed by a burst -// // refresh. -// postponed[bank]++; -// if ((postponed[bank] > maxpostpone) || (!pendingReq -// && !controllerCore.config.ControllerCoreRefForceMaxPostponeBurst)) { -// // Burst triggered by inactivity or max postpone value reached. -// nextRefTiming = SC_ZERO_TIME; -// nextState[bank] = ST_BURST; -// } else { -// nextRefTiming = tREFIx; -// nextState[bank] = ST_POSTPONE; -// } -// break; - -// case ST_BURST: -// // Burst postponed refreshes. -// pre = doRefresh(payload, time); -// postponed[bank]--; -// if (postponed[bank] == 0) { -// // All refreshes issued, next state will align to tREFIx -// nextRefTiming = SC_ZERO_TIME; -// nextState[bank] = ST_ALIGN; -// } else { -// nrt = tRFCx; -// if (pre) -// nrt += controllerCore.config.memSpec->tRP_old; -// nextRefTiming = nrt; -// nextState[bank] = ST_BURST; -// } -// break; -// case ST_ALIGN: -// // Align Refresh. Adjusting the timing so the next REF timing will be -// // a in a time multiple of tREFIx -// nextRefTiming = tREFIx; -// align = true; -// if (previousState[bank] == ST_PULLIN) { -// nextState[bank] = ST_SKIP; -// } else { -// nextState[bank] = ST_REFRESH; -// } -// break; -// default: -// SC_REPORT_FATAL(this->name(), "Invalid state in bw flex. ref. FSM."); -// break; -// } -// planNextRefresh(bank, nextRefTiming, align); -//} - -//void RefreshManagerBankwise::planNextRefresh(Bank bank, sc_time nextRefTiming, -// bool align) -//{ -// if (align) { -// nextPlannedRefreshs[bank] = trunc(nextPlannedRefreshs[bank].to_double() / -// tREFIx.to_double()) * tREFIx; -// } -// nextPlannedRefreshs[bank] += nextRefTiming; -// controllerCore.controller.send(REFTrigger, nextPlannedRefreshs[bank], -// refreshPayloads[bank]); -//} - -//void RefreshManagerBankwise::reInitialize(Bank bank, sc_time time) -//{ -// nextPlannedRefreshs[bank] = clkAlign(time, Alignment::DOWN); -// planNextRefresh(bank, tREFIx, true); -//} - -//bool RefreshManagerBankwise::isInvalidated(tlm::tlm_generic_payload &payload, -// sc_time time) -//{ -// return nextPlannedRefreshs[DramExtension::getExtension(payload).getBank()] > -// time; -//} - -//void RefreshManagerBankwise::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage(this->name(), message); -//} - diff --git a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h deleted file mode 100644 index bf094bfc..00000000 --- a/DRAMSys/library/src/controller/core/refresh/RefreshManagerBankwise.h +++ /dev/null @@ -1,83 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// * Éder F. Zulian -// */ - -//#ifndef REFRESHMANAGERBANKWISE_H -//#define REFRESHMANAGERBANKWISE_H - -////#include "../../../common/dramExtension.h" -//#include "IRefreshManager.h" -//#include "../configuration/MemSpec.h" - - -//class ControllerCore; - -//class RefreshManagerBankwise : public IRefreshManager, public sc_module -//{ -//public: -// RefreshManagerBankwise(sc_module_name /*name*/, ControllerCore &controllerCore); -// virtual ~RefreshManagerBankwise(); - -// virtual bool hasCollision(const ScheduledCommand &command) override; -// virtual void scheduleRefresh(tlm::tlm_generic_payload &payload, -// sc_time time) override; -// void reInitialize(Bank bank, sc_time time) override; -// bool isInvalidated(tlm::tlm_generic_payload &payload, sc_time time) override; - -//private: -// ControllerCore &controllerCore; -// RefreshTiming &timing; -// std::map nextPlannedRefreshs; -// sc_time tREFIx; -// sc_time tRFCx; -// std::map refreshPayloads; -// bool postponeEnabled; -// bool pullInEnabled; -// unsigned int maxpostpone; -// unsigned int maxpullin; -// std::map pulledin; -// std::map postponed; -// std::map currentState; -// std::map previousState; -// std::map nextState; - -// bool doRefresh(tlm::tlm_generic_payload &payload, sc_time time); -// void planNextRefresh(Bank bank, sc_time time, bool align); -// void printDebugMessage(std::string message); -//}; - -//#endif // REFRESHMANAGERBANKWISE_H - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp deleted file mode 100644 index 0c119726..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Éder F. Zulian - */ - -#include -#include -#include -#include "ActBChecker.h" -#include "../../timingCalculations.h" -#include "../../../../common/DebugManager.h" -#include "../../../Command.h" -#include "../../../../common/utils.h" - -using namespace std; - -void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const -{ - sc_assert(cmd.getCommand() == Command::ACTB); - ScheduledCommand lcb = state.getLastScheduledCommand(cmd.getBank()); - if (lcb.isValidCommand()) { - if (lcb.getCommand() == Command::PREB) { - cmd.establishMinDistanceFromStart(lcb.getStart(), - Configuration::getInstance().getTrpb()); - } else if (lcb.getCommand() == Command::PRE - || lcb.getCommand() == Command::PREA) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRP_old); - } else if (lcb.getCommand() == Command::RDA) { - cmd.establishMinDistanceFromStart(lcb.getStart(), - config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lcb.getCommand() == Command::WRA) { - cmd.establishMinDistanceFromStart(lcb.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() - + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lcb.getCommand() == Command::REFA) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tRFC_old); - } else if (lcb.getCommand() == Command::PDXP - || lcb.getCommand() == Command::PDXA) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXP); - } else if (lcb.getCommand() == Command::SREFEX) { - cmd.establishMinDistanceFromStart(lcb.getStart(), config.memSpec->tXS); - } else { - reportFatal("ActB Checker", - "ACTB can not follow " + commandToString(lcb.getCommand())); - } - } - ScheduledCommand lc; - if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); - } - delay_to_satisfy_activateToActivate_sameBank(cmd); - while (!(state.bus.isFree(cmd.getStart()) - && satsfies_activateToActivate_differentBank(cmd) - && satisfies_nActivateWindow(cmd))) { - cmd.delayStart(config.memSpec->clk); - } -} - -void ActBChecker::delay_to_satisfy_activateToActivate_sameBank( - ScheduledCommand &cmd) const -{ - ScheduledCommand lastActOnBank = state.getLastCommandOnBank(Command::ACT, - cmd.getBank()); - if (lastActOnBank.isValidCommand()) { - cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec->tRC); - } - ScheduledCommand lastActBOnBank = state.getLastCommandOnBank(Command::ACTB, - cmd.getBank()); - if (lastActBOnBank.isValidCommand()) { - cmd.establishMinDistanceFromStart(lastActBOnBank.getStart(), - Configuration::getInstance().getTrcb()); - } -} - -bool ActBChecker::satsfies_activateToActivate_differentBank( - ScheduledCommand &cmd) const -{ - for (auto act : state.lastActivatesB) { - sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ? - Configuration::getInstance().getTrrdb_L() : - Configuration::getInstance().getTrrdb_S()); - if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t - && t - cmd.getStart() < tRRD)) { - return false; - } - } -// for (auto act : state.lastActivates) { -// sc_time t = act.first, tRRD = (cmd.getBankGroup() == act.second.getBankGroup() ? -// config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old); -// if ((t < cmd.getStart() && cmd.getStart() - t < tRRD) || (cmd.getStart() <= t -// && t - cmd.getStart() < tRRD)) { -// return false; -// } -// } - return true; -} - -bool ActBChecker::satisfies_nActivateWindow(ScheduledCommand &cmd) const -{ - if (state.lastActivatesB.size() >= config.memSpec->nActivate) { - maplastActivates = state.lastActivatesB; - lastActivates.emplace(cmd.getStart(), cmd); - auto upper = lastActivates.begin(); - advance(upper, config.memSpec->nActivate); - auto lower = lastActivates.begin(); - while (upper != lastActivates.end()) { - if (upper->first - lower->first < Configuration::getInstance().getTfawb()) { - return false; - } - ++upper; - ++lower; - } - } - return true; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h deleted file mode 100644 index f1a04859..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Éder F. Zulian - */ - -#ifndef ACTBCHECKER_H -#define ACTBCHECKER_H - -#include -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class ActBChecker : public ICommandChecker -{ -public: - ActBChecker(const Configuration &config, - ControllerState &state) : config(config), state(state) {} - virtual ~ActBChecker() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; -private: - const Configuration &config; - ControllerState &state; - void delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) - const; - bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const; - bool satisfies_nActivateWindow(ScheduledCommand &command) const; -}; - -#endif // ACTBCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp deleted file mode 100644 index 8e3b6a65..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#include -#include -#include -#include "ActivateChecker.h" -#include "../../timingCalculations.h" -#include "../../../../common/DebugManager.h" -#include "../../../Command.h" -#include "../../../../common/utils.h" - -using namespace std; - -void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const -{ - sc_assert(command.getCommand() == Command::ACT); - - ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand( - command.getBank()); - if (lastCommandOnBank.isValidCommand()) { - if (lastCommandOnBank.getCommand() == Command::PREB - || lastCommandOnBank.getCommand() == Command::PRE - || lastCommandOnBank.getCommand() == Command::PREA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::RDA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::WRA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() - + config.memSpec->tWR + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::REFA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRFC_old); - } else if (lastCommandOnBank.getCommand() == Command::PDXP - || lastCommandOnBank.getCommand() == Command::PDXA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tXP); - } else if (lastCommandOnBank.getCommand() == Command::SREFEX) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tXS); - } else - reportFatal("Activate Checker", - "ACT can not follow " + commandToString(lastCommandOnBank.getCommand())); - } - - delay_to_satisfy_activateToActivate_sameBank(command); - - while (!(state.bus.isFree(command.getStart()) - && satsfies_activateToActivate_differentBank(command) - && satisfies_nActivateWindow(command))) { - command.delayStart(config.memSpec->clk); - } - -} - -void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank( - ScheduledCommand &command) const -{ - ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, - command.getBank()); - if (lastActivateOnBank.isValidCommand()) { - command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), - config.memSpec->tRC); - } - - ScheduledCommand lastActBOnBank = state.getLastCommandOnBank(Command::ACTB, - command.getBank()); - if (lastActBOnBank.isValidCommand()) { - command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), - config.memSpec->tRC); - } -} - -bool ActivateChecker::satsfies_activateToActivate_differentBank( - ScheduledCommand &command) const -{ -// for (auto act : state.lastActivates) { -// sc_time time = act.first; -// sc_time tRRD = (command.getBankGroup() == act.second.getBankGroup()) ? -// config.memSpec->tRRD_L_old : config.memSpec->tRRD_S_old; - -// if ((time < command.getStart() && command.getStart() - time < tRRD) -// || (command.getStart() <= time && time - command.getStart() < tRRD)) -// return false; -// } - return true; -} - -bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand &command) const -{ - /* - * there may be activates scheduled in the future, so emplace - * command in a copied set (not necessarily the last in time), - * and check if the n-act constraint holds for the whole set. - */ -// if (state.lastActivates.size() >= config.memSpec->nActivate) { -// map lastActivates = state.lastActivates; -// lastActivates.emplace(command.getStart(), command); -// auto upper = lastActivates.begin(); -// advance(upper, config.memSpec->nActivate); -// auto lower = lastActivates.begin(); - -// while (upper != lastActivates.end()) { -// if (upper->first - lower->first < config.memSpec->tNAW_old) -// return false; -// ++upper; -// ++lower; -// } -// } - - return true; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h deleted file mode 100644 index 1312505d..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef ACTIVATECHECKER_H -#define ACTIVATECHECKER_H - -#include -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class ActivateChecker: public ICommandChecker -{ -public: - ActivateChecker(const Configuration &config, - ControllerState &state) : config(config), state(state) {} - virtual ~ActivateChecker() {} - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; -private: - const Configuration &config; - ControllerState &state;//TODO make const - - void delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) - const; - bool satsfies_activateToActivate_differentBank(ScheduledCommand &command) const; - bool satisfies_nActivateWindow(ScheduledCommand &command) const; -}; - -#endif // ACTIVATECHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp deleted file mode 100644 index c4f8f007..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Lukas Steiner - */ - -#include "CheckerDDR3New.h" - -#include -#include -#include -#include -#include "../../timingCalculations.h" -#include "../../../../common/DebugManager.h" -#include "../../../Command.h" -#include "../../../../common/utils.h" - -using namespace std; - -sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) -{ - ScheduledCommand lastCommand; - - sc_time minTimeToWait = sc_time_stamp(); - - if (command == Command::ACT) - { - lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - - lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - - lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - - lastCommand = lastScheduledByCommand[Command::PREA]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::PDXP]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::REFA]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); - - lastCommand = lastScheduledByCommand[Command::SREFEX]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); - - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); - - lastCommand = lastScheduledByCommand[Command::ACT]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); - - minTimeToWait = max(minTimeToWait, timeToSatisfyFAW()); - } - else if (command == Command::RD || command == Command::RDA) - { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::SREFEX]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); - - lastCommand = lastScheduledByCommand[Command::RD]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - - lastCommand = lastScheduledByCommand[Command::WR]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - } - else if (command == Command::WR || command == Command::WRA) - { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - - lastCommand = lastScheduledByCommand[Command::SREFEX]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); - - lastCommand = lastScheduledByCommand[Command::RD]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - - lastCommand = lastScheduledByCommand[Command::WR]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - } - else if (command == Command::PRE) - { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); - - lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); - - lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - - lastCommand = lastScheduledByCommand[Command::PDXA]; - if (lastCommand.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - } - else - { - reportFatal("CheckerDDR3New", "Unknown command!"); - } - // Check if bus is free - if (lastScheduled.isValidCommand()) - minTimeToWait = max(minTimeToWait, lastScheduled.getStart() + memSpec->clk); - - return (minTimeToWait - sc_time_stamp()); -} - -sc_time CheckerDDR3New::timeToSatisfyFAW() -{ - if (lastActivates.size() < 4) - return sc_time_stamp(); - else - { - sc_time earliestTime = lastActivates.front() + memSpec->tFAW; - if (earliestTime > sc_time_stamp()) - return earliestTime; - else - return sc_time_stamp(); - } -} - -void CheckerDDR3New::insert(const ScheduledCommand &scheduledCommand) -{ - Command command = scheduledCommand.getCommand(); - printDebugMessage("Changing state on bank " + - to_string(scheduledCommand.getBank().ID()) + - " command is " + commandToString(command)); - - lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] = scheduledCommand; - lastScheduledByCommand[command] = scheduledCommand; - lastScheduled = scheduledCommand; - - // TODO: implement FAW for ACTB - if (command == Command::ACT) - { - if (lastActivates.size() == 4) - lastActivates.pop(); - lastActivates.push(scheduledCommand.getStart()); - } -} - -void CheckerDDR3New::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage("Checker", message); -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h deleted file mode 100644 index 085104e6..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2019, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Lukas Steiner - */ - -#ifndef CHECKERDDR3NEW_H -#define CHECKERDDR3NEW_H - -#include -#include -#include -#include "../ScheduledCommand.h" -#include "../../configuration/Configuration.h" -#include "../../configuration/MemSpec.h" -#include "../../../Command.h" -#include "../../../../common/dramExtensions.h" - -class CheckerDDR3New -{ -public: - CheckerDDR3New() - { - memSpec = dynamic_cast(Configuration::getInstance().memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - } - ~CheckerDDR3New() {} - - sc_time delayToSatisfyConstraints(Command command, Bank bank); - void insert(const ScheduledCommand &scheduledCommand); - -private: - const MemSpecDDR3 *memSpec; - - std::map> lastScheduledByCommandAndBank; - std::map lastScheduledByCommand; - ScheduledCommand lastScheduled; - - // Four activate window - std::queue lastActivates; - sc_time timeToSatisfyFAW(); - - //PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; - - void printDebugMessage(std::string message); -}; - -#endif // CHECKERDDR3NEW_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h deleted file mode 100644 index 3f38f93b..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ICommandChecker.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef ICOMMANDCHECKER_H -#define ICOMMANDCHECKER_H - -#include -#include "../ScheduledCommand.h" - - -class ICommandChecker -{ -public: - virtual ~ICommandChecker() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const = 0; -}; - - - -#endif // ICOMMANDCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp deleted file mode 100644 index 16ace13e..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Felipe S. Prado - */ - -#include "PowerDownChecker.h" -#include "../../timingCalculations.h" - -void PowerDownChecker::delayToSatisfyConstraints(ScheduledCommand &command) -const -{ - sc_assert(command.commandIsIn({Command::PDEA, Command::PDEP, Command::SREFEN, Command::PDXA, Command::PDXP, Command::SREFEX})); - - // Power Down commmand (one of the listed above) - Command pdnCmd = command.getCommand(); - Bank bank = command.getBank(); - - sc_time timeConstraint; - - if (pdnCmd == Command::PDEA || pdnCmd == Command::PDEP - || pdnCmd == Command::SREFEN) { - // Entering in one of the Power Down modes: - // PDNA - Active Power Down - // PDNP - Precharge Power Down - // SREF - Self Refresh - - // Get the last scheduled command - ScheduledCommand lastSchedCmd; - if(Configuration::getInstance().BankwiseLogic) - { - lastSchedCmd = state.getLastScheduledCommand(bank); - } - else - { - lastSchedCmd = state.getLastScheduledCommand(); - } - // TODO: Why do we only need to check the last scheduled command? bank_0_RDA -> bank_1_PRE -> SREFEN violates timing - if (lastSchedCmd.isValidCommand()) { - // Get the start time for the last scheduled command - sc_time lastSchedCmdStart = lastSchedCmd.getStart(); - // Get the last command - Command lastCmd = lastSchedCmd.getCommand(); - - timeConstraint = getTimeConstraintToEnterPowerDown(lastCmd, pdnCmd); - - command.establishMinDistanceFromStart(lastSchedCmdStart, timeConstraint); - } - - } else if (pdnCmd == Command::PDXA) { - // Leaving Active Power Down - timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, - bank).getStart(), timeConstraint); - } else if (pdnCmd == Command::PDXP) { - // Leaving Precharge Power Down - timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, - bank).getStart(), timeConstraint); - } else if (pdnCmd == Command::SREFEX) { - // Leaving Self Refresh - timeConstraint = config.memSpec->tCKESR; - command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, - bank).getStart(), timeConstraint); - } - - state.bus.moveCommandToNextFreeSlot(command); -} - -sc_time PowerDownChecker::getTimeConstraintToEnterPowerDown(Command lastCmd, - Command pdnCmd) const -{ - sc_assert(pdnCmd == Command::SREFEN || pdnCmd == Command::PDEA - || pdnCmd == Command::PDEP); - - sc_time constraint; - - if (lastCmd == Command::RD || lastCmd == Command::RDA) { - constraint = config.memSpec->tRL + config.memSpec->getReadAccessTime() + config.memSpec->clk; - } else if (lastCmd == Command::WR) { - constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR; - } else if (lastCmd == Command::WRA) { - constraint = config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->clk; - // TODO: for SREFEN the constraint is tRFC, for PDEP it is tREFPDEN, PDEA cannot be the next command after REFA (all banks closed) - } else if (lastCmd == Command::REFA) { - constraint = config.memSpec->tRFC_old; - // TODO: for PDEA/PDEP the constraint is tCLK, for SREFEN it is tXP - } else if (lastCmd == Command::PDXP || lastCmd == Command::PDXA) { - constraint = config.memSpec->tXP; - } else if (lastCmd == Command::SREFEX) { - constraint = config.memSpec->tXS; - // TODO: for PDEA/PDEP the constraint is tPRPDEN, for SREFEN the constraint is tRP - } else if (lastCmd == Command::PRE || lastCmd == Command::PREA) { - constraint = config.memSpec->tRP_old; - // TODO: ACT -> PDEA missing (tACTPDEN) - } else { - reportFatal("Powerdown checker", - commandToString(pdnCmd) + " can not follow " + commandToString(lastCmd)); - } - - return constraint; -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h deleted file mode 100644 index a1b5f53d..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef POWERDOWNCHECKER_H -#define POWERDOWNCHECKER_H - -#include - -#include "../../../ControllerState.h" -#include "../../configuration/Configuration.h" -#include "ICommandChecker.h" - -class PowerDownChecker : public ICommandChecker -{ -public: - PowerDownChecker(const Configuration &config, - ControllerState &state) : config(config), state(state) {} - virtual ~PowerDownChecker() {} - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; - -private: - const Configuration &config; - ControllerState &state; - sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, - Command pdnCmd) const; -}; - -#endif // POWERDOWNCHECKER_H - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp deleted file mode 100644 index 5a0f7229..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Éder F. Zulian - */ - -#include "PreBChecker.h" -#include "../../timingCalculations.h" -void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const -{ - sc_assert(cmd.getCommand() == Command::PREB); - ScheduledCommand lastCmd = state.getLastScheduledCommand(cmd.getBank()); - if (lastCmd.isValidCommand()) { - // TODO: unused? - if (lastCmd.getCommand() == Command::PREB) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), - Configuration::getInstance().getTrpb()); - } else if (lastCmd.getCommand() == Command::PRE) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); - } else if (lastCmd.getCommand() == Command::PREA) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRP_old); - // ------------ - } else if (lastCmd.getCommand() == Command::ACTB) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), - config.memSpec->tRCD); // XXX: trcd is less than the NEW! trasb! ok! - } else if (lastCmd.getCommand() == Command::ACT) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRCD); - } else if (lastCmd.getCommand() == Command::RD) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tRTP); - } else if (lastCmd.getCommand() == Command::WR) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); - } else if (lastCmd.getCommand() == Command::PDXA) { - cmd.establishMinDistanceFromStart(lastCmd.getStart(), config.memSpec->tXP); - } else { - reportFatal("PreB Checker", - "PREB can not follow " + commandToString(lastCmd.getCommand())); - } - } - ScheduledCommand lc; - // TODO: unused? - if ((lc = state.getLastCommand(Command::PREA)).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); - } - // ------------ - if ((lc = state.getLastCommandOnBank(Command::ACT, - cmd.getBank())).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); - } - if ((lc = state.getLastCommandOnBank(Command::ACTB, - cmd.getBank())).isValidCommand()) { - cmd.establishMinDistanceFromStart(lc.getStart(), - Configuration::getInstance().getTrasb()); - } - state.bus.moveCommandToNextFreeSlot(cmd); -} diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h deleted file mode 100644 index 980901a3..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Author: Éder F. Zulian - */ - -#ifndef PREBCHECKER_H -#define PREBCHECKER_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class PreBChecker: public ICommandChecker -{ -public: - PreBChecker(const Configuration &config, - ControllerState &state): config(config), state(state) {} - virtual ~PreBChecker() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; -private: - const Configuration &config; - ControllerState &state; -}; - -#endif // PREBCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp deleted file mode 100644 index 45380a72..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - * Felipe S. Prado - */ - -#include "PrechargeAllChecker.h" -#include "../../timingCalculations.h" - - -void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand &command) -const -{ - sc_assert(command.getCommand() == Command::PREA); - - // Consider all banks for the constraints, since precharge all command is supposed to happen at the same time on all banks - for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - if (lastCommand.isValidCommand()) { - // TODO: Where do these dependencies come from? - if (lastCommand.getCommand() == Command::PRE - || lastCommand.getCommand() == Command::PREB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRP_old); - // TODO: Why tRCD and not tRAS? - } else if (lastCommand.getCommand() == Command::ACT - || lastCommand.getCommand() == Command::ACTB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::RD) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRTP); - // TODO: missing - } else if (lastCommand.getCommand() == Command::RDA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::WR) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); - // TODO: missing - } else if (lastCommand.getCommand() == Command::WRA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::REFA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRFC_old); - // TODO: PREA after PDXP possible? - } else if (lastCommand.getCommand() == Command::PDXA - || lastCommand.getCommand() == Command::PDXP) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXP); - } else if (lastCommand.getCommand() == Command::SREFEX) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXS); - } else - reportFatal("Precharge All Checker", - "PREA can not follow " + commandToString(lastCommand.getCommand())); - } - } - - ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, - command.getBank()); - // TODO: Why do we only check the ACT of one bank? (always bank 0) - if (lastActivate.isValidCommand()) { - command.establishMinDistanceFromStart(lastActivate.getStart(), - config.memSpec->tRAS); - } - - state.bus.moveCommandToNextFreeSlot(command); -} - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h deleted file mode 100644 index 41133b4b..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef PRECHARGEALLCHECKER_H -#define PRECHARGEALLCHECKER_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class PrechargeAllChecker: public ICommandChecker -{ -public: - PrechargeAllChecker(const Configuration &config, ControllerState &state) : - config(config), state(state) - { - } - virtual ~PrechargeAllChecker() - { - } - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; - -private: - const Configuration &config; - ControllerState &state; -}; - - -#endif // PRECHARGEALLCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp deleted file mode 100644 index 3666f5f3..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#include "PrechargeChecker.h" -#include "../../timingCalculations.h" - - -void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand &command) -const -{ - //return; - sc_assert(command.getCommand() == Command::PRE); - - ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); - - if (lastCommand.isValidCommand()) { - // the first two cases happen when a resfresh interrups the command sequence of a transaction - // (e.g. commands to process transaction are PRE-ACT-RD and refresh happens after the PRE or after the ACT) - // TODO: unused? - if (lastCommand.getCommand() == Command::PRE - || lastCommand.getCommand() == Command::PREB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::ACT - || lastCommand.getCommand() == Command::ACTB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRCD); - } - // ------------- - else if (lastCommand.getCommand() == Command::RD) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRTP); - } else if (lastCommand.getCommand() == Command::WR) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR); - - } else if (lastCommand.getCommand() == Command::PDXA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXP); - } else - reportFatal("Precharge Checker", - "PRE can not follow " + commandToString(lastCommand.getCommand())); - } - - ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, - command.getBank()); - if (lastActivate.isValidCommand()) { - command.establishMinDistanceFromStart(lastActivate.getStart(), - config.memSpec->tRAS); - } - - state.bus.moveCommandToNextFreeSlot(command); -} - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h deleted file mode 100644 index 05b94dc1..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef PRECHARGECHECKER_H -#define PRECHARGECHECKER_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class PrechargeChecker: public ICommandChecker -{ -public: - PrechargeChecker(const Configuration &config, - ControllerState &state) : config(config), state(state) {} - virtual ~PrechargeChecker() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; - -private: - const Configuration &config; - ControllerState &state; -}; - - -#endif // PRECHARGECHECKER_ diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp deleted file mode 100644 index d47dee54..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#include "ReadChecker.h" -#include "../../timingCalculations.h" -#include "../../../../common/utils.h" -#include "WriteChecker.h" - -using namespace std; - -void ReadChecker::delayToSatisfyConstraints(ScheduledCommand &command) const -{ - sc_assert(command.getCommand() == Command::RD - || command.getCommand() == Command::RDA); - delayToSatisfyDLL(command); - ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); - - if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::ACT - || lastCommand.getCommand() == Command::ACTB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::RD) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - ReadChecker::readToRead(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::WR) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - ReadChecker::writeToRead(lastCommand, command)); - } else if (/*lastCommand.getCommand() == Command::PDXP - || */lastCommand.getCommand() == Command::PDXA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXP); - } else - reportFatal("Read Checker", - "RD/RDA can not follow " + commandToString(lastCommand.getCommand())); - } - - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { - command.delayStart(config.memSpec->clk); - } -} - -bool ReadChecker::collidesOnDataStrobe(ScheduledCommand &read) const -{ -// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { -// if (collidesWithStrobeCommand(read, strobeCommand)) -// return true; -// } - - return false; -} - -bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::RD - || strobeCommand.getCommand() == Command::RDA) { - return getDistance(read.getStart(), - strobeCommand.getStart()) < ReadChecker::readToRead(strobeCommand, read); - } else if (strobeCommand.getCommand() == Command::WR - || strobeCommand.getCommand() == Command::WRA) { - if (strobeCommand.getStart() >= read.getStart()) - return getDistance(read.getStart(), - strobeCommand.getStart()) < WriteChecker::readToWrite(read, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - read.getStart()) < ReadChecker::writeToRead(strobeCommand, read); - } else { - reportFatal("Read Checker", - "Invalid strobeCommand in data strobe commands " + commandToString( - strobeCommand.getCommand())); - return true; - } -} - -void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const -{ - ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, - read.getBank()); - if (lastSREFX.isValidCommand()) - read.establishMinDistanceFromStart(lastSREFX.getStart(), - config.memSpec->tXSDLL_old); -} - -sc_time ReadChecker::readToRead(ScheduledCommand &firstRead, - ScheduledCommand &secondRead) -{ - sc_assert(firstRead.getCommand() == Command::RD - || firstRead.getCommand() == Command::RDA); - sc_assert(secondRead.getCommand() == Command::RD - || secondRead.getCommand() == Command::RDA); - - MemSpec *config = Configuration::getInstance().memSpec; - sc_time tCCD = (firstRead.getBankGroup() == secondRead.getBankGroup()) ? - config->tCCD_L_old : config->tCCD_S_old; - // TODO: When is tCCD smaller than readAccessTime? - return max(tCCD, config->getReadAccessTime()); -} - -sc_time ReadChecker::writeToRead(ScheduledCommand &write, - ScheduledCommand &read) -{ - sc_assert(read.getCommand() == Command::RD - || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR - || write.getCommand() == Command::WRA); - - MemSpec *config = Configuration::getInstance().memSpec; - sc_time tWTR = (write.getBankGroup() == read.getBankGroup()) ? config->tWTR_L_old : - config->tWTR_S_old; - return config->tWL + config->getWriteAccessTime() + tWTR; -} - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h deleted file mode 100644 index d9c9cce8..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef READCHECKER_H -#define READCHECKER_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class ReadChecker: public ICommandChecker -{ -public: - ReadChecker(Configuration &config, ControllerState &state) : config(config), - state(state) {} - virtual ~ReadChecker() {} - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; - - static sc_time readToRead(ScheduledCommand &firstRead, - ScheduledCommand &secondRead); - static sc_time writeToRead(ScheduledCommand &write, ScheduledCommand &read); - -private: - const Configuration &config; - ControllerState &state; - - void delayToSatisfyDLL(ScheduledCommand &read) const; - bool collidesOnDataStrobe(ScheduledCommand &read) const; - bool collidesWithStrobeCommand(ScheduledCommand &read, - ScheduledCommand &strobeCommand) const; -}; - -#endif // READCHECKER_H - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp deleted file mode 100644 index 48b45eeb..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.cpp +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - * Felipe S. Prado - */ - -#include "RefreshChecker.h" -#include "../../timingCalculations.h" - -void RefreshChecker::delayToSatisfyConstraints(ScheduledCommand &command) const -{ - sc_assert(command.getCommand() == Command::REFA); - - if (config.BankwiseLogic) { - ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand( - command.getBank()); - - if (lastCommandOnBank.isValidCommand()) { - if (lastCommandOnBank.getCommand() == Command::PRE - || lastCommandOnBank.getCommand() == Command::PREA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::RDA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::WRA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP_old); - } else if (lastCommandOnBank.getCommand() == Command::PDXP - || lastCommandOnBank.getCommand() == Command::PDXA) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tXP); - } else if (lastCommandOnBank.getCommand() == Command::SREFEX) { - command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), - config.memSpec->tXS); - } else if (lastCommandOnBank.getCommand() == Command::REFA) { - } else - reportFatal("Refresh Checker", - "REFA can not follow " + commandToString(lastCommandOnBank.getCommand())); - } - } else { - for (unsigned int bank = 0; bank < config.memSpec->NumberOfBanks; ++bank) { - ScheduledCommand lastCommand = state.getLastScheduledCommand(Bank(bank)); - if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::PRE - || lastCommand.getCommand() == Command::PREA - || lastCommand.getCommand() == Command::PREB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::ACT - || lastCommand.getCommand() == Command::ACTB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::RDA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRTP + config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::WRA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tWL + config.memSpec->getWriteAccessTime() + config.memSpec->tWR + - config.memSpec->tRP_old); - } else if (lastCommand.getCommand() == Command::PDXA - || lastCommand.getCommand() == Command::PDXP) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXP); - } else if (lastCommand.getCommand() == Command::SREFEX) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXS); - } else if (lastCommand.getCommand() == Command::REFA) { - } else - reportFatal("Refresh Checker", - "Refresh can not follow " + commandToString(lastCommand.getCommand())); - } - } - } - - state.bus.moveCommandToNextFreeSlot(command); - - -} - - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h deleted file mode 100644 index ae7a4c9e..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/RefreshChecker.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef REFRESHCHECKER_H -#define REFRESHCHECKER_H - -#include "ICommandChecker.h" -#include "../../../ControllerState.h" -#include "../../configuration/Configuration.h" -#include - -class RefreshChecker : public ICommandChecker -{ -public: - RefreshChecker(const Configuration &config, ControllerState &state) : - config(config), state(state) - { - } - virtual ~RefreshChecker() - { - } - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; - -private: - const Configuration &config; - ControllerState &state; - -}; - - -#endif // REFRESHCHECKER_H diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp deleted file mode 100644 index df8fc8ed..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#include "WriteChecker.h" -#include "../../timingCalculations.h" -#include "../../../../common/utils.h" -#include "ReadChecker.h" - -using namespace std; - -void WriteChecker::delayToSatisfyConstraints(ScheduledCommand &command) const -{ - sc_assert(command.getCommand() == Command::WR - || command.getCommand() == Command::WRA); - - ScheduledCommand lastCommand = state.getLastScheduledCommand(command.getBank()); - - if (lastCommand.isValidCommand()) { - if (lastCommand.getCommand() == Command::ACT - || lastCommand.getCommand() == Command::ACTB) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tRCD); - } else if (lastCommand.getCommand() == Command::RD) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - WriteChecker::readToWrite(lastCommand, command)); - } else if (lastCommand.getCommand() == Command::WR) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - WriteChecker::writeToWrite(lastCommand, command)); - } else if (/*lastCommand.getCommand() == Command::PDXP - || */lastCommand.getCommand() == Command::PDXA) { - command.establishMinDistanceFromStart(lastCommand.getStart(), - config.memSpec->tXP); - } else - reportFatal("Write Checker", - "WR/WRA can not follow " + commandToString(lastCommand.getCommand())); - } - - while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe(command)) { - command.delayStart(config.memSpec->clk); - } -} - -bool WriteChecker::collidesOnDataStrobe(ScheduledCommand &write) const -{ -// for (ScheduledCommand &strobeCommand : state.lastDataStrobeCommands) { -// if (collidesWithStrobeCommand(write, strobeCommand)) -// return true; -// } - - return false; -} - -bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const -{ - if (strobeCommand.getCommand() == Command::WR - || strobeCommand.getCommand() == Command::WRA) { - return getDistance(write.getStart(), - strobeCommand.getStart()) < WriteChecker::writeToWrite(strobeCommand, write); - } else if (strobeCommand.getCommand() == Command::RD - || strobeCommand.getCommand() == Command::RDA) { - if (strobeCommand.getStart() >= write.getStart()) - return getDistance(write.getStart(), - strobeCommand.getStart()) < ReadChecker::writeToRead(write, strobeCommand); - else - return getDistance(strobeCommand.getStart(), - write.getStart()) < WriteChecker::readToWrite(strobeCommand, write); - } else { - reportFatal("Write Checker", - "Invalid strobeCommand in data strobe commands " + commandToString( - strobeCommand.getCommand())); - return true; - } -} - -sc_time WriteChecker::writeToWrite(ScheduledCommand &firstWrite, - ScheduledCommand &secondWrite) -{ - sc_assert(firstWrite.getCommand() == Command::WR - || firstWrite.getCommand() == Command::WRA); - sc_assert(secondWrite.getCommand() == Command::WR - || secondWrite.getCommand() == Command::WRA); - - MemSpec *config = Configuration::getInstance().memSpec; - sc_time tCCD = (firstWrite.getBankGroup() == secondWrite.getBankGroup()) ? - config->tCCD_L_old : config->tCCD_S_old; - // TODO: When is tCCD smaller than writeAccessTime? - return max(tCCD, config->getWriteAccessTime()); -} - -sc_time WriteChecker::readToWrite(ScheduledCommand &read __attribute__(( - unused)), ScheduledCommand &write __attribute__((unused))) -{ - sc_assert(read.getCommand() == Command::RD - || read.getCommand() == Command::RDA); - sc_assert(write.getCommand() == Command::WR - || write.getCommand() == Command::WRA); - - MemSpec *config = Configuration::getInstance().memSpec; - return config->tRL + config->getReadAccessTime() - config->tWL + config->clk * 2; -} - diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h b/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h deleted file mode 100644 index 4bddeb69..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/checker/WriteChecker.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef WRITECHECKER_H -#define WRITECHECKER_H - -#include "ICommandChecker.h" -#include "../../configuration/Configuration.h" -#include "../../../ControllerState.h" - -class WriteChecker : public ICommandChecker -{ -public: - WriteChecker(const Configuration &config, - ControllerState &state) : config(config), state(state) {} - virtual ~WriteChecker() {} - - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; - - static sc_time writeToWrite(ScheduledCommand &firstWrite, - ScheduledCommand &secondWrite); - static sc_time readToWrite(ScheduledCommand &read, ScheduledCommand &write); -private: - bool collidesOnDataStrobe(ScheduledCommand &write) const; - bool collidesWithStrobeCommand(ScheduledCommand &write, - ScheduledCommand &strobeCommand) const; - const Configuration &config; - ControllerState &state; -}; - - -#endif // WRITECHECKER_H diff --git a/DRAMSys/library/src/controller/core/timingCalculations.cpp b/DRAMSys/library/src/controller/core/timingCalculations.cpp index 2585ea4a..2fe9551a 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.cpp +++ b/DRAMSys/library/src/controller/core/timingCalculations.cpp @@ -36,13 +36,10 @@ #include "timingCalculations.h" #include "configuration/MemSpec.h" -#include "ControllerCore.h" #include "../../common/DebugManager.h" #include "configuration/Configuration.h" #include "../../common/utils.h" - - sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint) { diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index e2890c02..6878413b 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -35,12 +35,11 @@ #include "RefreshManager.h" #include "../../common/dramExtensions.h" #include "../core/configuration/Configuration.h" +#include "../../common/utils.h" RefreshManager::RefreshManager() { - // TODO: Change time of generation? - refreshPayload.set_extension(new GenerationExtension(SC_ZERO_TIME)); - refreshPayload.set_extension(new DramExtension()); + setUpDummy(refreshPayload); memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.cpp b/DRAMSys/library/src/controller/scheduler/Fifo.cpp deleted file mode 100644 index b3cc5689..00000000 --- a/DRAMSys/library/src/controller/scheduler/Fifo.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#include "Fifo.h" - -void Fifo::storeRequest(gp *payload) -{ - Bank bank = DramExtension::getExtension(payload).getBank(); - buffer[bank].emplace_back(payload); -} - -std::pair Fifo::getNextRequest(Bank bank) -{ - if (!buffer[bank].empty()) - { - gp *payload = buffer[bank].front(); - Command command = IScheduler::getNextCommand(payload); - if (command == Command::RD || command == Command::RDA - || command == Command::WR || command == Command::WRA) - { - buffer[bank].pop_front(); - } - - return std::pair(command, payload); - } - else - { - return std::pair(Command::NOP, NULL); - } -} - -gp *Fifo::getPendingRequest(Bank /*bank*/) -{ - return NULL; -} - - diff --git a/DRAMSys/library/src/controller/scheduler/Fifo.h b/DRAMSys/library/src/controller/scheduler/Fifo.h deleted file mode 100644 index 83f14124..00000000 --- a/DRAMSys/library/src/controller/scheduler/Fifo.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef FIFO_H -#define FIFO_H - -#include -#include -#include - -#include "../core/ControllerCore.h" -#include "../Command.h" -#include "IScheduler.h" - -class Fifo : public IScheduler -{ -public: - Fifo(ControllerCore &controllerCore) : IScheduler(controllerCore) {} - virtual ~Fifo() {} - - void storeRequest(gp *payload) override; - std::pair - getNextRequest(Bank bank) override; - virtual gp *getPendingRequest(Bank bank) override; - -private: - std::map> buffer; -}; - -#endif // FIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp deleted file mode 100644 index caebc826..00000000 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.cpp +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - * Éder F. Zulian - */ - -#include "FifoStrict.h" - -void FifoStrict::storeRequest(tlm::tlm_generic_payload *payload) -{ - Bank bank = DramExtension::getExtension(payload).getBank(); - buffer.push_back(std::pair(bank, payload)); -} - -std::pair FifoStrict::getNextRequest( - Bank bank) -{ - if (!buffer.empty()) { - - if (buffer.front().first == bank) { - // The next request in the FIFO is for the bank passed as parameter - - tlm::tlm_generic_payload *payload = buffer.front().second; - - // For a given request (a given payload) one or more commands will - // be sent to the DRAM in order to process it. - // - // getNextRequest() may be called more than once for the same - // enqueued request until the appropriate sequence of commands is - // sent to the DRAM. - // - // Every time getNextRequest() is called it calls - // getNextCommand() that returns the suitable command to be sent - // to the DRAM. - // - // getNextCommand() returns the proper command based on the - // internal status of the DRAM. - // - // In the worst case getNextCommand() needs to be called three - // times for a given element in the requests queue: first for - // precharge, second for activate and finally for read or write - // (accordingly the nature of the request). In contrast, for the - // case of an already open row (due to a previous request) the - // command itself could be directly issued. - // - Command command = IScheduler::getNextCommand(payload); - - if (commandIsIn(command, {Command::RD, Command::WR, Command::RDA, Command::WRA})) { - buffer.pop_front(); - - // Check if the next transaction is a blocked read or write - - if (!buffer.empty()) { - tlm::tlm_generic_payload *p = buffer.front().second; - Command cmd = IScheduler::getNextCommand(p); - if (commandIsIn(cmd, {Command::RD, Command::WR, Command::RDA, Command::WRA})) { - Bank b = DramExtension::getBank(p); - controller.blockedRequests.push(b); - } - } - } - - return std::pair(command, payload); - - } else { - // The next request in the FIFO is NOT for the bank passed as parameter. - - // Search for the next request related to the bank passed as parameter. - for (auto req = buffer.begin(); req != buffer.end(); req++) { - if (req->first == bank) { - // Found a request to this bank in the queue - tlm::tlm_generic_payload *payload = req->second; - - // Get the appropriate command to be sent to the DRAM - // regarding this request. - // - // Commands other than read and write will be issued. - // Reads and writes will not be issued since this - // scheduler executes all read and writes in a strict - // order. - Command command = getNextCommand(payload); - if (commandIsIn(command, {Command::RD, Command::WR, Command::RDA, Command::WRA})) { - // Reads and writes must be executed in order. Then if - // the next command for this request is read or write - // NOP will be returned and no operation will be - // performed. - return std::pair(Command::NOP, NULL); - } - else { - // Commands other than read and write are issued normally. - return std::pair(command, payload); - } - } - } - } - } - - return std::pair(Command::NOP, NULL); -} - -gp *FifoStrict::getPendingRequest(Bank /*bank*/) -{ - return NULL; -} diff --git a/DRAMSys/library/src/controller/scheduler/FifoStrict.h b/DRAMSys/library/src/controller/scheduler/FifoStrict.h deleted file mode 100644 index 5404cb8c..00000000 --- a/DRAMSys/library/src/controller/scheduler/FifoStrict.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - * Éder F. Zulian - */ - -#ifndef FIFOSTRICT_H -#define FIFOSTRICT_H - -#include -//#include -#include - -#include "../core/ControllerCore.h" -#include "../Command.h" -#include "IScheduler.h" - -class FifoStrict : public IScheduler -{ -public: - IController &controller; - FifoStrict(IController &controller, ControllerCore &controllerCore) - : IScheduler(controllerCore), controller(controller) {} - - virtual ~FifoStrict() {} - - void storeRequest(gp *payload) override; - std::pair - getNextRequest(Bank bank) override; - virtual gp *getPendingRequest(Bank bank) override; - -private: - std::deque> buffer; -}; - -#endif // FIFOSTRICT_H - diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp deleted file mode 100644 index daec88c0..00000000 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.cpp +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -//#include "FrFcfs.h" -//#include "../../common/dramExtensions.h" -//#include "../core/configuration/Configuration.h" -//#include - -//using namespace std; - -//// The FrFcfs (First Ready First Come First Served) is descibed in a 2000 paper from Rixner et al.: -//// Memory Access Scheduling -//// -//// The FrFcfs scheduler features for each bank in the DRAM a specific -//// scheduling buffer for example: -//// -//// Bank0: OOOOOOOO -//// Bank1: OOXXXXXX -//// ... ^ ^ -//// ... | | -//// ... back | -//// ... front -//// ... -//// Bank6: OOOOO0XX -//// Bank7: XXXXXXXX - -//void FrFcfs::storeRequest(gp *payload) -//{ -// // FIXME: Question: what if the buffer is full? IMHO the schedule function -// // should provide a true or false when the placement into the buffer worked -// // out or not (?). -// buffer[DramExtension::getExtension(payload).getBank()] -// .emplace_back(payload); -//} - -//std::pair FrFcfs::getNextRequest(Bank bank) -//{ -// // If the bank is empty like Bank0 in the example we do nothing -// if (buffer[bank].empty()) -// return std::pair(Command::NOP, NULL); - -// // In FrFcfs row hits have always the highest priority, therefore we search -// // for row hits. If we find a row hit, we remove the transaction from the -// // queue and send it to the DRAM. -// std::deque::iterator it = findRowHit(bank); -// if (it != buffer[bank].end()) -// { -// gp *payload = *it; -// buffer[bank].erase(it); -// return std::pair(getReadWriteCommand(payload), payload); -// } - -// // If there is no row hit, the FrFcfs takes always the oldest transaction -// // in the buffer, i.e. the transaction in the front. -// return std::pair(getNextCommand(buffer[bank].front()), -// buffer[bank].front()); -//} - -//// This function searches for a row hit in the scheduling queue of the specific -//// bank. If no row hit is found the end of the queue is returned. -//// -//// Note: end() Returns an iterator referring to the past-the-end element in the -//// deque container. The past-the-end element is the theoretical element that -//// would follow the last element in the deque container. It does not point to -//// any element, and thus shall not be dereferenced. -//std::deque::iterator FrFcfs::findRowHit(Bank bank) -//{ -// std::deque &queue = buffer[bank]; -// Row activeRow = controllerCore.getRowBufferStates().getRowInRowBuffer(bank); - -// if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) -// return queue.end(); - -// // Traverse the scheduling queue of the specific bank: -// for (auto it = queue.begin(); it != queue.end(); it++) -// { -// //Found row-hit and return the according iterator -// if (DramExtension::getRow(*it) == activeRow) -// return it; -// } - -// return queue.end(); -//} - -//gp *FrFcfs::getPendingRequest(Bank /*bank*/) -//{ -// return NULL; -//} diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfs.h b/DRAMSys/library/src/controller/scheduler/FrFcfs.h deleted file mode 100644 index b3fa643b..00000000 --- a/DRAMSys/library/src/controller/scheduler/FrFcfs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef FRFCFS_H -#define FRFCFS_H - -#include "IScheduler.h" -#include "../core/ControllerCore.h" -#include -#include -#include - -class FrFcfs : public IScheduler -{ -public: - FrFcfs(ControllerCore &controllerCore) : IScheduler(controllerCore) {} - virtual ~FrFcfs() {} - - void storeRequest(gp *payload) override; - std::pair - getNextRequest(Bank bank) override; - virtual gp *getPendingRequest(Bank bank) override; - -protected: - std::map> buffer; - std::deque::iterator findRowHit(Bank bank); - -private: - -}; - -#endif // FRFCFS_H diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp deleted file mode 100644 index 29da4399..00000000 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.cpp +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -//#include "FrFcfsGrp.h" - -//// The FrFcfsGrp (First Ready First Come First Served Grouper) works exactly -//// like the FrFcfsRp (First Ready First Come First Served Read Priority). -//// However writes are grouped! For detailed documentation look into the FrFcfs. -//// TODO: what is missed is a check if the buffers are full. This will only work -//// if we have buffers with a fixed size (Prado's future patch). - -//std::pair FrFcfsGrp::getNextRequest(Bank bank) -//{ -// // If the bank is empty we do nothing: -// if (buffer[bank].empty()) { -// return pair(Command::NOP, NULL); -// } - -// // If we are in write mode we should check if we should switch to read mode -// // because there are no writes anymore in the buffer. -// if (readMode == false) { -// if (getNumberOfRequest(tlm::TLM_WRITE_COMMAND) == 0) { -// readMode = true; -// } -// } else { // If we are in read mode but all reads are served we switch to write -// if (getNumberOfRequest(tlm::TLM_READ_COMMAND) == 0) { -// readMode = false; -// } -// } - -// // Now lets search for read and write commands. However keep in mind that -// // readMode is a shared variable for all the banks! -// if (readMode == true) { -// // 1. Seach for read hit: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *read = *it; - -// if (read->get_command() == tlm::TLM_READ_COMMAND) { -// // If there is a row hit: -// if (DramExtension::getRow(read) -// == controllerCore.getRowBufferStates() -// .getRowInRowBuffer(bank)) { -// if (hazardDetection(bank, it) == false) { -// buffer[bank].erase(it); -// printDebugMessage("Read Hit found"); -// return pair(getReadWriteCommand(read), -// read); -// } else { -// // If there was a hazard, switch the mode and try again: -// readMode = false; -// return getNextRequest(bank); -// } -// } -// } -// } - -// // 2. Search for read miss: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *read = *it; - -// if (read->get_command() == tlm::TLM_READ_COMMAND) { -// if (hazardDetection(bank, it) == false) { -// printDebugMessage("Read miss found"); -// return pair(getNextCommand(read), read); -// } else { -// // If there was a hazard, switch the mode and try again: -// readMode = false; -// return getNextRequest(bank); -// } -// } -// } -// } else { // write mode: -// // 3. Search for write hit: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *write = *it; - -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// // If there is a row hit: -// if (DramExtension::getRow(write) -// == controllerCore.getRowBufferStates() -// .getRowInRowBuffer(bank)) { -// buffer[bank].erase(it); -// printDebugMessage("Write Hit found"); -// return pair(getReadWriteCommand(write), -// write); -// } -// } -// } - -// // 4. Search for write miss: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *write = *it; - -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// printDebugMessage("Write miss found"); -// return pair(getNextCommand(write), write); -// } -// } -// } - -// // If nothing was found we check the other banks before we switch the mode: -// pair other(Command::NOP, NULL); -// unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; - -// for (unsigned int i = 1; i < B; i++) { -// Bank nextBank((bank.ID() + i) % B); -// ctrl->scheduleNextFromScheduler(nextBank); -// } - -// // If nothing was found in the current mode, switch the mode and try again: -// // FIXME: this is in my opinion not so clever yet, because we switch maybe -// // even though there are still reads/writes request on other banks ... -// readMode = !readMode; -// return getNextRequest(bank); - -// reportFatal("FrFcfsGrp", "Never should go here ..."); -//} - -//// There is a hazard if a read is found which will be scheduled before a write -//// to the same column and the same row of the same bank: -//bool FrFcfsGrp::hazardDetection(Bank bank, std::deque::iterator ext) -//{ -// gp *read = *ext; - -// //for(unsigned long i=0; i < id; i++) -// for (auto it = buffer[bank].begin(); it != ext; it++) { -// gp *write = *it; -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// if ((DramExtension::getExtension(read).getColumn() -// == DramExtension::getExtension(write).getColumn()) -// && (DramExtension::getExtension(read).getRow() -// == DramExtension::getExtension(write).getRow())) { -// printDebugMessage("Hazard Detected"); -// return true; -// } -// } -// } -// return false; -//} - -//// Estimate the number of writes/reads in all bank buffers: -//unsigned int FrFcfsGrp::getNumberOfRequest(tlm::tlm_command cmd) -//{ -// unsigned int numberOfRequests = 0; -// for (unsigned int i = 0; -// i < Configuration::getInstance().memSpec->NumberOfBanks; -// i++) { -// for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { -// gp *trans = *it; -// if (trans->get_command() == cmd) { -// numberOfRequests++; -// } -// } -// } - -// return numberOfRequests; -//} - -//void FrFcfsGrp::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); -//} diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h b/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h deleted file mode 100644 index ffcf0b5a..00000000 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsGrp.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -#ifndef FRFCFSGRP_H -#define FRFCFSGRP_H - -#include "FrFcfs.h" -#include "../Controller.h" - -class Controller; - -class FrFcfsGrp : public FrFcfs -{ -public: - FrFcfsGrp(ControllerCore &controllerCore, Controller *c) - : FrFcfs(controllerCore), ctrl(c), readMode(true) {} - - std::pair - getNextRequest(Bank bank) override; - -private: - Controller *ctrl; - bool hazardDetection(Bank bank, std::deque::iterator ext); - unsigned int getNumberOfRequest(tlm::tlm_command cmd); - void printDebugMessage(std::string message); - bool readMode; -}; - -#endif // FRFCFSGRP_H diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp deleted file mode 100644 index cdfa5fee..00000000 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsRp.cpp +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -//#include "FrFcfsRp.h" - -//// The FrFcfsRp (First Ready First Come First Served Read Priority) works -//// exactly like the FrFcfs but reads are prioratized over writes. -//// For detailed documentation look into the FrFcfs. - -//std::pair FrFcfsRp::getNextRequest(Bank bank) -//{ -// // If the bank is empty like Bank0 in the example we do nothing: -// if (buffer[bank].empty()) { -// return pair(Command::NOP, NULL); -// } - -// // Order of Priority: -// // 1. Read Hits (Hazard Check) -// // 2. Write Hits -// // 3. Read Miss (Hazard Check) -// // 4. Write Miss - -// // 1. Seach for read hit: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *read = *it; - -// if (read->get_command() == tlm::TLM_READ_COMMAND) { -// // If there is a row hit: -// if (DramExtension::getRow(read) -// == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { -// if (hazardDetection(bank, it) == false) { -// buffer[bank].erase(it); -// printDebugMessage("Read Hit found"); -// return pair(getReadWriteCommand(read), read); -// } -// } -// } -// } - -// // 2. Search for write hit: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *write = *it; - -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// // If there is a row hit: -// if (DramExtension::getRow(write) -// == controllerCore.getRowBufferStates().getRowInRowBuffer(bank)) { -// buffer[bank].erase(it); -// printDebugMessage("Write Hit found"); -// return pair(getReadWriteCommand(write), write); -// } -// } -// } - -// // For now return the oldest request but prefere also reads before writes: - -// // 3. Search for read miss: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *read = *it; - -// if (read->get_command() == tlm::TLM_READ_COMMAND) { -// if (hazardDetection(bank, it) == false) { -// printDebugMessage("Read miss found"); -// return pair(getNextCommand(read), read); -// } -// } -// } - -// // 3. Search for write miss: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *write = *it; - -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// printDebugMessage("Write miss found"); -// return pair(getNextCommand(write), write); -// } -// } - -// reportFatal("FrFcfsRp", "Never should go here ..."); -// return pair(Command::NOP, NULL); -//} - -//// There is a hazard if a read is found which will be scheduled before a write -//// to the same column and the same row of the same bank: -//bool FrFcfsRp::hazardDetection(Bank bank, std::deque::iterator ext) -//{ -// gp *read = *ext; - -// //for(unsigned long i=0; i < id; i++) -// for (auto it = buffer[bank].begin(); it != ext; it++) { -// gp *write = *it; -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// if ((DramExtension::getExtension(read).getColumn() -// == DramExtension::getExtension(write).getColumn()) -// && (DramExtension::getExtension(read).getRow() -// == DramExtension::getExtension(write).getRow())) { -// printDebugMessage("Hazard Detected"); -// return true; -// } -// } -// } -// return false; -//} - -//void FrFcfsRp::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage("FrFcfsRp", message); -//} diff --git a/DRAMSys/library/src/controller/scheduler/FrFcfsRp.h b/DRAMSys/library/src/controller/scheduler/FrFcfsRp.h deleted file mode 100644 index c1c10ca4..00000000 --- a/DRAMSys/library/src/controller/scheduler/FrFcfsRp.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2017, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -#ifndef FRFCFSRP_H -#define FRFCFSRP_H - -#include "FrFcfs.h" - -class FrFcfsRp : public FrFcfs -{ -public: - FrFcfsRp(ControllerCore &controllerCore) : FrFcfs(controllerCore) {} - std::pair - getNextRequest(Bank bank) override; - -private: - bool hazardDetection(Bank bank, std::deque::iterator ext); - void printDebugMessage(std::string message); -}; - -#endif // FRFCFSRP_H diff --git a/DRAMSys/library/src/controller/scheduler/Grp.cpp b/DRAMSys/library/src/controller/scheduler/Grp.cpp deleted file mode 100644 index 9a920ae7..00000000 --- a/DRAMSys/library/src/controller/scheduler/Grp.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2018, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -//#include "Grp.h" - -//// Grp (Grouper) just reorders w.r.t. read write grouping, however is not aware of the -//// row buffer. For a row buffer aware grouper refer to FrFcfsGrp. -//// TODO: what is missed is a check if the buffers are full. This will only work -//// if we have buffers with a fixed size (Prado's future patch). - -//std::pair Grp::getNextRequest(Bank bank) -//{ -// // If the bank is empty we do nothing: -// if (buffer[bank].empty()) { -// return pair(Command::NOP, NULL); -// } - -// // If we are in write mode we should check if we should switch to read mode -// // because there are no writes anymore in the buffer. -// if (readMode == false) { -// if (getNumberOfRequest(tlm::TLM_WRITE_COMMAND) == 0) { -// readMode = true; -// } -// } else { // If we are in read mode but all reads are served we switch to write -// if (getNumberOfRequest(tlm::TLM_READ_COMMAND) == 0) { -// readMode = false; -// } -// } - -// // Now lets search for read and write commands. However keep in mind that -// // readMode is a shared variable for all the banks! -// if (readMode == true) { -// // 1. Seach for read hit: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *read = *it; - -// if (read->get_command() == tlm::TLM_READ_COMMAND) { -// // If there is a row hit: -// if (DramExtension::getRow(read) -// == controllerCore.getRowBufferStates() -// .getRowInRowBuffer(bank)) { -// if (hazardDetection(bank, it) == false) { -// buffer[bank].erase(it); -// printDebugMessage("Read Hit found"); -// return pair(getReadWriteCommand(read), -// read); -// } else { -// // If there was a hazard, switch the mode and try again: -// readMode = false; -// return getNextRequest(bank); -// } -// } else { // if there is a row miss: -// if (hazardDetection(bank, it) == false) { -// printDebugMessage("Read miss found"); -// return pair(getNextCommand(read), read); -// } else { -// // If there was a hazard, switch the mode and try again: -// readMode = false; -// return getNextRequest(bank); -// } -// } -// } -// } - -// } else { // write mode: -// // 3. Search for write hit: -// for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) { -// gp *write = *it; - -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// // If there is a row hit: -// if (DramExtension::getRow(write) -// == controllerCore.getRowBufferStates() -// .getRowInRowBuffer(bank)) { -// buffer[bank].erase(it); -// printDebugMessage("Write Hit found"); -// return pair(getReadWriteCommand(write), -// write); -// } else { -// printDebugMessage("Write miss found"); -// return pair(getNextCommand(write), write); -// } -// } -// } -// } - -// // If nothing was found we check the other banks before we switch the mode: -// pair other(Command::NOP, NULL); -// unsigned int B = Configuration::getInstance().memSpec->NumberOfBanks; - -// for (unsigned int i = 1; i < B; i++) { -// Bank nextBank((bank.ID() + i) % B); -// ctrl->scheduleNextFromScheduler(nextBank); -// } - -// // If nothing was found in the current mode, switch the mode and try again: -// // FIXME: this is in my opinion not so clever yet, because we switch maybe -// // even though there are still reads/writes request on other banks ... -// readMode = !readMode; -// return getNextRequest(bank); - -// reportFatal("Grp", "Never should go here ..."); -//} - -//// There is a hazard if a read is found which will be scheduled before a write -//// to the same column and the same row of the same bank: -//bool Grp::hazardDetection(Bank bank, std::deque::iterator ext) -//{ -// gp *read = *ext; - -// //for(unsigned long i=0; i < id; i++) -// for (auto it = buffer[bank].begin(); it != ext; it++) { -// gp *write = *it; -// if (write->get_command() == tlm::TLM_WRITE_COMMAND) { -// if ((DramExtension::getExtension(read).getColumn() -// == DramExtension::getExtension(write).getColumn()) -// && (DramExtension::getExtension(read).getRow() -// == DramExtension::getExtension(write).getRow())) { -// printDebugMessage("Hazard Detected"); -// return true; -// } -// } -// } -// return false; -//} - -//// Estimate the number of writes/reads in all bank buffers: -//unsigned int Grp::getNumberOfRequest(tlm::tlm_command cmd) -//{ -// unsigned int numberOfRequests = 0; -// for (unsigned int i = 0; -// i < Configuration::getInstance().memSpec->NumberOfBanks; -// i++) { -// for (auto it = buffer[i].begin(); it != buffer[i].end(); it++) { -// gp *trans = *it; -// if (trans->get_command() == cmd) { -// numberOfRequests++; -// } -// } -// } - -// return numberOfRequests; -//} - -//void Grp::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage("FrFcfsGrp", message); -//} diff --git a/DRAMSys/library/src/controller/scheduler/Grp.h b/DRAMSys/library/src/controller/scheduler/Grp.h deleted file mode 100644 index 13ccea71..00000000 --- a/DRAMSys/library/src/controller/scheduler/Grp.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2018, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Matthias Jung - */ - -#ifndef GRP_H -#define GRP_H - -#include "FrFcfs.h" -#include "../Controller.h" - -class Controller; - -class Grp : public FrFcfs -{ -public: - Grp(ControllerCore &controllerCore, Controller *c) - : FrFcfs(controllerCore), ctrl(c), readMode(true) {} - - std::pair - getNextRequest(Bank bank) override; - -private: - Controller *ctrl; - bool hazardDetection(Bank bank, std::deque::iterator ext); - unsigned int getNumberOfRequest(tlm::tlm_command cmd); - void printDebugMessage(std::string message); - bool readMode; -}; - -#endif // GRP_H diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp b/DRAMSys/library/src/controller/scheduler/IScheduler.cpp deleted file mode 100644 index 47f3ccdc..00000000 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.cpp +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -//#include "IScheduler.h" -//#include "../../common/DebugManager.h" -//#include "../core/configuration/Configuration.h" - -//std::string IScheduler::sendername = "scheduler"; - -//void IScheduler::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage(IScheduler::sendername, message); -//} - -//// Get the next command that is necessary to process the request representend by the payload -//Command IScheduler::getNextCommand(gp &payload) -//{ -// Bank bank = DramExtension::getBank(payload); -// if (!controllerCore.getRowBufferStates().rowBufferIsOpen(bank)) -// { -// return Command::ACT; -// } -// else if (controllerCore.getRowBufferStates().rowBufferIsOpen(bank) && -// controllerCore.getRowBufferStates().getRowInRowBuffer(bank) != -// DramExtension::getRow(payload)) -// { -// return Command::PRE; -// } -// else -// { -// return getReadWriteCommand(payload); -// } -//} - -//Command IScheduler::getNextCommand(gp *payload) -//{ -// return getNextCommand(*payload); -//} - -//Command IScheduler::getReadWriteCommand(gp &payload) -//{ -// if (payload.get_command() == tlm::TLM_READ_COMMAND) -// { -// if (Configuration::getInstance().OpenPagePolicy) -// return Command::RD; -// else -// return Command::RDA; -// } -// else -// { -// if (Configuration::getInstance().OpenPagePolicy) -// return Command::WR; -// else -// return Command::WRA; -// } -//} - -//Command IScheduler::getReadWriteCommand(gp *payload) -//{ -// return getReadWriteCommand(*payload); -//} - diff --git a/DRAMSys/library/src/controller/scheduler/IScheduler.h b/DRAMSys/library/src/controller/scheduler/IScheduler.h deleted file mode 100644 index b40f29ec..00000000 --- a/DRAMSys/library/src/controller/scheduler/IScheduler.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Robert Gernhardt - * Matthias Jung - */ - -#ifndef ISCHEDULER_H -#define ISCHEDULER_H - -#include -#include "../../common/dramExtensions.h" -#include "../Command.h" -#include "../core/ControllerCore.h" - -typedef tlm::tlm_generic_payload gp; - -class IScheduler -{ -public: - virtual ~IScheduler() {} - IScheduler(ControllerCore &controllerCore) : controllerCore(controllerCore) {} - - virtual void storeRequest(gp *payload) = 0; - virtual std::pair getNextRequest(Bank bank) = 0; - virtual gp *getPendingRequest(Bank bank) = 0; - static std::string sendername; - -protected: - void printDebugMessage(std::string message); - Command getNextCommand(gp &payload); - Command getNextCommand(gp *payload); - - Command getReadWriteCommand(gp &payload); - Command getReadWriteCommand(gp *payload); - - ControllerCore &controllerCore; -}; - -#endif // ISCHEDULER_H diff --git a/DRAMSys/library/src/controller/scheduler/SMS.cpp b/DRAMSys/library/src/controller/scheduler/SMS.cpp deleted file mode 100644 index 80fe5c43..00000000 --- a/DRAMSys/library/src/controller/scheduler/SMS.cpp +++ /dev/null @@ -1,358 +0,0 @@ -#include "SMS.h" -#include - -using namespace std; - -void SMS::storeRequest(gp *payload) -{ - Thread thread = DramExtension::getExtension(payload).getThread(); - bool wasEmpty = isRequestBuffersEmpty(); - - requestBuffers[thread].emplace_back(payload); - - if (inFlightMemRequestCounter.find(thread) == inFlightMemRequestCounter.end()) { - inFlightMemRequestCounter[thread] = 0; - cacheMisses[thread] = 0; - } - inFlightMemRequestCounter[thread]++; - cacheMisses[thread]++; - - if (wasEmpty) { - newRequest.notify(SC_ZERO_TIME); - } -} - -std::pair SMS::getNextRequest(Bank bank) -{ - if (bankBuffers[bank].empty()) { - debugManager.printDebugMessage(name(), - "Get next request on bank " + to_string(bank.ID()) + " : EMPTY buffer"); - return pair(Command::NOP, NULL); - } else { - gp *payload = bankBuffers[bank].front(); - Command command = IScheduler::getNextCommand(payload); - if (command == Command::RD || command == Command::RDA - || command == Command::WR - || command == Command::WRA) { - inFlightMemRequestCounter[DramExtension::getExtension(payload).getThread()]--; - bankBuffers[bank].pop_front(); - } - - debugManager.printDebugMessage(name(), - "Get next request on bank " + to_string(bank.ID())); - return pair(command, payload); - } -} - -void SMS::batchScheduler() -{ - sc_time memClk = Configuration::getInstance().memSpec->clk; - std::default_random_engine generator; - std::bernoulli_distribution distribution((double) SJFprobability / 100.0); - - while (true) { - updateMPKCs(memClk); - if (isRequestBuffersEmpty()) { - wait(newRequest); - } else { - multiBatchFormation(memClk); - if (existReadyBatches()) { - if (!isSystemLightlyLoaded() && (existLowIntensityThread() - || distribution(generator))) { - pickSJF(); - } else { - pickRR(); - } - drainOnePayloadFromReadybatch(memClk); - } else { - wait(memClk); - } - } - } -} - -/** - * Pick a Thread according to Shortest-Job Policy - * Save the picked one into lastSelectedThread - * @return true if it can, otherwise false - */ -bool SMS::pickSJF() -{ - // find threads with ready batches - std::vector threadsWithReadyBatches; - for (const auto &each : readyBatchInclusiveEndLocs) { - if (!each.second.empty()) { - // marked as thread with non-empty request buffer - threadsWithReadyBatches.push_back(each.first); - } - } - - if (!threadsWithReadyBatches.empty()) { - // pick shortest-job thread among threads with non-empty request buffer - Thread &minThread = threadsWithReadyBatches.front(); - for (const auto &thread : threadsWithReadyBatches) { - if (inFlightMemRequestCounter[thread] < inFlightMemRequestCounter[minThread]) { - minThread = thread; - } - } - - // save selected thread - lastSelectedThread = readyBatchInclusiveEndLocs.find(minThread); - debugManager.printDebugMessage(name(), - "[SJF] Select ready batch of thread " + to_string(minThread.ID())); - return true; - } else { - return false; - } -} - -/** - * Drain the picked request buffer into bank buffers - * by move request one-by-one from start of the request buffer till last parameter - * @param memClk - * @param last - */ -void SMS::drainOnePayloadFromReadybatch(const sc_time &memClk) -{ - if (lastSelectedThread->second.empty()) { - return; - } - const Thread &selectedThread = lastSelectedThread->first; - - const size_t &inclusiveEndLoc = lastSelectedThread->second.front(); - assert(inclusiveEndLoc < requestBuffers.size()); - - for (size_t i = 0; i <= inclusiveEndLoc; ++i) { - wait(memClk); - Bank bank = DramExtension::getExtension( - requestBuffers[selectedThread].front()).getBank(); - bankBuffers[bank].emplace_back(requestBuffers[selectedThread].front()); - requestBuffers[selectedThread].pop_front(); - - // decrement inclusive end locations of ready batches - // except this ready batch - for (size_t i = 1; i < readyBatchInclusiveEndLocs[selectedThread].size(); ++i) { - --readyBatchInclusiveEndLocs[selectedThread][i]; - } - - debugManager.printDebugMessage(name(), - "[SJF] Drain request in the ready batch of thread " - + to_string((*lastSelectedThread).first.ID()) + " to bankbuffer " - + to_string(bank.ID())); - } - lastSelectedThread->second.pop_front(); -} - -/** - * Pick a Thread according to Round-Robin Policy - * Save the picked one into lastSelectedThread - * @return true if it can pick one, otherwise false - */ -bool SMS::pickRR() -{ - if (lastSelectedThread == readyBatchInclusiveEndLocs.end()) { - lastSelectedThread = readyBatchInclusiveEndLocs.begin(); - if (!(*lastSelectedThread).second.empty()) { - return true; - } - } - - std::map>::iterator savedOriginalNextSelectedThread = - lastSelectedThread; - - do { - lastSelectedThread++; - if (lastSelectedThread == readyBatchInclusiveEndLocs.end()) { - lastSelectedThread = readyBatchInclusiveEndLocs.begin(); - } - if (lastSelectedThread == savedOriginalNextSelectedThread) { - return false; - } - } while ((*lastSelectedThread).second.empty()); - - debugManager.printDebugMessage(name(), - "[RR] Select ready batch of thread " + to_string(( - *lastSelectedThread).first.ID())); - return true; -} - -bool SMS::isSystemLightlyLoaded() const -{ - unsigned int totalRequest = 0; - for (const auto &bankBuffer : bankBuffers) { - totalRequest += bankBuffer.second.size(); - } - return (totalRequest <= LOW_SYSTEM_LOAD); -} - -bool SMS::existLowIntensityThread() const -{ - for (const auto &mpkcPerThread : MPKCs) { - if (mpkcPerThread.second < LOW_MPKC) { - return true; - } - } - return false; -} - -bool SMS::isThresholdAgeExceeded(const Thread &thread, sc_time const &memClk, - size_t const &inclusiveBeginLoc, size_t const &exclusiveEndLoc) -{ - assert((exclusiveEndLoc - inclusiveBeginLoc) >= 1); - // find the oldest request in the thread's batch - sc_time oldestGenerationTime = sc_time_stamp(); - for (size_t i = inclusiveBeginLoc; i != exclusiveEndLoc; ++i) { - sc_time reqGenerationTime = GenerationExtension::getExtension( - requestBuffers[thread][i]).TimeOfGeneration(); - if (reqGenerationTime < oldestGenerationTime) { - oldestGenerationTime = reqGenerationTime; - } - } - - // check threshold age according to the thread's MPKC - sc_time oldestRequestAge = sc_time_stamp() - oldestGenerationTime; - if ((MPKCs[thread] <= MEDIUM_MPKC) - && (oldestRequestAge > (MEDIUM_THRESHOLD_AGE * memClk))) { - return true; - } else if ((MPKCs[thread] > MEDIUM_MPKC) - && (oldestRequestAge > (HIGH_THRESHOLD_AGE * memClk))) { - return true; - } else { - return false; - } -} - -void SMS::updateMPKCs(sc_time const &memClk) -{ - if (sc_time_stamp() % (MPKC_RESET_CYCLE * memClk) <= memClk) { - // reset for every 10k clk cycles - for (const auto &cacheMiss : cacheMisses) { - MPKCs[cacheMiss.first] = 0; - } - debugManager.printDebugMessage(name(), "Reset MKKCs"); - } else { - // update MPKC for every thread - for (const auto &cacheMiss : cacheMisses) { - MPKCs[cacheMiss.first] = (cacheMiss.second * 1000.0 * memClk) / - (sc_time_stamp()); - } - debugManager.printDebugMessage(name(), "Update MPKCs"); - } -} - -bool SMS::isExceededReqBufferSize(size_t const &exclusiveEndLoc) -{ - return exclusiveEndLoc <= Configuration::getInstance().RequestBufferSize; -} - -bool SMS::isRequestBuffersEmpty() const -{ - for (const auto &requestBuffer : requestBuffers) { - if (!requestBuffer.second.empty()) { - return false; - } - } - return true; -} - -bool SMS::existReadyBatches() const -{ - for (const auto &each : readyBatchInclusiveEndLocs) { - if (!each.second.empty()) { - return true; - } - } - return false; -} - -/** - * Form batch from begin iterator parameter of a request buffer - * If this batch is deemed ready, save the iterator pointing to its last element - * @param memClk - * @param begin - * @return true if this batch is ready, otherwise false - */ -bool SMS::batchFormation(sc_time const &memClk, Thread const &thread, - std::deque const &requestBuffer, size_t const &inclusiveBeginLoc) -{ - if (requestBuffer.empty()) { - return false; - } - - assert(inclusiveBeginLoc <= requestBuffer.size()); - if (requestBuffer.size() == inclusiveBeginLoc) { - return false; - } - - if (MPKCs[thread] < LOW_MPKC || isSystemLightlyLoaded()) { - // bypass requests by forming batch with only one request (threshold age is ZERO) - readyBatchInclusiveEndLocs[thread].push_back(inclusiveBeginLoc); - return true; - } else { - // forming batch with FIFO size & threshold age constraints - size_t firstDifferentRowAccessReqLoc = inclusiveBeginLoc; - Row firstRow = DramExtension::getRow(requestBuffer[inclusiveBeginLoc]); - bool isBatchReady = false; - size_t bufferSize = requestBuffer.size(); - while (firstDifferentRowAccessReqLoc != bufferSize - && DramExtension::getRow(requestBuffer[firstDifferentRowAccessReqLoc]) == - firstRow) { - ++firstDifferentRowAccessReqLoc; - if (firstDifferentRowAccessReqLoc < bufferSize) { - if (DramExtension::getRow(requestBuffer[firstDifferentRowAccessReqLoc]) != - firstRow - || isExceededReqBufferSize(firstDifferentRowAccessReqLoc) - || isThresholdAgeExceeded(thread, memClk, inclusiveBeginLoc, - firstDifferentRowAccessReqLoc)) { - isBatchReady = true; - break; - } - } else { - if (isExceededReqBufferSize(firstDifferentRowAccessReqLoc) - || isThresholdAgeExceeded(thread, memClk, inclusiveBeginLoc, - firstDifferentRowAccessReqLoc)) { - isBatchReady = true; - break; - } - } - } - - // store this ready batch location - if (isBatchReady) { - --firstDifferentRowAccessReqLoc; - readyBatchInclusiveEndLocs[thread].push_back(firstDifferentRowAccessReqLoc); - debugManager.printDebugMessage(name(), - "Deem batch ready - thread " + to_string(thread.ID())); - return true; - } else { - return false; - } - } -} - -void SMS::multiBatchFormation(sc_time const &memClk) -{ - for (auto &requestBuffer : requestBuffers) { - bool formed = false; - do { - if (readyBatchInclusiveEndLocs[requestBuffer.first].empty()) { - formed = batchFormation(memClk, requestBuffer.first, requestBuffer.second, 0); - } else { - formed = batchFormation(memClk, requestBuffer.first, requestBuffer.second, - readyBatchInclusiveEndLocs[requestBuffer.first].back() + 1); - } - } while (!requestBuffer.second.empty() && formed); - } -} - -gp *SMS::getPendingRequest(Bank bank) -{ - for (const auto &requestBuffer : requestBuffers) { - for (const auto &request : requestBuffer.second) { - if (DramExtension::getBank(request) == bank) { - return request; - } - } - } - return NULL; -} diff --git a/DRAMSys/library/src/controller/scheduler/SMS.h b/DRAMSys/library/src/controller/scheduler/SMS.h deleted file mode 100644 index 4019836b..00000000 --- a/DRAMSys/library/src/controller/scheduler/SMS.h +++ /dev/null @@ -1,88 +0,0 @@ -#ifndef SMS_H -#define SMS_H - -#include -#include -#include "sysc/utils/sc_report.h" -#include "IScheduler.h" -#include "../core/ControllerCore.h" -#include "../core/configuration/Configuration.h" -#include "../../common/dramExtensions.h" -#include "../../common/DebugManager.h" - -#define LOW_SYSTEM_LOAD 16 -#define LOW_MPKC 1 -#define MEDIUM_MPKC 10 -#define MEDIUM_THRESHOLD_AGE 50 -#define HIGH_THRESHOLD_AGE 200 -#define MPKC_RESET_CYCLE 10000 - -using namespace std; -typedef std::deque::iterator gp_deque_iterator; - -/** - * SMS - Staged Memory Scheduler involves 3 steps: - * 1. Arrage request in to each buffer of each thread - * 2. Forming ready batches for each thread, i.e all requests access the same row. The batch is deemed - * ready when the next request accesses different row OR When the buffer is full OR When this batch - * is too old - * 3. Send batches to bank buffers. The rules to send batches are Shortest-Job-First OR Round-Robin - * How we select the rule depends on the probability we setup earlier. - */ -class SMS: public sc_module, public IScheduler -{ -public: - SMS(sc_module_name /*_name*/, ControllerCore &controllerCore, - unsigned int SJFprobability) : IScheduler(controllerCore), - SJFprobability(SJFprobability), debugManager(DebugManager::getInstance()) - { - // initialize selected thread iterator - lastSelectedThread = readyBatchInclusiveEndLocs.end(); - SC_THREAD(batchScheduler); - } - SC_HAS_PROCESS(SMS); - - virtual ~SMS() - { - } - - virtual void storeRequest(gp *payload) override; - virtual std::pair getNextRequest(Bank bank) override; - virtual gp *getPendingRequest(Bank bank) override; - - void batchScheduler(); - -private: - std::map> requestBuffers; - std::map> bankBuffers; - std::map> readyBatchInclusiveEndLocs; - - std::map inFlightMemRequestCounter; - std::map cacheMisses; - std::map MPKCs; - unsigned int SJFprobability; - - std::map>::iterator lastSelectedThread; - sc_event newRequest; - - DebugManager &debugManager; - - bool batchFormation(sc_time const &memClk, Thread const &thread, - const std::deque &requestBuffer, const size_t &inclusiveBeginLoc); - void multiBatchFormation(const sc_time &memClk); - bool pickSJF(); - bool pickRR(); - void drainOnePayloadFromReadybatch(const sc_time &memClk); - - bool existLowIntensityThread() const; - bool isSystemLightlyLoaded() const; - bool isThresholdAgeExceeded(const Thread &thread, const sc_time &memClk, - const size_t &inclusiveBeginLoc, const size_t &exclusiveEndLoc); - bool isExceededReqBufferSize(size_t const &exclusiveEndLoc); - void updateMPKCs(const sc_time &memClk); - - bool isRequestBuffersEmpty() const; - bool existReadyBatches() const; -}; - -#endif // SMS_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 51c7a978..0654e28e 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -48,11 +48,9 @@ #include "../common/DebugManager.h" #include "../common/XmlAddressDecoder.h" #include "../common/CongenAddressDecoder.h" -#include "../controller/core/ControllerCore.h" #include "../controller/core/configuration/ConfigurationLoader.h" #include "../common/utils.h" #include "../simulation/TemperatureController.h" -#include "../controller/Controller.h" #include "../error/ecchamming.h" #include "DramRecordable.h" #include "DramDDR3.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 7123e4ad..24c5e858 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -48,7 +48,6 @@ #include "ReorderBuffer.h" #include #include -#include "../controller/RecordableController.h" #include "../common/third_party/tinyxml2/tinyxml2.h" #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index a8f08083..92a73217 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -50,7 +50,6 @@ #include #include "../common/DebugManager.h" #include "../common/dramExtensions.h" -#include "../controller/Controller.h" #include "../controller/core/timingCalculations.h" #include "../controller/core/configuration/Configuration.h" #include "../common/protocol.h" From 38a099b8e890d2dcec592a91170c4322ef3d4579 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 12 Aug 2019 16:41:44 +0200 Subject: [PATCH 066/183] Included RefreshChecker for different refresh modes. --- .../src/controller/checker/CheckerDDR3.cpp | 68 +++++++++++++------ .../src/controller/checker/CheckerDDR3.h | 66 ++++++++++++++++++ 2 files changed, 113 insertions(+), 21 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index fe8a8391..a3672e16 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -42,15 +42,16 @@ CheckerDDR3::CheckerDDR3() SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); if (config.ControllerCoreRefDisable) - { - timeForNextREFA = sc_max_time(); - timeForNextPREA = sc_max_time(); - } + refreshChecker = new RefreshCheckerDummy(); +// else if (config.BankwiseLogic) +// refreshChecker = new RefreshCheckerBankwise(); else - { - timeForNextREFA = memSpec->tREFI; - timeForNextPREA = timeForNextREFA - memSpec->tRP; - } + refreshChecker = new RefreshChecker(); +} + +CheckerDDR3::~CheckerDDR3() +{ + delete refreshChecker; } sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) @@ -87,8 +88,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) earliestTimeToStart = std::max(earliestTimeToStart, timeToSatisfyFAW()); - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; + refreshChecker->delayForACT(bank, earliestTimeToStart); } else if (command == Command::RD || command == Command::RDA) { @@ -103,8 +103,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; + refreshChecker->delayForRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) { @@ -119,8 +118,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; + refreshChecker->delayForWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { @@ -135,8 +133,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - if (earliestTimeToStart >= timeForNextPREA) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; + refreshChecker->delayForPRE(bank, earliestTimeToStart); } else { @@ -166,11 +163,12 @@ sc_time CheckerDDR3::timeToSatisfyFAW() void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) { Command command = scheduledCommand.getCommand(); + Bank bank = scheduledCommand.getBank(); PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + to_string(scheduledCommand.getBank().ID()) + " command is " + commandToString(command)); - lastScheduledByCommandAndBank[command][scheduledCommand.getBank()] = scheduledCommand; + lastScheduledByCommandAndBank[command][bank] = scheduledCommand; lastScheduledByCommand[command] = scheduledCommand; lastScheduled = scheduledCommand; @@ -182,8 +180,36 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) lastActivates.push(scheduledCommand.getStart()); } else if (command == Command::REFA) - { - timeForNextREFA += memSpec->tREFI; - timeForNextPREA = timeForNextREFA - memSpec->tRP; - } + refreshChecker->insert(bank); +} + +// TODO: max(earliestTimeToStart, ...) needed? +void RefreshChecker::delayForACT(const Bank &, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshChecker::delayForRD(const Bank &, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshChecker::delayForWR(const Bank &, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshChecker::delayForPRE(const Bank &, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= timeForNextPREA) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshChecker::insert(const Bank &) +{ + timeForNextREFA += memSpec->tREFI; + timeForNextPREA = timeForNextREFA - memSpec->tRP; } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 1deeb7fa..ab3bceec 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -40,10 +40,13 @@ #include "../core/configuration/MemSpec.h" #include "../core/configuration/Configuration.h" +class RefreshCheckerIF; + class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); + ~CheckerDDR3(); sc_time delayToSatisfyConstraints(Command, Bank); void insert(const ScheduledCommand &); @@ -57,8 +60,71 @@ private: sc_time timeForNextREFA; sc_time timeForNextPREA; + RefreshCheckerIF *refreshChecker; + // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; +class RefreshCheckerIF +{ +protected: + friend class CheckerDDR3; + RefreshCheckerIF() + { + Configuration config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + } + virtual ~RefreshCheckerIF() {} + + virtual void delayForACT(const Bank &, sc_time &) = 0; + virtual void delayForRD(const Bank &, sc_time &) = 0; + virtual void delayForWR(const Bank &, sc_time &) = 0; + virtual void delayForPRE(const Bank &, sc_time &) = 0; + virtual void insert(const Bank &) = 0; + + const MemSpecDDR3 *memSpec; +}; + +class RefreshCheckerDummy final : public RefreshCheckerIF +{ +private: + friend class CheckerDDR3; + RefreshCheckerDummy() {} + + void delayForACT(const Bank &, sc_time &) {} + void delayForRD(const Bank &, sc_time &) {} + void delayForWR(const Bank &, sc_time &) {} + void delayForPRE(const Bank &, sc_time &) {} + void insert(const Bank &) {} +}; + +class RefreshChecker final : public RefreshCheckerIF +{ +private: + friend class CheckerDDR3; + RefreshChecker() {} + + void delayForACT(const Bank &, sc_time &); + void delayForRD(const Bank &, sc_time &); + void delayForWR(const Bank &, sc_time &); + void delayForPRE(const Bank &, sc_time &); + void insert(const Bank &); + + sc_time timeForNextREFA = memSpec->tREFI; + sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; +}; + +//class RefreshCheckerBankwise final : public RefreshCheckerIF +//{ +//private: +// friend class CheckerDDR3; +// RefreshCheckerBankwise() {} + +// void delayToSatisfyConstraints(const Command &, const Bank &, sc_time &); +// void insert(const Command &, const Bank &); +//}; + #endif // CHECKERDDR3_H From 3b26997ea4fad7e04f2234609960bb0b844043f8 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 13 Aug 2019 11:39:15 +0200 Subject: [PATCH 067/183] Updated structure of RefreshManager for bankwise refresh implementation. --- .../library/src/controller/ControllerNew.cpp | 23 ++------- .../src/controller/refresh/RefreshManager.cpp | 50 +++++++++---------- .../src/controller/refresh/RefreshManager.h | 25 ++++------ .../refresh/RefreshManagerDummy.cpp | 9 +--- .../controller/refresh/RefreshManagerDummy.h | 3 +- .../src/controller/refresh/RefreshManagerIF.h | 3 +- 6 files changed, 45 insertions(+), 68 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 3f25d984..8ca1dfa2 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -61,8 +61,8 @@ ControllerNew::ControllerNew(sc_module_name name) : refreshManager = new RefreshManagerDummy(); else { - refreshManager = new RefreshManager(); - refreshEvent.notify(refreshManager->getInitialDelay()); + refreshManager = new RefreshManager(bankMachines); + refreshEvent.notify(refreshManager->getTriggerDelay()); } if (config.Scheduler == "FifoStrict") { @@ -128,22 +128,9 @@ void ControllerNew::controllerMethod() std::pair result; // (5.1) Check for refresh command (PREA or REFA) result = refreshManager->getNextCommand(); + refreshEvent.notify(refreshManager->getTriggerDelay()); if (result.second != nullptr) - { - sc_time delay = refreshManager->updateState(); - refreshEvent.notify(delay); - if (result.first == Command::PREA) - { - bool forcedPrecharges = false; - for (auto it : bankMachines) - forcedPrecharges |= it.second->forcePrecharge(); - // Send the PREA only if at least one bank was precharged - if (forcedPrecharges) - sendToDram(result.first, result.second); - } - else - sendToDram(result.first, result.second); - } + sendToDram(result.first, result.second); // (5.2) Check for other commands (PRE, ACT, RD or WR) else { @@ -170,7 +157,7 @@ void ControllerNew::controllerMethod() for (auto it : bankMachines) { sc_time delay = it.second->startBankMachine(); - if (delay != SC_ZERO_TIME) // must be checked to avoid + if (delay != SC_ZERO_TIME) // must be checked to avoid livelock bankMachineEvent.notify(delay); } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 6878413b..ff790e09 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -37,44 +37,44 @@ #include "../core/configuration/Configuration.h" #include "../../common/utils.h" -RefreshManager::RefreshManager() +RefreshManager::RefreshManager(std::map &bankMachines) : bankMachines(bankMachines) { setUpDummy(refreshPayload); memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - timeForNextREFA = memSpec->tREFI; - timeForNextPREA = timeForNextREFA - memSpec->tRP; + timeForNextTrigger = memSpec->tREFI - memSpec->tRP; } std::pair RefreshManager::getNextCommand() { - if (sc_time_stamp() == timeForNextPREA) - return std::pair(Command::PREA, &refreshPayload); - else if (sc_time_stamp() == timeForNextREFA) - return std::pair(Command::REFA, &refreshPayload); + if (sc_time_stamp() == timeForNextTrigger) + { + if (state == RmState::IDLE) + { + state = RmState::REFRESHING; + timeForNextTrigger += memSpec->tRP; + bool forcedPrecharges = false; + for (auto it : bankMachines) + forcedPrecharges |= it.second->forcePrecharge(); + if (forcedPrecharges) + return std::pair(Command::PREA, &refreshPayload); + else + return std::pair(Command::NOP, nullptr); + } + else + { + state = RmState::IDLE; + timeForNextTrigger += (memSpec->tREFI - memSpec->tRP); + return std::pair(Command::REFA, &refreshPayload); + } + } else return std::pair(Command::NOP, nullptr); } -sc_time RefreshManager::updateState() +sc_time RefreshManager::getTriggerDelay() { - if (state == RmState::IDLE) - { - state = RmState::REFRESHING; - timeForNextPREA += memSpec->tREFI; - return memSpec->tRP; - } - else - { - state = RmState::IDLE; - timeForNextREFA += memSpec->tREFI; - return (memSpec->tREFI - memSpec->tRP); - } -} - -sc_time RefreshManager::getInitialDelay() -{ - return timeForNextPREA; + return timeForNextTrigger - sc_time_stamp(); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 2882d342..3a395b29 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -41,33 +41,30 @@ #include "RefreshManagerIF.h" #include "../Command.h" #include "../core/configuration/MemSpec.h" +#include "../BankMachine.h" using namespace tlm; -enum class RmState -{ - IDLE, - REFRESHING -}; - class RefreshManager final : public RefreshManagerIF { public: - RefreshManager(); + RefreshManager(std::map &); std::pair getNextCommand(); - sc_time updateState(); - sc_time getInitialDelay(); + sc_time getTriggerDelay(); private: + enum class RmState + { + IDLE, + REFRESHING + }; + RmState state = RmState::IDLE; - const MemSpecDDR3 *memSpec; - + std::map &bankMachines; tlm_generic_payload refreshPayload; - - sc_time timeForNextREFA; - sc_time timeForNextPREA; + sc_time timeForNextTrigger; }; #endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp index 8a1fa224..5f77a543 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -39,12 +39,7 @@ std::pair RefreshManagerDummy::getNextCommand() return std::pair(Command::NOP, nullptr); } -sc_time RefreshManagerDummy::updateState() +sc_time RefreshManagerDummy::getTriggerDelay() { - return SC_ZERO_TIME; -} - -sc_time RefreshManagerDummy::getInitialDelay() -{ - return SC_ZERO_TIME; + return sc_max_time() - sc_time_stamp(); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 8031d82c..76ccb6fe 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -47,8 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF { public: std::pair getNextCommand(); - sc_time updateState(); - sc_time getInitialDelay(); + sc_time getTriggerDelay(); }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index 94999460..31601f0a 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -48,8 +48,7 @@ public: virtual ~RefreshManagerIF() {} virtual std::pair getNextCommand() = 0; - virtual sc_time updateState() = 0; - virtual sc_time getInitialDelay() = 0; + virtual sc_time getTriggerDelay() = 0; }; #endif // REFRESHMANAGERIF_H From c2022667c539774c17c1531dbe51f5420ef60ed1 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 13 Aug 2019 14:23:44 +0200 Subject: [PATCH 068/183] Included files for RefreshManagerBankwise. --- DRAMSys/library/library.pro | 6 ++++-- .../src/controller/refresh/RefreshManager.h | 8 +------- .../refresh/RefreshManagerBankwise.cpp | 6 ++++++ .../refresh/RefreshManagerBankwise.h | 19 +++++++++++++++++++ 4 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp create mode 100644 DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index ff3d9cc4..e97f529b 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -131,7 +131,8 @@ SOURCES += \ src/controller/ControllerRecordable.cpp \ src/controller/checker/CheckerDDR3.cpp \ src/controller/refresh/RefreshManager.cpp \ - src/controller/refresh/RefreshManagerDummy.cpp + src/controller/refresh/RefreshManagerDummy.cpp \ + src/controller/refresh/RefreshManagerBankwise.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -197,7 +198,8 @@ HEADERS += \ src/controller/checker/CheckerDDR3.h \ src/controller/refresh/RefreshManagerIF.h \ src/controller/refresh/RefreshManager.h \ - src/controller/refresh/RefreshManagerDummy.h + src/controller/refresh/RefreshManagerDummy.h \ + src/controller/refresh/RefreshManagerBankwise.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 3a395b29..58d8f05c 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -54,13 +54,7 @@ public: sc_time getTriggerDelay(); private: - enum class RmState - { - IDLE, - REFRESHING - }; - - RmState state = RmState::IDLE; + enum class RmState {IDLE, REFRESHING} state = RmState::IDLE; const MemSpecDDR3 *memSpec; std::map &bankMachines; tlm_generic_payload refreshPayload; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp new file mode 100644 index 00000000..5738683a --- /dev/null +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -0,0 +1,6 @@ +#include "RefreshManagerBankwise.h" + +//RefreshManagerBankwise::RefreshManagerBankwise() +//{ + +//} diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h new file mode 100644 index 00000000..7ef388a3 --- /dev/null +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -0,0 +1,19 @@ +#ifndef REFRESHMANAGERBANKWISE_H +#define REFRESHMANAGERBANKWISE_H + +#include "RefreshManagerIF.h" + +//class RefreshManagerBankwise : public RefreshManagerIF +//{ +//public: +// RefreshManagerBankwise(); + +// std::pair getNextCommand(); +// sc_time updateState(); +// sc_time getInitialDelay(); + +//private: + +//}; + +#endif // REFRESHMANAGERBANKWISE_H From 0918a786486b0e5c8f8b1bf31fd3f7a4ad607810 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 14 Aug 2019 09:44:24 +0200 Subject: [PATCH 069/183] Included GenericController for polymorphism. --- .../src/controller/GenericController.h | 22 +++++++++---------- DRAMSys/library/src/simulation/DRAMSys.cpp | 14 ++++++------ DRAMSys/library/src/simulation/DRAMSys.h | 3 +-- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/DRAMSys/library/src/controller/GenericController.h b/DRAMSys/library/src/controller/GenericController.h index 3dbffffd..5d49dc68 100644 --- a/DRAMSys/library/src/controller/GenericController.h +++ b/DRAMSys/library/src/controller/GenericController.h @@ -18,17 +18,6 @@ public: tlm_utils::simple_target_socket tSocket; // Arbiter side tlm_utils::simple_initiator_socket iSocket; // DRAM side -protected: - // Bind sockets with virtual functions - GenericController(sc_module_name name) : - sc_module(name), tSocket("tSocket"), iSocket("iSocket") - { - tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw); - tSocket.register_transport_dbg(this, &GenericController::transport_dbg); - iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw); - } - SC_HAS_PROCESS(GenericController); - // Destructor virtual ~GenericController() { @@ -69,6 +58,17 @@ protected: << std::endl; } +protected: + // Bind sockets with virtual functions + GenericController(sc_module_name name) : + sc_module(name), tSocket("tSocket"), iSocket("iSocket") + { + tSocket.register_nb_transport_fw(this, &GenericController::nb_transport_fw); + tSocket.register_transport_dbg(this, &GenericController::transport_dbg); + iSocket.register_nb_transport_bw(this, &GenericController::nb_transport_bw); + } + SC_HAS_PROCESS(GenericController); + // Virtual transport functions virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0; virtual unsigned int transport_dbg(tlm_generic_payload &) = 0; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 0654e28e..e41e1862 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -252,12 +252,12 @@ void DRAMSys::instantiateModules(const string &traceName, { std::string str = "controller" + std::to_string(i); - ControllerNew *controller; + GenericController *controller; if (recordingEnabled) controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]); else controller = new ControllerNew(str.c_str()); - newControllers.push_back(controller); + controllers.push_back(controller); str = "dram" + std::to_string(i); Dram *dram; @@ -315,15 +315,15 @@ void DRAMSys::bindSockets() i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind( - newControllers[i]->tSocket); - newControllers[i]->iSocket.bind(drams[i]->tSocket); + controllers[i]->tSocket); + controllers[i]->iSocket.bind(drams[i]->tSocket); } } else { for (size_t i = 0; i < Configuration::getInstance().NumberOfMemChannels; i++) { - arbiter->iSocket.bind(newControllers[i]->tSocket); - newControllers[i]->iSocket.bind(drams[i]->tSocket); + arbiter->iSocket.bind(controllers[i]->tSocket); + controllers[i]->iSocket.bind(drams[i]->tSocket); } } } @@ -351,7 +351,7 @@ DRAMSys::~DRAMSys() delete tlmChecker; } - for (auto controller : newControllers) { + for (auto controller : controllers) { delete controller; } } diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index 24c5e858..fa04d170 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -52,7 +52,6 @@ #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" #include "../controller/GenericController.h" -#include "../controller/ControllerNew.h" class DRAMSys : public sc_module { @@ -88,7 +87,7 @@ private: // All transactions pass through the same arbiter Arbiter *arbiter; // Each DRAM unit has a controller - std::vector newControllers; + std::vector controllers; //std::vector controllers; // TODO: Each DRAM has a reorder buffer (check this!) From 47ee187bc31201fac0e49527b04f5e98663993e7 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 14 Aug 2019 13:48:04 +0200 Subject: [PATCH 070/183] Working on RefreshManagerBankwise. --- .../src/controller/refresh/RefreshManager.cpp | 3 +- .../src/controller/refresh/RefreshManager.h | 4 -- .../refresh/RefreshManagerBankwise.cpp | 67 ++++++++++++++++++- .../refresh/RefreshManagerBankwise.h | 62 ++++++++++++++--- 4 files changed, 118 insertions(+), 18 deletions(-) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index ff790e09..67c987d4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -39,11 +39,12 @@ RefreshManager::RefreshManager(std::map &bankMachines) : bankMachines(bankMachines) { - setUpDummy(refreshPayload); memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + setUpDummy(refreshPayload); + timeForNextTrigger = memSpec->tREFI - memSpec->tRP; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 58d8f05c..801ee5df 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -35,11 +35,7 @@ #ifndef REFRESHMANAGER_H #define REFRESHMANAGER_H -#include -#include -#include #include "RefreshManagerIF.h" -#include "../Command.h" #include "../core/configuration/MemSpec.h" #include "../BankMachine.h" diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 5738683a..93dbe4b6 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -1,6 +1,67 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #include "RefreshManagerBankwise.h" +#include "../core/configuration/Configuration.h" +#include "../../common/utils.h" +#include "../../common/dramExtensions.h" -//RefreshManagerBankwise::RefreshManagerBankwise() -//{ +RefreshManagerBankwise::RefreshManagerBankwise(std::map &bankMachines) + : bankMachines(bankMachines) +{ + memSpec = dynamic_cast(Configuration::getInstance().memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); -//} + sc_time currentREFB = memSpec->tREFI - memSpec->clk * memSpec->NumberOfBanks; + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + { + setUpDummy(refreshPayloads[Bank(bankID)], Bank(bankID)); + triggerTimes.insert(std::pair(currentREFB, Bank(bankID))); + triggerTimes.insert(std::pair(currentPRE, Bank(bankID))); + currentREFB += memSpec->clk; + currentPRE += memSpec->clk; + } +} + +std::pair RefreshManagerBankwise::getNextCommand() +{ + +} + +sc_time RefreshManagerBankwise::getTriggerDelay() +{ + +} diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 7ef388a3..08758631 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -1,19 +1,61 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + #ifndef REFRESHMANAGERBANKWISE_H #define REFRESHMANAGERBANKWISE_H #include "RefreshManagerIF.h" +#include "../core/configuration/MemSpec.h" +#include "../BankMachine.h" +#include +#include -//class RefreshManagerBankwise : public RefreshManagerIF -//{ -//public: -// RefreshManagerBankwise(); +class RefreshManagerBankwise final : public RefreshManagerIF +{ +public: + RefreshManagerBankwise(std::map &); -// std::pair getNextCommand(); -// sc_time updateState(); -// sc_time getInitialDelay(); + std::pair getNextCommand(); + sc_time getTriggerDelay(); -//private: - -//}; +private: + const MemSpecDDR3 *memSpec; + std::map &bankMachines; + std::map refreshPayloads; + std::map triggerTimes; + enum class RmState {IDLE, REFRESHING}; + std::map states; +}; #endif // REFRESHMANAGERBANKWISE_H From 31101a0827a178dce92cf825e0d4d1d59fa84048 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 14 Aug 2019 20:19:27 +0200 Subject: [PATCH 071/183] Finished bankwise refresh. --- DRAMSys/library/src/controller/Command.cpp | 5 +- .../library/src/controller/ControllerNew.cpp | 8 +++ .../src/controller/checker/CheckerDDR3.cpp | 49 +++++++++++++++++-- .../src/controller/checker/CheckerDDR3.h | 23 ++++++--- .../controller/core/configuration/MemSpec.cpp | 2 + .../refresh/RefreshManagerBankwise.cpp | 31 ++++++++++-- .../refresh/RefreshManagerBankwise.h | 1 + 7 files changed, 103 insertions(+), 16 deletions(-) diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index fc2474ce..bfef86c0 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -72,7 +72,9 @@ std::string commandToString(Command command) case Command::REFA: return "REFA"; break; - + case Command::REFB: + return "REFB"; + break; case Command::PDEA: return "PDEA"; break; @@ -116,6 +118,7 @@ const std::vector &getAllCommands() Command::RDA, Command::WRA, Command::REFA, + Command::REFB, Command::PDEA, Command::PDXA, Command::PDEP, diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 8ca1dfa2..82d8074a 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -45,6 +45,7 @@ #include "checker/CheckerDDR3.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" +#include "refresh/RefreshManagerBankwise.h" ControllerNew::ControllerNew(sc_module_name name) : GenericController(name) @@ -59,6 +60,11 @@ ControllerNew::ControllerNew(sc_module_name name) : checker = new CheckerDDR3(); if (config.ControllerCoreRefDisable) refreshManager = new RefreshManagerDummy(); + else if (config.BankwiseLogic) + { + refreshManager = new RefreshManagerBankwise(bankMachines); + refreshEvent.notify(refreshManager->getTriggerDelay()); + } else { refreshManager = new RefreshManager(bankMachines); @@ -266,6 +272,8 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) phase = BEGIN_PRE_ALL; else if (command == Command::REFA) phase = BEGIN_REFA; + else if (command == Command::REFB) + phase = BEGIN_REFB; else SC_REPORT_FATAL("ControllerNew", "Unknown phase"); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index a3672e16..9fe18c8c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -43,8 +43,8 @@ CheckerDDR3::CheckerDDR3() if (config.ControllerCoreRefDisable) refreshChecker = new RefreshCheckerDummy(); -// else if (config.BankwiseLogic) -// refreshChecker = new RefreshCheckerBankwise(); + else if (config.BankwiseLogic) + refreshChecker = new RefreshCheckerBankwise(); else refreshChecker = new RefreshChecker(); } @@ -86,6 +86,10 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + earliestTimeToStart = std::max(earliestTimeToStart, timeToSatisfyFAW()); refreshChecker->delayForACT(bank, earliestTimeToStart); @@ -179,7 +183,7 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) lastActivates.pop(); lastActivates.push(scheduledCommand.getStart()); } - else if (command == Command::REFA) + else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); } @@ -211,5 +215,42 @@ void RefreshChecker::delayForPRE(const Bank &, sc_time &earliestTimeToStart) void RefreshChecker::insert(const Bank &) { timeForNextREFA += memSpec->tREFI; - timeForNextPREA = timeForNextREFA - memSpec->tRP; + timeForNextPREA += memSpec->tREFI; +} + +RefreshCheckerBankwise::RefreshCheckerBankwise() +{ + sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + { + timesForNextREFB[Bank(bankID)] = currentREFB; + timesForNextPRE[Bank(bankID)] = currentPRE; + currentREFB += memSpec->clk; + currentPRE += memSpec->clk; + } +} + +void RefreshCheckerBankwise::delayForACT(const Bank &bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRAS)) + earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; +} + +void RefreshCheckerBankwise::delayForRD(const Bank &bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRTP)) + earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; +} + +void RefreshCheckerBankwise::delayForWR(const Bank &bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; +} + +void RefreshCheckerBankwise::insert(const Bank &bank) +{ + timesForNextREFB[bank] += memSpec->tREFI; + timesForNextPRE[bank] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index ab3bceec..7357bdee 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -37,6 +37,7 @@ #include "CheckerIF.h" #include +#include #include "../core/configuration/MemSpec.h" #include "../core/configuration/Configuration.h" @@ -117,14 +118,20 @@ private: sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; }; -//class RefreshCheckerBankwise final : public RefreshCheckerIF -//{ -//private: -// friend class CheckerDDR3; -// RefreshCheckerBankwise() {} +class RefreshCheckerBankwise final : public RefreshCheckerIF +{ +private: + friend class CheckerDDR3; + RefreshCheckerBankwise(); -// void delayToSatisfyConstraints(const Command &, const Bank &, sc_time &); -// void insert(const Command &, const Bank &); -//}; + void delayForACT(const Bank &, sc_time &); + void delayForRD(const Bank &, sc_time &); + void delayForWR(const Bank &, sc_time &); + void delayForPRE(const Bank &, sc_time &) {} + void insert(const Bank &); + + std::map timesForNextREFB; + std::map timesForNextPRE; +}; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index 9b01d316..5d8f970c 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -96,6 +96,8 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay else if (command == Command::PREA) return tRP_old; else if (command == Command::REFA) + return tRFC_old; + else if (command == Command::REFB) return getElementFromMap(refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC; else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 93dbe4b6..2c978461 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -44,10 +44,12 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::map &ba if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - sc_time currentREFB = memSpec->tREFI - memSpec->clk * memSpec->NumberOfBanks; + sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + timeForNextTrigger = currentPRE; for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) { + states[Bank(bankID)] = RmState::IDLE; setUpDummy(refreshPayloads[Bank(bankID)], Bank(bankID)); triggerTimes.insert(std::pair(currentREFB, Bank(bankID))); triggerTimes.insert(std::pair(currentPRE, Bank(bankID))); @@ -58,10 +60,33 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::map &ba std::pair RefreshManagerBankwise::getNextCommand() { - + if (sc_time_stamp() == timeForNextTrigger) + { + auto it = triggerTimes.begin(); + Bank bank = it->second; + triggerTimes.erase(it); + triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->tREFI, bank)); + timeForNextTrigger = triggerTimes.begin()->first; + if (states[bank] == RmState::IDLE) + { + states[bank] = RmState::REFRESHING; + bool forcedPrecharge = bankMachines[bank]->forcePrecharge(); + if (forcedPrecharge) + return std::pair(Command::PRE, &refreshPayloads[bank]); + else + return std::pair(Command::NOP, nullptr); + } + else + { + states[bank] = RmState::IDLE; + return std::pair(Command::REFB, &refreshPayloads[bank]); + } + } + else + return std::pair(Command::NOP, nullptr); } sc_time RefreshManagerBankwise::getTriggerDelay() { - + return timeForNextTrigger - sc_time_stamp(); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 08758631..c38d56bd 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -54,6 +54,7 @@ private: std::map &bankMachines; std::map refreshPayloads; std::map triggerTimes; + sc_time timeForNextTrigger; enum class RmState {IDLE, REFRESHING}; std::map states; }; From 7d675a9837e7776061dc48ad9047fd251897bf80 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 14 Aug 2019 21:19:42 +0200 Subject: [PATCH 072/183] Renaming and minor improvements. --- .../src/controller/checker/CheckerDDR3.cpp | 40 ++++++++---------- .../src/controller/checker/CheckerDDR3.h | 42 +++++++++---------- 2 files changed, 39 insertions(+), 43 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 9fe18c8c..ebc5213a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -90,9 +90,9 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); - earliestTimeToStart = std::max(earliestTimeToStart, timeToSatisfyFAW()); + delayToSatisfyFAW(earliestTimeToStart); - refreshChecker->delayForACT(bank, earliestTimeToStart); + refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } else if (command == Command::RD || command == Command::RDA) { @@ -107,7 +107,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - refreshChecker->delayForRD(bank, earliestTimeToStart); + refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) { @@ -122,7 +122,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); - refreshChecker->delayForWR(bank, earliestTimeToStart); + refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { @@ -137,7 +137,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - refreshChecker->delayForPRE(bank, earliestTimeToStart); + refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); } else { @@ -150,17 +150,13 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) return (earliestTimeToStart - sc_time_stamp()); } -sc_time CheckerDDR3::timeToSatisfyFAW() +void CheckerDDR3::delayToSatisfyFAW(sc_time &earliestTimeToStart) { - if (lastActivates.size() < 4) - return sc_time_stamp(); - else + if (lastActivates.size() >= 4) { sc_time earliestTime = lastActivates.front() + memSpec->tFAW; - if (earliestTime > sc_time_stamp()) - return earliestTime; - else - return sc_time_stamp(); + if (earliestTime > earliestTimeToStart) + earliestTimeToStart = earliestTime; } } @@ -188,31 +184,31 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) } // TODO: max(earliestTimeToStart, ...) needed? -void RefreshChecker::delayForACT(const Bank &, sc_time &earliestTimeToStart) +void RefreshChecker::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::delayForRD(const Bank &, sc_time &earliestTimeToStart) +void RefreshChecker::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::delayForWR(const Bank &, sc_time &earliestTimeToStart) +void RefreshChecker::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::delayForPRE(const Bank &, sc_time &earliestTimeToStart) +void RefreshChecker::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= timeForNextPREA) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::insert(const Bank &) +void RefreshChecker::insert(Bank) { timeForNextREFA += memSpec->tREFI; timeForNextPREA += memSpec->tREFI; @@ -231,25 +227,25 @@ RefreshCheckerBankwise::RefreshCheckerBankwise() } } -void RefreshCheckerBankwise::delayForACT(const Bank &bank, sc_time &earliestTimeToStart) +void RefreshCheckerBankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRAS)) earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; } -void RefreshCheckerBankwise::delayForRD(const Bank &bank, sc_time &earliestTimeToStart) +void RefreshCheckerBankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRTP)) earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; } -void RefreshCheckerBankwise::delayForWR(const Bank &bank, sc_time &earliestTimeToStart) +void RefreshCheckerBankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; } -void RefreshCheckerBankwise::insert(const Bank &bank) +void RefreshCheckerBankwise::insert(Bank bank) { timesForNextREFB[bank] += memSpec->tREFI; timesForNextPRE[bank] += memSpec->tREFI; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 7357bdee..36cf8577 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -56,7 +56,7 @@ private: // Four activate window std::queue lastActivates; - sc_time timeToSatisfyFAW(); + void delayToSatisfyFAW(sc_time &); sc_time timeForNextREFA; sc_time timeForNextPREA; @@ -80,11 +80,11 @@ protected: } virtual ~RefreshCheckerIF() {} - virtual void delayForACT(const Bank &, sc_time &) = 0; - virtual void delayForRD(const Bank &, sc_time &) = 0; - virtual void delayForWR(const Bank &, sc_time &) = 0; - virtual void delayForPRE(const Bank &, sc_time &) = 0; - virtual void insert(const Bank &) = 0; + virtual void delayToSatisfyACT(Bank, sc_time &) = 0; + virtual void delayToSatisfyRD(Bank, sc_time &) = 0; + virtual void delayToSatisfyWR(Bank, sc_time &) = 0; + virtual void delayToSatisfyPRE(Bank, sc_time &) = 0; + virtual void insert(Bank) = 0; const MemSpecDDR3 *memSpec; }; @@ -95,11 +95,11 @@ private: friend class CheckerDDR3; RefreshCheckerDummy() {} - void delayForACT(const Bank &, sc_time &) {} - void delayForRD(const Bank &, sc_time &) {} - void delayForWR(const Bank &, sc_time &) {} - void delayForPRE(const Bank &, sc_time &) {} - void insert(const Bank &) {} + void delayToSatisfyACT(Bank, sc_time &) {} + void delayToSatisfyRD(Bank, sc_time &) {} + void delayToSatisfyWR(Bank, sc_time &) {} + void delayToSatisfyPRE(Bank, sc_time &) {} + void insert(Bank) {} }; class RefreshChecker final : public RefreshCheckerIF @@ -108,11 +108,11 @@ private: friend class CheckerDDR3; RefreshChecker() {} - void delayForACT(const Bank &, sc_time &); - void delayForRD(const Bank &, sc_time &); - void delayForWR(const Bank &, sc_time &); - void delayForPRE(const Bank &, sc_time &); - void insert(const Bank &); + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void delayToSatisfyPRE(Bank, sc_time &); + void insert(Bank); sc_time timeForNextREFA = memSpec->tREFI; sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; @@ -124,11 +124,11 @@ private: friend class CheckerDDR3; RefreshCheckerBankwise(); - void delayForACT(const Bank &, sc_time &); - void delayForRD(const Bank &, sc_time &); - void delayForWR(const Bank &, sc_time &); - void delayForPRE(const Bank &, sc_time &) {} - void insert(const Bank &); + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void delayToSatisfyPRE(Bank, sc_time &) {} + void insert(Bank); std::map timesForNextREFB; std::map timesForNextPRE; From 7b8bb86620d73f8d037ea652ca293937347c67cc Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 15 Aug 2019 14:55:55 +0200 Subject: [PATCH 073/183] Removed old timing parameters, moved DramPower configuration to specific Drams. --- .../configuration/ConfigurationLoader.cpp | 118 ++---------------- .../controller/core/configuration/MemSpec.cpp | 37 +++--- .../controller/core/configuration/MemSpec.h | 71 ++--------- DRAMSys/library/src/simulation/Dram.cpp | 94 +------------- DRAMSys/library/src/simulation/DramDDR3.cpp | 92 +++++++++++++- DRAMSys/library/src/simulation/DramDDR4.cpp | 91 +++++++++++++- DRAMSys/library/src/simulation/DramWideIO.cpp | 90 ++++++++++++- 7 files changed, 304 insertions(+), 289 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 5e3a9b44..7eec9599 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -199,11 +199,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->tCL = clk * queryUIntParameter(timings, "CL"); memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRAS_ORGR = parameterExists(timings, "RAS_ORGR") ? - clk * queryUIntParameter(timings, "RAS_ORGR") : memSpec->tRAS; memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRC_ORGR = parameterExists(timings, "RC_ORGR") ? - clk * queryUIntParameter(timings, "RC_ORGR") : memSpec->tRC; memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tRL = clk * queryUIntParameter(timings, "RL"); memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); @@ -232,39 +228,18 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) sc_time clk = memSpec->clk; memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? - clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? - clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ? - clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD; memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - - // TODO: old timings, will me removed - memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); - memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); - memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tREFI); // Currents and Volatages: TODO Check if this is correct. XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -305,8 +280,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? - clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); unsigned refMode = Configuration::getInstance().getRefMode(); if (refMode == 1) @@ -316,44 +289,17 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) else // if (refMode == 4) memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? - clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); - memSpec->tRRD_S_ORGR = parameterExists(timings, "RRD_S_ORGR") ? - clk * queryUIntParameter(timings, "RRD_S_ORGR") : memSpec->tRRD_S; memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); - memSpec->tRRD_L_ORGR = parameterExists(timings, "RRD_L_ORGR") ? - clk * queryUIntParameter(timings, "RRD_L_ORGR") : memSpec->tRRD_L; memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - - // TODO: old timings, will me removed - memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD_S"); - memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD_L"); - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD_S"); - memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD_L"); - memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR_S"); - memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR_L"); - memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XPDLL"); - memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XSDLL"); - unsigned refMode_old = Configuration::getInstance().getRefMode(); - if (refMode_old == 1) - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); - else if (refMode_old == 2) - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC2"); - else // if (refMode_old == 4) - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC4"); - memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); - memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tREFI); // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -396,41 +342,20 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCCDMW = clk * queryUIntParameter(timings, "CCDMW"); memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tFAW_ORGR = parameterExists(timings, "FAW_ORGR") ? - clk * queryUIntParameter(timings, "FAW_ORGR") : memSpec->tFAW; memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tREFIAB = clk * queryUIntParameter(timings, "REFIAB"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFCAB = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRPPB = clk * queryUIntParameter(timings, "RPPB"); - memSpec->tRPPB_ORGR = parameterExists(timings, "RPPB_ORGR") ? - clk * queryUIntParameter(timings, "RPPB_ORGR") : memSpec->tRPPB; + memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ? - clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD; - - - // TODO: old timings, will me removed - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tNAW_old = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tXPDLL_old = clk * queryUIntParameter(timings, "XP"); - memSpec->tXSDLL_old = clk * queryUIntParameter(timings, "XS"); - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFCAB"); - memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFIAB"); - memSpec->tRP_old = clk * queryUIntParameter(timings, "RPPB"); memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFCPB, + memSpec->tREFIPB); // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -472,35 +397,14 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); - memSpec->tRP_ORGR = parameterExists(timings, "RP_ORGR") ? - clk * queryUIntParameter(timings, "RP_ORGR") : memSpec->tRP; memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_ORGR = parameterExists(timings, "RRD_ORGR") ? - clk * queryUIntParameter(timings, "RRD_ORGR") : memSpec->tRRD; memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); - memSpec->tTAW_ORGR = parameterExists(timings, "TAW_ORGR") ? - clk * queryUIntParameter(timings, "TAW_ORGR") : memSpec->tTAW; memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - - // TODO: old timings, will me removed - memSpec->tRP_old = clk * queryUIntParameter(timings, "RP"); - memSpec->tRRD_S_old = clk * queryUIntParameter(timings, "RRD"); - memSpec->tRRD_L_old = memSpec->tRRD_S_old; - memSpec->tCCD_S_old = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCD_L_old = memSpec->tCCD_S_old; - memSpec->tNAW_old = clk * queryUIntParameter(timings, "TAW"); - memSpec->tWTR_S_old = clk * queryUIntParameter(timings, "WTR"); - memSpec->tWTR_L_old = memSpec->tWTR_S_old; - memSpec->tXPDLL_old = memSpec->tXP; - memSpec->tXSDLL_old = memSpec->tXS; - memSpec->tRFC_old = clk * queryUIntParameter(timings, "RFC"); - memSpec->tREFI_old = clk * queryUIntParameter(timings, "REFI"); - memSpec->refreshTimings.clear(); for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC_old, - memSpec->tREFI_old); + memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, + memSpec->tREFI); // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index 5d8f970c..30e8dd04 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -75,28 +75,23 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const } // Returns the execution time for commands that have a fixed execution time +// TODO: override this method for different MemSpecs? sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const { - if (command == Command::PREB) - return Configuration::getInstance().getTrpb(); - else if (command == Command::PRE || command == Command::PREA) - return tRP_old; - else if (command == Command::ACTB) - return tRCD; + if (command == Command::PRE || command == Command::PREA) + return tRP; else if (command == Command::ACT) return tRCD; else if (command == Command::RD) return tRL + getReadAccessTime(); else if (command == Command::RDA) - return tRTP + tRP_old; + return tRTP + tRP; else if (command == Command::WR) return tWL + getWriteAccessTime(); else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP_old; - else if (command == Command::PREA) - return tRP_old; + return tWL + getWriteAccessTime() + tWR + tRP; else if (command == Command::REFA) - return tRFC_old; + return tRFC; else if (command == Command::REFB) return getElementFromMap(refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC; @@ -110,27 +105,25 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay } } -sc_time MemSpecDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const { - if (command == Command::PREB) - return Configuration::getInstance().getTrpb(); - else if (command == Command::PRE || command == Command::PREA) - return tRP_old; - else if (command == Command::ACTB) - return tRCD; + if (command == Command::PRE) + return tRP; + else if (command == Command::PREA) + return tRPAB; else if (command == Command::ACT) return tRCD; else if (command == Command::RD) return tRL + getReadAccessTime(); else if (command == Command::RDA) - return tRTP + tRP_old; + return tRTP + tRP; else if (command == Command::WR) return tWL + getWriteAccessTime(); else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP_old; - else if (command == Command::PREA) - return tRP_old; + return tWL + getWriteAccessTime() + tWR + tRP; else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) { return getElementFromMap(refreshTimings, DramExtension::getExtension(payload).getBank()).tRFC; diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 7f5adacd..2cc6550a 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -76,6 +76,9 @@ struct MemSpec unsigned int NumberOfRows; unsigned int NumberOfColumns; unsigned int bitWidth; + unsigned int NumberOfBankGroups; + bool DLL; + bool termination; // Memspec Variables: double clkMHz; @@ -86,9 +89,7 @@ struct MemSpec sc_time tCL; // unused, will be used in the future sc_time tDQSCK; sc_time tRAS; // active-time (act -> pre same bank) - sc_time tRAS_ORGR; sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) - sc_time tRC_ORGR; sc_time tRCD; // act -> read/write sc_time tRL; // read latency (read command start to data strobe) sc_time tRTP; // read to precharge @@ -96,25 +97,9 @@ struct MemSpec sc_time tWR; // write recovery (write to precharge) sc_time tXP; // min delay to row access command after pdnpx pdnax sc_time tXS; // min delay to row access command after srefx - - - // TODO: move to specific memspecs - unsigned int NumberOfBankGroups; - bool DLL; - bool termination; - - sc_time tNAW_old; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else - sc_time tRP_old; // precharge-time (pre -> act same bank) - sc_time tRFC_old; // min ref->act delay 1X mode - sc_time tREFI_old; // auto refresh must be issued at an average periodic interval tREFI - sc_time tCCD_S_old; // max(bl, tCCD) is relevant for rd->rd - sc_time tCCD_L_old; - sc_time tRRD_S_old; // min time bw 2 succesive ACT to different banks (different bank group) - sc_time tRRD_L_old; // .. (same bank group) - sc_time tWTR_S_old; // write to read (different bank group) - sc_time tWTR_L_old; // .. (same bank group) - sc_time tXPDLL_old; // min delay to row access command after pdnpx pdnax for dll commands - sc_time tXSDLL_old; // min delay to row access command after srefx for dll commands + sc_time tREFI; + sc_time tRFC; + sc_time tRP; // Currents and Voltages: double iDD0; @@ -146,20 +131,6 @@ struct MemSpec std::map refreshTimings; //ensure that map is populated completely in memspecloader - //act and read/write commands remain for this timespan in history - sc_time tActHistory() - { - return tNAW_old; - } - sc_time tActBHistory() - { - return tNAW_old; - } - sc_time tDataStrobeHistory() - { - return tWTR_L_old; - } - virtual ~MemSpec() {} }; @@ -167,13 +138,7 @@ struct MemSpecDDR3 : public MemSpec { sc_time tCCD; sc_time tFAW; - sc_time tFAW_ORGR; - sc_time tREFI; - sc_time tRFC; - sc_time tRP; - sc_time tRP_ORGR; sc_time tRRD; - sc_time tRRD_ORGR; sc_time tWTR; sc_time tXPDLL; sc_time tXSDLL; @@ -184,22 +149,12 @@ struct MemSpecDDR4 : public MemSpec sc_time tCCD_S; sc_time tCCD_L; sc_time tFAW; - sc_time tFAW_ORGR; - sc_time tREFI; - sc_time tRFC; - sc_time tRP; - sc_time tRP_ORGR; sc_time tRRD_S; - sc_time tRRD_S_ORGR; sc_time tRRD_L; - sc_time tRRD_L_ORGR; sc_time tWTR_S; sc_time tWTR_L; sc_time tXPDLL; sc_time tXSDLL; - - // Returns the execution time for commands that have a fixed execution time - virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override; }; struct MemSpecLPDDR4 : public MemSpec @@ -208,31 +163,21 @@ struct MemSpecLPDDR4 : public MemSpec sc_time tCCDMW; sc_time tESCKE; sc_time tFAW; - sc_time tFAW_ORGR; sc_time tWTR; sc_time tPPD; - sc_time tREFIAB; sc_time tREFIPB; - sc_time tRFCAB; sc_time tRFCPB; sc_time tRPAB; - sc_time tRPPB; - sc_time tRPPB_ORGR; sc_time tRRD; - sc_time tRRD_ORGR; + + virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override; }; struct MemSpecWideIO : public MemSpec { sc_time tCCD; - sc_time tREFI; - sc_time tRFC; - sc_time tRP; - sc_time tRP_ORGR; sc_time tRRD; - sc_time tRRD_ORGR; sc_time tTAW; - sc_time tTAW_ORGR; sc_time tWTR; }; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 92a73217..bc5ae253 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -63,102 +63,10 @@ using namespace Data; Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") { // Adjust number of bytes per burst dynamically to the selected ecc controller - bytesPerBurst = Configuration::getInstance() - .adjustNumBytesAfterECC(bytesPerBurst); + bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerBurst); tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); - - MemSpec *memSpec = Configuration::getInstance().memSpec; - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); } Dram::~Dram() diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index c75aebe2..7b91109d 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -47,7 +47,95 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) // Parameters for DRAMPower MemSpecDDR3 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); if (memSpec == nullptr) - SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); + SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); - // TODO: Specific configuration of DRAMPower + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD / clk; + memTimingSpec.CCD_L = memSpec->tCCD / clk; + memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tFAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD / clk; + memTimingSpec.RRD_L = memSpec->tRRD / clk; + memTimingSpec.RRD_S = memSpec->tRRD / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tFAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR / clk; + memTimingSpec.WTR_L = memSpec->tWTR / clk; + memTimingSpec.WTR_S = memSpec->tWTR / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index e3bc459b..9f8e85d6 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -49,5 +49,94 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - // TODO: Specific configuration of DRAMPower + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tFAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tFAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); + } diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 4d5cc597..65cdeacb 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -67,7 +67,95 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - // TODO: Specific configuration of DRAMPower + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD / clk; + memTimingSpec.CCD_L = memSpec->tCCD / clk; + memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tTAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD / clk; + memTimingSpec.RRD_L = memSpec->tRRD / clk; + memTimingSpec.RRD_S = memSpec->tRRD / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tTAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR / clk; + memTimingSpec.WTR_L = memSpec->tWTR / clk; + memTimingSpec.WTR_S = memSpec->tWTR / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXP / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXS / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } DramWideIO::~DramWideIO() From 4d936892d9550d2a31a305394e963aa131b59314 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 18 Aug 2019 19:23:53 +0200 Subject: [PATCH 074/183] Included DRAMPower dummy, it can now be switched on and off again. --- DRAMSys/library/src/simulation/Dram.cpp | 41 ++-- DRAMSys/library/src/simulation/Dram.h | 11 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 176 +++++++------- DRAMSys/library/src/simulation/DramDDR4.cpp | 177 +++++++------- .../library/src/simulation/DramRecordable.cpp | 48 ++-- .../library/src/simulation/DramRecordable.h | 4 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 217 +++++++++--------- 7 files changed, 351 insertions(+), 323 deletions(-) diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index bc5ae253..36f1fa5c 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -56,7 +56,6 @@ #include "../common/utils.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -using namespace std; using namespace tlm; using namespace Data; @@ -71,23 +70,31 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") Dram::~Dram() { - if (!Configuration::getInstance().DatabaseRecording) - DRAMPower->calcEnergy(); + if (Configuration::getInstance().PowerAnalysis) + { + libDRAMPower *DRAMPower = dynamic_cast(this->DRAMPower); + if (DRAMPower == nullptr) + SC_REPORT_FATAL("Dram", "Power Analysis active but libDRAMPowerIF instantiated"); - // Print the final total energy and the average power for - // the simulation: - cout << name() << string(" Total Energy: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" pJ") - << endl; + if (!Configuration::getInstance().DatabaseRecording) + DRAMPower->calcEnergy(); - cout << name() << string(" Average Power: ") - << fixed << std::setprecision( 2 ) - << DRAMPower->getPower().average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM - << string(" mW") << endl; + // Print the final total energy and the average power for + // the simulation: + std::cout << name() << std::string(" Total Energy: ") + << std::fixed << std::setprecision( 2 ) + << DRAMPower->getEnergy().total_energy + * Configuration::getInstance().NumberOfDevicesOnDIMM + << std::string(" pJ") + << std::endl; + + std::cout << name() << std::string(" Average Power: ") + << std::fixed << std::setprecision( 2 ) + << DRAMPower->getPower().average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM + << std::string(" mW") << std::endl; + } + delete DRAMPower; if (Configuration::getInstance().UseMalloc) free(memory); @@ -96,8 +103,6 @@ Dram::~Dram() tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - MemSpec *memSpec = Configuration::getInstance().memSpec; - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 4ae01c33..48208e92 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -45,6 +45,7 @@ #include #include "../common/protocol.h" #include "../controller/core/configuration/Configuration.h" +#include "../controller/core/configuration/MemSpec.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; @@ -60,11 +61,16 @@ private: bool powerAnalysis = Configuration::getInstance().PowerAnalysis; protected: + Dram(sc_module_name); + SC_HAS_PROCESS(Dram); + + MemSpec *memSpec = Configuration::getInstance().memSpec; + // Data Storage: StorageMode StoreMode = Configuration::getInstance().StoreMode; unsigned char *memory; - libDRAMPower *DRAMPower; + libDRAMPowerIF *DRAMPower; virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay); @@ -77,9 +83,6 @@ protected: public: tlm_utils::simple_target_socket tSocket; - Dram(sc_module_name); - SC_HAS_PROCESS(Dram); - virtual ~Dram(); }; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 7b91109d..7655a1dd 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -38,6 +38,7 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../controller/core/configuration/MemSpec.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { @@ -45,97 +46,102 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); // Parameters for DRAMPower - MemSpecDDR3 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; + if (Configuration::getInstance().PowerAnalysis) + { + sc_time clk = memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD / clk; - memTimingSpec.CCD_L = memSpec->tCCD / clk; - memTimingSpec.CCD_S = memSpec->tCCD / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tFAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD / clk; - memTimingSpec.RRD_L = memSpec->tRRD / clk; - memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tFAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR / clk; - memTimingSpec.WTR_L = memSpec->tWTR / clk; - memTimingSpec.WTR_S = memSpec->tWTR / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD / clk; + memTimingSpec.CCD_L = memSpec->tCCD / clk; + memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tFAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD / clk; + memTimingSpec.RRD_L = memSpec->tRRD / clk; + memTimingSpec.RRD_S = memSpec->tRRD / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tFAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR / clk; + memTimingSpec.WTR_L = memSpec->tWTR / clk; + memTimingSpec.WTR_S = memSpec->tWTR / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, 0); + } + else + DRAMPower = new libDRAMPowerIF(); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 9f8e85d6..282225c5 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -38,6 +38,7 @@ #include "Dram.h" #include "../controller/core/configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../controller/core/configuration/MemSpec.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { @@ -45,98 +46,102 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); // Parameters for DRAMPower - MemSpecDDR4 *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; + if (Configuration::getInstance().PowerAnalysis) + { + sc_time clk = memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tFAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD_S / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tFAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tFAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD_S / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tFAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + DRAMPower = new libDRAMPower(powerSpec, 0); + } + else + DRAMPower = new libDRAMPowerIF(); } diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index c54e255d..fa131a8e 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -50,14 +50,25 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe { // Create a thread that is triggered every $powerWindowSize // to generate a Power over Time plot in the Trace analyzer: - SC_THREAD(powerWindow); + if (Configuration::getInstance().PowerAnalysis) + { + DRAMPower = dynamic_cast(Dram::DRAMPower); + if (DRAMPower == nullptr) + SC_REPORT_FATAL("DramRecordable", "Power Analysis active but libDRAMPowerIF instantiated"); + SC_THREAD(powerWindow); + } } template DramRecordable::~DramRecordable() { - this->DRAMPower->calcEnergy(); - recordPower(); + if (Configuration::getInstance().PowerAnalysis) + { + DRAMPower->calcEnergy(); + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + DRAMPower->getPower().window_average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM); + } tlmRecorder->closeConnection(); } @@ -65,18 +76,17 @@ template tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - MemSpec *memSpec = Configuration::getInstance().memSpec; // Recording time used by the traceAnalyzer sc_time recTime = sc_time_stamp() + delay; // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += memSpec->getExecutionTime(Command::PDXA, payload); + recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += memSpec->getExecutionTime(Command::PDXP, payload); + recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); else if (phase == END_SREF || phase == END_SREFB) - recTime += memSpec->getExecutionTime(Command::SREFEX, payload); + recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); @@ -106,37 +116,29 @@ void DramRecordable::powerWindow() // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clkCycles = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); + clkCycles = sc_time_stamp().value() / this->memSpec->clk.value(); - this->DRAMPower->calcWindowEnergy(clkCycles); + DRAMPower->calcWindowEnergy(clkCycles); // During operation the energy should never be zero since the device is always consuming - assert(!isEqual(this->DRAMPower->getEnergy().window_energy, 0.0)); + assert(!isEqual(DRAMPower->getEnergy().window_energy, 0.0)); // Store the time (in seconds) and the current average power (in mW) into the database - recordPower(); + tlmRecorder->recordPower(sc_time_stamp().to_seconds(), + DRAMPower->getPower().window_average_power + * Configuration::getInstance().NumberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW PRINTDEBUGMESSAGE(this->name(), string("\tWindow Energy: \t") + to_string( - this->DRAMPower->getEnergy().window_energy * + DRAMPower->getEnergy().window_energy * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[pJ]")); PRINTDEBUGMESSAGE(this->name(), string("\tWindow Average Power: \t") + to_string( - this->DRAMPower->getPower().window_average_power * + DRAMPower->getPower().window_average_power * Configuration::getInstance().NumberOfDevicesOnDIMM) + string("\t[mW]")); } while (true); } -template -void DramRecordable::recordPower() -{ - tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().NumberOfDevicesOnDIMM); -} - - template class DramRecordable; template class DramRecordable; template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/DramRecordable.h index aa09e778..df518bdc 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/DramRecordable.h @@ -57,6 +57,8 @@ private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay); TlmRecorder *tlmRecorder; + + libDRAMPower *DRAMPower; sc_time powerWindowSize = Configuration::getInstance().memSpec->clk * Configuration::getInstance().WindowSize; @@ -71,8 +73,6 @@ private: // This Thread is only triggered when Power Simulation is enabled. // It estimates the current average power which will be stored in the trace database for visualization purposes. void powerWindow(); - - void recordPower(); }; #endif // DRAMRECORDABLE_H diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 65cdeacb..dbc5b8fa 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -41,121 +41,131 @@ #include "../controller/core/configuration/Configuration.h" #include "../error/errormodel.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../controller/core/configuration/MemSpec.h" using namespace tlm; DramWideIO::DramWideIO(sc_module_name name) : Dram(name) { - // For each bank in a channel a error Model is created: - if (StoreMode == StorageMode::ErrorModel) - { - if (Configuration::getInstance().UseMalloc) - free(memory); - - for (unsigned i = 0; i < Configuration::getInstance().memSpec->NumberOfBanks; - i++) - { - errorModel *em; - std::string errorModelStr = "errorModel_bank" + std::to_string(i); - em = new errorModel(errorModelStr.c_str(), DRAMPower); - ememory.push_back(em); - } - } - // Parameters for DRAMPower - MemSpecWideIO *memSpec = dynamic_cast(Configuration::getInstance().memSpec); + MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; + if (Configuration::getInstance().PowerAnalysis) + { + sc_time clk = memSpec->clk; - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD / clk; - memTimingSpec.CCD_L = memSpec->tCCD / clk; - memTimingSpec.CCD_S = memSpec->tCCD / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tTAW / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI / clk; - memTimingSpec.RFC = memSpec->tRFC / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP / clk; - memTimingSpec.RRD = memSpec->tRRD / clk; - memTimingSpec.RRD_L = memSpec->tRRD / clk; - memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tTAW / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR / clk; - memTimingSpec.WTR_L = memSpec->tWTR / clk; - memTimingSpec.WTR_S = memSpec->tWTR / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXP / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXS / clk; + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD / clk; + memTimingSpec.CCD_L = memSpec->tCCD / clk; + memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tTAW / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI / clk; + memTimingSpec.RFC = memSpec->tRFC / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP / clk; + memTimingSpec.RRD = memSpec->tRRD / clk; + memTimingSpec.RRD_L = memSpec->tRRD / clk; + memTimingSpec.RRD_S = memSpec->tRRD / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tTAW / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR / clk; + memTimingSpec.WTR_L = memSpec->tWTR / clk; + memTimingSpec.WTR_S = memSpec->tWTR / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXP / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXS / clk; - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + libDRAMPower *DRAMPower = new libDRAMPower(powerSpec, 0); + + // For each bank in a channel a error Model is created: + if (StoreMode == StorageMode::ErrorModel) + { + if (Configuration::getInstance().UseMalloc) + free(memory); + + for (unsigned i = 0; i < memSpec->NumberOfBanks; i++) + { + errorModel *em; + std::string errorModelStr = "errorModel_bank" + std::to_string(i); + em = new errorModel(errorModelStr.c_str(), DRAMPower); + ememory.push_back(em); + } + } + this->DRAMPower = DRAMPower; + } + else + { + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramWideIO", "Error modeling without power analysis is not supported"); + DRAMPower = new libDRAMPowerIF(); + } } DramWideIO::~DramWideIO() @@ -168,13 +178,10 @@ DramWideIO::~DramWideIO() tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay) { - MemSpec *memSpec = Configuration::getInstance().memSpec; - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value() / - Configuration::getInstance().memSpec->clk.value(); + unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); if (phase == BEGIN_PREB) { From 8115aba222c91c5e979d51f5cbf80ad6424ce414 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 18 Aug 2019 19:56:17 +0200 Subject: [PATCH 075/183] Fixed wrong PRE -<> PREA test in TraceAnalyzer. --- DRAMSys/traceAnalyzer/scripts/tests.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index c38e1d2d..6b2877ca 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -321,7 +321,7 @@ def timing_constraint(FirstPhase, SecondPhase): FirstPhaseName = FirstPhase[0] SecondPhaseName = SecondPhase[0] - if (FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL"): + if ((FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL") and SecondPhaseName != "PRE_ALL"): return dramconfig.tRP elif (FirstPhaseName == "ACT"): From 3f7296f2a5dadc6c9077276830daf04c8fa0bd2e Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 19 Aug 2019 11:16:27 +0200 Subject: [PATCH 076/183] Removed RGR timing parameters. --- .../core/configuration/Configuration.cpp | 36 ------------------- .../core/configuration/Configuration.h | 14 -------- DRAMSys/library/src/simulation/DramDDR3.cpp | 14 ++++---- DRAMSys/library/src/simulation/DramDDR4.cpp | 14 ++++---- DRAMSys/library/src/simulation/DramWideIO.cpp | 14 ++++---- 5 files changed, 21 insertions(+), 71 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index 7e7000b6..03210066 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -236,18 +236,6 @@ void Configuration::setParameter(std::string name, std::string value) RGRB14 = string2bool(value); else if (name == "ControllerCoreRGRB15") RGRB15 = string2bool(value); - else if (name == "ControllerCoreRGRtRASBInClkCycles") - trasbclk = string2int(value); - else if (name == "ControllerCoreRGRtRRDB_LInClkCycles") - trrdblclk = string2int(value); - else if (name == "ControllerCoreRGRtRRDB_SInClkCycles") - trrdbsclk = string2int(value); - else if (name == "ControllerCoreRGRtRPBInClkCycles") - trpbclk = string2int(value); - else if (name == "ControllerCoreRGRtRCBInClkCycles") - trcbclk = string2int(value); - else if (name == "ControllerCoreRGRtFAWBInClkCycles") - tfawbclk = string2int(value); else if (name == "ControllerCoreRefForceMaxPostponeBurst") ControllerCoreRefForceMaxPostponeBurst = string2bool(value); else if (name == "ControllerCoreRefEnablePostpone") { @@ -401,30 +389,6 @@ unsigned int Configuration::getBytesPerBurst() return bytesPerBurst; } -sc_time Configuration::getTrasb() -{ - return trasbclk * memSpec->clk; -} -sc_time Configuration::getTrrdb_L() -{ - return trrdblclk * memSpec->clk; -} -sc_time Configuration::getTrrdb_S() -{ - return trrdbsclk * memSpec->clk; -} -sc_time Configuration::getTrpb() -{ - return trpbclk * memSpec->clk; -} -sc_time Configuration::getTrcb() -{ - return trcbclk * memSpec->clk; -} -sc_time Configuration::getTfawb() -{ - return tfawbclk * memSpec->clk; -} bool Configuration::getRGRBank(unsigned int w) { bool flg = w == 0 ? RGRB0 : w == 1 ? RGRB1 : w == 2 ? RGRB2 : w == 3 ? RGRB3 : w diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index fe09ecda..d17c2a95 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -88,20 +88,6 @@ struct Configuration unsigned int NumberOfMemChannels = 1; bool ControllerCoreRefDisable = false; bool RowGranularRef = false; - // TODO: will be removed in the future - unsigned int trasbclk = 0; - sc_time getTrasb(); - unsigned int trrdblclk = 0; - sc_time getTrrdb_L(); - unsigned int trrdbsclk = 0; - sc_time getTrrdb_S(); - unsigned int trpbclk = 0; - sc_time getTrpb(); - unsigned int trcbclk = 0; - sc_time getTrcb(); - unsigned int tfawbclk = 0; - sc_time getTfawb(); - // ----------------------------------- bool RGRB0 = true; bool RGRB1 = true; bool RGRB2 = true; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 7655a1dd..1b8f18c5 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -67,13 +67,13 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memArchSpec.dll = memSpec->DLL; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.FAWB = memSpec->tFAW / clk; + memTimingSpec.RASB = memSpec->tRAS / clk; + memTimingSpec.RCB = memSpec->tRC / clk; + memTimingSpec.RPB = memSpec->tRP / clk; + memTimingSpec.RRDB = memSpec->tRRD / clk; + memTimingSpec.RRDB_L = memSpec->tRRD / clk; + memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD / clk; memTimingSpec.CCD_L = memSpec->tCCD / clk; diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 282225c5..4d3a5781 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -67,13 +67,13 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memArchSpec.dll = memSpec->DLL; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.FAWB = memSpec->tFAW / clk; + memTimingSpec.RASB = memSpec->tRAS / clk; + memTimingSpec.RCB = memSpec->tRC / clk; + memTimingSpec.RPB = memSpec->tRP / clk; + memTimingSpec.RRDB = memSpec->tRRD_S / clk; + memTimingSpec.RRDB_L = memSpec->tRRD_L / clk; + memTimingSpec.RRDB_S = memSpec->tRRD_S / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD_S / clk; memTimingSpec.CCD_L = memSpec->tCCD_L / clk; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index dbc5b8fa..de3d902e 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -69,13 +69,13 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memArchSpec.dll = memSpec->DLL; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.FAWB = memSpec->tTAW / clk; + memTimingSpec.RASB = memSpec->tRAS / clk; + memTimingSpec.RCB = memSpec->tRC / clk; + memTimingSpec.RPB = memSpec->tRP / clk; + memTimingSpec.RRDB = memSpec->tRRD / clk; + memTimingSpec.RRDB_L = memSpec->tRRD / clk; + memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD / clk; memTimingSpec.CCD_L = memSpec->tCCD / clk; From 35af025d4c513a2ce054116c631de3ddc6b741dd Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 19 Aug 2019 13:51:27 +0200 Subject: [PATCH 077/183] Removed unused configuration parameters, moved some currents and voltages to specific memspecs. --- .../configuration/ConfigurationLoader.cpp | 92 ++++++------------- .../controller/core/configuration/MemSpec.h | 70 +++++++++----- DRAMSys/library/src/simulation/DramDDR3.cpp | 28 +++--- DRAMSys/library/src/simulation/DramDDR4.cpp | 22 ++--- DRAMSys/library/src/simulation/DramWideIO.cpp | 4 +- 5 files changed, 100 insertions(+), 116 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index 7eec9599..cf7bfaa4 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -181,7 +181,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); @@ -196,7 +196,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tCL = clk * queryUIntParameter(timings, "CL"); memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); memSpec->tRC = clk * queryUIntParameter(timings, "RC"); @@ -207,6 +206,17 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->tWR = clk * queryUIntParameter(timings, "WR"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + + // Currents and voltages + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); } void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) @@ -216,12 +226,9 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture - //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = 1; - memSpec->nActivate = 4; - memSpec->DLL = true; - memSpec->termination = true; + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->NumberOfBankGroups = 1; // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -243,21 +250,10 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // Currents and Volatages: TODO Check if this is correct. XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - memSpec->iDD02 = 0; memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - memSpec->iDD62 = 0; - memSpec->vDD = queryDoubleParameter(powers, "vdd"); - memSpec->vDD2 = 0; } void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) @@ -268,11 +264,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); - memSpec->nActivate = 4; - memSpec->DLL = true; - memSpec->termination = true; // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -286,8 +279,10 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); else if (refMode == 2) memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2"); - else // if (refMode == 4) + else if (refMode == 4) memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4"); + else + SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); @@ -303,20 +298,12 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); - memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); - memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } @@ -328,12 +315,9 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture: - //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = 1; - memSpec->nActivate = 4; - memSpec->DLL = false; // TODO: Correct? - memSpec->termination = true; // TODO: Correct? + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->NumberOfBankGroups = 1; // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -359,20 +343,12 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); - memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); - memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); - memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); - memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); + memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); + memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); + memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } @@ -383,12 +359,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemSpecification - //XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); - //memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO - memSpec->NumberOfBankGroups = 1; - memSpec->nActivate = 2; - memSpec->DLL = false; - memSpec->termination = false; + memSpec->NumberOfRanks = 1; + memSpec->NumberOfBankGroups = 1; // MemTimings specific for WideIO XMLElement *timings = memspec->FirstChildElement("memtimingspec"); @@ -408,28 +380,20 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); - memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12"); - memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2"); memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02"); memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1"); memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12"); - memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2"); - memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2"); - memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2"); - memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); memSpec->iDD52 = queryDoubleParameter(powers, "idd52"); - memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 2cc6550a..dd2c204d 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -43,6 +43,8 @@ #include "../../../common/dramExtensions.h" #include "../../Command.h" +using namespace tlm; + struct RefreshTiming { RefreshTiming() {} @@ -63,7 +65,7 @@ struct MemSpec // Returns the minimum execution time for commands that have a variable execution time sc_time getMinExecutionTimeForPowerDownCmd(Command command) const; - virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; + virtual sc_time getExecutionTime(Command command, tlm_generic_payload &payload) const; std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; @@ -71,23 +73,17 @@ struct MemSpec unsigned int NumberOfBanks; unsigned int NumberOfRanks; unsigned int BurstLength; - unsigned int nActivate; unsigned int DataRate; unsigned int NumberOfRows; unsigned int NumberOfColumns; unsigned int bitWidth; unsigned int NumberOfBankGroups; - bool DLL; - bool termination; // Memspec Variables: double clkMHz; sc_time clk; - sc_time tAL; // additive delay (delayed execution in dram) sc_time tCKE; // min time in pdna or pdnp sc_time tCKESR; // min time in sref - sc_time tCL; // unused, will be used in the future - sc_time tDQSCK; sc_time tRAS; // active-time (act -> pre same bank) sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) sc_time tRCD; // act -> read/write @@ -100,33 +96,19 @@ struct MemSpec sc_time tREFI; sc_time tRFC; sc_time tRP; + // only used in DRAMPower + sc_time tAL; // additive delay (delayed execution in dram) + sc_time tDQSCK; // Currents and Voltages: double iDD0; - double iDD02; - double iDD2P0; - double iDD2P02; - double iDD2P1; - double iDD2P12; double iDD2N; - double iDD2N2; - double iDD3P0; - double iDD3P02; - double iDD3P1; - double iDD3P12; double iDD3N; - double iDD3N2; double iDD4R; - double iDD4R2; double iDD4W; - double iDD4W2; double iDD5; - double iDD52; double iDD6; - double iDD62; double vDD; - double vDD2; - std::map refreshTimings; //ensure that map is populated completely in memspecloader @@ -142,6 +124,11 @@ struct MemSpecDDR3 : public MemSpec sc_time tWTR; sc_time tXPDLL; sc_time tXSDLL; + + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; }; struct MemSpecDDR4 : public MemSpec @@ -155,6 +142,14 @@ struct MemSpecDDR4 : public MemSpec sc_time tWTR_L; sc_time tXPDLL; sc_time tXSDLL; + + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; }; struct MemSpecLPDDR4 : public MemSpec @@ -170,7 +165,15 @@ struct MemSpecLPDDR4 : public MemSpec sc_time tRPAB; sc_time tRRD; - virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override; + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; + + virtual sc_time getExecutionTime(Command command, tlm_generic_payload &payload) const override; }; struct MemSpecWideIO : public MemSpec @@ -179,6 +182,23 @@ struct MemSpecWideIO : public MemSpec sc_time tRRD; sc_time tTAW; sc_time tWTR; + + double iDD02; + double iDD2P0; + double iDD2P02; + double iDD2P1; + double iDD2P12; + double iDD2N2; + double iDD3P0; + double iDD3P02; + double iDD3P1; + double iDD3P12; + double iDD3N2; + double iDD4R2; + double iDD4W2; + double iDD52; + double iDD62; + double vDD2; }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 1b8f18c5..1dc1ef3d 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -63,8 +63,8 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; memArchSpec.width = memSpec->bitWidth; memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + memArchSpec.twoVoltageDomains = false; + memArchSpec.dll = true; MemTimingSpec memTimingSpec; memTimingSpec.FAWB = memSpec->tFAW / clk; @@ -109,29 +109,29 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) MemPowerSpec memPowerSpec; memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd02 = 0; memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p02 = 0; memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2p12 = 0; memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd2n2 = 0; memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p02 = 0; memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3p12 = 0; memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd3n2 = 0; memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4r2 = 0; memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd4w2 = 0; memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd52 = 0; memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.idd62 = 0; memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; + memPowerSpec.vdd2 = 0; MemorySpecification powerSpec; powerSpec.id = memSpec->MemoryId; diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 4d3a5781..321a435a 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -63,8 +63,8 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; memArchSpec.width = memSpec->bitWidth; memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + memArchSpec.twoVoltageDomains = true; + memArchSpec.dll = true; MemTimingSpec memTimingSpec; memTimingSpec.FAWB = memSpec->tFAW / clk; @@ -111,23 +111,23 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memPowerSpec.idd0 = memSpec->iDD0; memPowerSpec.idd02 = memSpec->iDD02; memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p02 = 0; memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2p12 = 0; memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd2n2 = 0; memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p02 = 0; memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3p12 = 0; memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd3n2 = 0; memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4r2 = 0; memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd4w2 = 0; memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd52 = 0; memPowerSpec.idd6 = memSpec->iDD6; memPowerSpec.idd62 = memSpec->iDD62; memPowerSpec.vdd = memSpec->vDD; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index de3d902e..5f242226 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -65,8 +65,8 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; memArchSpec.width = memSpec->bitWidth; memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; + memArchSpec.twoVoltageDomains = true; + memArchSpec.dll = false; MemTimingSpec memTimingSpec; memTimingSpec.FAWB = memSpec->tTAW / clk; From 7c87b954ec850df1d5251ed91762cfcf4474a60f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 19 Aug 2019 15:11:49 +0200 Subject: [PATCH 078/183] Removed different refresh timings for different banks, removed ORGR parameters from mcconfigs. --- .../resources/configs/mcconfigs/fifo.xml | 7 --- .../configs/mcconfigs/fifoStrict.xml | 7 --- .../resources/configs/mcconfigs/fifo_ecc.xml | 7 --- .../resources/configs/mcconfigs/fr_fcfs.xml | 7 --- .../configs/mcconfigs/fr_fcfs_bw_buffer16.xml | 7 --- .../fr_fcfs_bw_buffer16_close_page.xml | 7 --- .../configs/mcconfigs/fr_fcfs_grp.xml | 7 --- .../mcconfigs/fr_fcfs_nbw_buffer16.xml | 16 ------- .../fr_fcfs_nbw_buffer16_close_page.xml | 7 --- .../configs/mcconfigs/fr_fcfs_rp.xml | 7 --- .../resources/configs/mcconfigs/grp.xml | 7 --- .../resources/configs/mcconfigs/par_bs.xml | 7 --- .../resources/configs/mcconfigs/rgrmccfg.xml | 7 --- .../resources/configs/mcconfigs/sms.xml | 7 --- .../configuration/ConfigurationLoader.cpp | 46 +++++-------------- .../controller/core/configuration/MemSpec.cpp | 14 +++--- .../controller/core/configuration/MemSpec.h | 13 +----- 17 files changed, 19 insertions(+), 161 deletions(-) diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml index d01b9248..fc05a577 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml index ed869b57..bc54f607 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml index d01b9248..fc05a577 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifo_ecc.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml index 20db08cd..bcaf76dd 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml index 61221894..d92d32da 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16.xml @@ -33,13 +33,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml index ff37370c..d4aa4a4c 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_bw_buffer16_close_page.xml @@ -33,13 +33,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml index dad77bf6..042cc5fb 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml index d6410aea..7cb5befd 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16.xml @@ -17,22 +17,6 @@ - - - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml index c8dd13c2..aa65b3ff 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_nbw_buffer16_close_page.xml @@ -33,13 +33,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml index 3f636ba0..4c0b43c6 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rp.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/grp.xml b/DRAMSys/library/resources/configs/mcconfigs/grp.xml index 753cca46..8b34759d 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/grp.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/grp.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml index 478ec618..aaec39ca 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/par_bs.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml index b17e59ce..2f8fb337 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/rgrmccfg.xml @@ -33,13 +33,6 @@ - - - - - - - diff --git a/DRAMSys/library/resources/configs/mcconfigs/sms.xml b/DRAMSys/library/resources/configs/mcconfigs/sms.xml index e1ccb478..3d9433da 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/sms.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/sms.xml @@ -34,13 +34,6 @@ - - - - - - - diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index cf7bfaa4..76b0b971 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -115,17 +115,16 @@ void ConfigurationLoader::loadMCConfig(Configuration &config, void ConfigurationLoader::loadMCConfig(Configuration &config, XMLElement *mcconfig) { - if (mcconfig->Attribute("src")) { + if (mcconfig->Attribute("src")) + { XMLDocument doc; string src(mcconfig->Attribute("src")); config.mcconfigUri = src; loadXML(src, doc); loadMCConfig(config, doc.FirstChildElement("mcconfig")); - } else { - loadConfig(config, mcconfig); } - - + else + loadConfig(config, mcconfig); } void ConfigurationLoader::loadMemSpec(Configuration &config, string memspecUri) @@ -143,32 +142,30 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, string memoryType = queryStringParameter(memspec, "memoryType"); if (memoryType == "DDR4") { - Configuration::getInstance().memSpec = new MemSpecDDR4; + Configuration::getInstance().memSpec = new MemSpecDDR4(); loadCommons(config, memspec); loadDDR4(config, memspec); } else if (memoryType == "DDR3") { - Configuration::getInstance().memSpec = new MemSpecDDR3; + Configuration::getInstance().memSpec = new MemSpecDDR3(); loadCommons(config, memspec); loadDDR3(config, memspec); } else if (memoryType == "LPDDR4") { - Configuration::getInstance().memSpec = new MemSpecLPDDR4; + Configuration::getInstance().memSpec = new MemSpecLPDDR4(); loadCommons(config, memspec); loadLPDDR4(config, memspec); } else if (memoryType == "WIDEIO_SDR") { - Configuration::getInstance().memSpec = new MemSpecWideIO; + Configuration::getInstance().memSpec = new MemSpecWideIO(); loadCommons(config, memspec); loadWideIO(config, memspec); } else - { reportFatal("ConfigurationLoader", "Unsupported DRAM type"); - } } void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec) @@ -181,7 +178,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); @@ -243,11 +239,6 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, - memSpec->tREFI); - // Currents and Volatages: TODO Check if this is correct. XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); @@ -272,8 +263,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) sc_time clk = memSpec->clk; memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); unsigned refMode = Configuration::getInstance().getRefMode(); if (refMode == 1) memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); @@ -283,7 +274,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4"); else SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported"); - memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S"); memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); @@ -291,11 +282,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, - memSpec->tREFI); - // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); @@ -336,11 +322,6 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFCPB, - memSpec->tREFIPB); - // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); @@ -373,11 +354,6 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - memSpec->refreshTimings.clear(); - for (unsigned int i = 0; i < memSpec->NumberOfBanks; ++i) - memSpec->refreshTimings[Bank(i)] = RefreshTiming(memSpec->tRFC, - memSpec->tREFI); - // Currents and Volatages: XMLElement *powers = memspec->FirstChildElement("mempowerspec"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index 30e8dd04..e94b1bbd 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -40,6 +40,8 @@ #include "../../Command.h" #include "Configuration.h" +using namespace tlm; + const std::vector &MemSpec::getBanks() const { static std::vector banks; @@ -76,7 +78,7 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const // Returns the execution time for commands that have a fixed execution time // TODO: override this method for different MemSpecs? -sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const +sc_time MemSpec::getExecutionTime(Command command, tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -93,8 +95,7 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) - return getElementFromMap(refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC; + return tRFC; else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) return clk; else @@ -105,7 +106,7 @@ sc_time MemSpec::getExecutionTime(Command command, tlm::tlm_generic_payload &pay } } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm_generic_payload &) const { if (command == Command::PRE) return tRP; @@ -124,10 +125,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm::tlm_generic_payloa else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) - { - return getElementFromMap(refreshTimings, - DramExtension::getExtension(payload).getBank()).tRFC; - } + return tRFCPB; else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) return clk; else diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index dd2c204d..059b78cb 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -45,15 +45,6 @@ using namespace tlm; -struct RefreshTiming -{ - RefreshTiming() {} - RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {} - - sc_time tRFC; - sc_time tREFI; -}; - struct MemSpec { const std::vector &getBanks() const; @@ -110,8 +101,8 @@ struct MemSpec double iDD6; double vDD; - std::map refreshTimings; - //ensure that map is populated completely in memspecloader + // For different refresh frequencies on different banks, not implemented + //std::map refreshTimings; virtual ~MemSpec() {} }; From cbeaef32de21e828bbc3b9a7ded89070e9bd6fc6 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 19 Aug 2019 16:17:31 +0200 Subject: [PATCH 079/183] Removed specific memspec dependency in RefreshManager, changed RefreshChecker to RefreshCheckerDDR3. --- .../library/src/controller/ControllerNew.cpp | 2 +- .../src/controller/ControllerRecordable.cpp | 2 +- .../src/controller/checker/CheckerDDR3.cpp | 30 +++++++++---------- .../src/controller/checker/CheckerDDR3.h | 22 +++++++------- .../controller/core/configuration/MemSpec.cpp | 4 +-- .../controller/core/configuration/MemSpec.h | 4 +-- .../src/controller/refresh/RefreshManager.cpp | 12 +++----- .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 4 +-- .../refresh/RefreshManagerBankwise.h | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 30 +++++++------------ .../library/src/simulation/DramRecordable.cpp | 6 ++-- DRAMSys/library/src/simulation/DramWideIO.cpp | 30 +++++++------------ 13 files changed, 64 insertions(+), 86 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 82d8074a..e20139a0 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -254,7 +254,7 @@ void ControllerNew::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) { - sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); + sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command); ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); checker->insert(scheduledCommand); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 218d221a..c522aead 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -62,7 +62,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl { if (command == Command::RD || command == Command::WR) { - sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command, *payload); + sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command); ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index ebc5213a..fb8bee41 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -42,11 +42,11 @@ CheckerDDR3::CheckerDDR3() SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); if (config.ControllerCoreRefDisable) - refreshChecker = new RefreshCheckerDummy(); + refreshChecker = new RefreshCheckerDDR3Dummy(); else if (config.BankwiseLogic) - refreshChecker = new RefreshCheckerBankwise(); + refreshChecker = new RefreshCheckerDDR3Bankwise(); else - refreshChecker = new RefreshChecker(); + refreshChecker = new RefreshCheckerDDR3(); } CheckerDDR3::~CheckerDDR3() @@ -182,39 +182,39 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); } - +//------------------------------------------------------------------------- // TODO: max(earliestTimeToStart, ...) needed? -void RefreshChecker::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= timeForNextPREA) earliestTimeToStart = timeForNextREFA + memSpec->tRFC; } -void RefreshChecker::insert(Bank) +void RefreshCheckerDDR3::insert(Bank) { timeForNextREFA += memSpec->tREFI; timeForNextPREA += memSpec->tREFI; } - -RefreshCheckerBankwise::RefreshCheckerBankwise() +//------------------------------------------------------------------------ +RefreshCheckerDDR3Bankwise::RefreshCheckerDDR3Bankwise() { sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); @@ -227,25 +227,25 @@ RefreshCheckerBankwise::RefreshCheckerBankwise() } } -void RefreshCheckerBankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRAS)) earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; } -void RefreshCheckerBankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRTP)) earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; } -void RefreshCheckerBankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) +void RefreshCheckerDDR3Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) { if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; } -void RefreshCheckerBankwise::insert(Bank bank) +void RefreshCheckerDDR3Bankwise::insert(Bank bank) { timesForNextREFB[bank] += memSpec->tREFI; timesForNextPRE[bank] += memSpec->tREFI; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 36cf8577..f4361425 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -41,7 +41,7 @@ #include "../core/configuration/MemSpec.h" #include "../core/configuration/Configuration.h" -class RefreshCheckerIF; +class RefreshCheckerDDR3IF; class CheckerDDR3 final : public CheckerIF { @@ -61,24 +61,24 @@ private: sc_time timeForNextREFA; sc_time timeForNextPREA; - RefreshCheckerIF *refreshChecker; + RefreshCheckerDDR3IF *refreshChecker; // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; -class RefreshCheckerIF +class RefreshCheckerDDR3IF { protected: friend class CheckerDDR3; - RefreshCheckerIF() + RefreshCheckerDDR3IF() { Configuration config = Configuration::getInstance(); memSpec = dynamic_cast(config.memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); } - virtual ~RefreshCheckerIF() {} + virtual ~RefreshCheckerDDR3IF() {} virtual void delayToSatisfyACT(Bank, sc_time &) = 0; virtual void delayToSatisfyRD(Bank, sc_time &) = 0; @@ -89,11 +89,11 @@ protected: const MemSpecDDR3 *memSpec; }; -class RefreshCheckerDummy final : public RefreshCheckerIF +class RefreshCheckerDDR3Dummy final : public RefreshCheckerDDR3IF { private: friend class CheckerDDR3; - RefreshCheckerDummy() {} + RefreshCheckerDDR3Dummy() {} void delayToSatisfyACT(Bank, sc_time &) {} void delayToSatisfyRD(Bank, sc_time &) {} @@ -102,11 +102,11 @@ private: void insert(Bank) {} }; -class RefreshChecker final : public RefreshCheckerIF +class RefreshCheckerDDR3 final : public RefreshCheckerDDR3IF { private: friend class CheckerDDR3; - RefreshChecker() {} + RefreshCheckerDDR3() {} void delayToSatisfyACT(Bank, sc_time &); void delayToSatisfyRD(Bank, sc_time &); @@ -118,11 +118,11 @@ private: sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; }; -class RefreshCheckerBankwise final : public RefreshCheckerIF +class RefreshCheckerDDR3Bankwise final : public RefreshCheckerDDR3IF { private: friend class CheckerDDR3; - RefreshCheckerBankwise(); + RefreshCheckerDDR3Bankwise(); void delayToSatisfyACT(Bank, sc_time &); void delayToSatisfyRD(Bank, sc_time &); diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index e94b1bbd..53ee7588 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -78,7 +78,7 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const // Returns the execution time for commands that have a fixed execution time // TODO: override this method for different MemSpecs? -sc_time MemSpec::getExecutionTime(Command command, tlm_generic_payload &) const +sc_time MemSpec::getExecutionTime(Command command) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -106,7 +106,7 @@ sc_time MemSpec::getExecutionTime(Command command, tlm_generic_payload &) const } } -sc_time MemSpecLPDDR4::getExecutionTime(Command command, tlm_generic_payload &) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command) const { if (command == Command::PRE) return tRP; diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 059b78cb..26f3197f 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -56,7 +56,7 @@ struct MemSpec // Returns the minimum execution time for commands that have a variable execution time sc_time getMinExecutionTimeForPowerDownCmd(Command command) const; - virtual sc_time getExecutionTime(Command command, tlm_generic_payload &payload) const; + virtual sc_time getExecutionTime(Command) const; std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; @@ -164,7 +164,7 @@ struct MemSpecLPDDR4 : public MemSpec double iDD62; double vDD2; - virtual sc_time getExecutionTime(Command command, tlm_generic_payload &payload) const override; + virtual sc_time getExecutionTime(Command) const override; }; struct MemSpecWideIO : public MemSpec diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 67c987d4..494e8983 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -39,13 +39,9 @@ RefreshManager::RefreshManager(std::map &bankMachines) : bankMachines(bankMachines) { - memSpec = dynamic_cast(Configuration::getInstance().memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - + memSpec = Configuration::getInstance().memSpec; setUpDummy(refreshPayload); - - timeForNextTrigger = memSpec->tREFI - memSpec->tRP; + timeForNextTrigger = memSpec->tREFI - memSpec->getExecutionTime(Command::PREA); } std::pair RefreshManager::getNextCommand() @@ -55,7 +51,7 @@ std::pair RefreshManager::getNextCommand() if (state == RmState::IDLE) { state = RmState::REFRESHING; - timeForNextTrigger += memSpec->tRP; + timeForNextTrigger += memSpec->getExecutionTime(Command::PREA); bool forcedPrecharges = false; for (auto it : bankMachines) forcedPrecharges |= it.second->forcePrecharge(); @@ -67,7 +63,7 @@ std::pair RefreshManager::getNextCommand() else { state = RmState::IDLE; - timeForNextTrigger += (memSpec->tREFI - memSpec->tRP); + timeForNextTrigger += (memSpec->tREFI - memSpec->getExecutionTime(Command::PREA)); return std::pair(Command::REFA, &refreshPayload); } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 801ee5df..953bdef4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -51,7 +51,7 @@ public: private: enum class RmState {IDLE, REFRESHING} state = RmState::IDLE; - const MemSpecDDR3 *memSpec; + const MemSpec *memSpec; std::map &bankMachines; tlm_generic_payload refreshPayload; sc_time timeForNextTrigger; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 2c978461..113e07d0 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -40,9 +40,7 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::map &bankMachines) : bankMachines(bankMachines) { - memSpec = dynamic_cast(Configuration::getInstance().memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); + memSpec = Configuration::getInstance().memSpec; sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index c38d56bd..64102936 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -50,7 +50,7 @@ public: sc_time getTriggerDelay(); private: - const MemSpecDDR3 *memSpec; + const MemSpec *memSpec; std::map &bankMachines; std::map refreshPayloads; std::map triggerTimes; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 36f1fa5c..77dac5ca 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -111,32 +111,28 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PREB) { DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB, - payload)); + sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB)); } else if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, - payload)); + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); } else if (phase == BEGIN_PRE_ALL) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, - delay + memSpec->getExecutionTime(Command::PREA, payload)); + delay + memSpec->getExecutionTime(Command::PREA)); } else if (phase == BEGIN_ACTB) { DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB, - payload)); + sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, - payload)); + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT)); } else if (phase == BEGIN_WR) { @@ -147,8 +143,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, - payload)); + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR)); } else if (phase == BEGIN_RD) { @@ -159,8 +154,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, - payload)); + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD)); } else if (phase == BEGIN_WRA) { @@ -171,8 +165,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, - payload)); + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA)); } else if (phase == BEGIN_RDA) { @@ -183,20 +176,19 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, - payload)); + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA, payload)); + delay + memSpec->getExecutionTime(Command::REFA)); } else if (phase == BEGIN_REFB) { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFA, payload)); + delay + memSpec->getExecutionTime(Command::REFA)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index fa131a8e..e52e679f 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -82,11 +82,11 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); + recTime += this->memSpec->getExecutionTime(Command::PDXA); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); + recTime += this->memSpec->getExecutionTime(Command::PDXP); else if (phase == END_SREF || phase == END_SREFB) - recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); + recTime += this->memSpec->getExecutionTime(Command::SREFEX); unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 5f242226..896f32e8 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -186,26 +186,23 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PREB) { DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB, - payload)); + sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB)); } else if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, - payload)); + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); } else if (phase == BEGIN_PRE_ALL) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL, - delay + memSpec->getExecutionTime(Command::PREA, payload)); + delay + memSpec->getExecutionTime(Command::PREA)); } else if (phase == BEGIN_ACTB) { DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB, - payload)); + sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) ememory[bank]->activate(row); @@ -213,8 +210,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, - payload)); + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -233,8 +229,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, - payload)); + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR)); } else if (phase == BEGIN_RD) { @@ -249,8 +244,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, - payload)); + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD)); } else if (phase == BEGIN_WRA) { @@ -265,8 +259,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, - payload)); + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA)); } else if (phase == BEGIN_RDA) { @@ -281,14 +274,13 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, - payload)); + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA, payload)); + delay + memSpec->getExecutionTime(Command::REFA)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -298,7 +290,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFA, payload)); + delay + memSpec->getExecutionTime(Command::REFA)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) From baa976dac400cd9ba838fa4b2c383c02258955c5 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 20 Aug 2019 09:51:55 +0200 Subject: [PATCH 080/183] Removed unused commands and extended protocol phases. --- DRAMSys/library/src/common/TlmRecorder.cpp | 4 -- DRAMSys/library/src/common/protocol.h | 17 +------- DRAMSys/library/src/controller/Command.cpp | 10 +---- DRAMSys/library/src/controller/Command.h | 5 +-- .../library/src/controller/ControllerNew.cpp | 2 +- DRAMSys/library/src/simulation/Dram.cpp | 40 ++--------------- DRAMSys/library/src/simulation/DramWideIO.cpp | 43 ++----------------- 7 files changed, 12 insertions(+), 109 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index fe9b056e..af1327e5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -249,10 +249,6 @@ void TlmRecorder::setUpTransactionTerminatingPhases() // Refresh Bank transactionTerminatingPhases.push_back(static_cast (END_REFB)); - transactionTerminatingPhases.push_back(static_cast - (END_ACTB)); - transactionTerminatingPhases.push_back(static_cast - (END_PREB)); // Phases for Power Down transactionTerminatingPhases.push_back(static_cast diff --git a/DRAMSys/library/src/common/protocol.h b/DRAMSys/library/src/common/protocol.h index 06af9c30..986ef847 100644 --- a/DRAMSys/library/src/common/protocol.h +++ b/DRAMSys/library/src/common/protocol.h @@ -39,17 +39,11 @@ #define PROTOCOL_H // DRAM Control Phases -DECLARE_EXTENDED_PHASE(BEGIN_PREB); -DECLARE_EXTENDED_PHASE(END_PREB); - DECLARE_EXTENDED_PHASE(BEGIN_PRE); DECLARE_EXTENDED_PHASE(END_PRE); -DECLARE_EXTENDED_PHASE(BEGIN_PRE_ALL); -DECLARE_EXTENDED_PHASE(END_PRE_ALL); - -DECLARE_EXTENDED_PHASE(BEGIN_ACTB); -DECLARE_EXTENDED_PHASE(END_ACTB); +DECLARE_EXTENDED_PHASE(BEGIN_PREA); +DECLARE_EXTENDED_PHASE(END_PREA); DECLARE_EXTENDED_PHASE(BEGIN_ACT); DECLARE_EXTENDED_PHASE(END_ACT); @@ -60,7 +54,6 @@ DECLARE_EXTENDED_PHASE(END_REFA); DECLARE_EXTENDED_PHASE(BEGIN_REFB); DECLARE_EXTENDED_PHASE(END_REFB); - // Phases for Read and Write DECLARE_EXTENDED_PHASE(BEGIN_WR); DECLARE_EXTENDED_PHASE(END_WR); @@ -94,11 +87,5 @@ DECLARE_EXTENDED_PHASE(END_PDNAB); DECLARE_EXTENDED_PHASE(BEGIN_SREFB); DECLARE_EXTENDED_PHASE(END_SREFB); - -//Triggers -DECLARE_EXTENDED_PHASE(REF_TRIGGER); -DECLARE_EXTENDED_PHASE(PDN_TRIGGER); - - #endif // PROTOCOL_H diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index bfef86c0..6259afe8 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -54,15 +54,9 @@ std::string commandToString(Command command) case Command::WRA: return "WRA"; break; - case Command::PREB: - return "PREB"; - break; case Command::PRE: return "PRE"; break; - case Command::ACTB: - return "ACTB"; - break; case Command::ACT: return "ACT"; break; @@ -108,10 +102,8 @@ std::string commandToString(Command command) const std::vector &getAllCommands() { - static std::vector allCommands( { Command::PREB, - Command::PRE, + static std::vector allCommands( { Command::PRE, Command::PREA, - Command::ACTB, Command::ACT, Command::RD, Command::WR, diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index c51c2a67..5ffa8c8c 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -39,12 +39,11 @@ #include #include -enum class Command { +enum class Command +{ NOP, - PREB, PRE, PREA, - ACTB, ACT, RD, WR, diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index e20139a0..4e7290b4 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -269,7 +269,7 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::WR) phase = BEGIN_WR; else if (command == Command::PREA) - phase = BEGIN_PRE_ALL; + phase = BEGIN_PREA; else if (command == Command::REFA) phase = BEGIN_REFA; else if (command == Command::REFB) diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 77dac5ca..092221c3 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -108,27 +108,17 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, // This is only needed for power simulation: unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); - if (phase == BEGIN_PREB) - { - DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB)); - } - else if (phase == BEGIN_PRE) + if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); } - else if (phase == BEGIN_PRE_ALL) + else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - sendToController(payload, END_PRE_ALL, + sendToController(payload, END_PREA, delay + memSpec->getExecutionTime(Command::PREA)); } - else if (phase == BEGIN_ACTB) - { - DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB)); - } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); @@ -199,14 +189,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } - else if (phase == BEGIN_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_PDNP) { DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); @@ -215,14 +197,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } - else if (phase == BEGIN_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_SREF) { DRAMPower->doCommand(MemCommand::SREN, bank, cycle); @@ -231,14 +205,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } - else if (phase == BEGIN_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else { SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 896f32e8..37c4efa0 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -183,30 +183,17 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, // This is only needed for power simulation: unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value(); - if (phase == BEGIN_PREB) - { - DRAMPower->doCommand(MemCommand::PREB, bank, cycle); - sendToController(payload, END_PREB, delay + memSpec->getExecutionTime(Command::PREB)); - } - else if (phase == BEGIN_PRE) + if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); } - else if (phase == BEGIN_PRE_ALL) + else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); - sendToController(payload, END_PRE_ALL, + sendToController(payload, END_PREA, delay + memSpec->getExecutionTime(Command::PREA)); } - else if (phase == BEGIN_ACTB) - { - DRAMPower->doCommand(MemCommand::ACTB, bank, cycle); - sendToController(payload, END_ACTB, delay + memSpec->getExecutionTime(Command::ACTB)); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - if (StoreMode == StorageMode::ErrorModel) - ememory[bank]->activate(row); - } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); @@ -301,14 +288,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } - else if (phase == BEGIN_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNAB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_PDNP) { DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); @@ -317,14 +296,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } - else if (phase == BEGIN_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_PDNPB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else if (phase == BEGIN_SREF) { DRAMPower->doCommand(MemCommand::SREN, bank, cycle); @@ -333,14 +304,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } - else if (phase == BEGIN_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } - else if (phase == END_SREFB) - { - SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"); - } else { SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); From 2ef1c2b18995ca562d7ef751a674a7a43ec7d4ef Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 20 Aug 2019 10:11:56 +0200 Subject: [PATCH 081/183] Removed RefreshCheckerIF, RefreshCheckerDummy is now used as base class. --- .../src/controller/checker/CheckerDDR3.cpp | 13 ++--- .../src/controller/checker/CheckerDDR3.h | 49 ++++++------------- 2 files changed, 22 insertions(+), 40 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index fb8bee41..60d5cf53 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -42,11 +42,11 @@ CheckerDDR3::CheckerDDR3() SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); if (config.ControllerCoreRefDisable) - refreshChecker = new RefreshCheckerDDR3Dummy(); + refreshChecker = new RefreshCheckerDDR3Dummy(memSpec); else if (config.BankwiseLogic) - refreshChecker = new RefreshCheckerDDR3Bankwise(); + refreshChecker = new RefreshCheckerDDR3Bankwise(memSpec); else - refreshChecker = new RefreshCheckerDDR3(); + refreshChecker = new RefreshCheckerDDR3(memSpec); } CheckerDDR3::~CheckerDDR3() @@ -182,7 +182,7 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); } -//------------------------------------------------------------------------- + // TODO: max(earliestTimeToStart, ...) needed? void RefreshCheckerDDR3::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) { @@ -213,8 +213,9 @@ void RefreshCheckerDDR3::insert(Bank) timeForNextREFA += memSpec->tREFI; timeForNextPREA += memSpec->tREFI; } -//------------------------------------------------------------------------ -RefreshCheckerDDR3Bankwise::RefreshCheckerDDR3Bankwise() + +RefreshCheckerDDR3Bankwise::RefreshCheckerDDR3Bankwise(const MemSpecDDR3 *memSpec) + : RefreshCheckerDDR3Dummy(memSpec) { sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index f4361425..b3416ea4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -41,7 +41,7 @@ #include "../core/configuration/MemSpec.h" #include "../core/configuration/Configuration.h" -class RefreshCheckerDDR3IF; +class RefreshCheckerDDR3Dummy; class CheckerDDR3 final : public CheckerIF { @@ -61,52 +61,34 @@ private: sc_time timeForNextREFA; sc_time timeForNextPREA; - RefreshCheckerDDR3IF *refreshChecker; + RefreshCheckerDDR3Dummy *refreshChecker; // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; -class RefreshCheckerDDR3IF +class RefreshCheckerDDR3Dummy { protected: friend class CheckerDDR3; - RefreshCheckerDDR3IF() - { - Configuration config = Configuration::getInstance(); - memSpec = dynamic_cast(config.memSpec); - if (memSpec == nullptr) - SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - } - virtual ~RefreshCheckerDDR3IF() {} + RefreshCheckerDDR3Dummy(const MemSpecDDR3 *memSpec) : memSpec(memSpec) {} + virtual ~RefreshCheckerDDR3Dummy() {} - virtual void delayToSatisfyACT(Bank, sc_time &) = 0; - virtual void delayToSatisfyRD(Bank, sc_time &) = 0; - virtual void delayToSatisfyWR(Bank, sc_time &) = 0; - virtual void delayToSatisfyPRE(Bank, sc_time &) = 0; - virtual void insert(Bank) = 0; + virtual void delayToSatisfyACT(Bank, sc_time &) {} + virtual void delayToSatisfyRD(Bank, sc_time &) {} + virtual void delayToSatisfyWR(Bank, sc_time &) {} + virtual void delayToSatisfyPRE(Bank, sc_time &) {} + virtual void insert(Bank) {} const MemSpecDDR3 *memSpec; }; -class RefreshCheckerDDR3Dummy final : public RefreshCheckerDDR3IF +class RefreshCheckerDDR3 final : public RefreshCheckerDDR3Dummy { private: friend class CheckerDDR3; - RefreshCheckerDDR3Dummy() {} - - void delayToSatisfyACT(Bank, sc_time &) {} - void delayToSatisfyRD(Bank, sc_time &) {} - void delayToSatisfyWR(Bank, sc_time &) {} - void delayToSatisfyPRE(Bank, sc_time &) {} - void insert(Bank) {} -}; - -class RefreshCheckerDDR3 final : public RefreshCheckerDDR3IF -{ -private: - friend class CheckerDDR3; - RefreshCheckerDDR3() {} + RefreshCheckerDDR3(const MemSpecDDR3 *memSpec) + : RefreshCheckerDDR3Dummy(memSpec) {} void delayToSatisfyACT(Bank, sc_time &); void delayToSatisfyRD(Bank, sc_time &); @@ -118,16 +100,15 @@ private: sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; }; -class RefreshCheckerDDR3Bankwise final : public RefreshCheckerDDR3IF +class RefreshCheckerDDR3Bankwise final : public RefreshCheckerDDR3Dummy { private: friend class CheckerDDR3; - RefreshCheckerDDR3Bankwise(); + RefreshCheckerDDR3Bankwise(const MemSpecDDR3 *); void delayToSatisfyACT(Bank, sc_time &); void delayToSatisfyRD(Bank, sc_time &); void delayToSatisfyWR(Bank, sc_time &); - void delayToSatisfyPRE(Bank, sc_time &) {} void insert(Bank); std::map timesForNextREFB; From 4881b8ae767e10e5f65daf935097bf4daeb95b72 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 20 Aug 2019 10:58:28 +0200 Subject: [PATCH 082/183] Implemented initial version of timing checker for WideIO. --- DRAMSys/library/library.pro | 6 +- .../library/src/controller/ControllerNew.cpp | 11 +- .../src/controller/checker/CheckerDDR3.cpp | 1 - .../src/controller/checker/CheckerDDR3.h | 3 - .../src/controller/checker/CheckerWideIO.cpp | 252 ++++++++++++++++++ .../src/controller/checker/CheckerWideIO.h | 115 ++++++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 14 +- 7 files changed, 388 insertions(+), 14 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerWideIO.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerWideIO.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index e97f529b..badadba5 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -132,7 +132,8 @@ SOURCES += \ src/controller/checker/CheckerDDR3.cpp \ src/controller/refresh/RefreshManager.cpp \ src/controller/refresh/RefreshManagerDummy.cpp \ - src/controller/refresh/RefreshManagerBankwise.cpp + src/controller/refresh/RefreshManagerBankwise.cpp \ + src/controller/checker/CheckerWideIO.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -199,7 +200,8 @@ HEADERS += \ src/controller/refresh/RefreshManagerIF.h \ src/controller/refresh/RefreshManager.h \ src/controller/refresh/RefreshManagerDummy.h \ - src/controller/refresh/RefreshManagerBankwise.h + src/controller/refresh/RefreshManagerBankwise.h \ + src/controller/checker/CheckerWideIO.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 4e7290b4..85b05f2b 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -43,6 +43,7 @@ #include "../common/protocol.h" #include "core/scheduling/ScheduledCommand.h" #include "checker/CheckerDDR3.h" +#include "checker/CheckerWideIO.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" @@ -57,7 +58,13 @@ ControllerNew::ControllerNew(sc_module_name name) : Configuration config = Configuration::getInstance(); - checker = new CheckerDDR3(); + if (config.memSpec->MemoryType == "DDR3") + checker = new CheckerDDR3(); + else if (config.memSpec->MemoryType == "WIDEIO_SDR") + checker = new CheckerWideIO(); + else + SC_REPORT_FATAL("ControllerNew", "Unsupported DRAM type"); + if (config.ControllerCoreRefDisable) refreshManager = new RefreshManagerDummy(); else if (config.BankwiseLogic) @@ -70,6 +77,7 @@ ControllerNew::ControllerNew(sc_module_name name) : refreshManager = new RefreshManager(bankMachines); refreshEvent.notify(refreshManager->getTriggerDelay()); } + if (config.Scheduler == "FifoStrict") { scheduler = new SchedulerFifo(); @@ -82,6 +90,7 @@ ControllerNew::ControllerNew(sc_module_name name) : } else SC_REPORT_FATAL("ControllerNew", "Selected scheduler not supported"); + for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 60d5cf53..ec859bde 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -172,7 +172,6 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) lastScheduledByCommand[command] = scheduledCommand; lastScheduled = scheduledCommand; - // TODO: implement FAW for ACTB if (command == Command::ACT) { if (lastActivates.size() == 4) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index b3416ea4..b30192eb 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -58,9 +58,6 @@ private: std::queue lastActivates; void delayToSatisfyFAW(sc_time &); - sc_time timeForNextREFA; - sc_time timeForNextPREA; - RefreshCheckerDDR3Dummy *refreshChecker; // PowerDown TODO: Implement this method? diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp new file mode 100644 index 00000000..05e9585c --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerWideIO.h" + +CheckerWideIO::CheckerWideIO() +{ + Configuration config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); + + if (config.ControllerCoreRefDisable) + refreshChecker = new RefreshCheckerWideIODummy(memSpec); + else if (config.BankwiseLogic) + refreshChecker = new RefreshCheckerWideIOBankwise(memSpec); + else + refreshChecker = new RefreshCheckerWideIO(memSpec); +} + +CheckerWideIO::~CheckerWideIO() +{ + delete refreshChecker; +} + +sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) +{ + ScheduledCommand lastCommand; + + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); + + lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + + lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRP); + + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); + + lastCommand = lastScheduledByCommand[Command::ACT]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRRD); + + lastCommand = lastScheduledByCommand[Command::REFA]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + + lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + + delayToSatisfyTAW(earliestTimeToStart); + + refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); + + lastCommand = lastScheduledByCommand[Command::RD]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + + lastCommand = lastScheduledByCommand[Command::WR]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + + refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); + + lastCommand = lastScheduledByCommand[Command::RD]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + + lastCommand = lastScheduledByCommand[Command::WR]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + + refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); + } + else if (command == Command::PRE) + { + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRAS); + + lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP); + + lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + + refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + } + else + { + reportFatal("CheckerWideIO", "Unknown command!"); + } + // Check if command bus is free + if (lastScheduled.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled.getStart() + memSpec->clk); + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerWideIO::delayToSatisfyTAW(sc_time &earliestTimeToStart) +{ + if (lastActivates.size() >= 2) + { + sc_time earliestTime = lastActivates.front() + memSpec->tTAW; + if (earliestTime > earliestTimeToStart) + earliestTimeToStart = earliestTime; + } +} + +void CheckerWideIO::insert(const ScheduledCommand &scheduledCommand) +{ + Command command = scheduledCommand.getCommand(); + Bank bank = scheduledCommand.getBank(); + PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + + to_string(scheduledCommand.getBank().ID()) + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank] = scheduledCommand; + lastScheduledByCommand[command] = scheduledCommand; + lastScheduled = scheduledCommand; + + if (command == Command::ACT) + { + if (lastActivates.size() == 2) + lastActivates.pop(); + lastActivates.push(scheduledCommand.getStart()); + } + else if (command == Command::REFA || command == Command::REFB) + refreshChecker->insert(bank); +} + +// TODO: max(earliestTimeToStart, ...) needed? +void RefreshCheckerWideIO::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerWideIO::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerWideIO::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerWideIO::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= timeForNextPREA) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerWideIO::insert(Bank) +{ + timeForNextREFA += memSpec->tREFI; + timeForNextPREA += memSpec->tREFI; +} + +RefreshCheckerWideIOBankwise::RefreshCheckerWideIOBankwise(const MemSpecWideIO *memSpec) + : RefreshCheckerWideIODummy(memSpec) +{ + sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + { + timesForNextREFB[Bank(bankID)] = currentREFB; + timesForNextPRE[Bank(bankID)] = currentPRE; + currentREFB += memSpec->clk; + currentPRE += memSpec->clk; + } +} + +void RefreshCheckerWideIOBankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRAS)) + earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; +} + +void RefreshCheckerWideIOBankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRTP)) + earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; +} + +void RefreshCheckerWideIOBankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; +} + +void RefreshCheckerWideIOBankwise::insert(Bank bank) +{ + timesForNextREFB[bank] += memSpec->tREFI; + timesForNextPRE[bank] += memSpec->tREFI; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h new file mode 100644 index 00000000..1751d3cc --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERWIDEIO_H +#define CHECKERWIDEIO_H + +#include "CheckerIF.h" +#include +#include +#include "../core/configuration/MemSpec.h" +#include "../core/configuration/Configuration.h" + +class RefreshCheckerWideIODummy; + +class CheckerWideIO final : public CheckerIF +{ +public: + CheckerWideIO(); + ~CheckerWideIO(); + sc_time delayToSatisfyConstraints(Command, Bank); + void insert(const ScheduledCommand &); + +private: + const MemSpecWideIO *memSpec; + + // Four activate window + std::queue lastActivates; + void delayToSatisfyTAW(sc_time &); + + RefreshCheckerWideIODummy *refreshChecker; + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; +}; + +class RefreshCheckerWideIODummy +{ +protected: + friend class CheckerWideIO; + RefreshCheckerWideIODummy(const MemSpecWideIO *memSpec) : memSpec(memSpec) {} + virtual ~RefreshCheckerWideIODummy() {} + + virtual void delayToSatisfyACT(Bank, sc_time &) {} + virtual void delayToSatisfyRD(Bank, sc_time &) {} + virtual void delayToSatisfyWR(Bank, sc_time &) {} + virtual void delayToSatisfyPRE(Bank, sc_time &) {} + virtual void insert(Bank) {} + + const MemSpecWideIO *memSpec; +}; + +class RefreshCheckerWideIO final : public RefreshCheckerWideIODummy +{ +private: + friend class CheckerWideIO; + RefreshCheckerWideIO(const MemSpecWideIO *memSpec) + : RefreshCheckerWideIODummy(memSpec) {} + + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void delayToSatisfyPRE(Bank, sc_time &); + void insert(Bank); + + sc_time timeForNextREFA = memSpec->tREFI; + sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; +}; + +class RefreshCheckerWideIOBankwise final : public RefreshCheckerWideIODummy +{ +private: + friend class CheckerWideIO; + RefreshCheckerWideIOBankwise(const MemSpecWideIO *); + + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void insert(Bank); + + std::map timesForNextREFB; + std::map timesForNextPRE; +}; + +#endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index e41e1862..ebaac161 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -269,13 +269,6 @@ void DRAMSys::instantiateModules(const string &traceName, else dram = new DramDDR3(str.c_str()); } - else if (memoryType == "DDR4") - { - if (recordingEnabled) - dram = new DramRecordable(str.c_str(), tlmRecorders[i]); - else - dram = new DramDDR4(str.c_str()); - } else if (memoryType == "WIDEIO_SDR") { if (recordingEnabled) @@ -283,6 +276,13 @@ void DRAMSys::instantiateModules(const string &traceName, else dram = new DramWideIO(str.c_str()); } + else if (memoryType == "DDR4") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramDDR4(str.c_str()); + } else { SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); From 1fc5f3bf8868878fea44754986ef80f316d176d4 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 20 Aug 2019 14:56:45 +0200 Subject: [PATCH 083/183] Some phase renaming in TraceAnalyzer. --- .../businessObjects/phases/phasefactory.cpp | 2 +- DRAMSys/traceAnalyzer/data/tracedb.cpp | 2 +- DRAMSys/traceAnalyzer/scripts/metrics.py | 14 ++--- DRAMSys/traceAnalyzer/scripts/tests.py | 54 +++++++++---------- 4 files changed, 36 insertions(+), 36 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 3f7dc143..8c92e00d 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -68,7 +68,7 @@ shared_ptr PhaseFactory::CreatePhase(ID id, const QString &dbPhaseName, else if (dbPhaseName == "ACT") return shared_ptr(new ACT(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, std::shared_ptr())); - else if (dbPhaseName == "PRE_ALL") + else if (dbPhaseName == "PREA") return shared_ptr(new PRECHARGE_ALL(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, std::shared_ptr())); else if (dbPhaseName == "REFA") diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index 305ebcb5..37ed9857 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -164,7 +164,7 @@ shared_ptr TraceDB::getNextPrecharge(ID currentTransactionId) { QSqlQuery query(database); QString queryText = queryTexts.queryHead + - "WHERE TransactionID > :currentID AND PhaseName IN ('PRE','PRE_ALL') LIMIT 1"; + "WHERE TransactionID > :currentID AND PhaseName IN ('PRE','PREA') LIMIT 1"; query.prepare(queryText); query.bindValue(":currentID", currentTransactionId); diff --git a/DRAMSys/traceAnalyzer/scripts/metrics.py b/DRAMSys/traceAnalyzer/scripts/metrics.py index feebd957..d3fc044d 100644 --- a/DRAMSys/traceAnalyzer/scripts/metrics.py +++ b/DRAMSys/traceAnalyzer/scripts/metrics.py @@ -239,8 +239,8 @@ def ACT_count(connection): @metric -def PRE_ALL_count(connection): - return get_phase_occurrences(connection, 'PRE_ALL') +def PREA_count(connection): + return get_phase_occurrences(connection, 'PREA') @metric @@ -327,17 +327,17 @@ def bank_overlap_ratio(connection): cursor.execute(""" select p1.PhaseBegin, p1.PhaseName from Phases p1 where - (p1.PhaseName = "ACT" or p1.PhaseName = "PRE_ALL" or p1.PhaseName = "PRE" or p1.PhaseName = "RDA" or p1.PhaseName = "WRA" or p1.PhaseName = "PREB" or p1.PhaseName = "ACTB") + (p1.PhaseName = "ACT" or p1.PhaseName = "PREA" or p1.PhaseName = "PRE" or p1.PhaseName = "RDA" or p1.PhaseName = "WRA" or p1.PhaseName = "PREB" or p1.PhaseName = "ACTB") order by PhaseBegin """) - prevPhase = "PRE_ALL" + prevPhase = "PREA" prevTime = 0 for c in cursor: trace.append([(int(c[0]/clk)), c[1]]) # Insert a pseudo precharge all to mark the end of the trace - trace.append([traceEnd, "PRE_ALL"]) + trace.append([traceEnd, "PREA"]) bankCounter = 0 bankTime = [] @@ -362,7 +362,7 @@ def bank_overlap_ratio(connection): print("Unexpected ACT. bankCounter was {0} valid range is python range {1}".format(bankCounter, validBankRange)) elif t[1] == "ACTB": actbCnt += 1 - elif(t[1] == "PRE_ALL"): + elif(t[1] == "PREA"): bankCounter = 0 elif(t[1] == "PRE"): if (bankCounter > 0): @@ -403,7 +403,7 @@ def bank_overlap_ratio(connection): # @metric # def number_of_precharges(connection): # cursor = connection.cursor() -# cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName IN ('PRE','PRE_ALL','RDA','WRA')") +# cursor.execute("SELECT COUNT(*) FROM Phases WHERE PhaseName IN ('PRE','PREA','RDA','WRA')") # result = cursor.fetchone() # return result[0] diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index 6b2877ca..eea095bd 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -233,9 +233,9 @@ def commandbus_slots_are_used_once(connection): cursor = connection.cursor() if (dramconfig.bankwiseLogic == "1"): - excludedPhases = "('REQ','RESP','PRE_ALL')" + excludedPhases = "('REQ','RESP','PREA')" else: - excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF','REFA')" + excludedPhases = "('REQ','RESP','PREA','PDNA','PDNP','SREF','REFA')" query = """SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count FROM Phases WHERE PhaseName NOT IN """ + excludedPhases + """ AND phasebegin>0 GROUP BY phaseBegin) WHERE count>1""" @@ -258,7 +258,7 @@ def phase_transitions_are_valid(connection): if (dramconfig.bankwiseLogic == "1"): validTransitions['PRE'] = set(['ACT', 'REFB', 'SREFB']) - validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA', 'PRE', 'PRE_ALL']) + validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA', 'PRE', 'PREA']) validTransitions['RD'] = set(['PRE', 'RD', 'RDA', 'WR', 'WRA', 'PDNAB']) validTransitions['WR'] = set(['PRE', 'RD', 'RDA', 'WR', 'WRA', 'PDNAB']) @@ -271,20 +271,20 @@ def phase_transitions_are_valid(connection): validTransitions['PDNPB'] = set(['ACT', 'REFB', 'SREFB']) validTransitions['SREFB'] = set(['ACT', 'REFB']) else: - validTransitions['PRE'] = set(['ACT', 'PRE_ALL', 'REFA']) - validTransitions['PRE_ALL'] = set(['REFA', 'SREF']) - validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA', 'PRE_ALL']) + validTransitions['PRE'] = set(['ACT', 'PREA', 'REFA']) + validTransitions['PREA'] = set(['REFA', 'SREF']) + validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA', 'PREA']) - validTransitions['RD'] = set(['PRE', 'PRE_ALL', 'RD', 'RDA', 'WR', 'WRA', 'PDNA']) - validTransitions['WR'] = set(['PRE', 'PRE_ALL', 'RD', 'RDA', 'WR', 'WRA', 'PDNA']) - validTransitions['RDA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) - validTransitions['WRA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) + validTransitions['RD'] = set(['PRE', 'PREA', 'RD', 'RDA', 'WR', 'WRA', 'PDNA']) + validTransitions['WR'] = set(['PRE', 'PREA', 'RD', 'RDA', 'WR', 'WRA', 'PDNA']) + validTransitions['RDA'] = set(['PREA', 'ACT', 'REFA', 'PDNA', 'PDNP']) + validTransitions['WRA'] = set(['PREA', 'ACT', 'REFA', 'PDNA', 'PDNP']) - validTransitions['REFA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) + validTransitions['REFA'] = set(['PREA', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) - validTransitions['PDNA'] = set(['PRE', 'PRE_ALL', 'ACT', 'RD', 'RDA', 'WR', 'WRA', 'REFA', 'PDNA', 'PDNP']) - validTransitions['PDNP'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) - validTransitions['SREF'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) + validTransitions['PDNA'] = set(['PRE', 'PREA', 'ACT', 'RD', 'RDA', 'WR', 'WRA', 'REFA', 'PDNA', 'PDNP']) + validTransitions['PDNP'] = set(['PREA', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) + validTransitions['SREF'] = set(['PREA', 'ACT', 'REFA', 'PDNA', 'PDNP']) if (dramconfig.bankwiseLogic == "1"): query = """SELECT @@ -294,13 +294,13 @@ def phase_transitions_are_valid(connection): WHERE (TBank=:bank) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" else: - # REFA, PRE_ALL, PDNA, PDNP and SREF are attributed to Bank 0 therefore this must be added to the order evaluation: + # REFA, PREA, PDNA, PDNP and SREF are attributed to Bank 0 therefore this must be added to the order evaluation: query = """SELECT PhaseName, phases.ID FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE - ((TBank=:bank) OR PhaseName IN ('PRE_ALL', 'SREF', 'PDNP', 'PDNA', 'REFA')) + ((TBank=:bank) OR PhaseName IN ('PREA', 'SREF', 'PDNP', 'PDNA', 'REFA')) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" for bankNumber in range(dramconfig.numberOfBanks): @@ -321,14 +321,14 @@ def timing_constraint(FirstPhase, SecondPhase): FirstPhaseName = FirstPhase[0] SecondPhaseName = SecondPhase[0] - if ((FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL") and SecondPhaseName != "PRE_ALL"): + if ((FirstPhaseName == "PRE" or FirstPhaseName == "PREA") and SecondPhaseName != "PREA"): return dramconfig.tRP elif (FirstPhaseName == "ACT"): return dramconfig.tRCD elif (FirstPhaseName == "RD"): - if (SecondPhaseName in ["PRE, PRE_ALL"]): + if (SecondPhaseName in ["PRE, PREA"]): return dramconfig.tRTP elif (SecondPhaseName in ["RD, RDA"]): return max(dramconfig.tCCD_L, getReadAccessTime()) @@ -338,7 +338,7 @@ def timing_constraint(FirstPhase, SecondPhase): return dramconfig.tRL + getReadAccessTime() + dramconfig.clk elif (FirstPhaseName == "WR"): - if (SecondPhaseName in ["PRE, PRE_ALL", "PDNA"]): + if (SecondPhaseName in ["PRE, PREA", "PDNA"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR elif (SecondPhaseName in ["RD, RDA"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWTR_L @@ -346,13 +346,13 @@ def timing_constraint(FirstPhase, SecondPhase): return max(dramconfig.tCCD_L, burstlength/dramconfig.dataRate) elif (FirstPhaseName == "RDA"): - if (SecondPhaseName in ["ACT", "PRE_ALL", "REFA"]): + if (SecondPhaseName in ["ACT", "PREA", "REFA"]): return dramconfig.tRTP + dramconfig.tRP elif (SecondPhaseName in ["PDNA", "PDNP"]): return dramconfig.tRL + getReadAccessTime() + dramconfig.clk elif (FirstPhaseName == "WRA"): - if (SecondPhaseName in ["ACT", "PRE_ALL", "REFA"]): + if (SecondPhaseName in ["ACT", "PREA", "REFA"]): return dramconfig.tWL + getWriteAccessTime() + dramconfig.tWR + dramconfig.tRP elif (SecondPhaseName in ["PDNA", "PDNP"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR + dramconfig.clk @@ -390,7 +390,7 @@ def timing_constraits_on_the_same_bank_hold(connection): AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" else: query = """SELECT PhaseName, phases.ID, PhaseBegin, PhaseEnd FROM phases INNER JOIN transactions ON phases.transact=transactions.ID - WHERE ((TBank=:bank) OR PhaseName IN ('PRE_ALL', 'SREF', 'PDNP', 'PDNA', 'REFA')) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" + WHERE ((TBank=:bank) OR PhaseName IN ('PREA', 'SREF', 'PDNP', 'PDNA', 'REFA')) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" for bankNumber in range(dramconfig.numberOfBanks): cursor.execute(query, {"bank": bankNumber}) lastRow = cursor.fetchone() @@ -416,21 +416,21 @@ def row_buffer_is_used_correctly(connection): FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE - ((TBank=:bank) OR (PhaseNAME = "REFA" AND TBank=0) OR (PhaseNAME = "PRE_ALL" AND TBank=0)) + ((TBank=:bank) OR (PhaseNAME = "REFA" AND TBank=0) OR (PhaseNAME = "PREA" AND TBank=0)) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" else: - # REFA, PRE_ALL, PDNA, PDNP and SREF are stored to bank0 for all the other banks we have also to grep this command: - # PhaseName IN ('PRE_ALL', 'SREF', 'PDNP', 'PDNA', 'REFA') + # REFA, PREA, PDNA, PDNP and SREF are stored to bank0 for all the other banks we have also to grep this command: + # PhaseName IN ('PREA', 'SREF', 'PDNP', 'PDNA', 'REFA') query = """SELECT PhaseName, phases.ID FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE - ((TBank=:bank) OR PhaseName IN ('PRE_ALL', 'SREF', 'PDNP', 'PDNA', 'REFA')) + ((TBank=:bank) OR PhaseName IN ('PREA', 'SREF', 'PDNP', 'PDNA', 'REFA')) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" # phases that precharge the bank and close the rowbuffer - prechargingPhases = set(['PRE', 'PRE_ALL', 'RDA', 'WRA']) + prechargingPhases = set(['PRE', 'PREA', 'RDA', 'WRA']) # phases that require the bank to be in active state and the rowbuffer to be opened accessingPhases = set(['RD', 'RDA', 'WR', 'WRA', 'PRE']) From f5f3c729e0d144a6d4d58d939d5286223a14e15f Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 22 Aug 2019 22:16:33 +0200 Subject: [PATCH 084/183] Temporary fix of memory leak. --- DRAMSys/library/src/controller/ControllerNew.cpp | 5 +++-- DRAMSys/library/src/simulation/MemoryManager.cpp | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 85b05f2b..e7bc495b 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -101,11 +101,12 @@ ControllerNew::~ControllerNew() { endBandwithIdleCollector(); - delete checker; for (auto it : bankMachines) delete it.second; - delete scheduler; delete commandMux; + delete scheduler; + delete refreshManager; + delete checker; } void ControllerNew::controllerMethod() diff --git a/DRAMSys/library/src/simulation/MemoryManager.cpp b/DRAMSys/library/src/simulation/MemoryManager.cpp index 08792b1e..68c08bbc 100644 --- a/DRAMSys/library/src/simulation/MemoryManager.cpp +++ b/DRAMSys/library/src/simulation/MemoryManager.cpp @@ -71,8 +71,8 @@ gp *MemoryManager::allocate() void MemoryManager::free(gp *payload) { - //unsigned char *dptr = payload->get_data_ptr(); - //delete[] dptr; + unsigned char *dptr = payload->get_data_ptr(); + delete[] dptr; payload->reset(); //clears all extensions freePayloads.push_back(payload); } From d4943bccc5df19491f88cc6b1965a0bc9be6957c Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 25 Aug 2019 23:13:05 +0200 Subject: [PATCH 085/183] Debug Manager cleanup. --- DRAMSys/library/src/common/DebugManager.cpp | 4 +++ DRAMSys/library/src/common/DebugManager.h | 8 +++--- .../core/configuration/TemperatureSimConfig.h | 18 +++++-------- DRAMSys/library/src/error/errormodel.cpp | 27 +++++++------------ DRAMSys/library/src/error/errormodel.h | 2 -- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 ++ DRAMSys/library/src/simulation/IArbiter.h | 5 ---- .../src/simulation/TemperatureController.cpp | 22 ++++++--------- .../src/simulation/TemperatureController.h | 8 +++--- 9 files changed, 37 insertions(+), 59 deletions(-) diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp index e58ec8f5..034e3747 100644 --- a/DRAMSys/library/src/common/DebugManager.cpp +++ b/DRAMSys/library/src/common/DebugManager.cpp @@ -35,6 +35,9 @@ */ #include "DebugManager.h" + +#ifdef DEBUGGING + #include "../controller/core/configuration/Configuration.h" using namespace std; @@ -76,3 +79,4 @@ DebugManager::~DebugManager() debugFile.close(); } } +#endif diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index 86306a46..ca3b1fec 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -39,11 +39,10 @@ //#define DEBUGGING -#ifdef DEBUGGING -#define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) -#else +#ifndef DEBUGGING #define PRINTDEBUGMESSAGE(sender, message) {} -#endif +#else +#define PRINTDEBUGMESSAGE(sender, message) DebugManager::getInstance().printDebugMessage(sender, message) #include #include @@ -70,5 +69,6 @@ private: ofstream debugFile; }; +#endif #endif // DEBUGMANAGER_H diff --git a/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h index b9acd733..11c0e32d 100644 --- a/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h @@ -76,7 +76,7 @@ struct TemperatureSimConfig void parsePowerInfoFile() { - printDebugMessage("Power Info File: " + powerInfoFile); + PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile) powerInfoFile = pathToResources + "/configs/thermalsim/" @@ -90,7 +90,7 @@ struct TemperatureSimConfig if (powInfoElem == NULL) { // Invalid file std::string errormsg = "Invalid Power Info File " + powerInfoFile; - printDebugMessage(errormsg); + PRINTDEBUGMESSAGE("TemperatureSimConfig", errormsg); SC_REPORT_FATAL("Temperature Sim Config", errormsg.c_str()); } @@ -115,21 +115,15 @@ struct TemperatureSimConfig { int i = 0; for (auto e : powerInitialValues) { - printDebugMessage("powerInitialValues[" + std::to_string( - i++) + "]: " + std::to_string(e)); + PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerInitialValues[" + + std::to_string(i++) + "]: " + std::to_string(e)); } i = 0; for (auto e : powerThresholds) { - printDebugMessage("powerThreshold[" + std::to_string(i++) + "]: " + - std::to_string(e)); + PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerThreshold[" + + std::to_string(i++) + "]: " + std::to_string(e)); } } - - void printDebugMessage(std::string message) - { - DebugManager::getInstance().printDebugMessage("Temperature Sim Config", - message); - } }; #endif // TEMPERATURESIMCONFIG_H diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index e2329750..cb73ee11 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -165,12 +165,12 @@ void errorModel::store(tlm::tlm_generic_payload &trans) msg << "bank: " << key.bank << " group: " << key.bankgroup << " bytes: " << key.bytes << " channel: " << key.channel << " column: " << key.column << " rank: " << key.rank << " row: " << key.row; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); // Check if the provided data length is correct: assert((bytesPerColumn * burstLenght) == trans.get_data_length()); - printDebugMessage(("Data length: " + std::to_string(trans.get_data_length()) + + PRINTDEBUGMESSAGE(name(), ("Data length: " + std::to_string(trans.get_data_length()) + " bytesPerColumn: " + std::to_string(bytesPerColumn)).c_str()); // Handle the DRAM burst, @@ -211,7 +211,7 @@ void errorModel::store(tlm::tlm_generic_payload &trans) std::stringstream msg; msg << "key.column is " << key.column << " numberOfColumns is " << numberOfColumns; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); assert(key.column <= numberOfColumns); } } @@ -269,7 +269,7 @@ void errorModel::markBitFlips() if (weakCells[i].flipped == false && weakCells[i].row == row) { std::stringstream msg; msg << "Maked weakCell[" << i << "] as flipped" << std::endl; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); weakCells[i].flipped = true; } @@ -334,7 +334,7 @@ void errorModel::activate(unsigned int row) << " row: " << key.row << " col: " << key.column << " bit: " << weakCells[i].bit; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); numberOfBitErrorEvents++; @@ -387,7 +387,7 @@ void errorModel::activate(unsigned int row) << grid[0] << grid[1] << grid[2] << std::endl << grid[3] << grid[4] << grid[5] << std::endl << grid[6] << grid[7] << grid[8]; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); } else { // Output on the Console: std::stringstream msg; @@ -399,7 +399,7 @@ void errorModel::activate(unsigned int row) << grid[0] << grid[1] << grid[2] << std::endl << grid[3] << grid[4] << grid[5] << std::endl << grid[6] << grid[7] << grid[8]; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); } } } @@ -431,7 +431,7 @@ unsigned int errorModel::getBit(DecodedAddress key, unsigned int byteInColumn, << " tempByte = " << (unsigned int)tempByte << " result = " << result; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); return result; } @@ -569,7 +569,7 @@ void errorModel::parseInputData() << " independent = " << errorMap[temp][retentionTime].independent << " dependent = " << errorMap[temp][retentionTime].dependent; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); } inputFile.close(); } else { @@ -670,7 +670,7 @@ void errorModel::prepareWeakCells() << " bit=" << weakCells[i].bit << " flip=" << weakCells[i].flipped << " dep=" << weakCells[i].dependent; - printDebugMessage(msg.str()); + PRINTDEBUGMESSAGE(name(), msg.str()); } } @@ -735,10 +735,3 @@ void errorModel::setContext(DecodedAddress addr) myBank) + " "; } } - -void errorModel::printDebugMessage(std::string message) -{ - std::stringstream msg; - msg << contextStr << message; - DebugManager::getInstance().printDebugMessage(this->name(), msg.str()); -} diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index 1f4e3b71..7dab8f3f 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -72,8 +72,6 @@ private: // context: std::string contextStr; - void printDebugMessage(std::string message); - // Online Parameters: unsigned int numberOfBitErrorEvents; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index ebaac161..596f0d74 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -179,11 +179,13 @@ void DRAMSys::logo() void DRAMSys::setupDebugManager(const string &traceName) { +#ifdef DEBUGGING auto &dbg = DebugManager::getInstance(); dbg.writeToConsole = false; dbg.writeToFile = true; if (dbg.writeToFile) dbg.openDebugFile(traceName + ".txt"); +#endif } void DRAMSys::setupTlmRecorders(const string &traceName, diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index a9c5ebd4..8826610f 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -89,11 +89,6 @@ protected: virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans) = 0; - void printDebugMessage(std::string message) - { - DebugManager::getInstance().printDebugMessage(this->name(), message); - } - void appendDramExtension(int socketId, tlm_generic_payload &payload) { // Append Generation Extension diff --git a/DRAMSys/library/src/simulation/TemperatureController.cpp b/DRAMSys/library/src/simulation/TemperatureController.cpp index 2e183a77..09489377 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.cpp +++ b/DRAMSys/library/src/simulation/TemperatureController.cpp @@ -52,7 +52,7 @@ double TemperatureController::temperatureConvert(double tKelvin) double TemperatureController::getTemperature(int deviceId, float currentPower) { - printDebugMessage("Temperature requested by device " + std::to_string( + PRINTDEBUGMESSAGE(name(), "Temperature requested by device " + std::to_string( deviceId) + " current power is " + std::to_string(currentPower)); if (dynamicTempSimEnabled == true) { @@ -66,7 +66,7 @@ double TemperatureController::getTemperature(int deviceId, float currentPower) return temperatureConvert(temperatureValues.at(deviceId)); } else { - printDebugMessage("Temperature is " + std::to_string(staticTemperature)); + PRINTDEBUGMESSAGE(name(), "Temperature is " + std::to_string(staticTemperature)); return staticTemperature; } } @@ -139,7 +139,7 @@ double TemperatureController::adjustThermalSimPeriod() period = period / periodAdjustFactor; cyclesSinceLastPeriodAdjust = 0; decreaseSimPeriod = false; - printDebugMessage("Thermal Simulation period reduced to " + std::to_string( + PRINTDEBUGMESSAGE(name(), "Thermal Simulation period reduced to " + std::to_string( period) + ". Target is " + std::to_string(targetPeriod)); } else { if (period != targetPeriod) { @@ -149,8 +149,8 @@ double TemperatureController::adjustThermalSimPeriod() period = period * (periodAdjustFactor / 2); if (period > targetPeriod) period = targetPeriod; - printDebugMessage("Thermal Simulation period increased to " + std::to_string( - period) + ". Target is " + std::to_string(targetPeriod)); + PRINTDEBUGMESSAGE(name(), "Thermal Simulation period increased to " + + std::to_string(period) + ". Target is " + std::to_string(targetPeriod)); } } } @@ -166,17 +166,11 @@ void TemperatureController::temperatureThread() int i = 0; for (auto t : temperatureValues) { - printDebugMessage("Temperature[" + std::to_string(i++) + "] is " + - std::to_string(t)); + PRINTDEBUGMESSAGE(name(), "Temperature[" + std::to_string(i++) + + "] is " + std::to_string(t)); } - printDebugMessage("Thermal simulation period is " + std::to_string(p)); + PRINTDEBUGMESSAGE(name(), "Thermal simulation period is " + std::to_string(p)); wait(sc_time(p, t_unit)); } } - -void TemperatureController::printDebugMessage(std::string message) -{ - DebugManager::getInstance().printDebugMessage(name(), message); -} - diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index 8d91d56a..fa16c1f0 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -72,8 +72,8 @@ public: std::string ip = Configuration::getInstance().temperatureSim.IceServerIp; unsigned int port = Configuration::getInstance().temperatureSim.IceServerPort; thermalSimulation = new IceWrapper(ip, port); - printDebugMessage("Dynamic temperature simulation. Server @ " + ip + ":" + - std::to_string(port)); + PRINTDEBUGMESSAGE(name(), "Dynamic temperature simulation. Server @ " + + ip + ":" + std::to_string(port)); #else SC_REPORT_FATAL(name(), "DRAMSys was build without support to dynamic temperature simulation. Check the README file for further details."); @@ -107,7 +107,7 @@ public: SC_THREAD(temperatureThread); } else { - printDebugMessage("Static temperature simulation. Temperature set to " + + PRINTDEBUGMESSAGE(name(), "Static temperature simulation. Temperature set to " + std::to_string(staticTemperature)); } } @@ -148,8 +148,6 @@ private: std::string temperatureMapFile; bool genPowerMap; std::string powerMapFile; - - void printDebugMessage(std::string message); }; #endif // TEMPERATURECONTROLLER_H From 7934d2e1603a648649febaaa34a8fd91621d82fc Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 26 Aug 2019 16:26:28 +0200 Subject: [PATCH 086/183] Renaming libDRAMPowerIF to libDRAMPowerDummy. --- DRAMSys/library/src/simulation/Dram.h | 2 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR4.cpp | 2 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index 48208e92..a9e38b75 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -70,7 +70,7 @@ protected: StorageMode StoreMode = Configuration::getInstance().StoreMode; unsigned char *memory; - libDRAMPowerIF *DRAMPower; + libDRAMPowerDummy *DRAMPower; virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase, sc_time &delay); diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 1dc1ef3d..acc9f865 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -143,5 +143,5 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) DRAMPower = new libDRAMPower(powerSpec, 0); } else - DRAMPower = new libDRAMPowerIF(); + DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 321a435a..71517b2e 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -143,5 +143,5 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) DRAMPower = new libDRAMPower(powerSpec, 0); } else - DRAMPower = new libDRAMPowerIF(); + DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 37c4efa0..ace2bc44 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -164,7 +164,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) { if (StoreMode == StorageMode::ErrorModel) SC_REPORT_FATAL("DramWideIO", "Error modeling without power analysis is not supported"); - DRAMPower = new libDRAMPowerIF(); + DRAMPower = new libDRAMPowerDummy(); } } From f40ace826b229bef5a7c5518eba902de4cb0c9c9 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 26 Aug 2019 17:14:23 +0200 Subject: [PATCH 087/183] Changed DRAMPower submodule commit and branch. --- .gitmodules | 2 +- DRAMSys/library/src/common/third_party/DRAMPower | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 458b70e3..14883ec7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,7 +4,7 @@ [submodule "DRAMSys/library/src/common/third_party/DRAMPower"] path = DRAMSys/library/src/common/third_party/DRAMPower url = https://github.com/tukl-msd/DRAMPower.git - branch = master + branch = rgr [submodule "DRAMSys/unitTests/googletest"] path = DRAMSys/unitTests/googletest url = https://github.com/google/googletest.git diff --git a/DRAMSys/library/src/common/third_party/DRAMPower b/DRAMSys/library/src/common/third_party/DRAMPower index 746d56ea..e65a108c 160000 --- a/DRAMSys/library/src/common/third_party/DRAMPower +++ b/DRAMSys/library/src/common/third_party/DRAMPower @@ -1 +1 @@ -Subproject commit 746d56ea53c5227428fff3e13716a68f259ad243 +Subproject commit e65a108c385d7964410364cdaedad56f0db96e1b From 7827a5f8690d00d18fc9e8ba50ce90d587d7c93f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 10 Sep 2019 15:22:05 +0200 Subject: [PATCH 088/183] Added some addressmappings and memspecs for WIDEIO and WIDEIO2. --- .../amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml | 11 ++++ .../configs/amconfigs/am_wideio_4x1Gb_brc.xml | 11 ++++ .../configs/amconfigs/am_wideio_4x1Gb_rbc.xml | 11 ++++ .../amconfigs/am_wideio_4x256Mb_brc.xml | 11 ++++ .../amconfigs/am_wideio_4x256Mb_rbc.xml | 11 ++++ .../configs/amconfigs/am_wideio_4x2Gb_brc.xml | 11 ++++ .../configs/amconfigs/am_wideio_4x2Gb_rbc.xml | 11 ++++ .../configs/amconfigs/am_wideio_4x4Gb_brc.xml | 11 ++++ .../configs/amconfigs/am_wideio_4x4Gb_rbc.xml | 11 ++++ .../amconfigs/am_wideio_4x512Mb_brc.xml | 11 ++++ .../amconfigs/am_wideio_4x512Mb_rbc.xml | 11 ++++ .../JEDEC_256Mb_WIDEIO-200_128bit.xml | 63 ++++++++++++++++++ .../JEDEC_256Mb_WIDEIO-266_128bit.xml | 63 ++++++++++++++++++ .../JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml | 66 +++++++++++++++++++ .../JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml | 66 +++++++++++++++++++ 15 files changed, 379 insertions(+) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml new file mode 100644 index 00000000..94ac21ae --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml new file mode 100644 index 00000000..ccaecd9c --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml new file mode 100644 index 00000000..2daf6367 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml new file mode 100644 index 00000000..93db07f7 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml new file mode 100644 index 00000000..45b5153f --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml new file mode 100644 index 00000000..8d044310 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml new file mode 100644 index 00000000..65cbcc32 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml new file mode 100644 index 00000000..ff474639 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml new file mode 100644 index 00000000..431d6176 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml new file mode 100644 index 00000000..97c6ad9f --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml new file mode 100644 index 00000000..a2f0141c --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml new file mode 100644 index 00000000..122ea9af --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml new file mode 100644 index 00000000..aebd11e8 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml new file mode 100644 index 00000000..1d4023c3 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml new file mode 100644 index 00000000..598303ad --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7fd5f05d3e196db2e2c1424a07d371c99986a483 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 11 Sep 2019 09:59:51 +0200 Subject: [PATCH 089/183] Renaming of ControllerNew to Controller. --- DRAMSys/library/library.pro | 4 +-- DRAMSys/library/src/controller/BankMachine.h | 2 +- .../{ControllerNew.cpp => Controller.cpp} | 34 +++++++++---------- .../{ControllerNew.h => Controller.h} | 14 ++++---- .../src/controller/ControllerRecordable.cpp | 6 ++-- .../src/controller/ControllerRecordable.h | 6 ++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 4 +-- 7 files changed, 35 insertions(+), 35 deletions(-) rename DRAMSys/library/src/controller/{ControllerNew.cpp => Controller.cpp} (90%) rename DRAMSys/library/src/controller/{ControllerNew.h => Controller.h} (93%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 19f5ede2..e5232799 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -124,7 +124,7 @@ SOURCES += \ src/simulation/DramWideIO.cpp \ src/controller/core/configuration/MemSpec.cpp \ src/controller/BankMachine.cpp \ - src/controller/ControllerNew.cpp \ + src/controller/Controller.cpp \ src/controller/scheduler/SchedulerFifo.cpp \ src/controller/scheduler/SchedulerFrFcfs.cpp \ src/controller/cmdmux/CmdMuxStrict.cpp \ @@ -188,7 +188,7 @@ HEADERS += \ src/simulation/DramWideIO.h \ src/controller/GenericController.h \ src/controller/BankMachine.h \ - src/controller/ControllerNew.h \ + src/controller/Controller.h \ src/controller/scheduler/SchedulerIF.h \ src/controller/scheduler/SchedulerFifo.h \ src/controller/scheduler/SchedulerFrFcfs.h \ diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 57e7aa5b..87c26072 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -39,7 +39,7 @@ #include #include #include "../common/dramExtensions.h" -#include "ControllerNew.h" +#include "Controller.h" #include "Command.h" #include "scheduler/SchedulerIF.h" #include "checker/CheckerIF.h" diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/Controller.cpp similarity index 90% rename from DRAMSys/library/src/controller/ControllerNew.cpp rename to DRAMSys/library/src/controller/Controller.cpp index e7bc495b..56749619 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -32,7 +32,7 @@ * Author: Lukas Steiner */ -#include "ControllerNew.h" +#include "Controller.h" #include "core/configuration/Configuration.h" #include "scheduler/SchedulerFifo.h" @@ -48,7 +48,7 @@ #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" -ControllerNew::ControllerNew(sc_module_name name) : +Controller::Controller(sc_module_name name) : GenericController(name) { SC_METHOD(controllerMethod); @@ -63,7 +63,7 @@ ControllerNew::ControllerNew(sc_module_name name) : else if (config.memSpec->MemoryType == "WIDEIO_SDR") checker = new CheckerWideIO(); else - SC_REPORT_FATAL("ControllerNew", "Unsupported DRAM type"); + SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); if (config.ControllerCoreRefDisable) refreshManager = new RefreshManagerDummy(); @@ -89,7 +89,7 @@ ControllerNew::ControllerNew(sc_module_name name) : commandMux = new CmdMuxOldest(); } else - SC_REPORT_FATAL("ControllerNew", "Selected scheduler not supported"); + SC_REPORT_FATAL("Controller", "Selected scheduler not supported"); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); @@ -97,7 +97,7 @@ ControllerNew::ControllerNew(sc_module_name name) : startBandwidthIdleCollector(); } -ControllerNew::~ControllerNew() +Controller::~Controller() { endBandwithIdleCollector(); @@ -109,7 +109,7 @@ ControllerNew::~ControllerNew() delete checker; } -void ControllerNew::controllerMethod() +void Controller::controllerMethod() { // (1) Release payload if arbiter has accepted the result if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) @@ -178,7 +178,7 @@ void ControllerNew::controllerMethod() } } -tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, +tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { sc_time notificationDelay = delay; @@ -205,7 +205,7 @@ tlm_sync_enum ControllerNew::nb_transport_fw(tlm_generic_payload &trans, return TLM_ACCEPTED; } -tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, +tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + @@ -220,13 +220,13 @@ tlm_sync_enum ControllerNew::nb_transport_bw(tlm_generic_payload &trans, return TLM_ACCEPTED; } -unsigned int ControllerNew::transport_dbg(tlm_generic_payload &) +unsigned int Controller::transport_dbg(tlm_generic_payload &) { - SC_REPORT_FATAL("ControllerNew", "Debug Transport not supported"); + SC_REPORT_FATAL("Controller", "Debug Transport not supported"); return 0; } -void ControllerNew::releasePayload() +void Controller::releasePayload() { uint64_t id = DramExtension::getPayloadID(payloadToRelease); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); @@ -240,7 +240,7 @@ void ControllerNew::releasePayload() startBandwidthIdleCollector(); } -void ControllerNew::acquirePayload() +void Controller::acquirePayload() { uint64_t id = DramExtension::getPayloadID(payloadToAcquire); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); @@ -256,13 +256,13 @@ void ControllerNew::acquirePayload() payloadToAcquire = nullptr; } -void ControllerNew::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) +void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) { sc_time delay = SC_ZERO_TIME; tSocket->nb_transport_bw(*payload, phase, delay); } -void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) +void Controller::sendToDram(Command command, tlm_generic_payload *payload) { sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command); ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); @@ -285,12 +285,12 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::REFB) phase = BEGIN_REFB; else - SC_REPORT_FATAL("ControllerNew", "Unknown phase"); + SC_REPORT_FATAL("Controller", "Unknown phase"); iSocket->nb_transport_fw(*payload, phase, delay); } -void ControllerNew::startBandwidthIdleCollector() +void Controller::startBandwidthIdleCollector() { if (!isIdle) { @@ -300,7 +300,7 @@ void ControllerNew::startBandwidthIdleCollector() } } -void ControllerNew::endBandwithIdleCollector() +void Controller::endBandwithIdleCollector() { if (isIdle) { diff --git a/DRAMSys/library/src/controller/ControllerNew.h b/DRAMSys/library/src/controller/Controller.h similarity index 93% rename from DRAMSys/library/src/controller/ControllerNew.h rename to DRAMSys/library/src/controller/Controller.h index 31bfc7ab..65d80668 100644 --- a/DRAMSys/library/src/controller/ControllerNew.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -32,8 +32,8 @@ * Author: Lukas Steiner */ -#ifndef CONTROLLERNEW_H -#define CONTROLLERNEW_H +#ifndef CONTROLLER_H +#define CONTROLLER_H #include #include @@ -57,12 +57,12 @@ using namespace tlm; class BankMachine; class SchedulerIF; -class ControllerNew : public GenericController +class Controller : public GenericController { public: - ControllerNew(sc_module_name); - SC_HAS_PROCESS(ControllerNew); - virtual ~ControllerNew(); + Controller(sc_module_name); + SC_HAS_PROCESS(Controller); + virtual ~Controller(); protected: virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &); @@ -102,4 +102,4 @@ private: void endBandwithIdleCollector(); }; -#endif // CONTROLLERNEW_H +#endif // CONTROLLER_H diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index c522aead..73c651d3 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -41,14 +41,14 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { recordPhase(trans, phase, delay); - return ControllerNew::nb_transport_fw(trans, phase, delay); + return Controller::nb_transport_fw(trans, phase, delay); } tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) { recordPhase(trans, phase, delay); - return ControllerNew::nb_transport_bw(trans, phase, delay); + return Controller::nb_transport_bw(trans, phase, delay); } void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) @@ -67,7 +67,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } - ControllerNew::sendToDram(command, payload); + Controller::sendToDram(command, payload); } void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index 17459b7d..60a70edd 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -35,14 +35,14 @@ #ifndef CONTROLLERRECORDABLE_H #define CONTROLLERRECORDABLE_H -#include "ControllerNew.h" +#include "Controller.h" #include "../common/TlmRecorder.h" -class ControllerRecordable final : public ControllerNew +class ControllerRecordable final : public Controller { public: ControllerRecordable(sc_module_name name, TlmRecorder *tlmRecorder) : - ControllerNew(name), tlmRecorder(tlmRecorder) {} + Controller(name), tlmRecorder(tlmRecorder) {} private: tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 596f0d74..3d5bba3a 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -56,7 +56,7 @@ #include "DramDDR3.h" #include "DramDDR4.h" #include "DramWideIO.h" -#include "../controller/ControllerNew.h" +#include "../controller/Controller.h" #include "../controller/ControllerRecordable.h" using namespace std; @@ -258,7 +258,7 @@ void DRAMSys::instantiateModules(const string &traceName, if (recordingEnabled) controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]); else - controller = new ControllerNew(str.c_str()); + controller = new Controller(str.c_str()); controllers.push_back(controller); str = "dram" + std::to_string(i); From 62841a359085832701026b5ca71b8512fb31ad88 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 11 Sep 2019 16:02:36 +0200 Subject: [PATCH 090/183] Implemented closed page policy. Fixed bug in trace analyzer tests. --- .../library/src/controller/BankMachine.cpp | 146 ++++++++++++------ DRAMSys/library/src/controller/BankMachine.h | 33 ++-- DRAMSys/library/src/controller/Controller.cpp | 18 ++- .../src/controller/ControllerRecordable.cpp | 2 +- .../src/controller/checker/CheckerDDR3.cpp | 16 ++ .../src/controller/cmdmux/CmdMuxStrict.cpp | 2 +- DRAMSys/traceAnalyzer/scripts/tests.py | 10 +- 7 files changed, 161 insertions(+), 66 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 0264d2b0..4818e017 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -37,53 +37,6 @@ BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) {} -sc_time BankMachine::startBankMachine() -{ - if (currentPayload == nullptr) - { - currentPayload = scheduler->getNextRequest(bank, this); - if (currentPayload == nullptr) - return SC_ZERO_TIME; - } - sc_time delay; - DramExtension extension = DramExtension::getExtension(currentPayload); - if (currentState == BmState::Precharged) // row miss - { - delay = checker->delayToSatisfyConstraints(Command::ACT, bank); - nextCommand = Command::ACT; - nextRow = extension.getRow(); - timeToSchedule = sc_time_stamp() + delay; - } - else if (currentState == BmState::Activated) - { - if (extension.getRow() == currentRow) // row hit - { - if (currentPayload->get_command() == TLM_READ_COMMAND) - { - delay = checker->delayToSatisfyConstraints(Command::RD, bank); - nextCommand = Command::RD; - timeToSchedule = sc_time_stamp() + delay; - } - else if (currentPayload->get_command() == TLM_WRITE_COMMAND) - { - delay = checker->delayToSatisfyConstraints(Command::WR, bank); - nextCommand = Command::WR; - timeToSchedule = sc_time_stamp() + delay; - } - else - SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); - } - else // row miss - { - delay = checker->delayToSatisfyConstraints(Command::PRE, bank); - nextCommand = Command::PRE; - nextRow = extension.getRow(); - timeToSchedule = sc_time_stamp() + delay; - } - } - return delay; -} - std::pair BankMachine::getNextCommand() { if (sc_time_stamp() == timeToSchedule) @@ -103,6 +56,11 @@ void BankMachine::updateState(Command command) currentState = BmState::Precharged; else if (command == Command::RD || command == Command::WR) currentPayload = nullptr; + else if (command == Command::RDA || command == Command::WRA) + { + currentState = BmState::Precharged; + currentPayload = nullptr; + } else SC_REPORT_FATAL("BankMachine", "Unknown phase"); } @@ -127,3 +85,97 @@ BmState BankMachine::getState() { return currentState; } + +BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} + +sc_time BankMachineOpen::startBankMachine() +{ + if (currentPayload == nullptr) + { + currentPayload = scheduler->getNextRequest(bank, this); + if (currentPayload == nullptr) + return SC_ZERO_TIME; + } + sc_time delay; + DramExtension extension = DramExtension::getExtension(currentPayload); + if (currentState == BmState::Precharged) // row miss + { + delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + nextCommand = Command::ACT; + nextRow = extension.getRow(); + } + else if (currentState == BmState::Activated) + { + if (extension.getRow() == currentRow) // row hit + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::RD, bank); + nextCommand = Command::RD; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::WR, bank); + nextCommand = Command::WR; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + else // row miss + { + delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + nextCommand = Command::PRE; + nextRow = extension.getRow(); + } + } + timeToSchedule = sc_time_stamp() + delay; + return delay; +} + +BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} + +sc_time BankMachineClosed::startBankMachine() +{ + if (currentPayload == nullptr) + { + currentPayload = scheduler->getNextRequest(bank, this); + if (currentPayload == nullptr) + return SC_ZERO_TIME; + } + sc_time delay; + DramExtension extension = DramExtension::getExtension(currentPayload); + if (currentState == BmState::Precharged) // row miss + { + delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + nextCommand = Command::ACT; + nextRow = extension.getRow(); + } + else if (currentState == BmState::Activated) + { + if (extension.getRow() == currentRow) // row hit + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::RDA, bank); + nextCommand = Command::RDA; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::WRA, bank); + nextCommand = Command::WRA; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + else // row miss + { + delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + nextCommand = Command::PRE; + nextRow = extension.getRow(); + } + } + timeToSchedule = sc_time_stamp() + delay; + return delay; +} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 87c26072..6ee71ff1 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -58,8 +58,8 @@ enum class BmState class BankMachine { public: - BankMachine(SchedulerIF *, CheckerIF*, Bank); - sc_time startBankMachine(); + virtual ~BankMachine() {} + virtual sc_time startBankMachine() = 0; std::pair getNextCommand(); void updateState(Command); bool forcePrecharge(); @@ -67,16 +67,31 @@ public: Row getOpenRow(); BmState getState(); -private: +protected: + BankMachine(SchedulerIF *, CheckerIF *, Bank); tlm_generic_payload *currentPayload = nullptr; - BmState currentState = BmState::Precharged; - Bank bank; - Row currentRow; - Row nextRow; - Command nextCommand; - sc_time timeToSchedule = SC_ZERO_TIME; SchedulerIF *scheduler; CheckerIF *checker; + Command nextCommand; + Row nextRow; + BmState currentState = BmState::Precharged; + Row currentRow; + sc_time timeToSchedule = SC_ZERO_TIME; + Bank bank; +}; + +class BankMachineOpen final : public BankMachine +{ +public: + BankMachineOpen(SchedulerIF *, CheckerIF *, Bank); + sc_time startBankMachine(); +}; + +class BankMachineClosed final : public BankMachine +{ +public: + BankMachineClosed(SchedulerIF *, CheckerIF *, Bank); + sc_time startBankMachine(); }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 56749619..59e56a7b 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -91,8 +91,16 @@ Controller::Controller(sc_module_name name) : else SC_REPORT_FATAL("Controller", "Selected scheduler not supported"); - for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); + if (config.OpenPagePolicy) + { + for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachineOpen(scheduler, checker, Bank(bankID)); + } + else + { + for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachineClosed(scheduler, checker, Bank(bankID)); + } startBandwidthIdleCollector(); } @@ -211,7 +219,7 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " + delay.to_string()); - if (phase == END_RD || phase == END_WR) + if (phase == END_RD || phase == END_RDA || phase == END_WR || phase == END_WRA) { std::pair element((sc_time_stamp() + delay), &trans); responseQueue.push(element); @@ -276,8 +284,12 @@ void Controller::sendToDram(Command command, tlm_generic_payload *payload) phase = BEGIN_PRE; else if (command == Command::RD) phase = BEGIN_RD; + else if (command == Command::RDA) + phase = BEGIN_RDA; else if (command == Command::WR) phase = BEGIN_WR; + else if (command == Command::WRA) + phase = BEGIN_WRA; else if (command == Command::PREA) phase = BEGIN_PREA; else if (command == Command::REFA) diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 73c651d3..8e3ed98e 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -60,7 +60,7 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phas void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload) { - if (command == Command::RD || command == Command::WR) + if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) { sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command); ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index ec859bde..61b04ff0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -103,10 +103,18 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommand = lastScheduledByCommand[Command::RDA]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommand = lastScheduledByCommand[Command::WR]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + lastCommand = lastScheduledByCommand[Command::WRA]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) @@ -118,10 +126,18 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + lastCommand = lastScheduledByCommand[Command::RDA]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + lastCommand = lastScheduledByCommand[Command::WR]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommand = lastScheduledByCommand[Command::WRA]; + if (lastCommand.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index 024beaf3..c640bd64 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -46,7 +46,7 @@ CmdMuxStrict::selectCommand(std::vector Date: Wed, 11 Sep 2019 20:36:45 +0200 Subject: [PATCH 091/183] Included adaptive page policy. --- .../configs/mcconfigs/fifoStrict.xml | 1 + .../resources/configs/mcconfigs/fr_fcfs.xml | 1 + .../library/src/controller/BankMachine.cpp | 140 +++++++++++++++++- DRAMSys/library/src/controller/BankMachine.h | 15 ++ DRAMSys/library/src/controller/Controller.cpp | 24 ++- .../core/configuration/Configuration.cpp | 2 + .../core/configuration/Configuration.h | 1 + .../core/configuration/TemperatureSimConfig.h | 2 +- .../controller/scheduler/SchedulerFifo.cpp | 26 +++- .../src/controller/scheduler/SchedulerFifo.h | 4 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 21 ++- .../controller/scheduler/SchedulerFrFcfs.h | 4 +- .../src/controller/scheduler/SchedulerIF.h | 4 +- 13 files changed, 231 insertions(+), 14 deletions(-) diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml index bc54f607..64b06284 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml @@ -1,5 +1,6 @@ + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml index bcaf76dd..35e118dc 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml @@ -1,5 +1,6 @@ + diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 4818e017..daeb6cc9 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -76,6 +76,11 @@ bool BankMachine::forcePrecharge() return false; } +Bank BankMachine::getBank() +{ + return bank; +} + Row BankMachine::getOpenRow() { return currentRow; @@ -93,7 +98,7 @@ sc_time BankMachineOpen::startBankMachine() { if (currentPayload == nullptr) { - currentPayload = scheduler->getNextRequest(bank, this); + currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) return SC_ZERO_TIME; } @@ -140,7 +145,7 @@ sc_time BankMachineClosed::startBankMachine() { if (currentPayload == nullptr) { - currentPayload = scheduler->getNextRequest(bank, this); + currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) return SC_ZERO_TIME; } @@ -179,3 +184,134 @@ sc_time BankMachineClosed::startBankMachine() timeToSchedule = sc_time_stamp() + delay; return delay; } + +BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} + +sc_time BankMachineOpenAdaptive::startBankMachine() +{ + if (currentPayload == nullptr) + { + currentPayload = scheduler->getNextRequest(this); + if (currentPayload == nullptr) + return SC_ZERO_TIME; + } + sc_time delay; + DramExtension extension = DramExtension::getExtension(currentPayload); + if (currentState == BmState::Precharged) // row miss + { + delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + nextCommand = Command::ACT; + nextRow = extension.getRow(); + } + else if (currentState == BmState::Activated) + { + if (extension.getRow() == currentRow) // row hit + { + if (scheduler->hasRequest(bank) && !scheduler->hasRowHit(bank, currentRow)) + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::RDA, bank); + nextCommand = Command::RDA; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::WRA, bank); + nextCommand = Command::WRA; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + else + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::RD, bank); + nextCommand = Command::RD; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::WR, bank); + nextCommand = Command::WR; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + } + else // row miss + { + delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + nextCommand = Command::PRE; + nextRow = extension.getRow(); + } + } + timeToSchedule = sc_time_stamp() + delay; + return delay; +} + +BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} + +sc_time BankMachineClosedAdaptive::startBankMachine() +{ + if (currentPayload == nullptr) + { + currentPayload = scheduler->getNextRequest(this); + if (currentPayload == nullptr) + return SC_ZERO_TIME; + } + sc_time delay; + DramExtension extension = DramExtension::getExtension(currentPayload); + if (currentState == BmState::Precharged) // row miss + { + delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + nextCommand = Command::ACT; + nextRow = extension.getRow(); + } + else if (currentState == BmState::Activated) + { + if (extension.getRow() == currentRow) // row hit + { + if (scheduler->hasRowHit(bank, currentRow)) + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::RD, bank); + nextCommand = Command::RD; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::WR, bank); + nextCommand = Command::WR; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + else + { + if (currentPayload->get_command() == TLM_READ_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::RDA, bank); + nextCommand = Command::RDA; + } + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) + { + delay = checker->delayToSatisfyConstraints(Command::WRA, bank); + nextCommand = Command::WRA; + } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + } + } + else // row miss TODO: remove this, can never happen + { + delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + nextCommand = Command::PRE; + nextRow = extension.getRow(); + SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); + } + } + timeToSchedule = sc_time_stamp() + delay; + return delay; +} diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 6ee71ff1..882059e3 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -64,6 +64,7 @@ public: void updateState(Command); bool forcePrecharge(); + Bank getBank(); Row getOpenRow(); BmState getState(); @@ -94,4 +95,18 @@ public: sc_time startBankMachine(); }; +class BankMachineOpenAdaptive final : public BankMachine +{ +public: + BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank); + sc_time startBankMachine(); +}; + +class BankMachineClosedAdaptive final : public BankMachine +{ +public: + BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank); + sc_time startBankMachine(); +}; + #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 59e56a7b..09f69eaf 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -93,13 +93,29 @@ Controller::Controller(sc_module_name name) : if (config.OpenPagePolicy) { - for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachineOpen(scheduler, checker, Bank(bankID)); + if (config.AdaptivePagePolicy) + { + for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID)); + } + else + { + for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachineOpen(scheduler, checker, Bank(bankID)); + } } else { - for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachineClosed(scheduler, checker, Bank(bankID)); + if (config.AdaptivePagePolicy) + { + for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID)); + } + else + { + for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + bankMachines[Bank(bankID)] = new BankMachineClosed(scheduler, checker, Bank(bankID)); + } } startBandwidthIdleCollector(); diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index 03210066..db52486c 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -138,6 +138,8 @@ void Configuration::setParameter(std::string name, std::string value) BankwiseLogic = string2bool(value); else if (name == "OpenPagePolicy") OpenPagePolicy = string2bool(value); + else if (name == "AdaptivePagePolicy") + AdaptivePagePolicy = string2bool(value); else if (name == "MaxNrOfTransactions") MaxNrOfTransactions = string2int(value); else if (name == "Scheduler") diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/controller/core/configuration/Configuration.h index d17c2a95..efab5eeb 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.h @@ -65,6 +65,7 @@ struct Configuration // MCConfig: bool BankwiseLogic = false; bool OpenPagePolicy = true; + bool AdaptivePagePolicy = false; unsigned int MaxNrOfTransactions = 8; std::string Scheduler; unsigned int SJFProbability; diff --git a/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h index 11c0e32d..f8344541 100644 --- a/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h @@ -76,7 +76,7 @@ struct TemperatureSimConfig void parsePowerInfoFile() { - PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile) + PRINTDEBUGMESSAGE("TemperatureSimConfig", "Power Info File: " + powerInfoFile); powerInfoFile = pathToResources + "/configs/thermalsim/" diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 626a3541..a3b1ef70 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -40,14 +40,34 @@ void SchedulerFifo::storeRequest(tlm_generic_payload *payload) buffer[bank].push(payload); } -tlm_generic_payload *SchedulerFifo::getNextRequest(Bank bank, BankMachine *) +tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) { + Bank bank = bankMachine->getBank(); if (!buffer[bank].empty()) { - tlm_generic_payload *result = buffer[bank].front(); + tlm_generic_payload *front = buffer[bank].front(); buffer[bank].pop(); - return result; + return front; } else return nullptr; } + +bool SchedulerFifo::hasRowHit(Bank bank, Row row) +{ + if (!buffer[bank].empty()) + { + tlm_generic_payload *front = buffer[bank].front(); + if (DramExtension::getRow(front) == row) + return true; + } + return false; +} + +bool SchedulerFifo::hasRequest(Bank bank) +{ + if (buffer[bank].empty()) + return false; + else + return true; +} diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index f6640d74..74783a87 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -48,7 +48,9 @@ class SchedulerFifo : public SchedulerIF { public: void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(Bank, BankMachine *); + tlm_generic_payload *getNextRequest(BankMachine *); + bool hasRowHit(Bank, Row); + bool hasRequest(Bank); private: std::map> buffer; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index c6cb27ae..405e389c 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -42,8 +42,9 @@ void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) buffer[bank].push_back(payload); } -tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BankMachine *bankMachine) +tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) { + Bank bank = bankMachine->getBank(); if (!buffer[bank].empty()) { BmState currentState = bankMachine->getState(); @@ -76,3 +77,21 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BankMachine *ban } return nullptr; } + +bool SchedulerFrFcfs::hasRowHit(Bank bank, Row row) +{ + for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) + { + if (DramExtension::getRow(*it) == row) + return true; + } + return false; +} + +bool SchedulerFrFcfs::hasRequest(Bank bank) +{ + if (buffer[bank].empty()) + return false; + else + return true; +} diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 819d7b50..ffc75edc 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -48,7 +48,9 @@ class SchedulerFrFcfs : public SchedulerIF { public: void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(Bank, BankMachine *); + tlm_generic_payload *getNextRequest(BankMachine *); + bool hasRowHit(Bank, Row); + bool hasRequest(Bank); private: std::map> buffer; }; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index e07f3d03..8568773b 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -50,7 +50,9 @@ class SchedulerIF public: virtual ~SchedulerIF() {} virtual void storeRequest(tlm_generic_payload *) = 0; - virtual tlm_generic_payload *getNextRequest(Bank, BankMachine *) = 0; + virtual tlm_generic_payload *getNextRequest(BankMachine *) = 0; + virtual bool hasRowHit(Bank, Row) = 0; + virtual bool hasRequest(Bank) = 0; }; #endif // SCHEDULERIF_H From 26c3bd23c1e12d4a79bc9bc44d0997aa6922ce2b Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 12 Sep 2019 10:55:59 +0200 Subject: [PATCH 092/183] Changed default colour grouping to phase. --- DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp | 2 +- DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h | 2 +- DRAMSys/traceAnalyzer/presentation/traceplot.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp index 45b46ec9..9865cd8a 100644 --- a/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp +++ b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp @@ -44,7 +44,7 @@ PornoTraceScroller::PornoTraceScroller(QWidget *parent): QwtPlot(parent), isInitialized(false), drawingProperties(false, false, - ColorGrouping::Transaction) + ColorGrouping::PhaseType) { setAxisScaleDraw(xBottom, new EngineeringScaleDraw); canvas()->setCursor(Qt::ArrowCursor); diff --git a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h index 21351fc3..a2db4a48 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h +++ b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h @@ -56,7 +56,7 @@ struct TraceDrawingProperties { unsigned int numberOfBanks; TraceDrawingProperties() : drawText(true), drawBorder(true), - colorGrouping(ColorGrouping::Transaction) {} + colorGrouping(ColorGrouping::PhaseType) {} TraceDrawingProperties(bool drawText, bool drawBorder, ColorGrouping colorGrouping) : drawText(drawText), drawBorder(drawBorder), colorGrouping(colorGrouping) {} diff --git a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp index 65434781..871b3e23 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp +++ b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp @@ -158,7 +158,7 @@ void TracePlot::setUpContextMenu() contextMenu->addActions({deselectAll}); QMenu *colorGroupingSubMenu = new QMenu("Group by", contextMenu); - colorGroupingSubMenu->addActions({setColorGroupingTransaction, setColorGroupingPhase, setColorGroupingThread}); + colorGroupingSubMenu->addActions({setColorGroupingPhase, setColorGroupingTransaction, setColorGroupingThread}); contextMenu->addMenu(colorGroupingSubMenu); QMenu *goToSubMenu = new QMenu("Go to", contextMenu); From b9700f1ee5dcbb7a0986084d367cadb477451e3f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 12 Sep 2019 14:56:06 +0200 Subject: [PATCH 093/183] Implemented some basics for ranks. --- DRAMSys/library/src/common/dramExtensions.cpp | 102 ++++++++++++------ DRAMSys/library/src/common/dramExtensions.h | 79 +++++++++----- DRAMSys/library/src/common/utils.cpp | 13 +-- DRAMSys/library/src/common/utils.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 4 +- DRAMSys/library/src/simulation/Arbiter.cpp | 7 +- 6 files changed, 139 insertions(+), 68 deletions(-) diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index cce8f853..399d1b2f 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -42,22 +42,21 @@ using namespace tlm; - DramExtension::DramExtension() : - thread(0), channel(0), bank(0), bankgroup(0), + thread(0), channel(0), rank(0), bankgroup(0), bank(0), row(0), column(0), burstlength(0), payloadID(0) {} -DramExtension::DramExtension(const Thread &thread, const Bank &bank, - const BankGroup &bankgroup, const Row &row, const Column &column, +DramExtension::DramExtension(const Thread &thread, const Rank &rank, const BankGroup &bankgroup, + const Bank &bank, const Row &row, const Column &column, unsigned int burstlength, uint64_t payloadID) : - thread(thread), channel(0), bank(bank), bankgroup(bankgroup), row(row), - column(column), burstlength(burstlength), payloadID(payloadID) {} + thread(thread), channel(0), rank(rank), bankgroup(bankgroup), bank(bank), + row(row), column(column), burstlength(burstlength), payloadID(payloadID) {} -DramExtension::DramExtension(const Thread &thread, const Channel &channel, - const Bank &bank, const BankGroup &bankgroup, const Row &row, +DramExtension::DramExtension(const Thread &thread, const Channel &channel, const Rank &rank, + const BankGroup &bankgroup, const Bank &bank, const Row &row, const Column &column, unsigned int burstlength, uint64_t payloadID) : - thread(thread), channel(channel), bank(bank), bankgroup(bankgroup), row(row), - column(column), burstlength(burstlength), payloadID(payloadID) {} + thread(thread), channel(channel), rank(rank), bankgroup(bankgroup), bank(bank), + row(row), column(column), burstlength(burstlength), payloadID(payloadID) {} DramExtension &DramExtension::getExtension(const tlm_generic_payload *payload) { @@ -73,14 +72,14 @@ DramExtension &DramExtension::getExtension(const tlm_generic_payload &payload) return DramExtension::getExtension(&payload); } -Bank DramExtension::getBank(const tlm_generic_payload *payload) +Thread DramExtension::getThread(const tlm_generic_payload *payload) { - return DramExtension::getExtension(payload).getBank(); + return DramExtension::getExtension(payload).getThread(); } -Bank DramExtension::getBank(const tlm_generic_payload &payload) +Thread DramExtension::getThread(const tlm_generic_payload &payload) { - return DramExtension::getBank(&payload); + return DramExtension::getThread(&payload); } Channel DramExtension::getChannel(const tlm_generic_payload *payload) @@ -93,14 +92,34 @@ Channel DramExtension::getChannel(const tlm_generic_payload &payload) return DramExtension::getChannel(&payload); } -Thread DramExtension::getThread(const tlm_generic_payload *payload) +Rank DramExtension::getRank(const tlm_generic_payload *payload) { - return DramExtension::getExtension(payload).getThread(); + return DramExtension::getExtension(payload).getRank(); } -Thread DramExtension::getThread(const tlm_generic_payload &payload) +Rank DramExtension::getRank(const tlm_generic_payload &payload) { - return DramExtension::getThread(&payload); + return DramExtension::getRank(&payload); +} + +BankGroup DramExtension::getBankGroup(const tlm_generic_payload *payload) +{ + return DramExtension::getExtension(payload).getBankGroup(); +} + +BankGroup DramExtension::getBankGroup(const tlm_generic_payload &payload) +{ + return DramExtension::getBankGroup(&payload); +} + +Bank DramExtension::getBank(const tlm_generic_payload *payload) +{ + return DramExtension::getExtension(payload).getBank(); +} + +Bank DramExtension::getBank(const tlm_generic_payload &payload) +{ + return DramExtension::getBank(&payload); } Row DramExtension::getRow(const tlm_generic_payload *payload) @@ -113,6 +132,16 @@ Row DramExtension::getRow(const tlm_generic_payload &payload) return DramExtension::getRow(&payload); } +Column DramExtension::getColumn(const tlm_generic_payload *payload) +{ + return DramExtension::getExtension(payload).getColumn(); +} + +Column DramExtension::getColumn(const tlm_generic_payload &payload) +{ + return DramExtension::getColumn(&payload); +} + uint64_t DramExtension::getPayloadID(const tlm_generic_payload *payload) { return DramExtension::getExtension(payload).getPayloadID(); @@ -125,15 +154,17 @@ uint64_t DramExtension::getPayloadID(const tlm_generic_payload &payload) tlm_extension_base *DramExtension::clone() const { - return new DramExtension(thread, bank, bankgroup, row, column, burstlength, payloadID); + return new DramExtension(thread, channel, rank, bankgroup, bank, row, column, burstlength, payloadID); } void DramExtension::copy_from(const tlm_extension_base &ext) { const DramExtension &cpyFrom = static_cast(ext); thread = cpyFrom.thread; - bank = cpyFrom.bank; + channel = cpyFrom.channel; + rank = cpyFrom.rank; bankgroup = cpyFrom.bankgroup; + bank = cpyFrom.bank; row = cpyFrom.row; column = cpyFrom.column; burstlength = cpyFrom.burstlength; @@ -149,9 +180,9 @@ Channel DramExtension::getChannel() const return channel; } -Bank DramExtension::getBank() const +Rank DramExtension::getRank() const { - return bank; + return rank; } BankGroup DramExtension::getBankGroup() const @@ -159,6 +190,11 @@ BankGroup DramExtension::getBankGroup() const return bankgroup; } +Bank DramExtension::getBank() const +{ + return bank; +} + Row DramExtension::getRow() const { return row; @@ -191,14 +227,12 @@ tlm_extension_base *GenerationExtension::clone() const void GenerationExtension::copy_from(const tlm_extension_base &ext) { - const GenerationExtension &cpyFrom = static_cast - (ext); + const GenerationExtension &cpyFrom = static_cast(ext); timeOfGeneration = cpyFrom.timeOfGeneration; } -GenerationExtension &GenerationExtension::getExtension(const - tlm::tlm_generic_payload *payload) +GenerationExtension &GenerationExtension::getExtension(const tlm_generic_payload *payload) { GenerationExtension *result = NULL; payload->get_extension(result); @@ -206,14 +240,12 @@ GenerationExtension &GenerationExtension::getExtension(const return *result; } -sc_time GenerationExtension::getTimeOfGeneration(const tlm::tlm_generic_payload - *payload) +sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload *payload) { return GenerationExtension::getExtension(payload).TimeOfGeneration(); } -sc_time GenerationExtension::getTimeOfGeneration(const tlm::tlm_generic_payload - &payload) +sc_time GenerationExtension::getTimeOfGeneration(const tlm_generic_payload &payload) { return GenerationExtension::getTimeOfGeneration(&payload); } @@ -245,6 +277,16 @@ bool operator !=(const Channel &lhs, const Channel &rhs) return !(lhs == rhs); } +//RANK +bool operator ==(const Rank &lhs, const Rank &rhs) +{ + return lhs.ID() == rhs.ID(); +} + +bool operator !=(const Rank &lhs, const Rank &rhs) +{ + return !(lhs == rhs); +} //BANKGROUP bool operator ==(const BankGroup &lhs, const BankGroup &rhs) diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index aa3a176b..0bb74af1 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -41,6 +41,8 @@ #include #include +using namespace tlm; + class Thread { public: @@ -69,6 +71,20 @@ private: unsigned int id; }; +class Rank +{ +public: + explicit Rank(unsigned int id) : id(id) {} + + unsigned int ID() const + { + return id; + } + +private: + unsigned int id; +}; + class BankGroup { public: @@ -145,39 +161,46 @@ private: }; -class DramExtension : public tlm::tlm_extension +class DramExtension : public tlm_extension { public: DramExtension(); - DramExtension(const Thread &thread, const Bank &bank, - const BankGroup &bankgroup, const Row &row, const Column &column, + DramExtension(const Thread &thread, const Rank &rank, const BankGroup &bankgroup, + const Bank &bank, const Row &row, const Column &column, unsigned int burstlength, uint64_t payloadID); - DramExtension(const Thread &thread, const Channel &channel, const Bank &bank, - const BankGroup &bankgroup, const Row &row, + DramExtension(const Thread &thread, const Channel &channel, const Rank &rank, + const BankGroup &bankgroup, const Bank &bank, const Row &row, const Column &column, unsigned int burstlength, uint64_t payloadID); virtual tlm_extension_base *clone() const; virtual void copy_from(const tlm_extension_base &ext); - static DramExtension &getExtension(const tlm::tlm_generic_payload *payload); - static DramExtension &getExtension(const tlm::tlm_generic_payload &payload); + static DramExtension &getExtension(const tlm_generic_payload *payload); + static DramExtension &getExtension(const tlm_generic_payload &payload); // Used for convience, caller could also use getExtension(..) to access these field - static Bank getBank(const tlm::tlm_generic_payload *payload); - static Bank getBank(const tlm::tlm_generic_payload &payload); - static Channel getChannel(const tlm::tlm_generic_payload *payload); - static Channel getChannel(const tlm::tlm_generic_payload &payload); - static Thread getThread(const tlm::tlm_generic_payload *payload); - static Thread getThread(const tlm::tlm_generic_payload &payload); - static Row getRow(const tlm::tlm_generic_payload *payload); - static Row getRow(const tlm::tlm_generic_payload &payload); - static uint64_t getPayloadID(const tlm::tlm_generic_payload *payload); - static uint64_t getPayloadID(const tlm::tlm_generic_payload &payload); + static Thread getThread(const tlm_generic_payload *payload); + static Thread getThread(const tlm_generic_payload &payload); + static Channel getChannel(const tlm_generic_payload *payload); + static Channel getChannel(const tlm_generic_payload &payload); + static Rank getRank(const tlm_generic_payload *payload); + static Rank getRank(const tlm_generic_payload &payload); + static BankGroup getBankGroup(const tlm_generic_payload *payload); + static BankGroup getBankGroup(const tlm_generic_payload &payload); + static Bank getBank(const tlm_generic_payload *payload); + static Bank getBank(const tlm_generic_payload &payload); + static Row getRow(const tlm_generic_payload *payload); + static Row getRow(const tlm_generic_payload &payload); + static Column getColumn(const tlm_generic_payload *payload); + static Column getColumn(const tlm_generic_payload &payload); + static uint64_t getPayloadID(const tlm_generic_payload *payload); + static uint64_t getPayloadID(const tlm_generic_payload &payload); Thread getThread() const; Channel getChannel() const; - Bank getBank() const; + Rank getRank() const; BankGroup getBankGroup() const; + Bank getBank() const; Row getRow() const; Column getColumn() const; @@ -188,8 +211,9 @@ public: private: Thread thread; Channel channel; - Bank bank; + Rank rank; BankGroup bankgroup; + Bank bank; Row row; Column column; unsigned int burstlength; @@ -200,21 +224,21 @@ private: // Used to indicate the time when a payload is created (in a traceplayer or in a core) // Note that this time can be different from the time the payload enters the DRAM system //(at that time the phase BEGIN_REQ is recorded), so timeOfGeneration =< time(BEGIN_REQ) -class GenerationExtension : public tlm::tlm_extension +class GenerationExtension : public tlm_extension { public: - GenerationExtension(sc_time timeOfGeneration) : timeOfGeneration( - timeOfGeneration) {} + GenerationExtension(sc_time timeOfGeneration) + : timeOfGeneration(timeOfGeneration) {} virtual tlm_extension_base *clone() const; virtual void copy_from(const tlm_extension_base &ext); - static GenerationExtension &getExtension(const tlm::tlm_generic_payload - *payload); + static GenerationExtension + &getExtension(const tlm_generic_payload *payload); sc_time TimeOfGeneration() const { return timeOfGeneration; } - static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload); - static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload); + static sc_time getTimeOfGeneration(const tlm_generic_payload *payload); + static sc_time getTimeOfGeneration(const tlm_generic_payload &payload); private: sc_time timeOfGeneration; @@ -228,6 +252,9 @@ bool operator<(const Thread &lhs, const Thread &rhs); bool operator==(const Channel &lhs, const Channel &rhs); bool operator!=(const Channel &lhs, const Channel &rhs); +bool operator==(const Rank &lhs, const Rank &rhs); +bool operator!=(const Rank &lhs, const Rank &rhs); + bool operator==(const BankGroup &lhs, const BankGroup &rhs); bool operator!=(const BankGroup &lhs, const BankGroup &rhs); diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 4f7c1489..af4890f0 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -43,6 +43,7 @@ using namespace std; using namespace tinyxml2; +using namespace tlm; bool TimeInterval::timeIsInInterval(sc_time time) { @@ -68,7 +69,7 @@ void reportFatal(std::string sender, std::string message) SC_REPORT_FATAL(sender.c_str(), message.c_str()); } -std::string phaseNameToString(tlm::tlm_phase phase) +std::string phaseNameToString(tlm_phase phase) { std::ostringstream oss; oss << phase; @@ -235,17 +236,17 @@ string loadTextFileContents(string filename) } } -void setUpDummy(tlm::tlm_generic_payload &payload, Bank bank) +void setUpDummy(tlm_generic_payload &payload, Rank rank, Bank bank) { payload.set_address(bank.getStartAddress()); - payload.set_command(tlm::TLM_READ_COMMAND); + payload.set_command(TLM_READ_COMMAND); payload.set_data_length(0); - payload.set_response_status(tlm::TLM_OK_RESPONSE); + payload.set_response_status(TLM_OK_RESPONSE); payload.set_dmi_allowed(false); payload.set_byte_enable_length(0); payload.set_streaming_width(0); - payload.set_extension(new DramExtension(Thread(UINT_MAX), bank, BankGroup(0), - Row(0), Column(0), 0, 0)); + payload.set_extension(new DramExtension(Thread(UINT_MAX), rank, BankGroup(0), + bank, Row(0), Column(0), 0, 0)); // payload takes ownership // TODO: Dummies muessen noch banggruppe und rank sauber bekommen .. noch was ueberlegen!!! } diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index d856c96e..003c6829 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -146,7 +146,7 @@ std::string queryStringParameter(tinyxml2::XMLElement *node, std::string name); bool queryBoolParameter(tinyxml2::XMLElement *node, std::string name); double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name); -void setUpDummy(tlm::tlm_generic_payload &payload, Bank bank = Bank(0)); +void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0)); #endif // UTILS_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 113e07d0..0a5c0d7d 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -41,14 +41,14 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::map &ba : bankMachines(bankMachines) { memSpec = Configuration::getInstance().memSpec; - + // TODO: implement for multiple ranks sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); timeForNextTrigger = currentPRE; for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) { states[Bank(bankID)] = RmState::IDLE; - setUpDummy(refreshPayloads[Bank(bankID)], Bank(bankID)); + setUpDummy(refreshPayloads[Bank(bankID)], Rank(0), Bank(bankID)); triggerTimes.insert(std::pair(currentREFB, Bank(bankID))); triggerTimes.insert(std::pair(currentPRE, Bank(bankID))); currentREFB += memSpec->clk; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index a5543332..62c7642a 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -216,8 +216,9 @@ void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) DecodedAddress decodedAddress = AddressDecoder::getInstance().decodeAddress(payload.get_address()); // Check the valid range of decodedAddress if (addressIsValid(decodedAddress)) { - DramExtension *extension = new DramExtension(Thread(socketId), Channel(decodedAddress.channel), - Bank(decodedAddress.bank), BankGroup(decodedAddress.bankgroup), + DramExtension *extension = new DramExtension(Thread(socketId), + Channel(decodedAddress.channel), Rank(decodedAddress.rank), + BankGroup(decodedAddress.bankgroup), Bank(decodedAddress.bank), Row(decodedAddress.row), Column(decodedAddress.column), burstlength, nextPayloadID[decodedAddress.channel]++); payload.set_auto_extension(extension); @@ -226,7 +227,7 @@ void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) } } -bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) +bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) { if (decodedAddress.channel >= AddressDecoder::getInstance().amount["channel"]) { return false; From 3a7557544f2d57139a332416b4c1a714ad2fb636 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 16 Sep 2019 15:16:14 +0200 Subject: [PATCH 094/183] Rank inclusion part 1. --- .../configs/amconfigs/am_ranktest.xml | 26 +++++++++ .../configs/memspecs/memspec_ranktest.xml | 55 +++++++++++++++++++ .../resources/simulations/ranktest.xml | 25 +++++++++ .../library/src/common/XmlAddressDecoder.cpp | 9 +-- .../library/src/controller/BankMachine.cpp | 30 ++++++---- DRAMSys/library/src/controller/BankMachine.h | 13 +++-- DRAMSys/library/src/controller/Controller.cpp | 14 +++-- DRAMSys/library/src/controller/Controller.h | 2 - DRAMSys/library/src/simulation/Arbiter.cpp | 7 ++- 9 files changed, 153 insertions(+), 28 deletions(-) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml create mode 100644 DRAMSys/library/resources/simulations/ranktest.xml diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml new file mode 100644 index 00000000..11b68c5c --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml @@ -0,0 +1,26 @@ + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml new file mode 100644 index 00000000..45606d2b --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/ranktest.xml b/DRAMSys/library/resources/simulations/ranktest.xml new file mode 100644 index 00000000..23de6d07 --- /dev/null +++ b/DRAMSys/library/resources/simulations/ranktest.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ranktest.stl + + diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index dfbb4dd8..65795e97 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -80,12 +80,13 @@ DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) { DecodedAddress result; result.channel = (addr & masks["channel"]) >> shifts["channel"]; - //result.rank = (addr & masks["rank"]) >> shifts["rank"]; + result.rank = (addr & masks["rank"]) >> shifts["rank"]; //result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"]; result.bank = (addr & masks["bank"]) >> shifts["bank"]; - result.bankgroup = result.bank % - Configuration::getInstance().memSpec->NumberOfBankGroups; - result.rank = result.bank % Configuration::getInstance().memSpec->NumberOfRanks; + unsigned banksPerGroup = Configuration::getInstance().memSpec->NumberOfBanks + / Configuration::getInstance().memSpec->NumberOfBankGroups; + result.bankgroup = result.bank / banksPerGroup; + //result.rank = result.bank % Configuration::getInstance().memSpec->NumberOfRanks; result.row = (addr & masks["row"]) >> shifts["row"]; result.column = (addr & masks["column"]) >> shifts["column"]; result.bytes = (addr & masks["bytes"]) >> shifts["bytes"]; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index daeb6cc9..7765ff9d 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -34,8 +34,9 @@ #include "BankMachine.h" -BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) - : scheduler(scheduler), checker(checker), bank(bank) {} +BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, + Rank rank, BankGroup bankgroup, Bank bank) + : scheduler(scheduler), checker(checker), rank(rank), bankgroup(bankgroup), bank(bank) {} std::pair BankMachine::getNextCommand() { @@ -76,6 +77,11 @@ bool BankMachine::forcePrecharge() return false; } +Rank BankMachine::getRank() +{ + return rank; +} + Bank BankMachine::getBank() { return bank; @@ -91,8 +97,9 @@ BmState BankMachine::getState() return currentState; } -BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) - : BankMachine(scheduler, checker, bank) {} +BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, + Rank rank, BankGroup bankgroup, Bank bank) + : BankMachine(scheduler, checker, rank, bankgroup, bank) {} sc_time BankMachineOpen::startBankMachine() { @@ -138,8 +145,9 @@ sc_time BankMachineOpen::startBankMachine() return delay; } -BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) - : BankMachine(scheduler, checker, bank) {} +BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, + Rank rank, BankGroup bankgroup, Bank bank) + : BankMachine(scheduler, checker, rank, bankgroup, bank) {} sc_time BankMachineClosed::startBankMachine() { @@ -185,8 +193,9 @@ sc_time BankMachineClosed::startBankMachine() return delay; } -BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) - : BankMachine(scheduler, checker, bank) {} +BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, + Rank rank, BankGroup bankgroup, Bank bank) + : BankMachine(scheduler, checker, rank, bankgroup, bank) {} sc_time BankMachineOpenAdaptive::startBankMachine() { @@ -250,8 +259,9 @@ sc_time BankMachineOpenAdaptive::startBankMachine() return delay; } -BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) - : BankMachine(scheduler, checker, bank) {} +BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, + Rank rank, BankGroup bankgroup, Bank bank) + : BankMachine(scheduler, checker, rank, bankgroup, bank) {} sc_time BankMachineClosedAdaptive::startBankMachine() { diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 882059e3..910afe6b 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -64,12 +64,13 @@ public: void updateState(Command); bool forcePrecharge(); + Rank getRank(); Bank getBank(); Row getOpenRow(); BmState getState(); protected: - BankMachine(SchedulerIF *, CheckerIF *, Bank); + BankMachine(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); tlm_generic_payload *currentPayload = nullptr; SchedulerIF *scheduler; CheckerIF *checker; @@ -78,34 +79,36 @@ protected: BmState currentState = BmState::Precharged; Row currentRow; sc_time timeToSchedule = SC_ZERO_TIME; + Rank rank; + BankGroup bankgroup; Bank bank; }; class BankMachineOpen final : public BankMachine { public: - BankMachineOpen(SchedulerIF *, CheckerIF *, Bank); + BankMachineOpen(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); sc_time startBankMachine(); }; class BankMachineClosed final : public BankMachine { public: - BankMachineClosed(SchedulerIF *, CheckerIF *, Bank); + BankMachineClosed(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); sc_time startBankMachine(); }; class BankMachineOpenAdaptive final : public BankMachine { public: - BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank); + BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); sc_time startBankMachine(); }; class BankMachineClosedAdaptive final : public BankMachine { public: - BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank); + BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); sc_time startBankMachine(); }; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 09f69eaf..849be582 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -96,12 +96,14 @@ Controller::Controller(sc_module_name name) : if (config.AdaptivePagePolicy) { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID)); + bankMachines[Bank(bankID)] + = new BankMachineOpenAdaptive(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); } else { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachineOpen(scheduler, checker, Bank(bankID)); + bankMachines[Bank(bankID)] + = new BankMachineOpen(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); } } else @@ -109,12 +111,14 @@ Controller::Controller(sc_module_name name) : if (config.AdaptivePagePolicy) { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID)); + bankMachines[Bank(bankID)] + = new BankMachineClosedAdaptive(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); } else { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] = new BankMachineClosed(scheduler, checker, Bank(bankID)); + bankMachines[Bank(bankID)] + = new BankMachineClosed(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); } } @@ -213,6 +217,8 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, payloadToAcquire = &trans; timeToAcquire = sc_time_stamp() + notificationDelay; beginReqEvent.notify(notificationDelay); + std::cout << "Bank: " << DramExtension::getBank(trans).ID() << ", BankGroup: " + << DramExtension::getBankGroup(trans).ID() << ", Rank: " << DramExtension::getRank(trans).ID() << std::endl; } else if (phase = END_RESP) { diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 65d80668..c9407b74 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -93,8 +93,6 @@ private: sc_event beginReqEvent, endRespEvent, bankMachineEvent, refreshEvent; sc_event_queue dataResponseEventQueue; - std::map commandFinishedTime; - // Bandwidth related sc_time idleStart; bool isIdle = false; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 62c7642a..0752e07c 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -235,10 +235,11 @@ bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) if (decodedAddress.bank >= AddressDecoder::getInstance().amount["bank"]) { return false; } - if (decodedAddress.bankgroup > - AddressDecoder::getInstance().amount["bankgroup"]) { + // TODO: this test case should be corrected! + /*if (decodedAddress.bankgroup >= AddressDecoder::getInstance().amount["bankgroup"]) { + std::cout << decodedAddress.bankgroup << " " << AddressDecoder::getInstance().amount["bankgroup"] << std::endl; return false; - } + }*/ if (decodedAddress.column >= AddressDecoder::getInstance().amount["column"]) { return false; } From 5d7495383e1d39ab870bfe3f521551f029a3b839 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 17 Sep 2019 18:16:52 +0200 Subject: [PATCH 095/183] Changed internal data structures from std::map to std::vector for faster access. --- DRAMSys/library/src/controller/Command.cpp | 8 +++- DRAMSys/library/src/controller/Command.h | 3 +- DRAMSys/library/src/controller/Controller.cpp | 36 +++++++-------- DRAMSys/library/src/controller/Controller.h | 3 +- .../src/controller/checker/CheckerDDR3.cpp | 46 ++++++++++--------- .../src/controller/checker/CheckerDDR3.h | 6 +-- .../src/controller/checker/CheckerIF.h | 6 +-- .../src/controller/checker/CheckerWideIO.cpp | 46 ++++++++++--------- .../src/controller/checker/CheckerWideIO.h | 6 +-- .../src/controller/refresh/RefreshManager.cpp | 4 +- .../src/controller/refresh/RefreshManager.h | 4 +- .../refresh/RefreshManagerBankwise.cpp | 20 ++++---- .../refresh/RefreshManagerBankwise.h | 9 ++-- .../controller/scheduler/SchedulerFifo.cpp | 24 ++++++---- .../src/controller/scheduler/SchedulerFifo.h | 5 +- .../controller/scheduler/SchedulerFrFcfs.cpp | 30 +++++++----- .../controller/scheduler/SchedulerFrFcfs.h | 5 +- 17 files changed, 146 insertions(+), 115 deletions(-) diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 6259afe8..2890bc36 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -102,7 +102,8 @@ std::string commandToString(Command command) const std::vector &getAllCommands() { - static std::vector allCommands( { Command::PRE, + static std::vector allCommands( { Command::NOP, + Command::PRE, Command::PREA, Command::ACT, Command::RD, @@ -121,6 +122,11 @@ const std::vector &getAllCommands() return allCommands; } +unsigned numberOfCommands() +{ + return 16; +} + bool commandIsIn(Command command, std::vector commands) { for (Command c : commands) { diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 5ffa8c8c..4bb09641 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -39,7 +39,7 @@ #include #include -enum class Command +enum Command { NOP, PRE, @@ -61,6 +61,7 @@ enum class Command std::string commandToString(Command command); const std::vector &getAllCommands(); +unsigned numberOfCommands(); bool commandIsIn(Command command, std::vector commands); #endif // COMMAND_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 849be582..99be6756 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -96,14 +96,14 @@ Controller::Controller(sc_module_name name) : if (config.AdaptivePagePolicy) { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] - = new BankMachineOpenAdaptive(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); + bankMachines.push_back(new BankMachineOpenAdaptive + (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); } else { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] - = new BankMachineOpen(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); + bankMachines.push_back(new BankMachineOpen + (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); } } else @@ -111,14 +111,14 @@ Controller::Controller(sc_module_name name) : if (config.AdaptivePagePolicy) { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] - = new BankMachineClosedAdaptive(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); + bankMachines.push_back(new BankMachineClosedAdaptive + (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); } else { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines[Bank(bankID)] - = new BankMachineClosed(scheduler, checker, Rank(0), BankGroup(0), Bank(bankID)); + bankMachines.push_back(new BankMachineClosed + (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); } } @@ -130,7 +130,7 @@ Controller::~Controller() endBandwithIdleCollector(); for (auto it : bankMachines) - delete it.second; + delete it; delete commandMux; delete scheduler; delete refreshManager; @@ -166,7 +166,7 @@ void Controller::controllerMethod() // (4) Start bank machines to issue new requests for current time for (auto it : bankMachines) - it.second->startBankMachine(); + it->startBankMachine(); // (5) Choose one request and send it to DRAM std::pair result; @@ -181,7 +181,7 @@ void Controller::controllerMethod() std::vector> readyCommands; for (auto it : bankMachines) { - result = it.second->getNextCommand(); + result = it->getNextCommand(); if (result.second != nullptr) readyCommands.push_back(result); } @@ -190,8 +190,8 @@ void Controller::controllerMethod() result = commandMux->selectCommand(readyCommands); if (result.second != nullptr) { - Bank bank = DramExtension::getBank(result.second); - bankMachines[bank]->updateState(result.first); + unsigned bankID = DramExtension::getBank(result.second).ID(); + bankMachines[bankID]->updateState(result.first); sendToDram(result.first, result.second); } } @@ -200,7 +200,7 @@ void Controller::controllerMethod() // (6) Restart bank machines to issue new requests for the future for (auto it : bankMachines) { - sc_time delay = it.second->startBankMachine(); + sc_time delay = it->startBankMachine(); if (delay != SC_ZERO_TIME) // must be checked to avoid livelock bankMachineEvent.notify(delay); } @@ -217,8 +217,8 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, payloadToAcquire = &trans; timeToAcquire = sc_time_stamp() + notificationDelay; beginReqEvent.notify(notificationDelay); - std::cout << "Bank: " << DramExtension::getBank(trans).ID() << ", BankGroup: " - << DramExtension::getBankGroup(trans).ID() << ", Rank: " << DramExtension::getRank(trans).ID() << std::endl; +// std::cout << "Bank: " << DramExtension::getBank(trans).ID() << ", BankGroup: " +// << DramExtension::getBankGroup(trans).ID() << ", Rank: " << DramExtension::getRank(trans).ID() << std::endl; } else if (phase = END_RESP) { @@ -243,8 +243,8 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, if (phase == END_RD || phase == END_RDA || phase == END_WR || phase == END_WRA) { - std::pair element((sc_time_stamp() + delay), &trans); - responseQueue.push(element); + // TODO: check this part (order of responses) + responseQueue.push({(sc_time_stamp() + delay), &trans}); dataResponseEventQueue.notify(delay); } return TLM_ACCEPTED; diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index c9407b74..64daab41 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -35,7 +35,6 @@ #ifndef CONTROLLER_H #define CONTROLLER_H -#include #include #include #include @@ -80,7 +79,7 @@ private: sc_time timeToRelease = SC_ZERO_TIME; std::queue> responseQueue; - std::map bankMachines; + std::vector bankMachines; CmdMuxIF *commandMux; SchedulerIF *scheduler; CheckerIF *checker; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 61b04ff0..2e183798 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -47,6 +47,10 @@ CheckerDDR3::CheckerDDR3() refreshChecker = new RefreshCheckerDDR3Bankwise(memSpec); else refreshChecker = new RefreshCheckerDDR3(memSpec); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); } CheckerDDR3::~CheckerDDR3() @@ -62,19 +66,19 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (command == Command::ACT) { - lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); @@ -86,7 +90,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); - lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); @@ -96,7 +100,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::RD || command == Command::RDA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); lastCommand = lastScheduledByCommand[Command::RD]; @@ -119,7 +123,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::WR || command == Command::WRA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); lastCommand = lastScheduledByCommand[Command::RD]; @@ -142,14 +146,14 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::PRE) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRAS); - lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP); - lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); @@ -184,7 +188,7 @@ void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) to_string(scheduledCommand.getBank().ID()) + " command is " + commandToString(command)); - lastScheduledByCommandAndBank[command][bank] = scheduledCommand; + lastScheduledByCommandAndBank[command][bank.ID()] = scheduledCommand; lastScheduledByCommand[command] = scheduledCommand; lastScheduled = scheduledCommand; @@ -236,8 +240,8 @@ RefreshCheckerDDR3Bankwise::RefreshCheckerDDR3Bankwise(const MemSpecDDR3 *memSpe sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) { - timesForNextREFB[Bank(bankID)] = currentREFB; - timesForNextPRE[Bank(bankID)] = currentPRE; + timesForNextREFB.push_back(currentREFB); + timesForNextPRE.push_back(currentPRE); currentREFB += memSpec->clk; currentPRE += memSpec->clk; } @@ -245,24 +249,24 @@ RefreshCheckerDDR3Bankwise::RefreshCheckerDDR3Bankwise(const MemSpecDDR3 *memSpe void RefreshCheckerDDR3Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) { - if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRAS)) - earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; } void RefreshCheckerDDR3Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) { - if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRTP)) - earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; } void RefreshCheckerDDR3Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) { - if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; } void RefreshCheckerDDR3Bankwise::insert(Bank bank) { - timesForNextREFB[bank] += memSpec->tREFI; - timesForNextPRE[bank] += memSpec->tREFI; + timesForNextREFB[bank.ID()] += memSpec->tREFI; + timesForNextPRE[bank.ID()] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index b30192eb..9082ea17 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -37,7 +37,7 @@ #include "CheckerIF.h" #include -#include +#include #include "../core/configuration/MemSpec.h" #include "../core/configuration/Configuration.h" @@ -108,8 +108,8 @@ private: void delayToSatisfyWR(Bank, sc_time &); void insert(Bank); - std::map timesForNextREFB; - std::map timesForNextPRE; + std::vector timesForNextREFB; + std::vector timesForNextPRE; }; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 9a7c4e0a..c1586373 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -36,7 +36,7 @@ #define CHECKERIF_H #include -#include +#include #include "../core/scheduling/ScheduledCommand.h" #include "../Command.h" #include "../../common/dramExtensions.h" @@ -51,8 +51,8 @@ public: virtual void insert(const ScheduledCommand &) = 0; protected: - std::map> lastScheduledByCommandAndBank; - std::map lastScheduledByCommand; + std::vector> lastScheduledByCommandAndBank; + std::vector lastScheduledByCommand; ScheduledCommand lastScheduled; // PowerDown TODO: Implement this method? diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 05e9585c..6cc5dc8f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -47,6 +47,10 @@ CheckerWideIO::CheckerWideIO() refreshChecker = new RefreshCheckerWideIOBankwise(memSpec); else refreshChecker = new RefreshCheckerWideIO(memSpec); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); } CheckerWideIO::~CheckerWideIO() @@ -62,19 +66,19 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) if (command == Command::ACT) { - lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); @@ -86,7 +90,7 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); - lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); @@ -96,7 +100,7 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::RD || command == Command::RDA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); lastCommand = lastScheduledByCommand[Command::RD]; @@ -111,7 +115,7 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::WR || command == Command::WRA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); lastCommand = lastScheduledByCommand[Command::RD]; @@ -126,14 +130,14 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::PRE) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRAS); - lastCommand = lastScheduledByCommandAndBank[Command::RD][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP); - lastCommand = lastScheduledByCommandAndBank[Command::WR][bank]; + lastCommand = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); @@ -168,7 +172,7 @@ void CheckerWideIO::insert(const ScheduledCommand &scheduledCommand) to_string(scheduledCommand.getBank().ID()) + " command is " + commandToString(command)); - lastScheduledByCommandAndBank[command][bank] = scheduledCommand; + lastScheduledByCommandAndBank[command][bank.ID()] = scheduledCommand; lastScheduledByCommand[command] = scheduledCommand; lastScheduled = scheduledCommand; @@ -220,8 +224,8 @@ RefreshCheckerWideIOBankwise::RefreshCheckerWideIOBankwise(const MemSpecWideIO * sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) { - timesForNextREFB[Bank(bankID)] = currentREFB; - timesForNextPRE[Bank(bankID)] = currentPRE; + timesForNextREFB.push_back(currentREFB); + timesForNextPRE.push_back(currentPRE); currentREFB += memSpec->clk; currentPRE += memSpec->clk; } @@ -229,24 +233,24 @@ RefreshCheckerWideIOBankwise::RefreshCheckerWideIOBankwise(const MemSpecWideIO * void RefreshCheckerWideIOBankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) { - if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRAS)) - earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; } void RefreshCheckerWideIOBankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) { - if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tRTP)) - earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; } void RefreshCheckerWideIOBankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) { - if (earliestTimeToStart >= (timesForNextPRE[bank] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timesForNextREFB[bank] + memSpec->tRFC; + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; } void RefreshCheckerWideIOBankwise::insert(Bank bank) { - timesForNextREFB[bank] += memSpec->tREFI; - timesForNextPRE[bank] += memSpec->tREFI; + timesForNextREFB[bank.ID()] += memSpec->tREFI; + timesForNextPRE[bank.ID()] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 1751d3cc..29950347 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -37,7 +37,7 @@ #include "CheckerIF.h" #include -#include +#include #include "../core/configuration/MemSpec.h" #include "../core/configuration/Configuration.h" @@ -108,8 +108,8 @@ private: void delayToSatisfyWR(Bank, sc_time &); void insert(Bank); - std::map timesForNextREFB; - std::map timesForNextPRE; + std::vector timesForNextREFB; + std::vector timesForNextPRE; }; #endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 494e8983..b0a5687f 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -37,7 +37,7 @@ #include "../core/configuration/Configuration.h" #include "../../common/utils.h" -RefreshManager::RefreshManager(std::map &bankMachines) : bankMachines(bankMachines) +RefreshManager::RefreshManager(std::vector &bankMachines) : bankMachines(bankMachines) { memSpec = Configuration::getInstance().memSpec; setUpDummy(refreshPayload); @@ -54,7 +54,7 @@ std::pair RefreshManager::getNextCommand() timeForNextTrigger += memSpec->getExecutionTime(Command::PREA); bool forcedPrecharges = false; for (auto it : bankMachines) - forcedPrecharges |= it.second->forcePrecharge(); + forcedPrecharges |= it->forcePrecharge(); if (forcedPrecharges) return std::pair(Command::PREA, &refreshPayload); else diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 953bdef4..4a9ccedf 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -44,7 +44,7 @@ using namespace tlm; class RefreshManager final : public RefreshManagerIF { public: - RefreshManager(std::map &); + RefreshManager(std::vector &); std::pair getNextCommand(); sc_time getTriggerDelay(); @@ -52,7 +52,7 @@ public: private: enum class RmState {IDLE, REFRESHING} state = RmState::IDLE; const MemSpec *memSpec; - std::map &bankMachines; + std::vector &bankMachines; tlm_generic_payload refreshPayload; sc_time timeForNextTrigger; }; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 0a5c0d7d..12bd1781 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -37,7 +37,7 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" -RefreshManagerBankwise::RefreshManagerBankwise(std::map &bankMachines) +RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines) : bankMachines(bankMachines) { memSpec = Configuration::getInstance().memSpec; @@ -45,10 +45,12 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::map &ba sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); timeForNextTrigger = currentPRE; + + refreshPayloads = std::vector(memSpec->NumberOfBanks); + states = std::vector(memSpec->NumberOfBanks, RmState::IDLE); for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) { - states[Bank(bankID)] = RmState::IDLE; - setUpDummy(refreshPayloads[Bank(bankID)], Rank(0), Bank(bankID)); + setUpDummy(refreshPayloads[bankID], Rank(0), Bank(bankID)); triggerTimes.insert(std::pair(currentREFB, Bank(bankID))); triggerTimes.insert(std::pair(currentPRE, Bank(bankID))); currentREFB += memSpec->clk; @@ -65,19 +67,19 @@ std::pair RefreshManagerBankwise::getNextCommand triggerTimes.erase(it); triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->tREFI, bank)); timeForNextTrigger = triggerTimes.begin()->first; - if (states[bank] == RmState::IDLE) + if (states[bank.ID()] == RmState::IDLE) { - states[bank] = RmState::REFRESHING; - bool forcedPrecharge = bankMachines[bank]->forcePrecharge(); + states[bank.ID()] = RmState::REFRESHING; + bool forcedPrecharge = bankMachines[bank.ID()]->forcePrecharge(); if (forcedPrecharge) - return std::pair(Command::PRE, &refreshPayloads[bank]); + return std::pair(Command::PRE, &refreshPayloads[bank.ID()]); else return std::pair(Command::NOP, nullptr); } else { - states[bank] = RmState::IDLE; - return std::pair(Command::REFB, &refreshPayloads[bank]); + states[bank.ID()] = RmState::IDLE; + return std::pair(Command::REFB, &refreshPayloads[bank.ID()]); } } else diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 64102936..97ae782a 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -40,23 +40,24 @@ #include "../BankMachine.h" #include #include +#include class RefreshManagerBankwise final : public RefreshManagerIF { public: - RefreshManagerBankwise(std::map &); + RefreshManagerBankwise(std::vector &); std::pair getNextCommand(); sc_time getTriggerDelay(); private: const MemSpec *memSpec; - std::map &bankMachines; - std::map refreshPayloads; + std::vector &bankMachines; + std::vector refreshPayloads; std::map triggerTimes; sc_time timeForNextTrigger; enum class RmState {IDLE, REFRESHING}; - std::map states; + std::vector states; }; #endif // REFRESHMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index a3b1ef70..9f0eb5ae 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -34,19 +34,25 @@ #include "SchedulerFifo.h" +SchedulerFifo::SchedulerFifo() +{ + buffer = std::vector> + (Configuration::getInstance().memSpec->NumberOfBanks); +} + void SchedulerFifo::storeRequest(tlm_generic_payload *payload) { - Bank bank = DramExtension::getBank(payload); - buffer[bank].push(payload); + unsigned bankID = DramExtension::getBank(payload).ID(); + buffer[bankID].push(payload); } tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) { - Bank bank = bankMachine->getBank(); - if (!buffer[bank].empty()) + unsigned bankID = bankMachine->getBank().ID(); + if (!buffer[bankID].empty()) { - tlm_generic_payload *front = buffer[bank].front(); - buffer[bank].pop(); + tlm_generic_payload *front = buffer[bankID].front(); + buffer[bankID].pop(); return front; } else @@ -55,9 +61,9 @@ tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) bool SchedulerFifo::hasRowHit(Bank bank, Row row) { - if (!buffer[bank].empty()) + if (!buffer[bank.ID()].empty()) { - tlm_generic_payload *front = buffer[bank].front(); + tlm_generic_payload *front = buffer[bank.ID()].front(); if (DramExtension::getRow(front) == row) return true; } @@ -66,7 +72,7 @@ bool SchedulerFifo::hasRowHit(Bank bank, Row row) bool SchedulerFifo::hasRequest(Bank bank) { - if (buffer[bank].empty()) + if (buffer[bank.ID()].empty()) return false; else return true; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index 74783a87..eac15127 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -36,7 +36,7 @@ #define SCHEDULERFIFO_H #include -#include +#include #include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" @@ -47,12 +47,13 @@ using namespace tlm; class SchedulerFifo : public SchedulerIF { public: + SchedulerFifo(); void storeRequest(tlm_generic_payload *); tlm_generic_payload *getNextRequest(BankMachine *); bool hasRowHit(Bank, Row); bool hasRequest(Bank); private: - std::map> buffer; + std::vector> buffer; }; #endif // SCHEDULERFIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index 405e389c..c9f2df18 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -36,40 +36,46 @@ #include +SchedulerFrFcfs::SchedulerFrFcfs() +{ + buffer = std::vector> + (Configuration::getInstance().memSpec->NumberOfBanks); +} + void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) { - Bank bank = DramExtension::getBank(payload); - buffer[bank].push_back(payload); + unsigned bankID = DramExtension::getBank(payload).ID(); + buffer[bankID].push_back(payload); } tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) { - Bank bank = bankMachine->getBank(); - if (!buffer[bank].empty()) + unsigned bankID = bankMachine->getBank().ID(); + if (!buffer[bankID].empty()) { BmState currentState = bankMachine->getState(); if (currentState == BmState::Precharged) { - tlm_generic_payload *result = buffer[bank].front(); - buffer[bank].erase(buffer[bank].begin()); + tlm_generic_payload *result = buffer[bankID].front(); + buffer[bankID].erase(buffer[bankID].begin()); return result; } else if (currentState == BmState::Activated) { // Search for row hit Row openRow = bankMachine->getOpenRow(); - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) + for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++) { if (DramExtension::getRow(*it) == openRow) { tlm_generic_payload *result = *it; - buffer[bank].erase(it); + buffer[bankID].erase(it); return result; } } // No row hit found - tlm_generic_payload *result = buffer[bank].front(); - buffer[bank].erase(buffer[bank].begin()); + tlm_generic_payload *result = buffer[bankID].front(); + buffer[bankID].erase(buffer[bankID].begin()); return result; } else @@ -80,7 +86,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) bool SchedulerFrFcfs::hasRowHit(Bank bank, Row row) { - for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++) + for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++) { if (DramExtension::getRow(*it) == row) return true; @@ -90,7 +96,7 @@ bool SchedulerFrFcfs::hasRowHit(Bank bank, Row row) bool SchedulerFrFcfs::hasRequest(Bank bank) { - if (buffer[bank].empty()) + if (buffer[bank.ID()].empty()) return false; else return true; diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index ffc75edc..9946e39f 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -36,7 +36,7 @@ #define SCHEDULERFRFCFS_H #include -#include +#include #include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" @@ -47,12 +47,13 @@ using namespace tlm; class SchedulerFrFcfs : public SchedulerIF { public: + SchedulerFrFcfs(); void storeRequest(tlm_generic_payload *); tlm_generic_payload *getNextRequest(BankMachine *); bool hasRowHit(Bank, Row); bool hasRequest(Bank); private: - std::map> buffer; + std::vector> buffer; }; #endif // SCHEDULERFRFCFS_H From 6eef8ff1e6da707c3a4d125cb06075507b391548 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 17 Sep 2019 21:31:57 +0200 Subject: [PATCH 096/183] Rank inclusion part 2. --- .../configs/memspecs/memspec_ranktest.xml | 2 +- .../library/src/common/XmlAddressDecoder.cpp | 4 +- .../library/src/controller/BankMachine.cpp | 72 ++++++++++--------- DRAMSys/library/src/controller/BankMachine.h | 14 ++-- DRAMSys/library/src/controller/Controller.cpp | 12 ++-- .../src/controller/checker/CheckerDDR3.cpp | 31 ++++---- .../src/controller/checker/CheckerDDR3.h | 5 +- .../src/controller/checker/CheckerIF.h | 3 +- .../src/controller/checker/CheckerWideIO.cpp | 31 ++++---- .../src/controller/checker/CheckerWideIO.h | 5 +- .../core/scheduling/ScheduledCommand.cpp | 5 ++ .../core/scheduling/ScheduledCommand.h | 1 + DRAMSys/library/src/simulation/Arbiter.cpp | 18 ++--- 13 files changed, 102 insertions(+), 101 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml index 45606d2b..cd5852ec 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml @@ -5,7 +5,7 @@ - + diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 65795e97..1c819b57 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -82,7 +82,9 @@ DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) result.channel = (addr & masks["channel"]) >> shifts["channel"]; result.rank = (addr & masks["rank"]) >> shifts["rank"]; //result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"]; - result.bank = (addr & masks["bank"]) >> shifts["bank"]; + unsigned banksPerRank = Configuration::getInstance().memSpec->NumberOfBanks + / Configuration::getInstance().memSpec->NumberOfRanks; + result.bank = ((addr & masks["bank"]) >> shifts["bank"]) + result.rank * banksPerRank; unsigned banksPerGroup = Configuration::getInstance().memSpec->NumberOfBanks / Configuration::getInstance().memSpec->NumberOfBankGroups; result.bankgroup = result.bank / banksPerGroup; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 7765ff9d..836edb97 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -34,9 +34,15 @@ #include "BankMachine.h" -BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, - Rank rank, BankGroup bankgroup, Bank bank) - : scheduler(scheduler), checker(checker), rank(rank), bankgroup(bankgroup), bank(bank) {} +BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : scheduler(scheduler), checker(checker), bank(bank) +{ + MemSpec *memSpec = Configuration::getInstance().memSpec; + unsigned banksPerRank = memSpec->NumberOfBanks / memSpec->NumberOfRanks; + unsigned banksPerGroup = memSpec->NumberOfBanks / memSpec->NumberOfBankGroups; + rank = Rank(bank.ID() / banksPerRank); + bankgroup = BankGroup(bank.ID() / banksPerGroup); +} std::pair BankMachine::getNextCommand() { @@ -97,9 +103,8 @@ BmState BankMachine::getState() return currentState; } -BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, - Rank rank, BankGroup bankgroup, Bank bank) - : BankMachine(scheduler, checker, rank, bankgroup, bank) {} +BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} sc_time BankMachineOpen::startBankMachine() { @@ -113,7 +118,7 @@ sc_time BankMachineOpen::startBankMachine() DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; nextRow = extension.getRow(); } @@ -123,12 +128,12 @@ sc_time BankMachineOpen::startBankMachine() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RD, bank); + delay = checker->delayToSatisfyConstraints(Command::RD, rank, bankgroup, bank); nextCommand = Command::RD; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WR, bank); + delay = checker->delayToSatisfyConstraints(Command::WR, rank, bankgroup, bank); nextCommand = Command::WR; } else @@ -136,7 +141,7 @@ sc_time BankMachineOpen::startBankMachine() } else // row miss { - delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; nextRow = extension.getRow(); } @@ -145,9 +150,8 @@ sc_time BankMachineOpen::startBankMachine() return delay; } -BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, - Rank rank, BankGroup bankgroup, Bank bank) - : BankMachine(scheduler, checker, rank, bankgroup, bank) {} +BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} sc_time BankMachineClosed::startBankMachine() { @@ -161,7 +165,7 @@ sc_time BankMachineClosed::startBankMachine() DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; nextRow = extension.getRow(); } @@ -171,12 +175,12 @@ sc_time BankMachineClosed::startBankMachine() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RDA, bank); + delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); nextCommand = Command::RDA; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WRA, bank); + delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); nextCommand = Command::WRA; } else @@ -184,7 +188,7 @@ sc_time BankMachineClosed::startBankMachine() } else // row miss { - delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; nextRow = extension.getRow(); } @@ -193,9 +197,8 @@ sc_time BankMachineClosed::startBankMachine() return delay; } -BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, - Rank rank, BankGroup bankgroup, Bank bank) - : BankMachine(scheduler, checker, rank, bankgroup, bank) {} +BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} sc_time BankMachineOpenAdaptive::startBankMachine() { @@ -209,7 +212,7 @@ sc_time BankMachineOpenAdaptive::startBankMachine() DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; nextRow = extension.getRow(); } @@ -221,12 +224,12 @@ sc_time BankMachineOpenAdaptive::startBankMachine() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RDA, bank); + delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); nextCommand = Command::RDA; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WRA, bank); + delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); nextCommand = Command::WRA; } else @@ -236,12 +239,12 @@ sc_time BankMachineOpenAdaptive::startBankMachine() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RD, bank); + delay = checker->delayToSatisfyConstraints(Command::RD, rank, bankgroup, bank); nextCommand = Command::RD; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WR, bank); + delay = checker->delayToSatisfyConstraints(Command::WR, rank, bankgroup, bank); nextCommand = Command::WR; } else @@ -250,7 +253,7 @@ sc_time BankMachineOpenAdaptive::startBankMachine() } else // row miss { - delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; nextRow = extension.getRow(); } @@ -259,9 +262,8 @@ sc_time BankMachineOpenAdaptive::startBankMachine() return delay; } -BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, - Rank rank, BankGroup bankgroup, Bank bank) - : BankMachine(scheduler, checker, rank, bankgroup, bank) {} +BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) + : BankMachine(scheduler, checker, bank) {} sc_time BankMachineClosedAdaptive::startBankMachine() { @@ -275,7 +277,7 @@ sc_time BankMachineClosedAdaptive::startBankMachine() DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { - delay = checker->delayToSatisfyConstraints(Command::ACT, bank); + delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; nextRow = extension.getRow(); } @@ -287,12 +289,12 @@ sc_time BankMachineClosedAdaptive::startBankMachine() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RD, bank); + delay = checker->delayToSatisfyConstraints(Command::RD, rank, bankgroup, bank); nextCommand = Command::RD; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WR, bank); + delay = checker->delayToSatisfyConstraints(Command::WR, rank, bankgroup, bank); nextCommand = Command::WR; } else @@ -302,12 +304,12 @@ sc_time BankMachineClosedAdaptive::startBankMachine() { if (currentPayload->get_command() == TLM_READ_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::RDA, bank); + delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); nextCommand = Command::RDA; } else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::WRA, bank); + delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); nextCommand = Command::WRA; } else @@ -316,7 +318,7 @@ sc_time BankMachineClosedAdaptive::startBankMachine() } else // row miss TODO: remove this, can never happen { - delay = checker->delayToSatisfyConstraints(Command::PRE, bank); + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; nextRow = extension.getRow(); SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 910afe6b..af4ac52d 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -70,7 +70,7 @@ public: BmState getState(); protected: - BankMachine(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); + BankMachine(SchedulerIF *, CheckerIF *, Bank); tlm_generic_payload *currentPayload = nullptr; SchedulerIF *scheduler; CheckerIF *checker; @@ -79,36 +79,36 @@ protected: BmState currentState = BmState::Precharged; Row currentRow; sc_time timeToSchedule = SC_ZERO_TIME; - Rank rank; - BankGroup bankgroup; + Rank rank = Rank(0); + BankGroup bankgroup = BankGroup(0); Bank bank; }; class BankMachineOpen final : public BankMachine { public: - BankMachineOpen(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); + BankMachineOpen(SchedulerIF *, CheckerIF *, Bank); sc_time startBankMachine(); }; class BankMachineClosed final : public BankMachine { public: - BankMachineClosed(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); + BankMachineClosed(SchedulerIF *, CheckerIF *, Bank); sc_time startBankMachine(); }; class BankMachineOpenAdaptive final : public BankMachine { public: - BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); + BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank); sc_time startBankMachine(); }; class BankMachineClosedAdaptive final : public BankMachine { public: - BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Rank, BankGroup, Bank); + BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank); sc_time startBankMachine(); }; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 99be6756..8c98beb5 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -96,14 +96,12 @@ Controller::Controller(sc_module_name name) : if (config.AdaptivePagePolicy) { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineOpenAdaptive - (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); + bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID))); } else { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineOpen - (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); + bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID))); } } else @@ -111,14 +109,12 @@ Controller::Controller(sc_module_name name) : if (config.AdaptivePagePolicy) { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineClosedAdaptive - (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); + bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID))); } else { for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) - bankMachines.push_back(new BankMachineClosed - (scheduler, checker, Rank(0), BankGroup(0), Bank(bankID))); + bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID))); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 2e183798..3e176fa8 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -50,7 +50,11 @@ CheckerDDR3::CheckerDDR3() lastScheduledByCommandAndBank = std::vector> (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); } CheckerDDR3::~CheckerDDR3() @@ -58,7 +62,7 @@ CheckerDDR3::~CheckerDDR3() delete refreshChecker; } -sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) +sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) { ScheduledCommand lastCommand; @@ -82,11 +86,11 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); - lastCommand = lastScheduledByCommand[Command::ACT]; + lastCommand = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRRD); - lastCommand = lastScheduledByCommand[Command::REFA]; + lastCommand = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); @@ -94,7 +98,8 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); - delayToSatisfyFAW(earliestTimeToStart); + if (lastActivates[rank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } @@ -170,33 +175,25 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Bank bank) return (earliestTimeToStart - sc_time_stamp()); } -void CheckerDDR3::delayToSatisfyFAW(sc_time &earliestTimeToStart) -{ - if (lastActivates.size() >= 4) - { - sc_time earliestTime = lastActivates.front() + memSpec->tFAW; - if (earliestTime > earliestTimeToStart) - earliestTimeToStart = earliestTime; - } -} - void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) { Command command = scheduledCommand.getCommand(); + Rank rank = scheduledCommand.getRank(); Bank bank = scheduledCommand.getBank(); PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + to_string(scheduledCommand.getBank().ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = scheduledCommand; + lastScheduledByCommandAndRank[command][rank.ID()] = scheduledCommand; lastScheduledByCommand[command] = scheduledCommand; lastScheduled = scheduledCommand; if (command == Command::ACT) { - if (lastActivates.size() == 4) - lastActivates.pop(); - lastActivates.push(scheduledCommand.getStart()); + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(scheduledCommand.getStart()); } else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 9082ea17..039856d6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -48,15 +48,14 @@ class CheckerDDR3 final : public CheckerIF public: CheckerDDR3(); ~CheckerDDR3(); - sc_time delayToSatisfyConstraints(Command, Bank); + sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank); void insert(const ScheduledCommand &); private: const MemSpecDDR3 *memSpec; // Four activate window - std::queue lastActivates; - void delayToSatisfyFAW(sc_time &); + std::vector> lastActivates; RefreshCheckerDDR3Dummy *refreshChecker; diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index c1586373..814102d3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -47,11 +47,12 @@ class CheckerIF public: virtual ~CheckerIF() {} - virtual sc_time delayToSatisfyConstraints(Command, Bank) = 0; + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) = 0; virtual void insert(const ScheduledCommand &) = 0; protected: std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; ScheduledCommand lastScheduled; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 6cc5dc8f..56331271 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -50,7 +50,11 @@ CheckerWideIO::CheckerWideIO() lastScheduledByCommandAndBank = std::vector> (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); } CheckerWideIO::~CheckerWideIO() @@ -58,7 +62,7 @@ CheckerWideIO::~CheckerWideIO() delete refreshChecker; } -sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) +sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) { ScheduledCommand lastCommand; @@ -82,11 +86,11 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); - lastCommand = lastScheduledByCommand[Command::ACT]; + lastCommand = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRRD); - lastCommand = lastScheduledByCommand[Command::REFA]; + lastCommand = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); @@ -94,7 +98,8 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) if (lastCommand.isValidCommand()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); - delayToSatisfyTAW(earliestTimeToStart); + if (lastActivates[rank.ID()].size() >= 2) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tTAW); refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } @@ -154,33 +159,25 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Bank bank) return (earliestTimeToStart - sc_time_stamp()); } -void CheckerWideIO::delayToSatisfyTAW(sc_time &earliestTimeToStart) -{ - if (lastActivates.size() >= 2) - { - sc_time earliestTime = lastActivates.front() + memSpec->tTAW; - if (earliestTime > earliestTimeToStart) - earliestTimeToStart = earliestTime; - } -} - void CheckerWideIO::insert(const ScheduledCommand &scheduledCommand) { Command command = scheduledCommand.getCommand(); + Rank rank = scheduledCommand.getRank(); Bank bank = scheduledCommand.getBank(); PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + to_string(scheduledCommand.getBank().ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = scheduledCommand; + lastScheduledByCommandAndRank[command][rank.ID()] = scheduledCommand; lastScheduledByCommand[command] = scheduledCommand; lastScheduled = scheduledCommand; if (command == Command::ACT) { - if (lastActivates.size() == 2) - lastActivates.pop(); - lastActivates.push(scheduledCommand.getStart()); + if (lastActivates[rank.ID()].size() == 2) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(scheduledCommand.getStart()); } else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 29950347..b8f8c460 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -48,15 +48,14 @@ class CheckerWideIO final : public CheckerIF public: CheckerWideIO(); ~CheckerWideIO(); - sc_time delayToSatisfyConstraints(Command, Bank); + sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank); void insert(const ScheduledCommand &); private: const MemSpecWideIO *memSpec; // Four activate window - std::queue lastActivates; - void delayToSatisfyTAW(sc_time &); + std::vector> lastActivates; RefreshCheckerWideIODummy *refreshChecker; diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index 6933c521..bdfebd0e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -90,6 +90,11 @@ sc_time ScheduledCommand::getExecutionTime() const return executionTime; } +Rank ScheduledCommand::getRank() const +{ + return extension.getRank(); +} + Bank ScheduledCommand::getBank() const { return extension.getBank(); diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h index cca521a2..9dde8bfb 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h @@ -72,6 +72,7 @@ public: Command getCommand() const; sc_time getExecutionTime() const; + Rank getRank() const; Bank getBank() const; BankGroup getBankGroup() const; Row getRow() const; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 0752e07c..45554403 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -229,17 +229,19 @@ void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) { + // TODO: correct this function if (decodedAddress.channel >= AddressDecoder::getInstance().amount["channel"]) { return false; } - if (decodedAddress.bank >= AddressDecoder::getInstance().amount["bank"]) { - return false; - } - // TODO: this test case should be corrected! - /*if (decodedAddress.bankgroup >= AddressDecoder::getInstance().amount["bankgroup"]) { - std::cout << decodedAddress.bankgroup << " " << AddressDecoder::getInstance().amount["bankgroup"] << std::endl; - return false; - }*/ +// if (decodedAddress.rank >= AddressDecoder::getInstance().amount["rank"]) { +// return false; +// } +// if (decodedAddress.bank >= AddressDecoder::getInstance().amount["bank"]) { +// return false; +// } +// if (decodedAddress.bankgroup >= AddressDecoder::getInstance().amount["bankgroup"]) { +// return false; +// } if (decodedAddress.column >= AddressDecoder::getInstance().amount["column"]) { return false; } From 330b07d0e71bfda6151fd98428669e4fc23ff522 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 18 Sep 2019 16:39:38 +0200 Subject: [PATCH 097/183] Changed data structures of Address Decoder for speedup. --- DRAMSys/library/src/common/AddressDecoder.cpp | 5 - DRAMSys/library/src/common/AddressDecoder.h | 17 ++- .../src/common/CongenAddressDecoder.cpp | 16 +-- .../library/src/common/CongenAddressDecoder.h | 4 +- .../library/src/common/XmlAddressDecoder.cpp | 109 ++++++++++++------ .../library/src/common/XmlAddressDecoder.h | 28 ++++- DRAMSys/library/src/common/utils.h | 2 +- DRAMSys/library/src/controller/Controller.cpp | 2 - .../core/configuration/Configuration.cpp | 4 +- DRAMSys/library/src/error/errormodel.cpp | 2 +- DRAMSys/library/src/error/errormodel.h | 4 +- DRAMSys/library/src/simulation/Arbiter.cpp | 25 ++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 15 +-- DRAMSys/library/src/simulation/Dram.cpp | 2 +- .../library/src/simulation/ExampleInitiator.h | 2 +- DRAMSys/library/src/simulation/IArbiter.h | 16 +-- 16 files changed, 152 insertions(+), 101 deletions(-) diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index b0a3b98f..81ea1252 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -60,8 +60,3 @@ void AddressDecoder::createInstance(Type t) break; } } - -AddressDecoder::AddressDecoder() -{ - -} diff --git a/DRAMSys/library/src/common/AddressDecoder.h b/DRAMSys/library/src/common/AddressDecoder.h index d240088b..b49f6e81 100644 --- a/DRAMSys/library/src/common/AddressDecoder.h +++ b/DRAMSys/library/src/common/AddressDecoder.h @@ -71,7 +71,7 @@ public: }; protected: - AddressDecoder(); + AddressDecoder() {} static AddressDecoder *m_pInstance; public: @@ -80,12 +80,21 @@ public: virtual void setConfiguration(std::string url) = 0; - virtual DecodedAddress decodeAddress(sc_dt::uint64 addr) = 0; - virtual sc_dt::uint64 encodeAddress(DecodedAddress n) = 0; + virtual DecodedAddress decodeAddress(uint64_t addr) = 0; + virtual uint64_t encodeAddress(DecodedAddress n) = 0; virtual void print() = 0; - std::map amount; + struct Amount + { + unsigned channel = 1; + unsigned rank = 1; + unsigned bankgroup = 1; + unsigned bank = 1; + unsigned row = 1; + unsigned column = 1; + unsigned bytes = 1; + } amount; }; #endif // ADDRESSDECODER_H diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.cpp b/DRAMSys/library/src/common/CongenAddressDecoder.cpp index ea11dcbc..fca1ea3b 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.cpp +++ b/DRAMSys/library/src/common/CongenAddressDecoder.cpp @@ -188,14 +188,14 @@ void CongenAddressDecoder::setConfiguration(std::string url) } // Fill the amount map. This is copied from xmlAddressDecoder without further investigation - amount["channel"] = 1; - amount["bank"] = pow(2.0, m_vBankBits.size()); - amount["row"] = pow(2.0, m_vRowBits.size()); - amount["column"] = pow(2.0, m_vColumnBits.size()); - amount["bytes"] = pow(2.0, m_nByteBits); + amount.channel = 1; + amount.bank = pow(2.0, m_vBankBits.size()); + amount.row = pow(2.0, m_vRowBits.size()); + amount.column = pow(2.0, m_vColumnBits.size()); + amount.bytes = pow(2.0, m_nByteBits); } -DecodedAddress CongenAddressDecoder::decodeAddress(sc_dt::uint64 addr) +DecodedAddress CongenAddressDecoder::decodeAddress(uint64_t addr) { DecodedAddress result; @@ -251,9 +251,9 @@ DecodedAddress CongenAddressDecoder::decodeAddress(sc_dt::uint64 addr) return result; } -sc_dt::uint64 CongenAddressDecoder::encodeAddress(DecodedAddress n) +uint64_t CongenAddressDecoder::encodeAddress(DecodedAddress n) { - sc_dt::uint64 address = 0; + uint64_t address = 0; // Bank // it->first: position of the target bit in the DecodedAddress struct field diff --git a/DRAMSys/library/src/common/CongenAddressDecoder.h b/DRAMSys/library/src/common/CongenAddressDecoder.h index 51778ecf..ed523d9d 100644 --- a/DRAMSys/library/src/common/CongenAddressDecoder.h +++ b/DRAMSys/library/src/common/CongenAddressDecoder.h @@ -101,8 +101,8 @@ public: virtual void setConfiguration(std::string url); - virtual DecodedAddress decodeAddress(sc_dt::uint64 addr); - virtual sc_dt::uint64 encodeAddress(DecodedAddress n); + virtual DecodedAddress decodeAddress(uint64_t addr); + virtual uint64_t encodeAddress(DecodedAddress n); static bool testConfigFile(std::string url); diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 1c819b57..325412f5 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -41,7 +41,6 @@ #include "bitset" #include "../controller/core/configuration/Configuration.h" -using namespace std; using namespace tinyxml2; XmlAddressDecoder::XmlAddressDecoder() @@ -56,54 +55,87 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) tinyxml2::XMLElement *addressMap = doc.RootElement(); string xmlNodeName(addressMap->Name()); - if ( xmlNodeName != "addressmapping") { + if (xmlNodeName != "addressmapping") reportFatal("AddressDecorder", "addressmap node expected"); - } for (XMLElement *child = addressMap->FirstChildElement(); - child != NULL; - child = child->NextSiblingElement()) { - int from; - int to; + child != NULL; child = child->NextSiblingElement()) + { + unsigned from; + unsigned to; child->QueryAttribute("from", &from); child->QueryAttribute("to", &to); - shifts[child->Name()] = from; - masks[child->Name()] = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); - amount[child->Name()] = pow(2.0, to - from + 1.0); + if (std::strcmp(child->Name(), "channel") == 0) + { + shifts.channel = from; + masks.channel = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.channel = pow(2.0, to - from + 1.0); + } + else if (std::strcmp(child->Name(), "rank") == 0) + { + shifts.rank = from; + masks.rank = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.rank = pow(2.0, to - from + 1.0); + std::cout << "Inside rank" << std::endl; + } + else if (std::strcmp(child->Name(), "bank") == 0) + { + shifts.bank = from; + masks.bank = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.bank = pow(2.0, to - from + 1.0); + } + else if (std::strcmp(child->Name(), "row") == 0) + { + shifts.row = from; + masks.row = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.row = pow(2.0, to - from + 1.0); + } + else if (std::strcmp(child->Name(), "column") == 0) + { + shifts.column = from; + masks.column = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.column = pow(2.0, to - from + 1.0); + } + else if (std::strcmp(child->Name(), "bytes") == 0) + { + shifts.bytes = from; + masks.bytes = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.bytes = pow(2.0, to - from + 1.0); + } + else + SC_REPORT_FATAL("XmlAddressDecoder", ("Unknown field " + std::string(child->Name())).c_str()); } + + banksPerRank = amount.bank; + amount.bank = amount.bank * amount.rank; + amount.bankgroup = Configuration::getInstance().memSpec->NumberOfBankGroups; + banksPerGroup = amount.bank / amount.bankgroup; } -DecodedAddress XmlAddressDecoder::decodeAddress(sc_dt::uint64 addr) +DecodedAddress XmlAddressDecoder::decodeAddress(uint64_t addr) { DecodedAddress result; - result.channel = (addr & masks["channel"]) >> shifts["channel"]; - result.rank = (addr & masks["rank"]) >> shifts["rank"]; - //result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"]; - unsigned banksPerRank = Configuration::getInstance().memSpec->NumberOfBanks - / Configuration::getInstance().memSpec->NumberOfRanks; - result.bank = ((addr & masks["bank"]) >> shifts["bank"]) + result.rank * banksPerRank; - unsigned banksPerGroup = Configuration::getInstance().memSpec->NumberOfBanks - / Configuration::getInstance().memSpec->NumberOfBankGroups; + result.channel = (addr & masks.channel) >> shifts.channel; + result.rank = (addr & masks.rank) >> shifts.rank; result.bankgroup = result.bank / banksPerGroup; - //result.rank = result.bank % Configuration::getInstance().memSpec->NumberOfRanks; - result.row = (addr & masks["row"]) >> shifts["row"]; - result.column = (addr & masks["column"]) >> shifts["column"]; - result.bytes = (addr & masks["bytes"]) >> shifts["bytes"]; + result.bank = ((addr & masks.bank) >> shifts.bank) + result.rank * banksPerRank; + result.row = (addr & masks.row) >> shifts.row; + result.column = (addr & masks.column) >> shifts.column; + result.bytes = (addr & masks.bytes) >> shifts.bytes; return result; } -sc_dt::uint64 XmlAddressDecoder::encodeAddress(DecodedAddress n) +uint64_t XmlAddressDecoder::encodeAddress(DecodedAddress n) { - return n.channel << shifts["channel"] | - n.rank << shifts["rank"] | - n.bankgroup << shifts["bankgroup"] | - n.row << shifts["row"] | - n.bank << shifts["bank"] | - n.column << shifts["column"] | - n.bytes << shifts["bytes"]; + return (n.channel << shifts.channel) | + (n.rank << shifts.rank) | + ((n.bank % banksPerRank) << shifts.bank) | + (n.row << shifts.row) | + (n.column << shifts.column) | + (n.bytes << shifts.bytes); } bool XmlAddressDecoder::testConfigFile(std::string url) @@ -120,10 +152,13 @@ bool XmlAddressDecoder::testConfigFile(std::string url) void XmlAddressDecoder::print() { - cout << headline << endl; - cout << "Address Mapping:" << endl << endl; - for (auto &pair : masks) { - cout << std::setw(16) << pair.first << ": " << bitset<48>(pair.second) << endl; - } - cout << endl; + std::cout << headline << std::endl; + std::cout << "Address Mapping:" << std::endl << std::endl; + std::cout << std::setw(10) << "channel: " << std::bitset<64>(masks.channel) << std::endl; + std::cout << std::setw(10) << "rank: " << std::bitset<64>(masks.rank) << std::endl; + std::cout << std::setw(10) << "bank: " << std::bitset<64>(masks.bank) << std::endl; + std::cout << std::setw(10) << "row: " << std::bitset<64>(masks.row) << std::endl; + std::cout << std::setw(10) << "column: " << std::bitset<64>(masks.column) << std::endl; + std::cout << std::setw(10) << "bytes: " << std::bitset<64>(masks.bytes) << std::endl; + std::cout << std::endl; } diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.h b/DRAMSys/library/src/common/XmlAddressDecoder.h index dfd65072..b0c848d7 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.h +++ b/DRAMSys/library/src/common/XmlAddressDecoder.h @@ -51,16 +51,36 @@ class XmlAddressDecoder : private AddressDecoder friend class AddressDecoder; private: - std::map masks; - std::map shifts; + struct Masks + { + uint64_t channel = 0; + uint64_t rank = 0; + uint64_t bank = 0; + uint64_t row = 0; + uint64_t column = 0; + uint64_t bytes = 0; + } masks; + + struct Shifts + { + unsigned channel = 0; + unsigned rank = 0; + unsigned bank = 0; + unsigned row = 0; + unsigned column = 0; + unsigned bytes = 0; + } shifts; + + unsigned banksPerGroup; + unsigned banksPerRank; tinyxml2::XMLElement *addressmapping; public: XmlAddressDecoder(); - virtual DecodedAddress decodeAddress(sc_dt::uint64 addr); - virtual sc_dt::uint64 encodeAddress(DecodedAddress n); + virtual DecodedAddress decodeAddress(uint64_t addr); + virtual uint64_t encodeAddress(DecodedAddress n); void setConfiguration(std::string url); diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index 003c6829..e997d99a 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -92,7 +92,7 @@ bool isIn(const T &value, const std::vector &collection) } constexpr const char headline[] = - "========================================================="; + "=========================================================================="; static inline void loadbar(unsigned int x, unsigned int n, diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 8c98beb5..15ae1e7a 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -213,8 +213,6 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, payloadToAcquire = &trans; timeToAcquire = sc_time_stamp() + notificationDelay; beginReqEvent.notify(notificationDelay); -// std::cout << "Bank: " << DramExtension::getBank(trans).ID() << ", BankGroup: " -// << DramExtension::getBankGroup(trans).ID() << ", Rank: " << DramExtension::getRank(trans).ID() << std::endl; } else if (phase = END_RESP) { diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index db52486c..724c2043 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -186,7 +186,7 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "NumberOfMemChannels") { NumberOfMemChannels = string2int(value); unsigned int maxNumberofMemChannels = - AddressDecoder::getInstance().amount["channel"]; + AddressDecoder::getInstance().amount.channel; if (NumberOfMemChannels > maxNumberofMemChannels) { SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name @@ -384,7 +384,7 @@ unsigned int Configuration::getBytesPerBurst() // offset of the N-byte-wide memory module (DIMM) (a single data word // or burst element has N bytes. N = 2^(# bits for byte offset)). unsigned int burstElementSizeInBytes = - AddressDecoder::getInstance().amount["bytes"]; + AddressDecoder::getInstance().amount.bytes; assert(bytesPerBurst == (burstElementSizeInBytes * memSpec->BurstLength)); } diff --git a/DRAMSys/library/src/error/errormodel.cpp b/DRAMSys/library/src/error/errormodel.cpp index cb73ee11..b23b8dff 100644 --- a/DRAMSys/library/src/error/errormodel.cpp +++ b/DRAMSys/library/src/error/errormodel.cpp @@ -48,7 +48,7 @@ void errorModel::init() // Get Configuration parameters: burstLenght = Configuration::getInstance().memSpec->BurstLength; numberOfColumns = Configuration::getInstance().memSpec->NumberOfColumns; - bytesPerColumn = AddressDecoder::getInstance().amount["bytes"]; + bytesPerColumn = AddressDecoder::getInstance().amount.bytes; // Adjust number of bytes per column dynamically to the selected ecc controller bytesPerColumn = Configuration::getInstance().adjustNumBytesAfterECC( diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index 7dab8f3f..23101b75 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -117,8 +117,8 @@ private: bool operator()( const DecodedAddress &first , const DecodedAddress &second) const { - sc_dt::uint64 addrFirst = AddressDecoder::getInstance().encodeAddress(first); - sc_dt::uint64 addrSecond = AddressDecoder::getInstance().encodeAddress(second); + uint64_t addrFirst = AddressDecoder::getInstance().encodeAddress(first); + uint64_t addrSecond = AddressDecoder::getInstance().encodeAddress(second); return addrFirst < addrSecond; } }; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 45554403..f275e057 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -229,24 +229,17 @@ void Arbiter::appendDramExtension(int socketId, tlm_generic_payload &payload) bool Arbiter::addressIsValid(DecodedAddress &decodedAddress) { - // TODO: correct this function - if (decodedAddress.channel >= AddressDecoder::getInstance().amount["channel"]) { + if (decodedAddress.channel >= AddressDecoder::getInstance().amount.channel) return false; - } -// if (decodedAddress.rank >= AddressDecoder::getInstance().amount["rank"]) { -// return false; -// } -// if (decodedAddress.bank >= AddressDecoder::getInstance().amount["bank"]) { -// return false; -// } -// if (decodedAddress.bankgroup >= AddressDecoder::getInstance().amount["bankgroup"]) { -// return false; -// } - if (decodedAddress.column >= AddressDecoder::getInstance().amount["column"]) { + if (decodedAddress.rank >= AddressDecoder::getInstance().amount.rank) return false; - } - if (decodedAddress.row >= AddressDecoder::getInstance().amount["row"]) { + if (decodedAddress.bankgroup >= AddressDecoder::getInstance().amount.bankgroup) + return false; + if (decodedAddress.bank >= AddressDecoder::getInstance().amount.bank) + return false; + if (decodedAddress.row >= AddressDecoder::getInstance().amount.row) + return false; + if (decodedAddress.column >= AddressDecoder::getInstance().amount.column) return false; - } return true; } diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 3d5bba3a..bfb16a85 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -87,10 +87,16 @@ DRAMSys::DRAMSys(sc_module_name name, Configuration::getInstance().setPathToResources(pathToResources); + // MemSpec must be initialized first because AddressDecoder needs + // the number of bankgroups + ConfigurationLoader::loadMemSpec(Configuration::getInstance(), + pathToResources + + "configs/memspecs/" + + memspec); + // The xmlAddressDecoder MUST be initialized before calling the // ConfigurationLoader because some information from the xmlAddressDecoder // is needed to assure the coherence of the configuration. - if (XmlAddressDecoder::testConfigFile(pathToResources + "configs/amconfigs/" + amconfig)) { AddressDecoder::createInstance(AddressDecoder::Type::XML); @@ -109,7 +115,7 @@ DRAMSys::DRAMSys(sc_module_name name, AddressDecoder::getInstance().print(); - // Setup the memory controller with the propriate xml file + // Setup rest of the memory controller with the propriate xml file ConfigurationLoader::loadMCConfig(Configuration::getInstance(), pathToResources + "configs/mcconfigs/" @@ -125,11 +131,6 @@ DRAMSys::DRAMSys(sc_module_name name, + "configs/thermalsim/" + thermalconfig); - ConfigurationLoader::loadMemSpec(Configuration::getInstance(), - pathToResources - + "configs/memspecs/" - + memspec); - // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. std::string simName; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 092221c3..53827b65 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -226,7 +226,7 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans) else { tlm_command cmd = trans.get_command(); - //sc_dt::uint64 adr = trans.get_address(); // TODO: - offset; + //uint64_t adr = trans.get_address(); // TODO: - offset; unsigned char *ptr = trans.get_data_ptr(); unsigned int len = trans.get_data_length(); //unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); diff --git a/DRAMSys/library/src/simulation/ExampleInitiator.h b/DRAMSys/library/src/simulation/ExampleInitiator.h index 7b227709..45233838 100644 --- a/DRAMSys/library/src/simulation/ExampleInitiator.h +++ b/DRAMSys/library/src/simulation/ExampleInitiator.h @@ -185,7 +185,7 @@ struct ExampleInitiator : sc_module } tlm::tlm_command cmd = trans.get_command(); - sc_dt::uint64 adr = trans.get_address(); + uint64_t adr = trans.get_address(); int *ptr = reinterpret_cast( trans.get_data_ptr() ); cout << hex << adr << " check, cmd=" << (cmd ? "write" : "read") diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 8826610f..5b18dc1a 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -114,21 +114,21 @@ protected: bool addressIsValid(DecodedAddress &decodedAddress) { if (decodedAddress.channel >= - XmlAddressDecoder::getInstance().amount["channel"]) { + XmlAddressDecoder::getInstance().amount.channel) { return false; } - if (decodedAddress.bank >= XmlAddressDecoder::getInstance().amount["bank"]) { - return false; - } - if (decodedAddress.bankgroup > - XmlAddressDecoder::getInstance().amount["bankgroup"]) { + if (decodedAddress.bank >= XmlAddressDecoder::getInstance().amount.bank) { return false; } +// if (decodedAddress.bankgroup > +// XmlAddressDecoder::getInstance().amount["bankgroup"]) { +// return false; +// } if (decodedAddress.column >= - XmlAddressDecoder::getInstance().amount["column"]) { + XmlAddressDecoder::getInstance().amount.column) { return false; } - if (decodedAddress.row >= XmlAddressDecoder::getInstance().amount["row"]) { + if (decodedAddress.row >= XmlAddressDecoder::getInstance().amount.row) { return false; } return true; From b918f0f9ea1716a24982c503f4bd9b21922a13be Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 18 Sep 2019 18:24:10 +0200 Subject: [PATCH 098/183] Added ranks to tdb files and TraceAnalyzer. --- .../resources/scripts/createTraceDB.sql | 3 ++- DRAMSys/library/src/common/TlmRecorder.cpp | 16 +++++++------ .../businessObjects/transaction.cpp | 10 ++++---- .../businessObjects/transaction.h | 18 +++++++++------ DRAMSys/traceAnalyzer/data/QueryTexts.h | 2 +- DRAMSys/traceAnalyzer/data/tracedb.cpp | 23 ++++++++++--------- .../presentation/transactiontreewidget.cpp | 3 ++- 7 files changed, 42 insertions(+), 33 deletions(-) diff --git a/DRAMSys/library/resources/scripts/createTraceDB.sql b/DRAMSys/library/resources/scripts/createTraceDB.sql index 1ba6c3aa..f9ac86ae 100644 --- a/DRAMSys/library/resources/scripts/createTraceDB.sql +++ b/DRAMSys/library/resources/scripts/createTraceDB.sql @@ -58,8 +58,9 @@ CREATE TABLE Transactions( Burstlength INTEGER, TThread INTEGER, TChannel INTEGER, - TBank INTEGER, + TRank INTEGER, TBankgroup INTEGER, + TBank INTEGER, TRow INTEGER, TColumn INTEGER, DataStrobeBegin INTEGER, diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 1ee81838..d18320e3 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -272,7 +272,7 @@ void TlmRecorder::setUpTransactionTerminatingPhases() void TlmRecorder::prepareSqlStatements() { insertTransactionString = - "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:bank,:bankgroup,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; + "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank,:bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)"; updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id"; updateDataStrobeString = @@ -359,20 +359,22 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData) sqlite3_bind_int(insertTransactionStatement, 6, recordingData.dramExtension.getChannel().ID()); sqlite3_bind_int(insertTransactionStatement, 7, - recordingData.dramExtension.getBank().ID()); + recordingData.dramExtension.getRank().ID()); sqlite3_bind_int(insertTransactionStatement, 8, recordingData.dramExtension.getBankGroup().ID()); sqlite3_bind_int(insertTransactionStatement, 9, - recordingData.dramExtension.getRow().ID()); + recordingData.dramExtension.getBank().ID()); sqlite3_bind_int(insertTransactionStatement, 10, + recordingData.dramExtension.getRow().ID()); + sqlite3_bind_int(insertTransactionStatement, 11, recordingData.dramExtension.getColumn().ID()); - sqlite3_bind_int64(insertTransactionStatement, 11, - recordingData.timeOnDataStrobe.start.value()); sqlite3_bind_int64(insertTransactionStatement, 12, - recordingData.timeOnDataStrobe.end.value()); + recordingData.timeOnDataStrobe.start.value()); sqlite3_bind_int64(insertTransactionStatement, 13, + recordingData.timeOnDataStrobe.end.value()); + sqlite3_bind_int64(insertTransactionStatement, 14, recordingData.timeOfGeneration.value()); - sqlite3_bind_text(insertTransactionStatement, 14, + sqlite3_bind_text(insertTransactionStatement, 15, recordingData.cmd.c_str(), recordingData.cmd.length(), NULL); executeSqlStatement(insertTransactionStatement); diff --git a/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp b/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp index 9bdec5f5..306141fd 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/transaction.cpp @@ -39,11 +39,11 @@ using namespace std; Transaction::Transaction(ID id, unsigned int address, unsigned int burstlength, - unsigned int thread, unsigned int channel, unsigned int bank, - unsigned int bankgroup, unsigned int row, unsigned int column, Timespan span, - Timespan spanOnDataStrobe) - : address(address), burstlength(burstlength), thread(thread), channel(channel), - bank(bank), bankgroup(bankgroup), row(row), column(column), span(span), + unsigned int thread, unsigned int channel, unsigned int rank, + unsigned int bankgroup, unsigned int bank, unsigned int row, unsigned int column, + Timespan span, Timespan spanOnDataStrobe) + : address(address), burstlength(burstlength), thread(thread), channel(channel), rank(rank), + bankgroup(bankgroup), bank(bank), row(row), column(column), span(span), spanOnDataStrobe(spanOnDataStrobe), id(id) {} void Transaction::addPhase(shared_ptr phase) diff --git a/DRAMSys/traceAnalyzer/businessObjects/transaction.h b/DRAMSys/traceAnalyzer/businessObjects/transaction.h index 767c4f48..d58a7c56 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/transaction.h +++ b/DRAMSys/traceAnalyzer/businessObjects/transaction.h @@ -48,8 +48,8 @@ typedef unsigned int ID; class Transaction { private: - unsigned int address, burstlength, thread, channel, bank, bankgroup, row, - column; + unsigned int address, burstlength, thread, channel, rank, + bankgroup, bank, row, column; Timespan span; Timespan spanOnDataStrobe; ID id; @@ -57,9 +57,9 @@ private: public: Transaction(ID id, unsigned int address, unsigned int burstlength, - unsigned int thread, unsigned int channel, unsigned int bank, - unsigned int bankgroup, unsigned int row, unsigned int column, Timespan span, - Timespan spanOnDataStrobe); + unsigned int thread, unsigned int channel, unsigned int rank, + unsigned int bankgroup, unsigned int bank, unsigned int row, unsigned int column, + Timespan span, Timespan spanOnDataStrobe); void draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &yMap, const QRectF &canvasRect, bool highlight, @@ -85,14 +85,18 @@ public: { return channel; } - unsigned int Bank() const + unsigned int Rank() const { - return bank; + return rank; } unsigned int BankGroup() const { return bankgroup; } + unsigned int Bank() const + { + return bank; + } unsigned int Row() const { return row; diff --git a/DRAMSys/traceAnalyzer/data/QueryTexts.h b/DRAMSys/traceAnalyzer/data/QueryTexts.h index aeccca6d..96aab29e 100644 --- a/DRAMSys/traceAnalyzer/data/QueryTexts.h +++ b/DRAMSys/traceAnalyzer/data/QueryTexts.h @@ -46,7 +46,7 @@ struct TransactionQueryTexts { TransactionQueryTexts() { queryHead = - "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end,DataStrobeBegin,DataStrobeEnd, Address,Burstlength, TThread, TChannel, TBank,TBankgroup, TRow, TColumn,Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd " + "SELECT Transactions.ID AS TransactionID, Ranges.begin, Ranges.end,DataStrobeBegin,DataStrobeEnd, Address,Burstlength, TThread, TChannel, TRank, TBankgroup, TBank, TRow, TColumn,Phases.ID AS PhaseID, PhaseName, PhaseBegin, PhaseEnd " " FROM Transactions INNER JOIN Phases ON Phases.Transact = Transactions.ID INNER JOIN Ranges ON Transactions.Range = Ranges.ID "; selectTransactionsByTimespan = queryHead + diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index 37ed9857..326db059 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -346,22 +346,23 @@ vector> TraceDB::parseTransactionsFromQuery( currentID = id; Timespan span(query.value(1).toLongLong(), query.value(2).toLongLong()); Timespan spanOnStrobe(query.value(3).toLongLong(), query.value(4).toLongLong()); - unsigned int address = query.value(5).toInt(); + unsigned int address = query.value(5).toInt(); unsigned int burstlength = query.value(6).toInt(); unsigned int thread = query.value(7).toInt(); unsigned int channel = query.value(8).toInt(); - unsigned int bank = query.value(9).toInt(); - unsigned int bankgroup = query.value(10).toInt(); - unsigned int row = query.value(11).toInt(); - unsigned int column = query.value(12).toInt(); - result.push_back(shared_ptr(new Transaction(id, address, - burstlength, thread, channel, bank, bankgroup, row, column, span, - spanOnStrobe))); + unsigned int rank = query.value(9).toInt(); + unsigned int bankgroup = query.value(10).toInt(); + unsigned int bank = query.value(11).toInt(); + unsigned int row = query.value(12).toInt(); + unsigned int column = query.value(13).toInt(); + result.push_back(shared_ptr(new Transaction(id, address, burstlength, + thread, channel, rank, bankgroup, bank, row, column, + span, spanOnStrobe))); } - unsigned int phaseID = query.value(13).toInt(); - QString phaseName = query.value(14).toString(); - Timespan span(query.value(15).toLongLong(), query.value(16).toLongLong()); + unsigned int phaseID = query.value(14).toInt(); + QString phaseName = query.value(15).toString(); + Timespan span(query.value(16).toLongLong(), query.value(17).toLongLong()); result.at(result.size() - 1)->addPhase(PhaseFactory::CreatePhase(phaseID, phaseName, span, result.at(result.size() - 1), *this)); } diff --git a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp index 49211af4..1809d53b 100644 --- a/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp +++ b/DRAMSys/traceAnalyzer/presentation/transactiontreewidget.cpp @@ -101,8 +101,9 @@ TransactionTreeWidget::TransactionTreeItem::TransactionTreeItem( this->addChild(new QTreeWidgetItem( {"Lenght", prettyFormatTime(transaction->Span().timeCovered())})); this->addChild(new QTreeWidgetItem( {"Channel", QString::number(transaction->Channel())})); - this->addChild(new QTreeWidgetItem( {"Bank", QString::number(transaction->Bank())} )); + this->addChild(new QTreeWidgetItem( {"Rank", QString::number(transaction->Rank())} )); this->addChild(new QTreeWidgetItem( {"Bankgroup", QString::number(transaction->BankGroup())} )); + this->addChild(new QTreeWidgetItem( {"Bank", QString::number(transaction->Bank())} )); this->addChild(new QTreeWidgetItem( {"Row", QString::number(transaction->Row())} )); this->addChild(new QTreeWidgetItem( {"Column", QString::number(transaction->Column())} )); this->addChild(new QTreeWidgetItem( {"Address", QString("0x") + QString::number(transaction->Address(), 16)} )); From d06d9eec2cebdffe0ed7eac5d9c8b6490cd88a82 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 19 Sep 2019 14:45:38 +0200 Subject: [PATCH 099/183] Changed data structures of timing checkers from ScheduledCommand to sc_time. --- .../library/src/common/XmlAddressDecoder.cpp | 1 - DRAMSys/library/src/controller/Controller.cpp | 5 +- .../src/controller/checker/CheckerDDR3.cpp | 151 +++++++++--------- .../src/controller/checker/CheckerDDR3.h | 2 +- .../src/controller/checker/CheckerIF.h | 10 +- .../src/controller/checker/CheckerWideIO.cpp | 127 +++++++-------- .../src/controller/checker/CheckerWideIO.h | 2 +- 7 files changed, 143 insertions(+), 155 deletions(-) diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 325412f5..786c3335 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -78,7 +78,6 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) shifts.rank = from; masks.rank = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); amount.rank = pow(2.0, to - from + 1.0); - std::cout << "Inside rank" << std::endl; } else if (std::strcmp(child->Name(), "bank") == 0) { diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 15ae1e7a..3cf55f09 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -288,9 +288,8 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) void Controller::sendToDram(Command command, tlm_generic_payload *payload) { - sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command); - ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); - checker->insert(scheduledCommand); + DramExtension extension = DramExtension::getExtension(payload); + checker->insert(command, extension.getRank(), extension.getBank()); sc_time delay = SC_ZERO_TIME; tlm_phase phase; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 3e176fa8..6661b967 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -48,11 +48,11 @@ CheckerDDR3::CheckerDDR3() else refreshChecker = new RefreshCheckerDDR3(memSpec); - lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); - lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); - lastScheduledByCommand = std::vector(numberOfCommands()); + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); lastActivates = std::vector>(memSpec->NumberOfRanks); } @@ -64,39 +64,38 @@ CheckerDDR3::~CheckerDDR3() sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) { - ScheduledCommand lastCommand; - + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::ACT) { - lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommand = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRRD); + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); - lastCommand = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); if (lastActivates[rank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); @@ -105,62 +104,62 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG } else if (command == Command::RD || command == Command::RDA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommand = lastScheduledByCommand[Command::RD]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommand = lastScheduledByCommand[Command::RDA]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommand = lastScheduledByCommand[Command::WR]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - lastCommand = lastScheduledByCommand[Command::WRA]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommand = lastScheduledByCommand[Command::RD]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = lastScheduledByCommand[Command::RDA]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = lastScheduledByCommand[Command::WR]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommand = lastScheduledByCommand[Command::WRA]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRAS); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); - lastCommand = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP); + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); - lastCommand = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR); refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); } @@ -169,31 +168,27 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG reportFatal("CheckerDDR3", "Unknown command!"); } // Check if command bus is free - if (lastScheduled.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled.getStart() + memSpec->clk); + //if (lastScheduled.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); return (earliestTimeToStart - sc_time_stamp()); } -void CheckerDDR3::insert(const ScheduledCommand &scheduledCommand) +void CheckerDDR3::insert(Command command, Rank rank, Bank bank) { - Command command = scheduledCommand.getCommand(); - Rank rank = scheduledCommand.getRank(); - Bank bank = scheduledCommand.getBank(); - PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + - to_string(scheduledCommand.getBank().ID()) + - " command is " + commandToString(command)); + PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); - lastScheduledByCommandAndBank[command][bank.ID()] = scheduledCommand; - lastScheduledByCommandAndRank[command][rank.ID()] = scheduledCommand; - lastScheduledByCommand[command] = scheduledCommand; - lastScheduled = scheduledCommand; + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastScheduled = sc_time_stamp(); if (command == Command::ACT) { if (lastActivates[rank.ID()].size() == 4) lastActivates[rank.ID()].pop(); - lastActivates[rank.ID()].push(scheduledCommand.getStart()); + lastActivates[rank.ID()].push(sc_time_stamp()); } else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 039856d6..5b5a52b8 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -49,7 +49,7 @@ public: CheckerDDR3(); ~CheckerDDR3(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank); - void insert(const ScheduledCommand &); + void insert(Command, Rank, Bank); private: const MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 814102d3..8a914b88 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -48,13 +48,13 @@ public: virtual ~CheckerIF() {} virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) = 0; - virtual void insert(const ScheduledCommand &) = 0; + virtual void insert(Command, Rank, Bank) = 0; protected: - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - ScheduledCommand lastScheduled; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastScheduled; // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 56331271..8369fb0f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -48,11 +48,11 @@ CheckerWideIO::CheckerWideIO() else refreshChecker = new RefreshCheckerWideIO(memSpec); - lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); - lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); - lastScheduledByCommand = std::vector(numberOfCommands()); + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); lastActivates = std::vector>(memSpec->NumberOfRanks); } @@ -64,39 +64,38 @@ CheckerWideIO::~CheckerWideIO() sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) { - ScheduledCommand lastCommand; - + sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); if (command == Command::ACT) { - lastCommand = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRC); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); - lastCommand = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRRD); + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); - lastCommand = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommand = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRFC); + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); if (lastActivates[rank.ID()].size() >= 2) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tTAW); @@ -105,46 +104,46 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban } else if (command == Command::RD || command == Command::RDA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommand = lastScheduledByCommand[Command::RD]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - lastCommand = lastScheduledByCommand[Command::WR]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRCD); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); - lastCommand = lastScheduledByCommand[Command::RD]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = lastScheduledByCommand[Command::WR]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tCCD); + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { - lastCommand = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRAS); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); - lastCommand = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tRTP); + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); - lastCommand = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommand.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR); refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); } @@ -153,31 +152,27 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban reportFatal("CheckerWideIO", "Unknown command!"); } // Check if command bus is free - if (lastScheduled.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled.getStart() + memSpec->clk); + //if (lastScheduled.isValidCommand()) + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); return (earliestTimeToStart - sc_time_stamp()); } -void CheckerWideIO::insert(const ScheduledCommand &scheduledCommand) +void CheckerWideIO::insert(Command command, Rank rank, Bank bank) { - Command command = scheduledCommand.getCommand(); - Rank rank = scheduledCommand.getRank(); - Bank bank = scheduledCommand.getBank(); - PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + - to_string(scheduledCommand.getBank().ID()) + - " command is " + commandToString(command)); + PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); - lastScheduledByCommandAndBank[command][bank.ID()] = scheduledCommand; - lastScheduledByCommandAndRank[command][rank.ID()] = scheduledCommand; - lastScheduledByCommand[command] = scheduledCommand; - lastScheduled = scheduledCommand; + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastScheduled = sc_time_stamp(); if (command == Command::ACT) { if (lastActivates[rank.ID()].size() == 2) lastActivates[rank.ID()].pop(); - lastActivates[rank.ID()].push(scheduledCommand.getStart()); + lastActivates[rank.ID()].push(sc_time_stamp()); } else if (command == Command::REFA || command == Command::REFB) refreshChecker->insert(bank); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index b8f8c460..6d48bbd9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -49,7 +49,7 @@ public: CheckerWideIO(); ~CheckerWideIO(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank); - void insert(const ScheduledCommand &); + void insert(Command, Rank, Bank); private: const MemSpecWideIO *memSpec; From 97542d5f976270ec7f3aa1fa234162c58b7ee5a1 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 19 Sep 2019 14:46:55 +0200 Subject: [PATCH 100/183] Included missing memory allocation in Dram. --- .../core/configuration/Configuration.cpp | 4 ++++ DRAMSys/library/src/simulation/Dram.cpp | 17 +++++++++++++++++ DRAMSys/library/src/simulation/Dram.h | 3 --- DRAMSys/library/src/simulation/DramWideIO.cpp | 3 --- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp index 724c2043..e9adcbec 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/controller/core/configuration/Configuration.cpp @@ -335,6 +335,8 @@ void Configuration::setParameters(std::map std::uint64_t Configuration::getSimMemSizeInBytes() { // 1. Get number of banks, rows, columns and data width in bits for one die (or chip) + std::uint64_t ranks = memSpec->NumberOfRanks; + std::uint64_t bankgroups = memSpec->NumberOfBankGroups; std::uint64_t banks = memSpec->NumberOfBanks; std::uint64_t rows = memSpec->NumberOfRows; std::uint64_t columns = memSpec->NumberOfColumns; @@ -348,6 +350,8 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::cout << headline << std::endl << std::endl; std::cout << std::setw(24) << "Memory size in bytes : " << memorySize << std::endl; + std::cout << std::setw(24) << "Number of ranks : " << ranks << std::endl; + std::cout << std::setw(24) << "Number of bankgroups : " << bankgroups << std::endl; std::cout << std::setw(24) << "Number of banks : " << banks << std::endl; std::cout << std::setw(24) << "Number of rows : " << rows << std::endl; std::cout << std::setw(24) << "Number of columns : " << columns << std::endl; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 53827b65..cca8b2c2 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -62,8 +62,25 @@ using namespace Data; Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") { // Adjust number of bytes per burst dynamically to the selected ecc controller + // TODO: ECC only used for WideIO? bytesPerBurst = Configuration::getInstance().adjustNumBytesAfterECC(bytesPerBurst); + uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes(); + if (StoreMode == StorageMode::Store) + { + if (Configuration::getInstance().UseMalloc) + { + memory = (unsigned char *)malloc(memorySize); + if (!memory) + SC_REPORT_FATAL(this->name(), "Memory allocation failed"); + } + else + { + // allocate and model storage of one DRAM channel using memory map + memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + } + } + tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); } diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index a9e38b75..d5dc3ef9 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -57,9 +57,6 @@ class Dram : public sc_module private: unsigned int bytesPerBurst = Configuration::getInstance().getBytesPerBurst(); - // Power Model related - bool powerAnalysis = Configuration::getInstance().PowerAnalysis; - protected: Dram(sc_module_name); SC_HAS_PROCESS(Dram); diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index ace2bc44..0bbaf9c5 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -147,9 +147,6 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) // For each bank in a channel a error Model is created: if (StoreMode == StorageMode::ErrorModel) { - if (Configuration::getInstance().UseMalloc) - free(memory); - for (unsigned i = 0; i < memSpec->NumberOfBanks; i++) { errorModel *em; From 5fe5529c7cf6279f12cd074898b44ed09643c899 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 20 Sep 2019 17:35:01 +0200 Subject: [PATCH 101/183] Included various command lengths. --- .../resources/scripts/createTraceDB.sql | 19 ++++ DRAMSys/library/src/common/TlmRecorder.cpp | 30 +++++++ DRAMSys/library/src/common/TlmRecorder.h | 11 +-- .../controller/core/configuration/MemSpec.h | 17 ++++ .../businessObjects/commandlengths.h | 68 +++++++++++++++ .../businessObjects/phases/phasefactory.cpp | 87 +++++++++---------- DRAMSys/traceAnalyzer/data/tracedb.cpp | 35 ++++++++ DRAMSys/traceAnalyzer/data/tracedb.h | 8 ++ DRAMSys/traceAnalyzer/traceAnalyzer.pro | 3 +- 9 files changed, 225 insertions(+), 53 deletions(-) create mode 100644 DRAMSys/traceAnalyzer/businessObjects/commandlengths.h diff --git a/DRAMSys/library/resources/scripts/createTraceDB.sql b/DRAMSys/library/resources/scripts/createTraceDB.sql index f9ac86ae..e9c71b76 100644 --- a/DRAMSys/library/resources/scripts/createTraceDB.sql +++ b/DRAMSys/library/resources/scripts/createTraceDB.sql @@ -1,5 +1,6 @@ DROP TABLE IF EXISTS Phases; DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; DROP TABLE IF EXISTS Comments; DROP TABLE IF EXISTS ranges; DROP TABLE IF EXISTS Transactions; @@ -29,6 +30,24 @@ CREATE TABLE GeneralInfo( ControllerThread INTEGER ); +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + CREATE TABLE Power( time DOUBLE, AveragePower DOUBLE diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index d18320e3..b569823d 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -78,6 +78,7 @@ TlmRecorder::~TlmRecorder() sqlite3_finalize(insertPhaseStatement); sqlite3_finalize(updatePhaseStatement); sqlite3_finalize(insertGeneralInfoStatement); + sqlite3_finalize(insertCommandLengthsStatement); sqlite3_finalize(insertDebugMessageStatement); sqlite3_finalize(updateDataStrobeStatement); sqlite3_finalize(insertPowerStatement); @@ -285,6 +286,9 @@ void TlmRecorder::prepareSqlStatements() insertGeneralInfoString = "INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,clk,UnitOfTime,MCconfig,Memspec,Traces, WindowSize, FlexibleRefresh, MaxRefBurst, ControllerThread) VALUES" "(:numberOfTransactions,:end,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,:traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread)"; + insertCommandLengthsString = + "INSERT INTO CommandLengths VALUES" + "(:ACT, :PRE, :PREA, :RD, :RDA, :WR, :WRA, :REFA, :REFB, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)"; insertDebugMessageString = "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)"; @@ -299,6 +303,8 @@ void TlmRecorder::prepareSqlStatements() &updateDataStrobeStatement, 0); sqlite3_prepare_v2(db, insertGeneralInfoString.c_str(), -1, &insertGeneralInfoStatement, 0); + sqlite3_prepare_v2(db, insertCommandLengthsString.c_str(), -1, + &insertCommandLengthsStatement, 0); sqlite3_prepare_v2(db, insertDebugMessageString.c_str(), -1, &insertDebugMessageStatement, 0); sqlite3_prepare_v2(db, insertPowerString.c_str(), -1, &insertPowerStatement, 0); @@ -348,6 +354,29 @@ void TlmRecorder::insertGeneralInfo() executeSqlStatement(insertGeneralInfoStatement); } +void TlmRecorder::insertCommandLengths() +{ + MemSpec *memSpec = Configuration::getInstance().memSpec; + + sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->clACT); + sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->clPRE); + sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->clPREA); + sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->clRD); + sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->clRDA); + sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->clWR); + sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->clWRA); + sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->clREFA); + sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->clREFB); + sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->clPDEA); + sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->clPDXA); + sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->clPDEP); + sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->clPDXP); + sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->clSREFEN); + sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->clSREFEX); + + executeSqlStatement(insertCommandLengthsStatement); +} + void TlmRecorder::insertTransactionInDB(Transaction &recordingData) { sqlite3_bind_int(insertTransactionStatement, 1, recordingData.id); @@ -430,6 +459,7 @@ void TlmRecorder::closeConnection() { commitRecordedDataToDB(); insertGeneralInfo(); + insertCommandLengths(); PRINTDEBUGMESSAGE(name(), "Number of transactions written to DB: " + std::to_string(totalNumTransactions - 1)); PRINTDEBUGMESSAGE(name(), "tlmPhaseRecorder:\tEnd Recording"); diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index f1a7e860..122678b5 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -125,6 +125,7 @@ private: void commitRecordedDataToDB(); void insertGeneralInfo(); + void insertCommandLengths(); void insertTransactionInDB(Transaction &recordingData); void insertRangeInDB(unsigned int id, const sc_time &begin, const sc_time &end); void insertPhaseInDB(string phaseName, const sc_time &begin, const sc_time &end, @@ -141,12 +142,12 @@ private: std::vector transactionTerminatingPhases; sqlite3 *db = NULL; sqlite3_stmt *insertTransactionStatement, *insertRangeStatement, - *updateRangeStatement, - *insertPhaseStatement, *updatePhaseStatement, *insertGeneralInfoStatement, + *updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement, + *insertGeneralInfoStatement, *insertCommandLengthsStatement, *insertDebugMessageStatement, *updateDataStrobeStatement, *insertPowerStatement; - std::string insertTransactionString, insertRangeString, updateRangeString, - insertPhaseString, updatePhaseString, insertGeneralInfoString, - insertDebugMessageString, updateDataStrobeString, insertPowerString; + std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString, + updatePhaseString, insertGeneralInfoString, insertCommandLengthsString, + insertDebugMessageString, updateDataStrobeString, insertPowerString; }; #endif // TLMRECORDER_H diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 26f3197f..1d84d11c 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -104,6 +104,23 @@ struct MemSpec // For different refresh frequencies on different banks, not implemented //std::map refreshTimings; + // Command lengths on bus: + unsigned clACT = 1; + unsigned clPRE = 1; + unsigned clPREA = 1; + unsigned clRD = 1; + unsigned clRDA = 1; + unsigned clWR = 1; + unsigned clWRA = 1; + unsigned clREFA = 1; + unsigned clREFB = 1; + unsigned clPDEA = 1; + unsigned clPDXA = 1; + unsigned clPDEP = 1; + unsigned clPDXP = 1; + unsigned clSREFEN = 1; + unsigned clSREFEX = 1; + virtual ~MemSpec() {} }; diff --git a/DRAMSys/traceAnalyzer/businessObjects/commandlengths.h b/DRAMSys/traceAnalyzer/businessObjects/commandlengths.h new file mode 100644 index 00000000..63c9ed75 --- /dev/null +++ b/DRAMSys/traceAnalyzer/businessObjects/commandlengths.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef COMMANDLENGTHS_H +#define COMMANDLENGTHS_H + +struct CommandLengths +{ + unsigned ACT; + unsigned PRE; + unsigned PREA; + unsigned RD; + unsigned RDA; + unsigned WR; + unsigned WRA; + unsigned REFA; + unsigned REFB; + unsigned PDEA; + unsigned PDXA; + unsigned PDEP; + unsigned PDXP; + unsigned SREFEN; + unsigned SREFEX; + + CommandLengths(unsigned ACT, unsigned PRE, unsigned PREA, + unsigned RD, unsigned RDA, unsigned WR, unsigned WRA, + unsigned REFA, unsigned REFB, unsigned PDEA, unsigned PDXA, + unsigned PDEP, unsigned PDXP, unsigned SREFEN, unsigned SREFEX) : + ACT(ACT), PRE(PRE), PREA(PREA), RD(RD), RDA(RDA), WR(WR), WRA(WRA), + REFA(REFA), REFB(REFB), PDEA(PDEA), PDXA(PDXA), + PDEP(PDEP), PDXP(PDXP), SREFEN(SREFEN), SREFEX(SREFEX) {} + + CommandLengths() {} +}; + +#endif // COMMANDLENGTHS_H diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp index 8c92e00d..e505deb7 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phasefactory.cpp @@ -48,71 +48,64 @@ shared_ptr PhaseFactory::CreatePhase(ID id, const QString &dbPhaseName, const Timespan &span, const shared_ptr &trans, TraceDB &database) { traceTime clk = database.getGeneralInfo().clkPeriod; + const CommandLengths &cl = database.getCommandLengths(); if (dbPhaseName == "REQ") - return shared_ptr(new REQ(id, span, trans, {}, - std::shared_ptr())); + return shared_ptr(new REQ(id, span, trans, {}, std::shared_ptr())); else if (dbPhaseName == "RESP") - return shared_ptr(new RESP(id, span, trans, {}, - std::shared_ptr())); + return shared_ptr(new RESP(id, span, trans, {}, std::shared_ptr())); - else if (dbPhaseName == "PREB") return shared_ptr(new PREB(id, span, - trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); + else if (dbPhaseName == "PREB") + return shared_ptr(new PREB(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk)}, std::shared_ptr())); else if (dbPhaseName == "PRE") - return shared_ptr(new PRE(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); - else if (dbPhaseName == "ACTB") return shared_ptr(new ACTB(id, span, - trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); + return shared_ptr(new PRE(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PRE)}, std::shared_ptr())); + else if (dbPhaseName == "ACTB") + return shared_ptr(new ACTB(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk)}, std::shared_ptr())); else if (dbPhaseName == "ACT") - return shared_ptr(new ACT(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); + return shared_ptr(new ACT(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.ACT)}, std::shared_ptr())); else if (dbPhaseName == "PREA") - return shared_ptr(new PRECHARGE_ALL(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); + return shared_ptr(new PRECHARGE_ALL(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.PREA)}, std::shared_ptr())); else if (dbPhaseName == "REFA") - return shared_ptr(new REFA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); + return shared_ptr(new REFA(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.REFA)}, std::shared_ptr())); else if (dbPhaseName == "REFB") - return shared_ptr(new REFB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr())); - + return shared_ptr(new REFB(id, span, trans, + {Timespan(span.Begin(), span.Begin() + clk * cl.REFB)}, std::shared_ptr())); else if (dbPhaseName == "RD") - return shared_ptr(new RD(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr - (new Timespan(trans->SpanOnDataStrobe())))); + return shared_ptr(new RD(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RD)}, + std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); else if (dbPhaseName == "RDA") - return shared_ptr(new RDA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr - (new Timespan(trans->SpanOnDataStrobe())))); + return shared_ptr(new RDA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.RDA)}, + std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); else if (dbPhaseName == "WR") - return shared_ptr(new WR(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr - (new Timespan(trans->SpanOnDataStrobe())))); + return shared_ptr(new WR(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WR)}, + std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); else if (dbPhaseName == "WRA") - return shared_ptr(new WRA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk)}, - std::shared_ptr - (new Timespan(trans->SpanOnDataStrobe())))); + return shared_ptr(new WRA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.WRA)}, + std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); else if (dbPhaseName == "PDNA") - return shared_ptr(new PDNA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), Timespan(span.End() - clk, span.End())}, - std::shared_ptr())); + return shared_ptr(new PDNA(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEA), + Timespan(span.End() - clk * cl.PDXA, span.End())}, std::shared_ptr())); else if (dbPhaseName == "PDNAB") - return shared_ptr(new PDNAB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), Timespan(span.End() - clk, span.End())}, - std::shared_ptr())); + return shared_ptr(new PDNAB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), + Timespan(span.End() - clk, span.End())}, std::shared_ptr())); else if (dbPhaseName == "PDNP") - return shared_ptr(new PDNP(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), Timespan(span.End() - clk, span.End())}, - std::shared_ptr())); + return shared_ptr(new PDNP(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.PDEP), + Timespan(span.End() - clk * cl.PDXP, span.End())}, std::shared_ptr())); else if (dbPhaseName == "PDNPB") - return shared_ptr(new PDNPB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), Timespan(span.End() - clk, span.End())}, - std::shared_ptr())); + return shared_ptr(new PDNPB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), + Timespan(span.End() - clk, span.End())}, std::shared_ptr())); else if (dbPhaseName == "SREF") - return shared_ptr(new SREF(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), Timespan(span.End() - clk, span.End())}, - std::shared_ptr())); + return shared_ptr(new SREF(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk * cl.SREFEN), + Timespan(span.End() - clk * cl.SREFEX, span.End())}, std::shared_ptr())); else if (dbPhaseName == "SREFB") - return shared_ptr(new SREFB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), Timespan(span.End() - clk, span.End())}, - std::shared_ptr())); + return shared_ptr(new SREFB(id, span, trans, {Timespan(span.Begin(), span.Begin() + clk), + Timespan(span.End() - clk, span.End())}, std::shared_ptr())); else - throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + - " unkown to phasefactory"); + throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + " unkown to phasefactory"); } diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index 326db059..2e99fc07 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -70,6 +70,7 @@ TraceDB::TraceDB(QString path, bool openExisting) dropAndCreateTables(); prepareQueries(); generalInfo = getGeneralInfoFromDB(); + commandLengths = getCommandLengthsFromDB(); } void TraceDB::prepareQueries() @@ -273,6 +274,40 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() } } +CommandLengths TraceDB::getCommandLengthsFromDB() +{ + QSqlQuery query(database); + query.prepare("SELECT * FROM CommandLengths"); + executeQuery(query); + + if (query.next()) + { + unsigned ACT = query.value(0).toInt(); + unsigned PRE = query.value(1).toInt(); + unsigned PREA = query.value(2).toInt(); + unsigned RD = query.value(3).toInt(); + unsigned RDA = query.value(4).toInt(); + unsigned WR = query.value(5).toInt(); + unsigned WRA = query.value(6).toInt(); + unsigned REFA = query.value(7).toInt(); + unsigned REFB = query.value(8).toInt(); + unsigned PDEA = query.value(9).toInt(); + unsigned PDXA = query.value(10).toInt(); + unsigned PDEP = query.value(11).toInt(); + unsigned PDXP = query.value(12).toInt(); + unsigned SREFEN = query.value(13).toInt(); + unsigned SREFEX = query.value(14).toInt(); + + return CommandLengths(ACT, PRE, PREA, RD, RDA, WR, WRA, REFA, REFB, + PDEA, PDXA, PDEP, PDXP, SREFEN, SREFEX); + } + else + { + throw sqlException("Tracefile corrupted. No command lengths table", + this->pathToDB.toStdString()); + } +} + unsigned int TraceDB::getNumberOfPhases() { QSqlQuery query(database); diff --git a/DRAMSys/traceAnalyzer/data/tracedb.h b/DRAMSys/traceAnalyzer/data/tracedb.h index 7ab07040..60afb9b8 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.h +++ b/DRAMSys/traceAnalyzer/data/tracedb.h @@ -48,6 +48,7 @@ #include #include "businessObjects/transaction.h" #include "businessObjects/generalinfo.h" +#include "businessObjects/commandlengths.h" #include "businessObjects/phases/phasefactory.h" #include "businessObjects/comment.h" #include "QueryTexts.h" @@ -76,6 +77,11 @@ public: return generalInfo; } + const CommandLengths &getCommandLengths() + { + return commandLengths; + } + std::vector> getTransactionsWithCustomQuery( QString queryText); std::vector> getTransactionsInTimespan( @@ -100,6 +106,7 @@ private: QString pathToDB; QSqlDatabase database; GeneralInfo generalInfo; + CommandLengths commandLengths; QSqlQuery insertPhaseQuery; QSqlQuery insertTransactionQuery; @@ -122,6 +129,7 @@ private: unsigned int getNumberOfPhases(); GeneralInfo getGeneralInfoFromDB(); + CommandLengths getCommandLengthsFromDB(); }; diff --git a/DRAMSys/traceAnalyzer/traceAnalyzer.pro b/DRAMSys/traceAnalyzer/traceAnalyzer.pro index e30300c5..9db5fe69 100644 --- a/DRAMSys/traceAnalyzer/traceAnalyzer.pro +++ b/DRAMSys/traceAnalyzer/traceAnalyzer.pro @@ -156,7 +156,8 @@ HEADERS += businessObjects/transaction.h \ presentation/tracemetrictreewidget.h \ businessObjects/calculatedMetric.h \ businessObjects/tracecalculatedmetrics.h \ - businessObjects/phases/phase.h + businessObjects/phases/phase.h \ + businessObjects/commandlengths.h FORMS += \ From 650e1d405b13a1ad2c4db91523fd74f8d2178908 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 23 Sep 2019 10:23:02 +0200 Subject: [PATCH 102/183] Removed ScheduledCommand dependencies. --- DRAMSys/library/src/controller/Controller.cpp | 1 - .../library/src/controller/ControllerRecordable.cpp | 4 +--- DRAMSys/library/src/controller/checker/CheckerIF.h | 1 - .../src/controller/core/configuration/MemSpec.cpp | 11 +++++++++++ .../src/controller/core/configuration/MemSpec.h | 3 +++ 5 files changed, 15 insertions(+), 5 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 3cf55f09..20f98d58 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -41,7 +41,6 @@ #include "cmdmux/CmdMuxOldest.h" #include "../common/dramExtensions.h" #include "../common/protocol.h" -#include "core/scheduling/ScheduledCommand.h" #include "checker/CheckerDDR3.h" #include "checker/CheckerWideIO.h" #include "refresh/RefreshManager.h" diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 8e3ed98e..55788b15 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -62,9 +62,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl { if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) { - sc_time execTime = Configuration::getInstance().memSpec->getExecutionTime(command); - ScheduledCommand scheduledCommand(command, sc_time_stamp(), execTime, *payload); - TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); + TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } Controller::sendToDram(command, payload); diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 8a914b88..34cd9777 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -37,7 +37,6 @@ #include #include -#include "../core/scheduling/ScheduledCommand.h" #include "../Command.h" #include "../../common/dramExtensions.h" #include "../../common/DebugManager.h" diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp index 53ee7588..dc31e2f5 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp @@ -76,6 +76,17 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const } } +TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const +{ + // TODO: implement this function for different memspecs, add AL for DDR3 + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); +} + // Returns the execution time for commands that have a fixed execution time // TODO: override this method for different MemSpecs? sc_time MemSpec::getExecutionTime(Command command) const diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 1d84d11c..156f75e8 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -42,6 +42,7 @@ #include #include "../../../common/dramExtensions.h" #include "../../Command.h" +#include "../../../common/utils.h" using namespace tlm; @@ -58,6 +59,8 @@ struct MemSpec virtual sc_time getExecutionTime(Command) const; + virtual TimeInterval getIntervalOnDataStrobe(Command) const; + std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; From c1b741d89b2c061c27fdae335502484813f05b56 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 23 Sep 2019 13:24:47 +0200 Subject: [PATCH 103/183] Changed directory of configuration, added attribute unused to suppress warnings. --- DRAMSys/library/library.pro | 18 +++++++++--------- DRAMSys/library/src/common/DebugManager.cpp | 2 +- DRAMSys/library/src/common/TlmRecorder.cpp | 2 +- .../library/src/common/XmlAddressDecoder.cpp | 2 +- DRAMSys/library/src/common/dramExtensions.cpp | 2 +- .../core => common}/timingCalculations.cpp | 8 ++++---- .../core => common}/timingCalculations.h | 3 +-- .../core => }/configuration/Configuration.cpp | 2 +- .../core => }/configuration/Configuration.h | 4 ++-- .../configuration/ConfigurationLoader.cpp | 4 ++-- .../configuration/ConfigurationLoader.h | 4 ++-- .../core => }/configuration/MemSpec.cpp | 5 ++++- .../core => }/configuration/MemSpec.h | 6 +++--- .../configuration/TemperatureSimConfig.h | 12 ++++++------ DRAMSys/library/src/controller/Controller.cpp | 6 +++--- .../src/controller/ControllerRecordable.cpp | 16 ++++++++-------- .../library/src/controller/GenericController.h | 2 +- .../src/controller/checker/CheckerDDR3.cpp | 2 +- .../src/controller/checker/CheckerDDR3.h | 6 +++--- .../library/src/controller/checker/CheckerIF.h | 2 +- .../src/controller/checker/CheckerWideIO.cpp | 2 +- .../src/controller/checker/CheckerWideIO.h | 6 +++--- .../core/scheduling/ScheduledCommand.cpp | 4 ++-- .../src/controller/refresh/RefreshManager.cpp | 2 +- .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 2 +- .../refresh/RefreshManagerBankwise.h | 2 +- DRAMSys/library/src/error/errormodel.h | 2 +- DRAMSys/library/src/simulation/Arbiter.h | 4 ++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 4 ++-- DRAMSys/library/src/simulation/Dram.cpp | 4 ++-- DRAMSys/library/src/simulation/Dram.h | 4 ++-- DRAMSys/library/src/simulation/DramDDR3.cpp | 4 ++-- DRAMSys/library/src/simulation/DramDDR4.cpp | 4 ++-- .../library/src/simulation/DramRecordable.cpp | 12 ++++++------ DRAMSys/library/src/simulation/DramWideIO.cpp | 4 ++-- DRAMSys/library/src/simulation/IArbiter.h | 2 +- .../library/src/simulation/MemoryManager.cpp | 2 +- .../src/simulation/TemperatureController.cpp | 6 +++--- .../src/simulation/TemperatureController.h | 2 +- DRAMSys/library/src/simulation/TracePlayer.h | 4 ++-- 41 files changed, 94 insertions(+), 92 deletions(-) rename DRAMSys/library/src/{controller/core => common}/timingCalculations.cpp (94%) rename DRAMSys/library/src/{controller/core => common}/timingCalculations.h (97%) rename DRAMSys/library/src/{controller/core => }/configuration/Configuration.cpp (99%) rename DRAMSys/library/src/{controller/core => }/configuration/Configuration.h (98%) rename DRAMSys/library/src/{controller/core => }/configuration/ConfigurationLoader.cpp (99%) rename DRAMSys/library/src/{controller/core => }/configuration/ConfigurationLoader.h (97%) rename DRAMSys/library/src/{controller/core => }/configuration/MemSpec.cpp (98%) rename DRAMSys/library/src/{controller/core => }/configuration/MemSpec.h (98%) rename DRAMSys/library/src/{controller/core => }/configuration/TemperatureSimConfig.h (93%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index e5232799..b7eae32c 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -89,14 +89,14 @@ SOURCES += \ src/common/third_party/tinyxml2/tinyxml2.cpp \ src/common/TlmRecorder.cpp \ src/common/DebugManager.cpp \ - src/controller/core/configuration/Configuration.cpp \ + src/configuration/Configuration.cpp \ src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ src/controller/core/powerdown/PowerDownManagerBankwise.cpp \ src/controller/core/powerdown/PowerDownManager.cpp \ src/controller/core/scheduling/ScheduledCommand.cpp \ src/simulation/MemoryManager.cpp \ src/simulation/TemperatureController.cpp \ - src/controller/core/configuration/ConfigurationLoader.cpp \ + src/configuration/ConfigurationLoader.cpp \ src/controller/core/powerdown/NoPowerDown.cpp \ src/controller/Command.cpp \ src/error/errormodel.cpp \ @@ -115,14 +115,14 @@ SOURCES += \ src/simulation/Arbiter.cpp \ src/common/CongenAddressDecoder.cpp \ src/common/XmlAddressDecoder.cpp \ - src/controller/core/timingCalculations.cpp \ + src/common/timingCalculations.cpp \ src/common/dramExtensions.cpp \ src/common/utils.cpp \ src/simulation/DramDDR3.cpp \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ - src/controller/core/configuration/MemSpec.cpp \ + src/configuration/MemSpec.cpp \ src/controller/BankMachine.cpp \ src/controller/Controller.cpp \ src/controller/scheduler/SchedulerFifo.cpp \ @@ -142,7 +142,7 @@ HEADERS += \ src/common/tlm2_base_protocol_checker.h \ src/common/protocol.h \ src/common/DebugManager.h \ - src/controller/core/configuration/Configuration.h \ + src/configuration/Configuration.h \ src/controller/core/powerdown/PowerDownManagerTimeout.h \ src/controller/core/powerdown/PowerDownManagerBankwise.h \ src/controller/core/powerdown/PowerDownManager.h \ @@ -153,7 +153,7 @@ HEADERS += \ src/simulation/Arbiter.h \ src/common/libDRAMPower.h \ src/simulation/ReorderBuffer.h \ - src/controller/core/configuration/MemSpec.h \ + src/configuration/MemSpec.h \ src/simulation/StlPlayer.h \ src/simulation/TracePlayerListener.h \ src/simulation/TraceGenerator.h \ @@ -161,7 +161,7 @@ HEADERS += \ src/controller/core/powerdown/NoPowerDown.h \ src/controller/Command.h \ src/controller/core/powerdown/IPowerDownManager.h \ - src/controller/core/configuration/ConfigurationLoader.h \ + src/configuration/ConfigurationLoader.h \ src/error/errormodel.h \ src/simulation/ExampleInitiator.h \ src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h \ @@ -178,10 +178,10 @@ HEADERS += \ src/common/AddressDecoder.h \ src/common/CongenAddressDecoder.h \ src/common/XmlAddressDecoder.h \ - src/controller/core/timingCalculations.h \ + src/common/timingCalculations.h \ src/common/dramExtensions.h \ src/common/utils.h \ - src/controller/core/configuration/TemperatureSimConfig.h \ + src/configuration/TemperatureSimConfig.h \ src/simulation/DramDDR3.h \ src/simulation/DramDDR4.h \ src/simulation/DramRecordable.h \ diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp index 034e3747..ec50b87e 100644 --- a/DRAMSys/library/src/common/DebugManager.cpp +++ b/DRAMSys/library/src/common/DebugManager.cpp @@ -38,7 +38,7 @@ #ifdef DEBUGGING -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" using namespace std; void DebugManager::printDebugMessage(string sender, string message) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index b569823d..97c6709b 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -43,7 +43,7 @@ #include "protocol.h" #include "dramExtensions.h" #include "XmlAddressDecoder.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" using namespace std; diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 786c3335..2da48e45 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -39,7 +39,7 @@ #include #include "utils.h" #include "bitset" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" using namespace tinyxml2; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 399d1b2f..d49666bf 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -36,7 +36,7 @@ */ #include "dramExtensions.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "map" #include "utils.h" diff --git a/DRAMSys/library/src/controller/core/timingCalculations.cpp b/DRAMSys/library/src/common/timingCalculations.cpp similarity index 94% rename from DRAMSys/library/src/controller/core/timingCalculations.cpp rename to DRAMSys/library/src/common/timingCalculations.cpp index 2fe9551a..ddf06098 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.cpp +++ b/DRAMSys/library/src/common/timingCalculations.cpp @@ -35,10 +35,10 @@ */ #include "timingCalculations.h" -#include "configuration/MemSpec.h" -#include "../../common/DebugManager.h" -#include "configuration/Configuration.h" -#include "../../common/utils.h" +#include "../configuration/MemSpec.h" +#include "DebugManager.h" +#include "../configuration/Configuration.h" +#include "utils.h" sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint) diff --git a/DRAMSys/library/src/controller/core/timingCalculations.h b/DRAMSys/library/src/common/timingCalculations.h similarity index 97% rename from DRAMSys/library/src/controller/core/timingCalculations.h rename to DRAMSys/library/src/common/timingCalculations.h index 4e8966ee..7288b93c 100644 --- a/DRAMSys/library/src/controller/core/timingCalculations.h +++ b/DRAMSys/library/src/common/timingCalculations.h @@ -39,8 +39,7 @@ #include #include -#include "../../common/dramExtensions.h" -#include "../Command.h" +#include "dramExtensions.h" sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint); diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp similarity index 99% rename from DRAMSys/library/src/controller/core/configuration/Configuration.cpp rename to DRAMSys/library/src/configuration/Configuration.cpp index e9adcbec..0624ae55 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -40,7 +40,7 @@ #include "Configuration.h" #include "ConfigurationLoader.h" -#include "../../../common/XmlAddressDecoder.h" +#include "../common/XmlAddressDecoder.h" using namespace std; diff --git a/DRAMSys/library/src/controller/core/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h similarity index 98% rename from DRAMSys/library/src/controller/core/configuration/Configuration.h rename to DRAMSys/library/src/configuration/Configuration.h index efab5eeb..9802b58e 100644 --- a/DRAMSys/library/src/controller/core/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -44,9 +44,9 @@ #include #include "MemSpec.h" #include "TemperatureSimConfig.h" -#include "../../../common/utils.h" +#include "../common/utils.h" -#include "../../../error/eccbaseclass.h" +#include "../error/eccbaseclass.h" enum class StorageMode {NoStorage, Store, ErrorModel}; diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp similarity index 99% rename from DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp rename to DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 76b0b971..71ae8b25 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -37,7 +37,7 @@ #include "ConfigurationLoader.h" #include "MemSpec.h" -#include "../timingCalculations.h" +#include "../common/timingCalculations.h" using namespace tinyxml2; using namespace std; @@ -192,7 +192,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); memSpec->tRC = clk * queryUIntParameter(timings, "RC"); memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/library/src/configuration/ConfigurationLoader.h similarity index 97% rename from DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h rename to DRAMSys/library/src/configuration/ConfigurationLoader.h index 7a4e0410..142a6918 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.h @@ -39,8 +39,8 @@ #define CONFIGURATIONLOADER_H #include -#include "../../../common/third_party/tinyxml2/tinyxml2.h" -#include "../../../common/utils.h" +#include "../common/third_party/tinyxml2/tinyxml2.h" +#include "../common/utils.h" #include "Configuration.h" class ConfigurationLoader diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp b/DRAMSys/library/src/configuration/MemSpec.cpp similarity index 98% rename from DRAMSys/library/src/controller/core/configuration/MemSpec.cpp rename to DRAMSys/library/src/configuration/MemSpec.cpp index dc31e2f5..891252d2 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/MemSpec.cpp @@ -37,7 +37,7 @@ #include #include -#include "../../Command.h" +#include "../controller/Command.h" #include "Configuration.h" using namespace tlm; @@ -84,7 +84,10 @@ TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const else if (command == Command::WR || command == Command::WRA) return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); else + { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } } // Returns the execution time for commands that have a fixed execution time diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/configuration/MemSpec.h similarity index 98% rename from DRAMSys/library/src/controller/core/configuration/MemSpec.h rename to DRAMSys/library/src/configuration/MemSpec.h index 156f75e8..6d277e5a 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/configuration/MemSpec.h @@ -40,9 +40,9 @@ #include #include -#include "../../../common/dramExtensions.h" -#include "../../Command.h" -#include "../../../common/utils.h" +#include "../common/dramExtensions.h" +#include "../controller/Command.h" +#include "../common/utils.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h b/DRAMSys/library/src/configuration/TemperatureSimConfig.h similarity index 93% rename from DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h rename to DRAMSys/library/src/configuration/TemperatureSimConfig.h index f8344541..a0505bbf 100644 --- a/DRAMSys/library/src/controller/core/configuration/TemperatureSimConfig.h +++ b/DRAMSys/library/src/configuration/TemperatureSimConfig.h @@ -41,9 +41,9 @@ #include #include -#include "../../../common/DebugManager.h" -#include "../../../common/third_party/tinyxml2/tinyxml2.h" -#include "../../../common/utils.h" +#include "../common/DebugManager.h" +#include "../common/third_party/tinyxml2/tinyxml2.h" +#include "../common/utils.h" struct TemperatureSimConfig { @@ -113,13 +113,13 @@ struct TemperatureSimConfig void showTemperatureSimConfig() { - int i = 0; - for (auto e : powerInitialValues) { + int i __attribute__((unused)) = 0; + for (auto e __attribute__((unused)) : powerInitialValues) { PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerInitialValues[" + std::to_string(i++) + "]: " + std::to_string(e)); } i = 0; - for (auto e : powerThresholds) { + for (auto e __attribute__((unused)) : powerThresholds) { PRINTDEBUGMESSAGE("TemperatureSimConfig", "powerThreshold[" + std::to_string(i++) + "]: " + std::to_string(e)); } diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 20f98d58..335fa01b 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -34,7 +34,7 @@ #include "Controller.h" -#include "core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "scheduler/SchedulerFifo.h" #include "scheduler/SchedulerFrFcfs.h" #include "cmdmux/CmdMuxStrict.h" @@ -251,7 +251,7 @@ unsigned int Controller::transport_dbg(tlm_generic_payload &) void Controller::releasePayload() { - uint64_t id = DramExtension::getPayloadID(payloadToRelease); + uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToRelease); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); payloadToRelease->release(); @@ -265,7 +265,7 @@ void Controller::releasePayload() void Controller::acquirePayload() { - uint64_t id = DramExtension::getPayloadID(payloadToAcquire); + uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToAcquire); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); if (numberOfPayloads == 0) diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 55788b15..aa2c7722 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -35,7 +35,7 @@ #include "ControllerRecordable.h" #include "../common/protocol.h" -#include "core/configuration/Configuration.h" +#include "../configuration/Configuration.h" tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay) @@ -72,13 +72,13 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase pha { sc_time recTime = delay + sc_time_stamp(); - unsigned int thr = DramExtension::getExtension(trans).getThread().ID(); - unsigned int ch = DramExtension::getExtension(trans).getChannel().ID(); - unsigned int bg = DramExtension::getExtension(trans).getBankGroup().ID(); - unsigned int bank = DramExtension::getExtension(trans).getBank().ID(); - unsigned int row = DramExtension::getExtension(trans).getRow().ID(); - unsigned int col = DramExtension::getExtension(trans).getColumn().ID(); - uint64_t id = DramExtension::getExtension(trans).getPayloadID(); + unsigned int thr __attribute__((unused)) = DramExtension::getExtension(trans).getThread().ID(); + unsigned int ch __attribute__((unused)) = DramExtension::getExtension(trans).getChannel().ID(); + unsigned int bg __attribute__((unused)) = DramExtension::getExtension(trans).getBankGroup().ID(); + unsigned int bank __attribute__((unused)) = DramExtension::getExtension(trans).getBank().ID(); + unsigned int row __attribute__((unused)) = DramExtension::getExtension(trans).getRow().ID(); + unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID(); + uint64_t id __attribute__((unused)) = DramExtension::getExtension(trans).getPayloadID(); PRINTDEBUGMESSAGE(name(), "Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( diff --git a/DRAMSys/library/src/controller/GenericController.h b/DRAMSys/library/src/controller/GenericController.h index 5d49dc68..896d6fcd 100644 --- a/DRAMSys/library/src/controller/GenericController.h +++ b/DRAMSys/library/src/controller/GenericController.h @@ -5,7 +5,7 @@ #include #include #include -#include "core/configuration/Configuration.h" +#include "../configuration/Configuration.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 6661b967..38da02a6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -62,7 +62,7 @@ CheckerDDR3::~CheckerDDR3() delete refreshChecker; } -sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) +sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 5b5a52b8..b3632ba4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -38,8 +38,8 @@ #include "CheckerIF.h" #include #include -#include "../core/configuration/MemSpec.h" -#include "../core/configuration/Configuration.h" +#include "../../configuration/MemSpec.h" +#include "../../configuration/Configuration.h" class RefreshCheckerDDR3Dummy; @@ -48,7 +48,7 @@ class CheckerDDR3 final : public CheckerIF public: CheckerDDR3(); ~CheckerDDR3(); - sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank); + sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; void insert(Command, Rank, Bank); private: diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 34cd9777..f01350fa 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -46,7 +46,7 @@ class CheckerIF public: virtual ~CheckerIF() {} - virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) = 0; + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; virtual void insert(Command, Rank, Bank) = 0; protected: diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 8369fb0f..60901022 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -62,7 +62,7 @@ CheckerWideIO::~CheckerWideIO() delete refreshChecker; } -sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) +sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 6d48bbd9..cddbe9f5 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -38,8 +38,8 @@ #include "CheckerIF.h" #include #include -#include "../core/configuration/MemSpec.h" -#include "../core/configuration/Configuration.h" +#include "../../configuration/MemSpec.h" +#include "../../configuration/Configuration.h" class RefreshCheckerWideIODummy; @@ -48,7 +48,7 @@ class CheckerWideIO final : public CheckerIF public: CheckerWideIO(); ~CheckerWideIO(); - sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank); + sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; void insert(Command, Rank, Bank); private: diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index bdfebd0e..e26a56c0 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -35,9 +35,9 @@ */ #include "ScheduledCommand.h" -#include "../timingCalculations.h" +#include "../../../common/timingCalculations.h" #include "../../../common/utils.h" -#include "../configuration/Configuration.h" +#include "../../../configuration/Configuration.h" //#include "../configuration/MemSpec.h" bool ScheduledCommand::isNoCommand() const diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index b0a5687f..ce63d093 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -34,7 +34,7 @@ #include "RefreshManager.h" #include "../../common/dramExtensions.h" -#include "../core/configuration/Configuration.h" +#include "../../configuration/Configuration.h" #include "../../common/utils.h" RefreshManager::RefreshManager(std::vector &bankMachines) : bankMachines(bankMachines) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 4a9ccedf..9c424674 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -36,7 +36,7 @@ #define REFRESHMANAGER_H #include "RefreshManagerIF.h" -#include "../core/configuration/MemSpec.h" +#include "../../configuration/MemSpec.h" #include "../BankMachine.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 12bd1781..59a45813 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -33,7 +33,7 @@ */ #include "RefreshManagerBankwise.h" -#include "../core/configuration/Configuration.h" +#include "../../configuration/Configuration.h" #include "../../common/utils.h" #include "../../common/dramExtensions.h" diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 97ae782a..c58d4595 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -36,7 +36,7 @@ #define REFRESHMANAGERBANKWISE_H #include "RefreshManagerIF.h" -#include "../core/configuration/MemSpec.h" +#include "../../configuration/MemSpec.h" #include "../BankMachine.h" #include #include diff --git a/DRAMSys/library/src/error/errormodel.h b/DRAMSys/library/src/error/errormodel.h index 23101b75..d027d9b3 100644 --- a/DRAMSys/library/src/error/errormodel.h +++ b/DRAMSys/library/src/error/errormodel.h @@ -39,7 +39,7 @@ #include #include #include -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "../common/XmlAddressDecoder.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 1be19fe8..b8576eda 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -48,8 +48,8 @@ #include #include "../common/XmlAddressDecoder.h" #include "../common/dramExtensions.h" -#include "../controller/core/timingCalculations.h" -#include "../controller/core/configuration/ConfigurationLoader.h" +#include "../common/timingCalculations.h" +#include "../configuration/ConfigurationLoader.h" using namespace std; using namespace tlm; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index bfb16a85..dcae5552 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -48,7 +48,7 @@ #include "../common/DebugManager.h" #include "../common/XmlAddressDecoder.h" #include "../common/CongenAddressDecoder.h" -#include "../controller/core/configuration/ConfigurationLoader.h" +#include "../configuration/ConfigurationLoader.h" #include "../common/utils.h" #include "../simulation/TemperatureController.h" #include "../error/ecchamming.h" @@ -178,7 +178,7 @@ void DRAMSys::logo() #undef BOLDBLUETXT } -void DRAMSys::setupDebugManager(const string &traceName) +void DRAMSys::setupDebugManager(const string &traceName __attribute__((unused))) { #ifdef DEBUGGING auto &dbg = DebugManager::getInstance(); diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index cca8b2c2..1475747e 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -50,8 +50,8 @@ #include #include "../common/DebugManager.h" #include "../common/dramExtensions.h" -#include "../controller/core/timingCalculations.h" -#include "../controller/core/configuration/Configuration.h" +#include "../common/timingCalculations.h" +#include "../configuration/Configuration.h" #include "../common/protocol.h" #include "../common/utils.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index d5dc3ef9..ea0a2822 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -44,8 +44,8 @@ #include #include #include "../common/protocol.h" -#include "../controller/core/configuration/Configuration.h" -#include "../controller/core/configuration/MemSpec.h" +#include "../configuration/Configuration.h" +#include "../configuration/MemSpec.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index acc9f865..66d70e08 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -36,9 +36,9 @@ #include "DramDDR3.h" #include "Dram.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../controller/core/configuration/MemSpec.h" +#include "../configuration/MemSpec.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 71517b2e..36caf370 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -36,9 +36,9 @@ #include "DramDDR4.h" #include "Dram.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../controller/core/configuration/MemSpec.h" +#include "../configuration/MemSpec.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index e52e679f..c0eeec7d 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -88,12 +88,12 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay else if (phase == END_SREF || phase == END_SREFB) recTime += this->memSpec->getExecutionTime(Command::SREFEX); - unsigned int thr = DramExtension::getExtension(payload).getThread().ID(); - unsigned int ch = DramExtension::getExtension(payload).getChannel().ID(); - unsigned int bg = DramExtension::getExtension(payload).getBankGroup().ID(); - unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); - unsigned int row = DramExtension::getExtension(payload).getRow().ID(); - unsigned int col = DramExtension::getExtension(payload).getColumn().ID(); + unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID(); + unsigned int ch __attribute__((unused)) = DramExtension::getExtension(payload).getChannel().ID(); + unsigned int bg __attribute__((unused)) = DramExtension::getExtension(payload).getBankGroup().ID(); + unsigned int bank __attribute__((unused)) = DramExtension::getExtension(payload).getBank().ID(); + unsigned int row __attribute__((unused)) = DramExtension::getExtension(payload).getRow().ID(); + unsigned int col __attribute__((unused)) = DramExtension::getExtension(payload).getColumn().ID(); PRINTDEBUGMESSAGE(this->name(), "Recording " + phaseNameToString(phase) + " thread " + to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string( diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 0bbaf9c5..41f05077 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -38,10 +38,10 @@ #include #include #include "Dram.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "../error/errormodel.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../controller/core/configuration/MemSpec.h" +#include "../configuration/MemSpec.h" using namespace tlm; diff --git a/DRAMSys/library/src/simulation/IArbiter.h b/DRAMSys/library/src/simulation/IArbiter.h index 5b18dc1a..1ad91a0e 100644 --- a/DRAMSys/library/src/simulation/IArbiter.h +++ b/DRAMSys/library/src/simulation/IArbiter.h @@ -44,7 +44,7 @@ #include #include #include -#include "../controller/core/configuration/ConfigurationLoader.h" +#include "../configuration/ConfigurationLoader.h" using namespace std; using namespace tlm; diff --git a/DRAMSys/library/src/simulation/MemoryManager.cpp b/DRAMSys/library/src/simulation/MemoryManager.cpp index 49f2a014..f5dee080 100644 --- a/DRAMSys/library/src/simulation/MemoryManager.cpp +++ b/DRAMSys/library/src/simulation/MemoryManager.cpp @@ -36,7 +36,7 @@ #include "MemoryManager.h" #include "../common/DebugManager.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include using namespace std; diff --git a/DRAMSys/library/src/simulation/TemperatureController.cpp b/DRAMSys/library/src/simulation/TemperatureController.cpp index 09489377..04fb716d 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.cpp +++ b/DRAMSys/library/src/simulation/TemperatureController.cpp @@ -37,7 +37,7 @@ #include #include "TemperatureController.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" double TemperatureController::temperatureConvert(double tKelvin) { @@ -164,8 +164,8 @@ void TemperatureController::temperatureThread() updateTemperatures(); double p = adjustThermalSimPeriod(); - int i = 0; - for (auto t : temperatureValues) { + int i __attribute__((unused)) = 0; + for (auto t __attribute__((unused)) : temperatureValues) { PRINTDEBUGMESSAGE(name(), "Temperature[" + std::to_string(i++) + "] is " + std::to_string(t)); } diff --git a/DRAMSys/library/src/simulation/TemperatureController.h b/DRAMSys/library/src/simulation/TemperatureController.h index fa16c1f0..aeb02e00 100644 --- a/DRAMSys/library/src/simulation/TemperatureController.h +++ b/DRAMSys/library/src/simulation/TemperatureController.h @@ -44,7 +44,7 @@ #include "../common/DebugManager.h" #include "../common/utils.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #ifdef THERMALSIM #include "IceWrapper.h" diff --git a/DRAMSys/library/src/simulation/TracePlayer.h b/DRAMSys/library/src/simulation/TracePlayer.h index 9adbcb51..b866e5ce 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.h +++ b/DRAMSys/library/src/simulation/TracePlayer.h @@ -47,10 +47,10 @@ #include #include #include "MemoryManager.h" -#include "../controller/core/configuration/Configuration.h" +#include "../configuration/Configuration.h" #include "../common/DebugManager.h" #include "../common/XmlAddressDecoder.h" -#include "../controller/core/timingCalculations.h" +#include "../common/timingCalculations.h" #include "TracePlayerListener.h" using namespace std; From bda10dca2f7ef0c319b2fcb711b796d2c886a366 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 23 Sep 2019 14:31:47 +0200 Subject: [PATCH 104/183] Individual memspec files for different DRAMs. --- DRAMSys/library/library.pro | 13 ++- .../library/src/common/timingCalculations.cpp | 2 +- .../library/src/configuration/Configuration.h | 2 +- .../src/configuration/ConfigurationLoader.cpp | 9 +- .../configuration/{ => memspec}/MemSpec.cpp | 37 +------ .../src/configuration/{ => memspec}/MemSpec.h | 97 +------------------ .../src/configuration/memspec/MemSpecDDR3.h | 57 +++++++++++ .../src/configuration/memspec/MemSpecDDR4.h | 63 ++++++++++++ .../configuration/memspec/MemSpecLPDDR4.cpp | 67 +++++++++++++ .../src/configuration/memspec/MemSpecLPDDR4.h | 65 +++++++++++++ .../src/configuration/memspec/MemSpecWideIO.h | 66 +++++++++++++ .../src/controller/checker/CheckerDDR3.h | 2 +- .../src/controller/checker/CheckerWideIO.h | 2 +- .../core/scheduling/ScheduledCommand.cpp | 1 - .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.h | 2 +- DRAMSys/library/src/simulation/Dram.h | 2 +- DRAMSys/library/src/simulation/DramDDR3.cpp | 2 +- DRAMSys/library/src/simulation/DramDDR4.cpp | 2 +- DRAMSys/library/src/simulation/DramWideIO.cpp | 4 +- 20 files changed, 352 insertions(+), 145 deletions(-) rename DRAMSys/library/src/configuration/{ => memspec}/MemSpec.cpp (77%) rename DRAMSys/library/src/configuration/{ => memspec}/MemSpec.h (69%) create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index b7eae32c..3bc74e25 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -122,7 +122,7 @@ SOURCES += \ src/simulation/DramDDR4.cpp \ src/simulation/DramRecordable.cpp \ src/simulation/DramWideIO.cpp \ - src/configuration/MemSpec.cpp \ + src/configuration/memspec/MemSpec.cpp \ src/controller/BankMachine.cpp \ src/controller/Controller.cpp \ src/controller/scheduler/SchedulerFifo.cpp \ @@ -134,7 +134,8 @@ SOURCES += \ src/controller/refresh/RefreshManager.cpp \ src/controller/refresh/RefreshManagerDummy.cpp \ src/controller/refresh/RefreshManagerBankwise.cpp \ - src/controller/checker/CheckerWideIO.cpp + src/controller/checker/CheckerWideIO.cpp \ + src/configuration/memspec/MemSpecLPDDR4.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -153,7 +154,7 @@ HEADERS += \ src/simulation/Arbiter.h \ src/common/libDRAMPower.h \ src/simulation/ReorderBuffer.h \ - src/configuration/MemSpec.h \ + src/configuration/memspec/MemSpec.h \ src/simulation/StlPlayer.h \ src/simulation/TracePlayerListener.h \ src/simulation/TraceGenerator.h \ @@ -202,7 +203,11 @@ HEADERS += \ src/controller/refresh/RefreshManager.h \ src/controller/refresh/RefreshManagerDummy.h \ src/controller/refresh/RefreshManagerBankwise.h \ - src/controller/checker/CheckerWideIO.h + src/controller/checker/CheckerWideIO.h \ + src/configuration/memspec/MemSpecDDR3.h \ + src/configuration/memspec/MemSpecWideIO.h \ + src/configuration/memspec/MemSpecDDR4.h \ + src/configuration/memspec/MemSpecLPDDR4.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/common/timingCalculations.cpp b/DRAMSys/library/src/common/timingCalculations.cpp index ddf06098..be69fb44 100644 --- a/DRAMSys/library/src/common/timingCalculations.cpp +++ b/DRAMSys/library/src/common/timingCalculations.cpp @@ -35,7 +35,7 @@ */ #include "timingCalculations.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpec.h" #include "DebugManager.h" #include "../configuration/Configuration.h" #include "utils.h" diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index 9802b58e..e8fb6bc6 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -42,7 +42,7 @@ #include #include #include -#include "MemSpec.h" +#include "memspec/MemSpec.h" #include "TemperatureSimConfig.h" #include "../common/utils.h" diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 71ae8b25..d003def8 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -36,7 +36,11 @@ */ #include "ConfigurationLoader.h" -#include "MemSpec.h" +#include "memspec/MemSpec.h" +#include "memspec/MemSpecDDR3.h" +#include "memspec/MemSpecDDR4.h" +#include "memspec/MemSpecWideIO.h" +#include "memspec/MemSpecLPDDR4.h" #include "../common/timingCalculations.h" using namespace tinyxml2; @@ -189,7 +193,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); memSpec->clk = FrequencyToClk(memSpec->clkMHz); sc_time clk = memSpec->clk; - memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); @@ -236,6 +239,7 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tRP = clk * queryUIntParameter(timings, "RP"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); @@ -279,6 +283,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L"); memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S"); memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L"); + memSpec->tAL = clk * queryUIntParameter(timings, "AL"); memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); diff --git a/DRAMSys/library/src/configuration/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp similarity index 77% rename from DRAMSys/library/src/configuration/MemSpec.cpp rename to DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 891252d2..83b32a7f 100644 --- a/DRAMSys/library/src/configuration/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -37,8 +37,8 @@ #include #include -#include "../controller/Command.h" -#include "Configuration.h" +#include "../../controller/Command.h" +#include "../Configuration.h" using namespace tlm; @@ -78,7 +78,6 @@ sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const { - // TODO: implement this function for different memspecs, add AL for DDR3 if (command == Command::RD || command == Command::RDA) return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); else if (command == Command::WR || command == Command::WRA) @@ -91,7 +90,6 @@ TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const } // Returns the execution time for commands that have a fixed execution time -// TODO: override this method for different MemSpecs? sc_time MemSpec::getExecutionTime(Command command) const { if (command == Command::PRE || command == Command::PREA) @@ -101,6 +99,7 @@ sc_time MemSpec::getExecutionTime(Command command) const else if (command == Command::RD) return tRL + getReadAccessTime(); else if (command == Command::RDA) + // this time is wrong (controller internally waits for tRAS) return tRTP + tRP; else if (command == Command::WR) return tWL + getWriteAccessTime(); @@ -119,33 +118,3 @@ sc_time MemSpec::getExecutionTime(Command command) const return SC_ZERO_TIME; } } - -sc_time MemSpecLPDDR4::getExecutionTime(Command command) const -{ - if (command == Command::PRE) - return tRP; - else if (command == Command::PREA) - return tRPAB; - else if (command == Command::ACT) - return tRCD; - else if (command == Command::RD) - return tRL + getReadAccessTime(); - else if (command == Command::RDA) - return tRTP + tRP; - else if (command == Command::WR) - return tWL + getWriteAccessTime(); - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; - else if (command == Command::REFA) - return tRFC; - else if (command == Command::REFB) - return tRFCPB; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } -} diff --git a/DRAMSys/library/src/configuration/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h similarity index 69% rename from DRAMSys/library/src/configuration/MemSpec.h rename to DRAMSys/library/src/configuration/memspec/MemSpec.h index 6d277e5a..f053be72 100644 --- a/DRAMSys/library/src/configuration/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -40,9 +40,9 @@ #include #include -#include "../common/dramExtensions.h" -#include "../controller/Command.h" -#include "../common/utils.h" +#include "../../common/dramExtensions.h" +#include "../../controller/Command.h" +#include "../../common/utils.h" using namespace tlm; @@ -91,7 +91,6 @@ struct MemSpec sc_time tRFC; sc_time tRP; // only used in DRAMPower - sc_time tAL; // additive delay (delayed execution in dram) sc_time tDQSCK; // Currents and Voltages: @@ -104,10 +103,7 @@ struct MemSpec double iDD6; double vDD; - // For different refresh frequencies on different banks, not implemented - //std::map refreshTimings; - - // Command lengths on bus: + // Command lengths on bus, standardly one clock cycle: unsigned clACT = 1; unsigned clPRE = 1; unsigned clPREA = 1; @@ -127,90 +123,5 @@ struct MemSpec virtual ~MemSpec() {} }; -struct MemSpecDDR3 : public MemSpec -{ - sc_time tCCD; - sc_time tFAW; - sc_time tRRD; - sc_time tWTR; - sc_time tXPDLL; - sc_time tXSDLL; - - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; -}; - -struct MemSpecDDR4 : public MemSpec -{ - sc_time tCCD_S; - sc_time tCCD_L; - sc_time tFAW; - sc_time tRRD_S; - sc_time tRRD_L; - sc_time tWTR_S; - sc_time tWTR_L; - sc_time tXPDLL; - sc_time tXSDLL; - - double iDD02; - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; - double iDD62; - double vDD2; -}; - -struct MemSpecLPDDR4 : public MemSpec -{ - sc_time tCCD; - sc_time tCCDMW; - sc_time tESCKE; - sc_time tFAW; - sc_time tWTR; - sc_time tPPD; - sc_time tREFIPB; - sc_time tRFCPB; - sc_time tRPAB; - sc_time tRRD; - - double iDD02; - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; - double iDD62; - double vDD2; - - virtual sc_time getExecutionTime(Command) const override; -}; - -struct MemSpecWideIO : public MemSpec -{ - sc_time tCCD; - sc_time tRRD; - sc_time tTAW; - sc_time tWTR; - - double iDD02; - double iDD2P0; - double iDD2P02; - double iDD2P1; - double iDD2P12; - double iDD2N2; - double iDD3P0; - double iDD3P02; - double iDD3P1; - double iDD3P12; - double iDD3N2; - double iDD4R2; - double iDD4W2; - double iDD52; - double iDD62; - double vDD2; -}; - #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h new file mode 100644 index 00000000..4589288a --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECDDR3_H +#define MEMSPECDDR3_H + +#include "MemSpec.h" + +struct MemSpecDDR3 : public MemSpec +{ + sc_time tCCD; + sc_time tFAW; + sc_time tRRD; + sc_time tWTR; + sc_time tXPDLL; + sc_time tXSDLL; + sc_time tAL; + + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; +}; + +#endif // MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h new file mode 100644 index 00000000..5df15101 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECDDR4_H +#define MEMSPECDDR4_H + +#include "MemSpec.h" + +struct MemSpecDDR4 : public MemSpec +{ + sc_time tCCD_S; + sc_time tCCD_L; + sc_time tFAW; + sc_time tRRD_S; + sc_time tRRD_L; + sc_time tWTR_S; + sc_time tWTR_L; + sc_time tAL; + sc_time tXPDLL; + sc_time tXSDLL; + + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; +}; + +#endif // MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp new file mode 100644 index 00000000..5bfeeef6 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecLPDDR4.h" + +sc_time MemSpecLPDDR4::getExecutionTime(Command command) const +{ + if (command == Command::PRE) + return tRP; + else if (command == Command::PREA) + return tRPAB; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD) + return tRL + getReadAccessTime(); + else if (command == Command::RDA) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFCPB; + else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) + return clk; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h new file mode 100644 index 00000000..cbb86823 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECLPDDR4_H +#define MEMSPECLPDDR4_H + +#include "MemSpec.h" + +struct MemSpecLPDDR4 : public MemSpec +{ + sc_time tCCD; + sc_time tCCDMW; + sc_time tESCKE; + sc_time tFAW; + sc_time tWTR; + sc_time tPPD; + sc_time tREFIPB; + sc_time tRFCPB; + sc_time tRPAB; + sc_time tRRD; + + double iDD02; + double iDD2P0; + double iDD2P1; + double iDD3P0; + double iDD3P1; + double iDD62; + double vDD2; + + virtual sc_time getExecutionTime(Command) const override; +}; + +#endif // MEMSPECLPDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h new file mode 100644 index 00000000..fd9f1cc5 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECWIDEIO_H +#define MEMSPECWIDEIO_H + +#include "MemSpec.h" + +struct MemSpecWideIO : public MemSpec +{ + sc_time tCCD; + sc_time tRRD; + sc_time tTAW; + sc_time tWTR; + + double iDD02; + double iDD2P0; + double iDD2P02; + double iDD2P1; + double iDD2P12; + double iDD2N2; + double iDD3P0; + double iDD3P02; + double iDD3P1; + double iDD3P12; + double iDD3N2; + double iDD4R2; + double iDD4W2; + double iDD52; + double iDD62; + double vDD2; +}; + +#endif // MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index b3632ba4..45043c94 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -38,7 +38,7 @@ #include "CheckerIF.h" #include #include -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpecDDR3.h" #include "../../configuration/Configuration.h" class RefreshCheckerDDR3Dummy; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index cddbe9f5..db22f8f7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -38,7 +38,7 @@ #include "CheckerIF.h" #include #include -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpecWideIO.h" #include "../../configuration/Configuration.h" class RefreshCheckerWideIODummy; diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp index e26a56c0..c9950e9a 100644 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp @@ -38,7 +38,6 @@ #include "../../../common/timingCalculations.h" #include "../../../common/utils.h" #include "../../../configuration/Configuration.h" -//#include "../configuration/MemSpec.h" bool ScheduledCommand::isNoCommand() const { diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 9c424674..e18192b4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -36,7 +36,7 @@ #define REFRESHMANAGER_H #include "RefreshManagerIF.h" -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" using namespace tlm; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index c58d4595..b4a9c6da 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -36,7 +36,7 @@ #define REFRESHMANAGERBANKWISE_H #include "RefreshManagerIF.h" -#include "../../configuration/MemSpec.h" +#include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" #include #include diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/Dram.h index ea0a2822..7b1bf5e0 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/Dram.h @@ -45,7 +45,7 @@ #include #include "../common/protocol.h" #include "../configuration/Configuration.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpec.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 66d70e08..0f507b74 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -38,7 +38,7 @@ #include "Dram.h" #include "../configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpecDDR3.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 36caf370..f62eb99c 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -38,7 +38,7 @@ #include "Dram.h" #include "../configuration/Configuration.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpecDDR4.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 41f05077..98699d02 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -41,7 +41,7 @@ #include "../configuration/Configuration.h" #include "../error/errormodel.h" #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/MemSpec.h" +#include "../configuration/memspec/MemSpecWideIO.h" using namespace tlm; @@ -76,7 +76,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.RRDB = memSpec->tRRD / clk; memTimingSpec.RRDB_L = memSpec->tRRD / clk; memTimingSpec.RRDB_S = memSpec->tRRD / clk; - memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.AL = 0; memTimingSpec.CCD = memSpec->tCCD / clk; memTimingSpec.CCD_L = memSpec->tCCD / clk; memTimingSpec.CCD_S = memSpec->tCCD / clk; From 102b0667fd3443bffacc345a859eb9505ade1a8a Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 23 Sep 2019 20:07:00 +0200 Subject: [PATCH 105/183] Added bankgroups to address decoding. --- .../configs/amconfigs/am_ranktest.xml | 12 +++--- .../configs/mcconfigs/fifoStrict.xml | 2 +- .../configs/memspecs/memspec_ranktest.xml | 2 +- .../library/src/common/XmlAddressDecoder.cpp | 38 ++++++++++++------- .../library/src/common/XmlAddressDecoder.h | 3 ++ DRAMSys/library/src/common/utils.h | 2 +- 6 files changed, 37 insertions(+), 22 deletions(-) diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml index 11b68c5c..fc62b956 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml @@ -16,11 +16,11 @@ B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y --> - - - - - - + + + + + + diff --git a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml index 64b06284..1226d09a 100644 --- a/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml +++ b/DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml @@ -1,6 +1,6 @@ - + diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml index cd5852ec..6fc6b6be 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml @@ -5,7 +5,7 @@ - + diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 2da48e45..7b476781 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -79,6 +79,12 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) masks.rank = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); amount.rank = pow(2.0, to - from + 1.0); } + else if (std::strcmp(child->Name(), "bankgroup") == 0) + { + shifts.bankgroup = from; + masks.bankgroup = pow(2.0, to + 1.0) - pow(2.0, from + 0.0); + amount.bankgroup = pow(2.0, to - from + 1.0); + } else if (std::strcmp(child->Name(), "bank") == 0) { shifts.bank = from; @@ -107,10 +113,12 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) SC_REPORT_FATAL("XmlAddressDecoder", ("Unknown field " + std::string(child->Name())).c_str()); } - banksPerRank = amount.bank; - amount.bank = amount.bank * amount.rank; - amount.bankgroup = Configuration::getInstance().memSpec->NumberOfBankGroups; - banksPerGroup = amount.bank / amount.bankgroup; + banksPerGroup = amount.bank; + banksPerRank = banksPerGroup * amount.bankgroup; + amount.bank = banksPerRank * amount.rank; + + bankgroupsPerRank = amount.bankgroup; + amount.bankgroup = bankgroupsPerRank * amount.rank; } @@ -119,8 +127,10 @@ DecodedAddress XmlAddressDecoder::decodeAddress(uint64_t addr) DecodedAddress result; result.channel = (addr & masks.channel) >> shifts.channel; result.rank = (addr & masks.rank) >> shifts.rank; - result.bankgroup = result.bank / banksPerGroup; - result.bank = ((addr & masks.bank) >> shifts.bank) + result.rank * banksPerRank; + result.bankgroup = ((addr & masks.bankgroup) >> shifts.bankgroup) + + result.rank * bankgroupsPerRank; + result.bank = ((addr & masks.bank) >> shifts.bank) + + result.bankgroup * banksPerGroup; result.row = (addr & masks.row) >> shifts.row; result.column = (addr & masks.column) >> shifts.column; result.bytes = (addr & masks.bytes) >> shifts.bytes; @@ -131,7 +141,8 @@ uint64_t XmlAddressDecoder::encodeAddress(DecodedAddress n) { return (n.channel << shifts.channel) | (n.rank << shifts.rank) | - ((n.bank % banksPerRank) << shifts.bank) | + ((n.bankgroup % bankgroupsPerRank) << shifts.bankgroup) | + ((n.bank % banksPerGroup) << shifts.bank) | (n.row << shifts.row) | (n.column << shifts.column) | (n.bytes << shifts.bytes); @@ -153,11 +164,12 @@ void XmlAddressDecoder::print() { std::cout << headline << std::endl; std::cout << "Address Mapping:" << std::endl << std::endl; - std::cout << std::setw(10) << "channel: " << std::bitset<64>(masks.channel) << std::endl; - std::cout << std::setw(10) << "rank: " << std::bitset<64>(masks.rank) << std::endl; - std::cout << std::setw(10) << "bank: " << std::bitset<64>(masks.bank) << std::endl; - std::cout << std::setw(10) << "row: " << std::bitset<64>(masks.row) << std::endl; - std::cout << std::setw(10) << "column: " << std::bitset<64>(masks.column) << std::endl; - std::cout << std::setw(10) << "bytes: " << std::bitset<64>(masks.bytes) << std::endl; + std::cout << std::setw(11) << "channel: " << std::bitset<64>(masks.channel) << std::endl; + std::cout << std::setw(11) << "rank: " << std::bitset<64>(masks.rank) << std::endl; + std::cout << std::setw(11) << "bankgroup: " << std::bitset<64>(masks.bankgroup) << std::endl; + std::cout << std::setw(11) << "bank: " << std::bitset<64>(masks.bank) << std::endl; + std::cout << std::setw(11) << "row: " << std::bitset<64>(masks.row) << std::endl; + std::cout << std::setw(11) << "column: " << std::bitset<64>(masks.column) << std::endl; + std::cout << std::setw(11) << "bytes: " << std::bitset<64>(masks.bytes) << std::endl; std::cout << std::endl; } diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.h b/DRAMSys/library/src/common/XmlAddressDecoder.h index b0c848d7..85a9c0ca 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.h +++ b/DRAMSys/library/src/common/XmlAddressDecoder.h @@ -55,6 +55,7 @@ private: { uint64_t channel = 0; uint64_t rank = 0; + uint64_t bankgroup = 0; uint64_t bank = 0; uint64_t row = 0; uint64_t column = 0; @@ -65,6 +66,7 @@ private: { unsigned channel = 0; unsigned rank = 0; + unsigned bankgroup = 0; unsigned bank = 0; unsigned row = 0; unsigned column = 0; @@ -73,6 +75,7 @@ private: unsigned banksPerGroup; unsigned banksPerRank; + unsigned bankgroupsPerRank; tinyxml2::XMLElement *addressmapping; diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index e997d99a..9def2069 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -92,7 +92,7 @@ bool isIn(const T &value, const std::vector &collection) } constexpr const char headline[] = - "=========================================================================="; + "==========================================================================="; static inline void loadbar(unsigned int x, unsigned int n, From fc10f72773b19cc256f6b2b1d2aecac8eb962d6f Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 23 Sep 2019 22:16:56 +0200 Subject: [PATCH 106/183] Minor changes in address mapping and configuration. --- .../configs/amconfigs/am_ranktest.xml | 5 +- .../configs/memspecs/memspec_ranktest.xml | 4 +- .../library/src/common/XmlAddressDecoder.cpp | 12 +++- .../src/configuration/Configuration.cpp | 70 ++++++++++--------- .../src/configuration/ConfigurationLoader.cpp | 24 ++++--- DRAMSys/library/src/simulation/DRAMSys.cpp | 38 +++++----- 6 files changed, 81 insertions(+), 72 deletions(-) diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml index fc62b956..e0a858fe 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml @@ -16,9 +16,8 @@ B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y --> - - - + + diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml index 6fc6b6be..b4e43e4d 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.xml @@ -5,8 +5,8 @@ - - + + diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 7b476781..39d38d04 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -114,11 +114,19 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) } banksPerGroup = amount.bank; - banksPerRank = banksPerGroup * amount.bankgroup; - amount.bank = banksPerRank * amount.rank; + amount.bank = banksPerGroup * amount.bankgroup * amount.rank; bankgroupsPerRank = amount.bankgroup; amount.bankgroup = bankgroupsPerRank * amount.rank; + + Configuration &config = Configuration::getInstance(); + MemSpec *memSpec = config.memSpec; + + if (config.NumberOfMemChannels != amount.channel || memSpec->NumberOfRanks != amount.rank + || memSpec->NumberOfBankGroups != amount.bankgroup || memSpec->NumberOfBanks != amount.bank + || memSpec->NumberOfRows != amount.row || memSpec->NumberOfColumns != amount.column + || config.NumberOfDevicesOnDIMM * memSpec->bitWidth != amount.bytes * 8) + SC_REPORT_FATAL("XmlAddressDecoder", "Memspec and addressmapping do not match"); } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 0624ae55..5026d578 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -145,13 +145,14 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "Scheduler") Scheduler = value; else if (name == "SJFProbability") - if (string2int(value) > 100 || string2int(value) < 0) { + { + if (string2int(value) > 100 || string2int(value) < 0) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be between 0 and 100.").c_str()); - } else { + else SJFProbability = string2int(value); - } + } else if (name == "RequestBufferSize") RequestBufferSize = string2int(value); else if (name == "Capsize") @@ -175,36 +176,31 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "EnableWindowing") EnableWindowing = string2bool(value); else if (name == "WindowSize") - if (string2int(value) < 1) { + { + if (string2int(value) < 1) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); - } else + else WindowSize = string2int(value); + } else if (name == "Debug") Debug = string2bool(value); - else if (name == "NumberOfMemChannels") { + else if (name == "NumberOfMemChannels") NumberOfMemChannels = string2int(value); - unsigned int maxNumberofMemChannels = - AddressDecoder::getInstance().amount.channel; - if (NumberOfMemChannels > maxNumberofMemChannels) { - SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " - + name - + ". Value is out of range. The maximum value according to " - + "the address mapping configuration file is " - + std::to_string(maxNumberofMemChannels) + ".").c_str()); - } - } else if (name == "ControllerCoreRefDisable") + else if (name == "ControllerCoreRefDisable") ControllerCoreRefDisable = string2bool(value); else if (name == "ControllerCoreRGR") RowGranularRef = string2bool(value); else if (name == "ControllerCoreRGRRowInc") RowInc = string2int(value); - else if (name == "ControllerCoreRefMode") { + else if (name == "ControllerCoreRefMode") + { RefMode = string2int(value); if (RefMode != 1 && RefMode != 2 && RefMode != 4) SC_REPORT_FATAL("Configuration", (name + " invalid value.").c_str()); - } else if (name == "ControllerCoreRefNumARCmdsIntREFI") + } + else if (name == "ControllerCoreRefNumARCmdsIntREFI") NumAR = string2int(value); else if (name == "ControllerCoreRGRB0") RGRB0 = string2bool(value); @@ -240,11 +236,11 @@ void Configuration::setParameter(std::string name, std::string value) RGRB15 = string2bool(value); else if (name == "ControllerCoreRefForceMaxPostponeBurst") ControllerCoreRefForceMaxPostponeBurst = string2bool(value); - else if (name == "ControllerCoreRefEnablePostpone") { + else if (name == "ControllerCoreRefEnablePostpone") ControllerCoreRefEnablePostpone = string2bool(value); - } else if (name == "ControllerCoreRefEnablePullIn") { + else if (name == "ControllerCoreRefEnablePullIn") ControllerCoreRefEnablePullIn = string2bool(value); - } else if (name == "ControllerCoreRefMaxPostponed") + else if (name == "ControllerCoreRefMaxPostponed") ControllerCoreRefMaxPostponed = string2int(value); else if (name == "ControllerCoreRefMaxPulledIn") ControllerCoreRefMaxPulledIn = string2int(value); @@ -253,21 +249,25 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "SimulationProgressBar") SimulationProgressBar = string2bool(value); else if (name == "NumberOfDevicesOnDIMM") - if (string2int(value) < 1) { + { + if (string2int(value) < 1) SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str()); - } else + else NumberOfDevicesOnDIMM = string2int(value); - else if (name == "AddressOffset") { + } + else if (name == "AddressOffset") + { #ifdef DRAMSYS_GEM5 AddressOffset = string2ull(value); #else AddressOffset = 0; #endif - } else if (name == "UseMalloc") { + } + else if (name == "UseMalloc") UseMalloc = string2bool(value); - } else if (name == "CheckTLM2Protocol") + else if (name == "CheckTLM2Protocol") CheckTLM2Protocol = string2bool(value); else if (name == "ECCControllerMode") ECCMode = string2ECCControllerMode(value); @@ -279,22 +279,25 @@ void Configuration::setParameter(std::string name, std::string value) else if (name == "StoreMode") StoreMode = string2StoreMode(value); // Temperature Simulation related - else if (name == "TemperatureScale") { - if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") { + else if (name == "TemperatureScale") + { + if (value != "Celsius" && value != "Fahrenheit" && value != "Kelvin") SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ".").c_str()); - } temperatureSim.TemperatureScale = value; - } else if (name == "StaticTemperatureDefaultValue") + } + else if (name == "StaticTemperatureDefaultValue") temperatureSim.StaticTemperatureDefaultValue = string2int(value); else if (name == "ThermalSimPeriod") temperatureSim.ThermalSimPeriod = std::stod(value.c_str()); else if (name == "ThermalSimUnit") temperatureSim.ThermalSimUnit = string2TimeUnit(value); - else if (name == "PowerInfoFile") { + else if (name == "PowerInfoFile") + { temperatureSim.powerInfoFile = value; temperatureSim.parsePowerInfoFile(); - } else if (name == "IceServerIp") + } + else if (name == "IceServerIp") temperatureSim.IceServerIp = value; else if (name == "IceServerPort") temperatureSim.IceServerPort = string2int(value); @@ -306,10 +309,9 @@ void Configuration::setParameter(std::string name, std::string value) temperatureSim.GenerateTemperatureMap = string2bool(value); else if (name == "GeneratePowerMap") temperatureSim.GeneratePowerMap = string2bool(value); - else { + else SC_REPORT_FATAL("Configuration", ("Parameter " + name + " not defined in Configuration").c_str()); - } } void Configuration::setPathToResources(std::string path) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index d003def8..de402431 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -181,7 +181,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); @@ -227,7 +226,8 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = 1; + memSpec->NumberOfBankGroups = memSpec->NumberOfRanks; + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -260,7 +260,8 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups") * memSpec->NumberOfRanks; + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -308,7 +309,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture: XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = 1; + memSpec->NumberOfBankGroups = memSpec->NumberOfRanks; + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -338,18 +340,20 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } -void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) +void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) { MemSpecWideIO *memSpec = dynamic_cast(config.memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); - // MemSpecification - memSpec->NumberOfRanks = 1; - memSpec->NumberOfBankGroups = 1; + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->NumberOfBankGroups = memSpec->NumberOfRanks; + memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; // MemTimings specific for WideIO - XMLElement *timings = memspec->FirstChildElement("memtimingspec"); + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); @@ -360,7 +364,7 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); // Currents and Volatages: - XMLElement *powers = memspec->FirstChildElement("mempowerspec"); + XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index dcae5552..21ce0f0b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -87,16 +87,28 @@ DRAMSys::DRAMSys(sc_module_name name, Configuration::getInstance().setPathToResources(pathToResources); - // MemSpec must be initialized first because AddressDecoder needs - // the number of bankgroups + // Load config and initialize modules ConfigurationLoader::loadMemSpec(Configuration::getInstance(), pathToResources + "configs/memspecs/" + memspec); - // The xmlAddressDecoder MUST be initialized before calling the - // ConfigurationLoader because some information from the xmlAddressDecoder - // is needed to assure the coherence of the configuration. + ConfigurationLoader::loadMCConfig(Configuration::getInstance(), + pathToResources + + "configs/mcconfigs/" + + mcconfig); + + ConfigurationLoader::loadSimConfig(Configuration::getInstance(), + pathToResources + + "configs/simulator/" + + simconfig); + + ConfigurationLoader::loadTemperatureSimConfig(Configuration::getInstance(), + pathToResources + + "configs/thermalsim/" + + thermalconfig); + + // Load addressmapping if (XmlAddressDecoder::testConfigFile(pathToResources + "configs/amconfigs/" + amconfig)) { AddressDecoder::createInstance(AddressDecoder::Type::XML); @@ -115,22 +127,6 @@ DRAMSys::DRAMSys(sc_module_name name, AddressDecoder::getInstance().print(); - // Setup rest of the memory controller with the propriate xml file - ConfigurationLoader::loadMCConfig(Configuration::getInstance(), - pathToResources - + "configs/mcconfigs/" - + mcconfig); - - ConfigurationLoader::loadSimConfig(Configuration::getInstance(), - pathToResources - + "configs/simulator/" - + simconfig); - - ConfigurationLoader::loadTemperatureSimConfig(Configuration::getInstance(), - pathToResources - + "configs/thermalsim/" - + thermalconfig); - // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. std::string simName; From 805490d05c21d23437ba81a1db4252d13ee298c8 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 24 Sep 2019 14:14:56 +0200 Subject: [PATCH 107/183] Correction of address mappings. --- DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml | 1 - .../resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml | 1 - .../configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml | 1 - .../configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml | 1 - .../configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml | 1 - .../configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml | 1 - .../configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml | 1 - .../configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml | 1 - DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml | 1 - DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml | 1 - .../configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml | 1 - DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml | 1 - DRAMSys/library/resources/configs/amconfigs/rgram.xml | 1 - 13 files changed, 13 deletions(-) diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml index 497a2388..8d73c4c5 100755 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml @@ -1,5 +1,4 @@ - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml index a508caa7..7b392322 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml @@ -14,7 +14,6 @@ B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml index 2422faf3..886385fe 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml @@ -26,7 +26,6 @@ --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml index 7ba3e518..48f2962a 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml @@ -26,7 +26,6 @@ --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml index 39d66692..5500c9ae 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml @@ -16,7 +16,6 @@ B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml index 46cb5158..fb4d44ed 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml @@ -16,7 +16,6 @@ R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml index 6f384970..0106b60d 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml @@ -16,7 +16,6 @@ B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml index 7f9e64fe..c87cdd44 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml @@ -16,7 +16,6 @@ R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml index dfddfbc9..66341554 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml @@ -1,5 +1,4 @@ - diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml index 8323d7b5..cb042a68 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml @@ -1,5 +1,4 @@ - diff --git a/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml index b387e522..a4d04ebe 100644 --- a/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml @@ -11,7 +11,6 @@ --> - diff --git a/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml b/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml index 689aad68..c616ec0c 100644 --- a/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml @@ -1,5 +1,4 @@ - diff --git a/DRAMSys/library/resources/configs/amconfigs/rgram.xml b/DRAMSys/library/resources/configs/amconfigs/rgram.xml index b5e85906..82e8bea2 100644 --- a/DRAMSys/library/resources/configs/amconfigs/rgram.xml +++ b/DRAMSys/library/resources/configs/amconfigs/rgram.xml @@ -1,5 +1,4 @@ - From 149bfee201040acf94854fb40a7c012194d40060 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 24 Sep 2019 15:16:09 +0200 Subject: [PATCH 108/183] Corrected refresh mode (1x, 2x and 4x) for DDR4. --- .../src/configuration/ConfigurationLoader.cpp | 10 +++++++- DRAMSys/traceAnalyzer/scripts/tests.py | 24 +++++++++---------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index de402431..91967821 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -269,14 +269,22 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); unsigned refMode = Configuration::getInstance().getRefMode(); if (refMode == 1) + { + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + } else if (refMode == 2) + { + memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2"); + } else if (refMode == 4) + { + memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4"); + } else SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index 7b874c6b..c82dbc81 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -39,9 +39,7 @@ class DramConfig(object): tXS = 0 # min delay to row access command after srefx tXSDLL = 0 # min delay to row access command after srefx for dll commands tAL = 0 # additive delay (delayed execution in dram) - tRFC = 0 # min ref->act delay 1X - tRFC2 = 0 # min ref->act delay 2X - tRFC4 = 0 # min ref->act delay 4X + tRFC = 0 # min ref->act delay tREFI = 0 # time between REF commands def readConfigFromFiles(self, connection): @@ -114,10 +112,15 @@ class DramConfig(object): self.tXS = self.clk * memspec.getIntValue("XS") self.tXSDLL = self.clk * memspec.getIntValue("XSDLL") self.tAL = self.clk * memspec.getIntValue("AL") - self.tRFC = self.clk * memspec.getIntValue("RFC") - self.tRFC2 = self.clk * memspec.getIntValue("RFC2") - self.tRFC4 = self.clk * memspec.getIntValue("RFC4") - self.tREFI = self.clk * memspec.getIntValue("REFI") + if (self.refMode == "4"): + self.tRFC = self.clk * memspec.getIntValue("RFC4") + self.tREFI = self.clk * (memspec.getIntValue("REFI") / 4) + elif (self.refMode == "2"): + self.tRFC = self.clk * memspec.getIntValue("RFC2") + self.tREFI = self.clk * (memspec.getIntValue("REFI") / 2) + else: + self.tRFC = self.clk * memspec.getIntValue("RFC") + self.tREFI = self.clk * memspec.getIntValue("REFI") elif (self. memoryType == "DDR3"): self.nActivateWindow = 4 @@ -358,12 +361,7 @@ def timing_constraint(FirstPhase, SecondPhase): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR + dramconfig.clk elif (FirstPhaseName == "REFA"): - if dramconfig.refMode == "4": - return dramconfig.tRFC4 - elif dramconfig.refMode == "2": - return dramconfig.tRFC2 - else: - return dramconfig.tRFC + return dramconfig.tRFC elif (FirstPhaseName in ["PDNA", "PDNP"]): # print("{0}".format(FirstPhaseName)) From 2690755024399f98d7198fb3f7e039c48c80744f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 24 Sep 2019 15:17:25 +0200 Subject: [PATCH 109/183] Included JEDEC based memspecs, address mapping and simulation for DDR4. --- .../am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml | 7 ++ .../memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml | 64 +++++++++++++++++++ .../memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml | 64 +++++++++++++++++++ .../resources/configs/simulator/ddr4.xml | 29 +++++++++ .../resources/simulations/ddr4-example.xml | 25 ++++++++ 5 files changed, 189 insertions(+) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml create mode 100644 DRAMSys/library/resources/configs/simulator/ddr4.xml create mode 100644 DRAMSys/library/resources/simulations/ddr4-example.xml diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml new file mode 100644 index 00000000..83fa9e4c --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml new file mode 100644 index 00000000..d4801b92 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml new file mode 100644 index 00000000..49b10280 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.xml b/DRAMSys/library/resources/configs/simulator/ddr4.xml new file mode 100644 index 00000000..8975c326 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr4.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/ddr4-example.xml b/DRAMSys/library/resources/simulations/ddr4-example.xml new file mode 100644 index 00000000..0d0606db --- /dev/null +++ b/DRAMSys/library/resources/simulations/ddr4-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + From cfbce483bd50ed015f4936f90b0949dece9b6725 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 24 Sep 2019 15:18:37 +0200 Subject: [PATCH 110/183] Included timing checker for DDR4. --- DRAMSys/library/library.pro | 6 +- DRAMSys/library/src/controller/Controller.cpp | 5 +- .../src/controller/checker/CheckerDDR3.cpp | 5 +- .../src/controller/checker/CheckerDDR3.h | 7 +- .../src/controller/checker/CheckerDDR4.cpp | 304 ++++++++++++++++++ .../src/controller/checker/CheckerDDR4.h | 127 ++++++++ .../src/controller/checker/CheckerIF.h | 8 +- .../src/controller/checker/CheckerWideIO.cpp | 5 +- .../src/controller/checker/CheckerWideIO.h | 7 +- 9 files changed, 456 insertions(+), 18 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerDDR4.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerDDR4.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 3bc74e25..5c0df5d3 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -135,7 +135,8 @@ SOURCES += \ src/controller/refresh/RefreshManagerDummy.cpp \ src/controller/refresh/RefreshManagerBankwise.cpp \ src/controller/checker/CheckerWideIO.cpp \ - src/configuration/memspec/MemSpecLPDDR4.cpp + src/configuration/memspec/MemSpecLPDDR4.cpp \ + src/controller/checker/CheckerDDR4.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -207,7 +208,8 @@ HEADERS += \ src/configuration/memspec/MemSpecDDR3.h \ src/configuration/memspec/MemSpecWideIO.h \ src/configuration/memspec/MemSpecDDR4.h \ - src/configuration/memspec/MemSpecLPDDR4.h + src/configuration/memspec/MemSpecLPDDR4.h \ + src/controller/checker/CheckerDDR4.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 335fa01b..cc50efd3 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -42,6 +42,7 @@ #include "../common/dramExtensions.h" #include "../common/protocol.h" #include "checker/CheckerDDR3.h" +#include "checker/CheckerDDR4.h" #include "checker/CheckerWideIO.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" @@ -59,6 +60,8 @@ Controller::Controller(sc_module_name name) : if (config.memSpec->MemoryType == "DDR3") checker = new CheckerDDR3(); + else if (config.memSpec->MemoryType == "DDR4") + checker = new CheckerDDR4(); else if (config.memSpec->MemoryType == "WIDEIO_SDR") checker = new CheckerWideIO(); else @@ -288,7 +291,7 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) void Controller::sendToDram(Command command, tlm_generic_payload *payload) { DramExtension extension = DramExtension::getExtension(payload); - checker->insert(command, extension.getRank(), extension.getBank()); + checker->insert(command, extension.getRank(), extension.getBankGroup(), extension.getBank()); sc_time delay = SC_ZERO_TIME; tlm_phase phase; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 38da02a6..e1c85404 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -168,13 +168,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG reportFatal("CheckerDDR3", "Unknown command!"); } // Check if command bus is free - //if (lastScheduled.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); return (earliestTimeToStart - sc_time_stamp()); } -void CheckerDDR3::insert(Command command, Rank rank, Bank bank) +void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) { PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + bank.ID() + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 45043c94..169f5878 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -49,11 +49,16 @@ public: CheckerDDR3(); ~CheckerDDR3(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; - void insert(Command, Rank, Bank); + void insert(Command, Rank, BankGroup, Bank); private: const MemSpecDDR3 *memSpec; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastScheduled; + // Four activate window std::vector> lastActivates; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp new file mode 100644 index 00000000..f35bd770 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerDDR4.h" + +CheckerDDR4::CheckerDDR4() +{ + Configuration config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); + + if (config.ControllerCoreRefDisable) + refreshChecker = new RefreshCheckerDDR4Dummy(memSpec); + else if (config.BankwiseLogic) + refreshChecker = new RefreshCheckerDDR4Bankwise(memSpec); + else + refreshChecker = new RefreshCheckerDDR4(memSpec); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndBankGroup = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); + + burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; +} + +CheckerDDR4::~CheckerDDR4() +{ + delete refreshChecker; +} + +sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +{ + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_S); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + if (lastActivates[rank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + + refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWTR_L); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWTR_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWTR_L); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWTR_S); + + refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + + burstClocks + 2 * memSpec->clk - memSpec->tWL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + + burstClocks + 2 * memSpec->clk - memSpec->tWL); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); + + refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWR); + + refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + } + else + { + reportFatal("CheckerDDR4", "Unknown command!"); + } + // Check if command bus is free + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastScheduled = sc_time_stamp(); + + if (command == Command::ACT) + { + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); + } + else if (command == Command::REFA || command == Command::REFB) + refreshChecker->insert(bank); +} + +// TODO: max(earliestTimeToStart, ...) needed? +void RefreshCheckerDDR4::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerDDR4::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerDDR4::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - burstClocks - memSpec->tWR)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerDDR4::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= timeForNextPREA) + earliestTimeToStart = timeForNextREFA + memSpec->tRFC; +} + +void RefreshCheckerDDR4::insert(Bank) +{ + timeForNextREFA += memSpec->tREFI; + timeForNextPREA += memSpec->tREFI; +} + +RefreshCheckerDDR4Bankwise::RefreshCheckerDDR4Bankwise(const MemSpecDDR4 *memSpec) + : RefreshCheckerDDR4Dummy(memSpec) +{ + sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + { + timesForNextREFB.push_back(currentREFB); + timesForNextPRE.push_back(currentPRE); + currentREFB += memSpec->clk; + currentPRE += memSpec->clk; + } +} + +void RefreshCheckerDDR4Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; +} + +void RefreshCheckerDDR4Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; +} + +void RefreshCheckerDDR4Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - burstClocks - memSpec->tWR)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; +} + +void RefreshCheckerDDR4Bankwise::insert(Bank bank) +{ + timesForNextREFB[bank.ID()] += memSpec->tREFI; + timesForNextPRE[bank.ID()] += memSpec->tREFI; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h new file mode 100644 index 00000000..581c4821 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERDDR4_H +#define CHECKERDDR4_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecDDR4.h" +#include "../../configuration/Configuration.h" + +class RefreshCheckerDDR4Dummy; + +class CheckerDDR4 final : public CheckerIF +{ +public: + CheckerDDR4(); + ~CheckerDDR4(); + sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; + void insert(Command, Rank, BankGroup, Bank); + +private: + const MemSpecDDR4 *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastScheduled; + + // Four activate window + std::vector> lastActivates; + + RefreshCheckerDDR4Dummy *refreshChecker; + + sc_time burstClocks; + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; +}; + +class RefreshCheckerDDR4Dummy +{ +protected: + friend class CheckerDDR4; + RefreshCheckerDDR4Dummy(const MemSpecDDR4 *memSpec) : memSpec(memSpec) + { + burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; + } + virtual ~RefreshCheckerDDR4Dummy() {} + + virtual void delayToSatisfyACT(Bank, sc_time &) {} + virtual void delayToSatisfyRD(Bank, sc_time &) {} + virtual void delayToSatisfyWR(Bank, sc_time &) {} + virtual void delayToSatisfyPRE(Bank, sc_time &) {} + virtual void insert(Bank) {} + + const MemSpecDDR4 *memSpec; + + sc_time burstClocks; +}; + +class RefreshCheckerDDR4 final : public RefreshCheckerDDR4Dummy +{ +private: + friend class CheckerDDR4; + RefreshCheckerDDR4(const MemSpecDDR4 *memSpec) + : RefreshCheckerDDR4Dummy(memSpec) {} + + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void delayToSatisfyPRE(Bank, sc_time &); + void insert(Bank); + + sc_time timeForNextREFA = memSpec->tREFI; + sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; +}; + +class RefreshCheckerDDR4Bankwise final : public RefreshCheckerDDR4Dummy +{ +private: + friend class CheckerDDR4; + RefreshCheckerDDR4Bankwise(const MemSpecDDR4 *); + + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void insert(Bank); + + std::vector timesForNextREFB; + std::vector timesForNextPRE; +}; + +#endif // CHECKERDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index f01350fa..2fe47f2a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -47,13 +47,7 @@ public: virtual ~CheckerIF() {} virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; - virtual void insert(Command, Rank, Bank) = 0; - -protected: - std::vector> lastScheduledByCommandAndBank; - std::vector> lastScheduledByCommandAndRank; - std::vector lastScheduledByCommand; - sc_time lastScheduled; + virtual void insert(Command, Rank, BankGroup, Bank) = 0; // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 60901022..895bbcb2 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -152,13 +152,12 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban reportFatal("CheckerWideIO", "Unknown command!"); } // Check if command bus is free - //if (lastScheduled.isValidCommand()) - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); return (earliestTimeToStart - sc_time_stamp()); } -void CheckerWideIO::insert(Command command, Rank rank, Bank bank) +void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) { PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + bank.ID() + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index db22f8f7..58fb4560 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -49,11 +49,16 @@ public: CheckerWideIO(); ~CheckerWideIO(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; - void insert(Command, Rank, Bank); + void insert(Command, Rank, BankGroup, Bank); private: const MemSpecWideIO *memSpec; + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastScheduled; + // Four activate window std::vector> lastActivates; From 47949922f3a0ff6352ec25386de0fb4b80c2b0b0 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 26 Sep 2019 13:26:17 +0200 Subject: [PATCH 111/183] Included LPDDR4 memspec. --- .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml | 98 +++++++++++++++++++ .../configuration/memspec/MemSpecLPDDR4.cpp | 15 +++ .../src/configuration/memspec/MemSpecLPDDR4.h | 3 +- 3 files changed, 115 insertions(+), 1 deletion(-) create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml new file mode 100644 index 00000000..3dddacb7 --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 5bfeeef6..c6a37e7e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -65,3 +65,18 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command) const } } +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tDQSCK /*+ DQSQ*/, + sc_time_stamp() + tRL + tDQSCK /*+ DQSQ*/ + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL /*+ tDQSS + tDQS2DQ*/, + sc_time_stamp() + tWL /*+ tDQSS + tDQS2DQ*/ + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); + return TimeInterval(); + } +} + diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index cbb86823..65b857c2 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -59,7 +59,8 @@ struct MemSpecLPDDR4 : public MemSpec double iDD62; double vDD2; - virtual sc_time getExecutionTime(Command) const override; + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECLPDDR4_H From 8b7760a585ac4d25f00c0afd149e80163a99c476 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 26 Sep 2019 16:49:40 +0200 Subject: [PATCH 112/183] LPDDR4 address mapping and memspec. --- .../configs/amconfigs/am_lpddr4_8Gbx16_brc.xml | 6 ++++++ .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml | 16 +++++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml new file mode 100644 index 00000000..efaf9f9b --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml index 3dddacb7..75a2cf67 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml @@ -18,8 +18,6 @@ - - @@ -27,20 +25,24 @@ - - - - + + + + + + + + + - From 4950a2587e63f901d57881fc7d21c8bdeca839a4 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 26 Sep 2019 16:55:20 +0200 Subject: [PATCH 113/183] Included LPDDR4 memspec and Dram, changed structure of MemSpec.h, removed ScheduledCommand. --- DRAMSys/library/library.pro | 11 +- .../src/configuration/ConfigurationLoader.cpp | 88 ++++++++--- .../src/configuration/memspec/MemSpec.cpp | 69 ++------- .../src/configuration/memspec/MemSpec.h | 31 +--- .../src/configuration/memspec/MemSpecDDR3.cpp | 88 +++++++++++ .../src/configuration/memspec/MemSpecDDR3.h | 22 +++ .../src/configuration/memspec/MemSpecDDR4.cpp | 88 +++++++++++ .../src/configuration/memspec/MemSpecDDR4.h | 22 +++ .../configuration/memspec/MemSpecLPDDR4.cpp | 53 +++++-- .../src/configuration/memspec/MemSpecLPDDR4.h | 40 ++++- .../configuration/memspec/MemSpecWideIO.cpp | 88 +++++++++++ .../src/configuration/memspec/MemSpecWideIO.h | 22 +++ .../core/scheduling/ScheduledCommand.cpp | 145 ------------------ .../core/scheduling/ScheduledCommand.h | 95 ------------ .../src/controller/refresh/RefreshManager.cpp | 4 +- .../refresh/RefreshManagerBankwise.cpp | 6 +- DRAMSys/library/src/simulation/DramLPDDR4.cpp | 56 +++++++ DRAMSys/library/src/simulation/DramLPDDR4.h | 51 ++++++ 18 files changed, 603 insertions(+), 376 deletions(-) create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp delete mode 100644 DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h create mode 100644 DRAMSys/library/src/simulation/DramLPDDR4.cpp create mode 100644 DRAMSys/library/src/simulation/DramLPDDR4.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 5c0df5d3..095f0c77 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -93,7 +93,6 @@ SOURCES += \ src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ src/controller/core/powerdown/PowerDownManagerBankwise.cpp \ src/controller/core/powerdown/PowerDownManager.cpp \ - src/controller/core/scheduling/ScheduledCommand.cpp \ src/simulation/MemoryManager.cpp \ src/simulation/TemperatureController.cpp \ src/configuration/ConfigurationLoader.cpp \ @@ -135,8 +134,12 @@ SOURCES += \ src/controller/refresh/RefreshManagerDummy.cpp \ src/controller/refresh/RefreshManagerBankwise.cpp \ src/controller/checker/CheckerWideIO.cpp \ + src/configuration/memspec/MemSpecDDR3.cpp \ + src/configuration/memspec/MemSpecDDR4.cpp \ + src/configuration/memspec/MemSpecWideIO.cpp \ src/configuration/memspec/MemSpecLPDDR4.cpp \ - src/controller/checker/CheckerDDR4.cpp + src/controller/checker/CheckerDDR4.cpp \ + src/simulation/DramLPDDR4.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -148,7 +151,6 @@ HEADERS += \ src/controller/core/powerdown/PowerDownManagerTimeout.h \ src/controller/core/powerdown/PowerDownManagerBankwise.h \ src/controller/core/powerdown/PowerDownManager.h \ - src/controller/core/scheduling/ScheduledCommand.h \ src/simulation/TracePlayer.h \ src/simulation/MemoryManager.h \ src/simulation/Dram.h \ @@ -209,7 +211,8 @@ HEADERS += \ src/configuration/memspec/MemSpecWideIO.h \ src/configuration/memspec/MemSpecDDR4.h \ src/configuration/memspec/MemSpecLPDDR4.h \ - src/controller/checker/CheckerDDR4.h + src/controller/checker/CheckerDDR4.h \ + src/simulation/DramLPDDR4.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 91967821..e21b9552 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -187,23 +187,10 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec memSpec->NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); memSpec->bitWidth = queryUIntParameter(architecture, "width"); - // MemTimings + // Clock XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); memSpec->clk = FrequencyToClk(memSpec->clkMHz); - sc_time clk = memSpec->clk; - memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); - memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); - memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); - memSpec->tRC = clk * queryUIntParameter(timings, "RC"); - memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); - memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); - memSpec->tWL = clk * queryUIntParameter(timings, "WL"); - memSpec->tWR = clk * queryUIntParameter(timings, "WR"); - memSpec->tXP = clk * queryUIntParameter(timings, "XP"); - memSpec->tXS = clk * queryUIntParameter(timings, "XS"); // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -232,6 +219,18 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); @@ -266,6 +265,18 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S"); memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L"); memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); @@ -323,19 +334,34 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); - memSpec->tCCDMW = clk * queryUIntParameter(timings, "CCDMW"); - memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); - memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); - memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB"); + memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB"); memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); - memSpec->tREFI = clk * queryUIntParameter(timings, "REFIAB"); - memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); - memSpec->tRFC = clk * queryUIntParameter(timings, "RFCAB"); - memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); - memSpec->tRPAB = clk * queryUIntParameter(timings, "RPAB"); - memSpec->tRP = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRPST = clk * queryUIntParameter(timings, "RPST"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS"); + memSpec->tDQS2DQ = clk * queryUIntParameter(timings, "DQS2DQ"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWPRE = clk * queryUIntParameter(timings, "WPRE"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tSR = clk * queryUIntParameter(timings, "SR"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XSR"); + memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE"); // Currents and Volatages: XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); @@ -363,6 +389,18 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); sc_time clk = memSpec->clk; + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 83b32a7f..1dd1c790 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -62,59 +62,16 @@ sc_time MemSpec::getWriteAccessTime() const return clk * (BurstLength / DataRate); } -sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const -{ - if (command == Command::PDEA || command == Command::PDEP) - return tCKE; - else if (command == Command::SREFEN) - return tCKESR; - else - { - SC_REPORT_FATAL("getMinimalExecutionTime", - "command is not know or command has a fixed execution time"); - return SC_ZERO_TIME; - } -} - -TimeInterval MemSpec::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - -// Returns the execution time for commands that have a fixed execution time -sc_time MemSpec::getExecutionTime(Command command) const -{ - if (command == Command::PRE || command == Command::PREA) - return tRP; - else if (command == Command::ACT) - return tRCD; - else if (command == Command::RD) - return tRL + getReadAccessTime(); - else if (command == Command::RDA) - // this time is wrong (controller internally waits for tRAS) - return tRTP + tRP; - else if (command == Command::WR) - return tWL + getWriteAccessTime(); - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; - else if (command == Command::REFA) - return tRFC; - else if (command == Command::REFB) - return tRFC; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; - else - { - SC_REPORT_FATAL("getExecutionTime", - "command not known or command doesn't have a fixed execution time"); - return SC_ZERO_TIME; - } -} +//sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const +//{ +// if (command == Command::PDEA || command == Command::PDEP) +// return tCKE; +// else if (command == Command::SREFEN) +// return tCKESR; +// else +// { +// SC_REPORT_FATAL("getMinimalExecutionTime", +// "command is not know or command has a fixed execution time"); +// return SC_ZERO_TIME; +// } +//} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index f053be72..687eedb9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -51,15 +51,16 @@ struct MemSpec const std::vector &getBanks() const; sc_time getWriteAccessTime() const; - sc_time getReadAccessTime() const; + virtual sc_time getRefreshIntervalAB() const = 0; + virtual sc_time getRefreshIntervalSB() const = 0; + + virtual sc_time getExecutionTime(Command) const = 0; + virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; + // Returns the minimum execution time for commands that have a variable execution time - sc_time getMinExecutionTimeForPowerDownCmd(Command command) const; - - virtual sc_time getExecutionTime(Command) const; - - virtual TimeInterval getIntervalOnDataStrobe(Command) const; + //virtual sc_time getMinExecutionTimeForPowerDownCmd(Command command) const = 0; std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; @@ -73,25 +74,9 @@ struct MemSpec unsigned int bitWidth; unsigned int NumberOfBankGroups; - // Memspec Variables: + // Clock double clkMHz; sc_time clk; - sc_time tCKE; // min time in pdna or pdnp - sc_time tCKESR; // min time in sref - sc_time tRAS; // active-time (act -> pre same bank) - sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) - sc_time tRCD; // act -> read/write - sc_time tRL; // read latency (read command start to data strobe) - sc_time tRTP; // read to precharge - sc_time tWL; // write latency - sc_time tWR; // write recovery (write to precharge) - sc_time tXP; // min delay to row access command after pdnpx pdnax - sc_time tXS; // min delay to row access command after srefx - sc_time tREFI; - sc_time tRFC; - sc_time tRP; - // only used in DRAMPower - sc_time tDQSCK; // Currents and Voltages: double iDD0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp new file mode 100644 index 00000000..211dff12 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecDDR3.h" + +sc_time MemSpecDDR3::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecDDR3::getRefreshIntervalSB() const +{ + SC_REPORT_FATAL("MemSpecDDR3", "Per bank refresh not supported"); + return SC_ZERO_TIME; +} + +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecDDR3::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD || command == Command::RDA) + return tRL + getReadAccessTime(); +// else if (command == Command::RDA) +// // TODO: this time is wrong (controller internally waits for tRAS) +// return tRTP + tRP; + else if (command == Command::WR || command == Command::WRA) + return tWL + getWriteAccessTime(); +// else if (command == Command::WRA) +// return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFC; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 4589288a..dab0eb87 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -40,6 +40,22 @@ struct MemSpecDDR3 : public MemSpec { + // Memspec Variables: + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; sc_time tCCD; sc_time tFAW; sc_time tRRD; @@ -52,6 +68,12 @@ struct MemSpecDDR3 : public MemSpec double iDD2P1; double iDD3P0; double iDD3P1; + + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalSB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp new file mode 100644 index 00000000..892983cb --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecDDR4.h" + +sc_time MemSpecDDR4::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecDDR4::getRefreshIntervalSB() const +{ + SC_REPORT_FATAL("MemSpecDDR4", "Per bank refresh not supported"); + return SC_ZERO_TIME; +} + +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecDDR4::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD) + return tRL + getReadAccessTime(); + else if (command == Command::RDA) + // this time is wrong (controller internally waits for tRAS) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFC; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 5df15101..f7056339 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -40,6 +40,22 @@ struct MemSpecDDR4 : public MemSpec { + // Memspec Variables: + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; sc_time tCCD_S; sc_time tCCD_L; sc_time tFAW; @@ -58,6 +74,12 @@ struct MemSpecDDR4 : public MemSpec double iDD3P1; double iDD62; double vDD2; + + sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index c6a37e7e..12566856 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -35,28 +35,51 @@ #include "MemSpecLPDDR4.h" +MemSpecLPDDR4::MemSpecLPDDR4() +{ + clACT = 4; + clPRE = 2; + clPREA = 2; + clRD = 4; + clRDA = 4; + clWR = 4; + clWRA = 4; + clREFA = 2; + clREFB = 2; + clSREFEN = 2; + clSREFEX = 2; +} + +sc_time MemSpecLPDDR4::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecLPDDR4::getRefreshIntervalSB() const +{ + return tREFIpb; +} + sc_time MemSpecLPDDR4::getExecutionTime(Command command) const { if (command == Command::PRE) - return tRP; + return tRPpb + clk; else if (command == Command::PREA) - return tRPAB; + return tRPab + clk; else if (command == Command::ACT) - return tRCD; + return tRCD + 3 * clk; else if (command == Command::RD) - return tRL + getReadAccessTime(); + return tRL + tDQSCK + getReadAccessTime() + 3 * clk; else if (command == Command::RDA) - return tRTP + tRP; + return getReadAccessTime() - 5 * clk + tRTP + tRPpb; else if (command == Command::WR) - return tWL + getWriteAccessTime(); + return tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk; else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; + return tWL + getWriteAccessTime() + 4 * clk + tWR + tRPpb; else if (command == Command::REFA) - return tRFC; + return tRFCab + clk; else if (command == Command::REFB) - return tRFCPB; - else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) - return clk; + return tRFCpb + clk; else { SC_REPORT_FATAL("getExecutionTime", @@ -68,11 +91,11 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command) const TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK /*+ DQSQ*/, - sc_time_stamp() + tRL + tDQSCK /*+ DQSQ*/ + getReadAccessTime()); + return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * clk, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime() + 3 * clk); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL /*+ tDQSS + tDQS2DQ*/, - sc_time_stamp() + tWL /*+ tDQSS + tDQS2DQ*/ + getWriteAccessTime()); + return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * clk, + sc_time_stamp() + tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk); else { SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 65b857c2..17edc1a0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -40,16 +40,35 @@ struct MemSpecLPDDR4 : public MemSpec { - sc_time tCCD; - sc_time tCCDMW; - sc_time tESCKE; - sc_time tFAW; - sc_time tWTR; + // Memspec Variables: + sc_time tREFI; + sc_time tREFIpb; + sc_time tRFCab; + sc_time tRFCpb; + sc_time tRPab; + sc_time tRPpb; sc_time tPPD; - sc_time tREFIPB; - sc_time tRFCPB; - sc_time tRPAB; + sc_time tRAS; + sc_time tRCD; + sc_time tFAW; sc_time tRRD; + sc_time tCCD; + sc_time tRL; + sc_time tRPST; + sc_time tDQSCK; + sc_time tRTP; + sc_time tWL; + sc_time tDQSS; + sc_time tDQS2DQ; + sc_time tWR; + sc_time tWPRE; + sc_time tWTR; + sc_time tXP; + sc_time tSR; + sc_time tXSR; + sc_time tESCKE; + sc_time tCKE; + sc_time tCMDCKE; double iDD02; double iDD2P0; @@ -59,6 +78,11 @@ struct MemSpecLPDDR4 : public MemSpec double iDD62; double vDD2; + MemSpecLPDDR4(); + + sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getExecutionTime(Command) const override; TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp new file mode 100644 index 00000000..406b2c0a --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecWideIO.h" + +sc_time MemSpecWideIO::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecWideIO::getRefreshIntervalSB() const +{ + SC_REPORT_FATAL("MemSpecWideIO", "Per bank refresh not supported"); + return SC_ZERO_TIME; +} + +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecWideIO::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD) + return tRL + getReadAccessTime(); + else if (command == Command::RDA) + // this time is wrong (controller internally waits for tRAS) + return tRTP + tRP; + else if (command == Command::WR) + return tWL + getWriteAccessTime(); + else if (command == Command::WRA) + return tWL + getWriteAccessTime() + tWR + tRP; + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFC; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index fd9f1cc5..35fc6b2b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -40,6 +40,22 @@ struct MemSpecWideIO : public MemSpec { + // Memspec Variables: + sc_time tCKE; // min time in pdna or pdnp + sc_time tCKESR; // min time in sref + sc_time tRAS; // active-time (act -> pre same bank) + sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) + sc_time tRCD; // act -> read/write + sc_time tRL; // read latency (read command start to data strobe) + sc_time tRTP; // read to precharge + sc_time tWL; // write latency + sc_time tWR; // write recovery (write to precharge) + sc_time tXP; // min delay to row access command after pdnpx pdnax + sc_time tXS; // min delay to row access command after srefx + sc_time tREFI; + sc_time tRFC; + sc_time tRP; + sc_time tDQSCK; sc_time tCCD; sc_time tRRD; sc_time tTAW; @@ -61,6 +77,12 @@ struct MemSpecWideIO : public MemSpec double iDD52; double iDD62; double vDD2; + + sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp deleted file mode 100644 index c9950e9a..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.cpp +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Robert Gernhardt - * Matthias Jung - */ - -#include "ScheduledCommand.h" -#include "../../../common/timingCalculations.h" -#include "../../../common/utils.h" -#include "../../../configuration/Configuration.h" - -bool ScheduledCommand::isNoCommand() const -{ - return (command == Command::NOP && start == SC_ZERO_TIME - && executionTime == SC_ZERO_TIME && end == SC_ZERO_TIME); -} - -bool ScheduledCommand::isValidCommand() const -{ - return !isNoCommand(); -} - -const sc_time ScheduledCommand::getStart() const -{ - return start; -} - -void ScheduledCommand::setStart(sc_time newStart) -{ - start = newStart; - end = newStart + executionTime; -} - -void ScheduledCommand::delayStart(sc_time delay) -{ - setStart(start + delay); -} - -// Delays the command so that its start is at least value(constraint) from timepoint previous apart. -// If passed a constraint of 0ns, method will make sure that command starts no earlier than at timepoint previous -void ScheduledCommand::establishMinDistanceFromStart(sc_time previous, - sc_time constraint) -{ - delayStart(getDelayToMeetConstraint(previous, start, constraint)); -} - -sc_time ScheduledCommand::getEnd() const -{ - return end; -} - -Command ScheduledCommand::getCommand() const -{ - return command; -} - -sc_time ScheduledCommand::getExecutionTime() const -{ - return executionTime; -} - -Rank ScheduledCommand::getRank() const -{ - return extension.getRank(); -} - -Bank ScheduledCommand::getBank() const -{ - return extension.getBank(); -} - -BankGroup ScheduledCommand::getBankGroup() const -{ - return extension.getBankGroup(); -} - -Row ScheduledCommand::getRow() const -{ - return extension.getRow(); -} - -unsigned int ScheduledCommand::getBurstLength() const -{ - return extension.getBurstlength(); -} - -bool ScheduledCommand::operator ==(const ScheduledCommand &b) const -{ - return b.command == command && b.start == start - && b.executionTime == executionTime && b.end == end; -} - -bool ScheduledCommand::commandIsIn(const std::vector &commandSet) const -{ - return isIn(command, commandSet); -} - -TimeInterval ScheduledCommand::getIntervalOnDataStrobe() const -{ - //only read and write commands have an assoicated time on the data strobe - sc_assert(getCommand() == Command::RD || getCommand() == Command::RDA - || getCommand() == Command::WR - || getCommand() == Command::WRA); - - MemSpec *timings = Configuration::getInstance().memSpec; - - if (getCommand() == Command::RD || getCommand() == Command::RDA) { - return TimeInterval(getStart() + timings->tRL, - getStart() + timings->tRL + timings->getReadAccessTime()); - } else { - return TimeInterval(getStart() + timings->tWL - timings->clk / 2, - getStart() + timings->tWL + timings->getWriteAccessTime() - - timings->clk / 2); - } -} diff --git a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h b/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h deleted file mode 100644 index 9dde8bfb..00000000 --- a/DRAMSys/library/src/controller/core/scheduling/ScheduledCommand.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2015, University of Kaiserslautern - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Janik Schlemminger - * Matthias Jung - */ - -#ifndef SCHEDULEDCOMMAND_H -#define SCHEDULEDCOMMAND_H - -#include -#include -#include "../../Command.h" -#include "../../../common/dramExtensions.h" -#include "../../../common/utils.h" - -class ScheduledCommand -{ -public: - ScheduledCommand(Command command, sc_time start, sc_time executionTime, - const DramExtension &extension) : - command(command), start(start), executionTime(executionTime), - end(start + executionTime), extension(extension) {} - - ScheduledCommand(Command command, sc_time start, sc_time executionTime, - const tlm::tlm_generic_payload &payload) : - ScheduledCommand(command, start, executionTime, - DramExtension::getExtension(payload)) {} - - ScheduledCommand() : - command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), - end(SC_ZERO_TIME), extension() {} - - bool isNoCommand() const; - bool isValidCommand() const; - - const sc_time getStart() const; - void setStart(sc_time newStart); - void delayStart(sc_time delay); - void establishMinDistanceFromStart(sc_time previous, sc_time constraint); - - sc_time getEnd() const; - Command getCommand() const; - sc_time getExecutionTime() const; - - Rank getRank() const; - Bank getBank() const; - BankGroup getBankGroup() const; - Row getRow() const; - - unsigned int getBurstLength() const; - bool operator ==(const ScheduledCommand &b) const; - bool commandIsIn(const std::vector &commandSet) const; - - TimeInterval getIntervalOnDataStrobe() const; - -private: - Command command; - sc_time start; - sc_time executionTime; - sc_time end; - DramExtension extension; -}; - -#endif // SCHEDULEDCOMMAND_H - diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index ce63d093..1dad68de 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -41,7 +41,7 @@ RefreshManager::RefreshManager(std::vector &bankMachines) : bankM { memSpec = Configuration::getInstance().memSpec; setUpDummy(refreshPayload); - timeForNextTrigger = memSpec->tREFI - memSpec->getExecutionTime(Command::PREA); + timeForNextTrigger = memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA); } std::pair RefreshManager::getNextCommand() @@ -63,7 +63,7 @@ std::pair RefreshManager::getNextCommand() else { state = RmState::IDLE; - timeForNextTrigger += (memSpec->tREFI - memSpec->getExecutionTime(Command::PREA)); + timeForNextTrigger += (memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA)); return std::pair(Command::REFA, &refreshPayload); } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 59a45813..6ebd7d16 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -42,8 +42,8 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM { memSpec = Configuration::getInstance().memSpec; // TODO: implement for multiple ranks - sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); + sc_time currentREFB = memSpec->getRefreshIntervalSB() - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->getExecutionTime(Command::PRE)); timeForNextTrigger = currentPRE; refreshPayloads = std::vector(memSpec->NumberOfBanks); @@ -65,7 +65,7 @@ std::pair RefreshManagerBankwise::getNextCommand auto it = triggerTimes.begin(); Bank bank = it->second; triggerTimes.erase(it); - triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->tREFI, bank)); + triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->getRefreshIntervalSB(), bank)); timeForNextTrigger = triggerTimes.begin()->first; if (states[bank.ID()] == RmState::IDLE) { diff --git a/DRAMSys/library/src/simulation/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/DramLPDDR4.cpp new file mode 100644 index 00000000..3041d406 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramLPDDR4.cpp @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramLPDDR4.h" + +#include "../configuration/memspec/MemSpecLPDDR4.h" + +DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4"); + + // Parameters for DRAMPower + MemSpecLPDDR4 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramLPDDR4", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + { + SC_REPORT_FATAL("DramLPDDR4", "DRAMPower not supported for LPDDR4"); + } + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/DramLPDDR4.h b/DRAMSys/library/src/simulation/DramLPDDR4.h new file mode 100644 index 00000000..4377ec56 --- /dev/null +++ b/DRAMSys/library/src/simulation/DramLPDDR4.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMLPDDR4_H +#define DRAMLPDDR4_H + +#include +#include +#include "Dram.h" + +class DramLPDDR4 : public Dram +{ +public: + DramLPDDR4(sc_module_name); + SC_HAS_PROCESS(DramLPDDR4); + virtual ~DramLPDDR4() {} +}; + +#endif // DRAMLPDDR4_H From 04ec683b57fb120203bb8ecfad076da895f0dda4 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 26 Sep 2019 21:31:17 +0200 Subject: [PATCH 114/183] Included LPDDR4 timing checker and example. --- DRAMSys/library/library.pro | 6 +- .../resources/configs/simulator/lpddr4.xml | 29 ++ .../resources/simulations/lpddr4-example.xml | 25 ++ DRAMSys/library/src/common/TlmRecorder.cpp | 30 +- .../src/configuration/memspec/MemSpec.cpp | 10 + .../src/configuration/memspec/MemSpec.h | 27 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 34 +-- DRAMSys/library/src/controller/Controller.cpp | 3 + .../src/controller/checker/CheckerLPDDR4.cpp | 268 ++++++++++++++++++ .../src/controller/checker/CheckerLPDDR4.h | 119 ++++++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 8 + .../library/src/simulation/DramRecordable.cpp | 2 + 12 files changed, 508 insertions(+), 53 deletions(-) create mode 100644 DRAMSys/library/resources/configs/simulator/lpddr4.xml create mode 100644 DRAMSys/library/resources/simulations/lpddr4-example.xml create mode 100644 DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerLPDDR4.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 095f0c77..88b450ef 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -139,7 +139,8 @@ SOURCES += \ src/configuration/memspec/MemSpecWideIO.cpp \ src/configuration/memspec/MemSpecLPDDR4.cpp \ src/controller/checker/CheckerDDR4.cpp \ - src/simulation/DramLPDDR4.cpp + src/simulation/DramLPDDR4.cpp \ + src/controller/checker/CheckerLPDDR4.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -212,7 +213,8 @@ HEADERS += \ src/configuration/memspec/MemSpecDDR4.h \ src/configuration/memspec/MemSpecLPDDR4.h \ src/controller/checker/CheckerDDR4.h \ - src/simulation/DramLPDDR4.h + src/simulation/DramLPDDR4.h \ + src/controller/checker/CheckerLPDDR4.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.xml b/DRAMSys/library/resources/configs/simulator/lpddr4.xml new file mode 100644 index 00000000..87b02763 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/lpddr4-example.xml b/DRAMSys/library/resources/simulations/lpddr4-example.xml new file mode 100644 index 00000000..6f227578 --- /dev/null +++ b/DRAMSys/library/resources/simulations/lpddr4-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 97c6709b..8944286e 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -358,21 +358,21 @@ void TlmRecorder::insertCommandLengths() { MemSpec *memSpec = Configuration::getInstance().memSpec; - sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->clACT); - sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->clPRE); - sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->clPREA); - sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->clRD); - sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->clRDA); - sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->clWR); - sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->clWRA); - sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->clREFA); - sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->clREFB); - sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->clPDEA); - sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->clPDXA); - sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->clPDEP); - sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->clPDXP); - sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->clSREFEN); - sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->clSREFEX); + sqlite3_bind_int(insertCommandLengthsStatement, 1, memSpec->commandLength[Command::ACT]); + sqlite3_bind_int(insertCommandLengthsStatement, 2, memSpec->commandLength[Command::PRE]); + sqlite3_bind_int(insertCommandLengthsStatement, 3, memSpec->commandLength[Command::PREA]); + sqlite3_bind_int(insertCommandLengthsStatement, 4, memSpec->commandLength[Command::RD]); + sqlite3_bind_int(insertCommandLengthsStatement, 5, memSpec->commandLength[Command::RDA]); + sqlite3_bind_int(insertCommandLengthsStatement, 6, memSpec->commandLength[Command::WR]); + sqlite3_bind_int(insertCommandLengthsStatement, 7, memSpec->commandLength[Command::WRA]); + sqlite3_bind_int(insertCommandLengthsStatement, 8, memSpec->commandLength[Command::REFA]); + sqlite3_bind_int(insertCommandLengthsStatement, 9, memSpec->commandLength[Command::REFB]); + sqlite3_bind_int(insertCommandLengthsStatement, 10, memSpec->commandLength[Command::PDEA]); + sqlite3_bind_int(insertCommandLengthsStatement, 11, memSpec->commandLength[Command::PDXA]); + sqlite3_bind_int(insertCommandLengthsStatement, 12, memSpec->commandLength[Command::PDEP]); + sqlite3_bind_int(insertCommandLengthsStatement, 13, memSpec->commandLength[Command::PDXP]); + sqlite3_bind_int(insertCommandLengthsStatement, 14, memSpec->commandLength[Command::SREFEN]); + sqlite3_bind_int(insertCommandLengthsStatement, 15, memSpec->commandLength[Command::SREFEX]); executeSqlStatement(insertCommandLengthsStatement); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 1dd1c790..d7e77ab3 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -42,6 +42,11 @@ using namespace tlm; +MemSpec::MemSpec() +{ + commandLength = std::vector(numberOfCommands(), 1); +} + const std::vector &MemSpec::getBanks() const { static std::vector banks; @@ -62,6 +67,11 @@ sc_time MemSpec::getWriteAccessTime() const return clk * (BurstLength / DataRate); } +unsigned MemSpec::getCommandLength(Command command) const +{ + return commandLength[command]; +} + //sc_time MemSpec::getMinExecutionTimeForPowerDownCmd(Command command) const //{ // if (command == Command::PDEA || command == Command::PDEP) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 687eedb9..84ae02ba 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -39,7 +39,7 @@ #define MEMSPEC_H #include -#include +#include #include "../../common/dramExtensions.h" #include "../../controller/Command.h" #include "../../common/utils.h" @@ -48,6 +48,9 @@ using namespace tlm; struct MemSpec { + MemSpec(); + virtual ~MemSpec() {} + const std::vector &getBanks() const; sc_time getWriteAccessTime() const; @@ -59,6 +62,8 @@ struct MemSpec virtual sc_time getExecutionTime(Command) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; + unsigned getCommandLength(Command) const; + // Returns the minimum execution time for commands that have a variable execution time //virtual sc_time getMinExecutionTimeForPowerDownCmd(Command command) const = 0; @@ -88,24 +93,8 @@ struct MemSpec double iDD6; double vDD; - // Command lengths on bus, standardly one clock cycle: - unsigned clACT = 1; - unsigned clPRE = 1; - unsigned clPREA = 1; - unsigned clRD = 1; - unsigned clRDA = 1; - unsigned clWR = 1; - unsigned clWRA = 1; - unsigned clREFA = 1; - unsigned clREFB = 1; - unsigned clPDEA = 1; - unsigned clPDXA = 1; - unsigned clPDEP = 1; - unsigned clPDXP = 1; - unsigned clSREFEN = 1; - unsigned clSREFEX = 1; - - virtual ~MemSpec() {} + // Command lengths on bus, standardly one clock cycle + std::vector commandLength; }; #endif // MEMSPEC_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 12566856..11c3c29d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -37,17 +37,17 @@ MemSpecLPDDR4::MemSpecLPDDR4() { - clACT = 4; - clPRE = 2; - clPREA = 2; - clRD = 4; - clRDA = 4; - clWR = 4; - clWRA = 4; - clREFA = 2; - clREFB = 2; - clSREFEN = 2; - clSREFEX = 2; + commandLength[Command::ACT] = 4; + commandLength[Command::PRE] = 2; + commandLength[Command::PREA] = 2; + commandLength[Command::RD] = 4; + commandLength[Command::RDA] = 4; + commandLength[Command::WR] = 4; + commandLength[Command::WRA] = 4; + commandLength[Command::REFA] = 2; + commandLength[Command::REFB] = 2; + commandLength[Command::SREFEN] = 2; + commandLength[Command::SREFEX] = 2; } sc_time MemSpecLPDDR4::getRefreshIntervalAB() const @@ -68,14 +68,14 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command) const return tRPab + clk; else if (command == Command::ACT) return tRCD + 3 * clk; - else if (command == Command::RD) + else if (command == Command::RD || command == Command::RDA) return tRL + tDQSCK + getReadAccessTime() + 3 * clk; - else if (command == Command::RDA) - return getReadAccessTime() - 5 * clk + tRTP + tRPpb; - else if (command == Command::WR) +// else if (command == Command::RDA) +// return getReadAccessTime() - 5 * clk + tRTP + tRPpb; + else if (command == Command::WR || command == Command::WRA) return tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk; - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + 4 * clk + tWR + tRPpb; +// else if (command == Command::WRA) +// return tWL + getWriteAccessTime() + 4 * clk + tWR + tRPpb; else if (command == Command::REFA) return tRFCab + clk; else if (command == Command::REFB) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index cc50efd3..612acac8 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -44,6 +44,7 @@ #include "checker/CheckerDDR3.h" #include "checker/CheckerDDR4.h" #include "checker/CheckerWideIO.h" +#include "checker/CheckerLPDDR4.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" @@ -64,6 +65,8 @@ Controller::Controller(sc_module_name name) : checker = new CheckerDDR4(); else if (config.memSpec->MemoryType == "WIDEIO_SDR") checker = new CheckerWideIO(); + else if (config.memSpec->MemoryType == "LPDDR4") + checker = new CheckerLPDDR4(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp new file mode 100644 index 00000000..70ceb04d --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerLPDDR4.h" + +CheckerLPDDR4::CheckerLPDDR4() +{ + Configuration config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); + + if (config.ControllerCoreRefDisable) + refreshChecker = new RefreshCheckerLPDDR4Dummy(memSpec); + else if (config.BankwiseLogic) + refreshChecker = new RefreshCheckerLPDDR4Bankwise(memSpec); + else + refreshChecker = new RefreshCheckerLPDDR4(memSpec); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); +} + +CheckerLPDDR4::~CheckerLPDDR4() +{ + delete refreshChecker; +} + +sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +{ + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab - 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - 2 * memSpec->clk); + + if (lastActivates[rank.ID()].size() >= 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + + refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + + refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + } + else + { + reportFatal("CheckerLPDDR4", "Unknown command!"); + } + // Check if command bus is free + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp() + (memSpec->getCommandLength(command) - 1) * memSpec->clk; + + if (command == Command::ACT) + { + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); + } + else if (command == Command::REFA || command == Command::REFB) + refreshChecker->insert(bank); +} + +// TODO: max(earliestTimeToStart, ...) needed? +void RefreshCheckerLPDDR4::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; +} + +void RefreshCheckerLPDDR4::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; +} + +void RefreshCheckerLPDDR4::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; +} + +void RefreshCheckerLPDDR4::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= timeForNextPREA) + earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; +} + +void RefreshCheckerLPDDR4::insert(Bank) +{ + timeForNextREFA += memSpec->tREFI; + timeForNextPREA += memSpec->tREFI; +} + +RefreshCheckerLPDDR4Bankwise::RefreshCheckerLPDDR4Bankwise(const MemSpecLPDDR4 *memSpec) + : RefreshCheckerLPDDR4Dummy(memSpec) +{ + sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRPpb); + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) + { + timesForNextREFB.push_back(currentREFB); + timesForNextPRE.push_back(currentPRE); + currentREFB += memSpec->clk; + currentPRE += memSpec->clk; + } +} + +void RefreshCheckerLPDDR4Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFCpb; +} + +void RefreshCheckerLPDDR4Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFCpb; +} + +void RefreshCheckerLPDDR4Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) +{ + if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) + earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFCpb; +} + +void RefreshCheckerLPDDR4Bankwise::insert(Bank bank) +{ + timesForNextREFB[bank.ID()] += memSpec->tREFI; + timesForNextPRE[bank.ID()] += memSpec->tREFI; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h new file mode 100644 index 00000000..1d8f6ffd --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERLPDDR4_H +#define CHECKERLPDDR4_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecLPDDR4.h" +#include "../../configuration/Configuration.h" + +class RefreshCheckerLPDDR4Dummy; + +class CheckerLPDDR4 final : public CheckerIF +{ +public: + CheckerLPDDR4(); + ~CheckerLPDDR4(); + sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; + void insert(Command, Rank, BankGroup, Bank); + +private: + const MemSpecLPDDR4 *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastCommandOnBus; + + // Four activate window + std::vector> lastActivates; + + RefreshCheckerLPDDR4Dummy *refreshChecker; + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; +}; + +class RefreshCheckerLPDDR4Dummy +{ +protected: + friend class CheckerLPDDR4; + RefreshCheckerLPDDR4Dummy(const MemSpecLPDDR4 *memSpec) : memSpec(memSpec) {} + virtual ~RefreshCheckerLPDDR4Dummy() {} + + virtual void delayToSatisfyACT(Bank, sc_time &) {} + virtual void delayToSatisfyRD(Bank, sc_time &) {} + virtual void delayToSatisfyWR(Bank, sc_time &) {} + virtual void delayToSatisfyPRE(Bank, sc_time &) {} + virtual void insert(Bank) {} + + const MemSpecLPDDR4 *memSpec; +}; + +class RefreshCheckerLPDDR4 final : public RefreshCheckerLPDDR4Dummy +{ +private: + friend class CheckerLPDDR4; + RefreshCheckerLPDDR4(const MemSpecLPDDR4 *memSpec) + : RefreshCheckerLPDDR4Dummy(memSpec) {} + + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void delayToSatisfyPRE(Bank, sc_time &); + void insert(Bank); + + sc_time timeForNextREFA = memSpec->tREFI; + sc_time timeForNextPREA = timeForNextREFA - memSpec->tRPpb; +}; + +class RefreshCheckerLPDDR4Bankwise final : public RefreshCheckerLPDDR4Dummy +{ +private: + friend class CheckerLPDDR4; + RefreshCheckerLPDDR4Bankwise(const MemSpecLPDDR4 *); + + void delayToSatisfyACT(Bank, sc_time &); + void delayToSatisfyRD(Bank, sc_time &); + void delayToSatisfyWR(Bank, sc_time &); + void insert(Bank); + + std::vector timesForNextREFB; + std::vector timesForNextPRE; +}; + +#endif // CHECKERLPDDR4_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 21ce0f0b..ecf8af92 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -56,6 +56,7 @@ #include "DramDDR3.h" #include "DramDDR4.h" #include "DramWideIO.h" +#include "DramLPDDR4.h" #include "../controller/Controller.h" #include "../controller/ControllerRecordable.h" @@ -282,6 +283,13 @@ void DRAMSys::instantiateModules(const string &traceName, else dram = new DramDDR4(str.c_str()); } + else if (memoryType == "LPDDR4") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramLPDDR4(str.c_str()); + } else { SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index c0eeec7d..15093d8c 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -40,6 +40,7 @@ #include "DramDDR3.h" #include "DramDDR4.h" #include "DramWideIO.h" +#include "DramLPDDR4.h" #include "../common/utils.h" using namespace tlm; @@ -142,4 +143,5 @@ void DramRecordable::powerWindow() template class DramRecordable; template class DramRecordable; template class DramRecordable; +template class DramRecordable; From 7868af4b5118af336f349dbec4031d3298dab16f Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 1 Oct 2019 20:53:01 +0200 Subject: [PATCH 115/183] Implemented first version of new refresh (no REFB). --- .../src/configuration/ConfigurationLoader.cpp | 28 ++- .../src/configuration/memspec/MemSpec.h | 12 +- .../library/src/controller/BankMachine.cpp | 22 +-- DRAMSys/library/src/controller/BankMachine.h | 3 +- DRAMSys/library/src/controller/Controller.cpp | 123 ++++++++----- DRAMSys/library/src/controller/Controller.h | 4 +- .../src/controller/checker/CheckerDDR3.cpp | 167 +++++++----------- .../src/controller/checker/CheckerDDR3.h | 53 ------ .../src/controller/cmdmux/CmdMuxStrict.cpp | 11 +- .../src/controller/refresh/RefreshManager.cpp | 78 +++++--- .../src/controller/refresh/RefreshManager.h | 14 +- .../refresh/RefreshManagerBankwise.cpp | 13 +- .../refresh/RefreshManagerBankwise.h | 8 +- .../refresh/RefreshManagerDummy.cpp | 2 +- .../controller/refresh/RefreshManagerDummy.h | 3 +- .../src/controller/refresh/RefreshManagerIF.h | 3 +- DRAMSys/traceAnalyzer/scripts/tests.py | 8 +- 17 files changed, 280 insertions(+), 272 deletions(-) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index e21b9552..36f8ee10 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -213,8 +213,11 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = memSpec->NumberOfRanks; - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = 1; + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; // MemTimings specific for DDR3 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -259,8 +262,11 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups") * memSpec->NumberOfRanks; - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; // MemTimings specific for DDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -328,8 +334,11 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture: XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = memSpec->NumberOfRanks; - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = 1; + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; // MemTimings specific for LPDDR4 XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); @@ -383,8 +392,11 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); - memSpec->NumberOfBankGroups = memSpec->NumberOfRanks; - memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks") * memSpec->NumberOfRanks; + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = 1; + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; // MemTimings specific for WideIO XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 84ae02ba..d14f6029 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -70,14 +70,18 @@ struct MemSpec std::string MemoryId = "not defined."; std::string MemoryType = "not defined."; - unsigned int NumberOfBanks; unsigned int NumberOfRanks; - unsigned int BurstLength; - unsigned int DataRate; + unsigned int NumberOfBankGroups; + unsigned int NumberOfBanks; unsigned int NumberOfRows; unsigned int NumberOfColumns; + unsigned int BurstLength; + unsigned int DataRate; unsigned int bitWidth; - unsigned int NumberOfBankGroups; + + unsigned int BanksPerRank; + unsigned int BanksPerGroup; + unsigned int GroupsPerRank; // Clock double clkMHz; diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 836edb97..1953dd30 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -38,15 +38,13 @@ BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : scheduler(scheduler), checker(checker), bank(bank) { MemSpec *memSpec = Configuration::getInstance().memSpec; - unsigned banksPerRank = memSpec->NumberOfBanks / memSpec->NumberOfRanks; - unsigned banksPerGroup = memSpec->NumberOfBanks / memSpec->NumberOfBankGroups; - rank = Rank(bank.ID() / banksPerRank); - bankgroup = BankGroup(bank.ID() / banksPerGroup); + rank = Rank(bank.ID() / memSpec->BanksPerRank); + bankgroup = BankGroup(bank.ID() / memSpec->BanksPerGroup); } std::pair BankMachine::getNextCommand() { - if (sc_time_stamp() == timeToSchedule) + if (sc_time_stamp() == timeToSchedule && !blocked) return std::pair(nextCommand, currentPayload); else return std::pair(Command::NOP, nullptr); @@ -59,7 +57,7 @@ void BankMachine::updateState(Command command) currentState = BmState::Activated; currentRow = nextRow; } - else if (command == Command::PRE) + else if (command == Command::PRE || command == Command::PREA) currentState = BmState::Precharged; else if (command == Command::RD || command == Command::WR) currentPayload = nullptr; @@ -68,19 +66,15 @@ void BankMachine::updateState(Command command) currentState = BmState::Precharged; currentPayload = nullptr; } + else if (command == Command::REFA || command == Command::REFB) + blocked = false; else SC_REPORT_FATAL("BankMachine", "Unknown phase"); } -bool BankMachine::forcePrecharge() +void BankMachine::block() { - if (currentState != BmState::Precharged) - { - currentState = BmState::Precharged; - return true; - } - else - return false; + blocked = true; } Rank BankMachine::getRank() diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index af4ac52d..eed17816 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -62,7 +62,7 @@ public: virtual sc_time startBankMachine() = 0; std::pair getNextCommand(); void updateState(Command); - bool forcePrecharge(); + void block(); Rank getRank(); Bank getBank(); @@ -82,6 +82,7 @@ protected: Rank rank = Rank(0); BankGroup bankgroup = BankGroup(0); Bank bank; + bool blocked = false; }; class BankMachineOpen final : public BankMachine diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 612acac8..ead8b620 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -58,31 +58,20 @@ Controller::Controller(sc_module_name name) : dont_initialize(); Configuration config = Configuration::getInstance(); + MemSpec *memSpec = config.memSpec; + maxNumberOfPayloads = config.MaxNrOfTransactions; - if (config.memSpec->MemoryType == "DDR3") + if (memSpec->MemoryType == "DDR3") checker = new CheckerDDR3(); - else if (config.memSpec->MemoryType == "DDR4") + else if (memSpec->MemoryType == "DDR4") checker = new CheckerDDR4(); - else if (config.memSpec->MemoryType == "WIDEIO_SDR") + else if (memSpec->MemoryType == "WIDEIO_SDR") checker = new CheckerWideIO(); - else if (config.memSpec->MemoryType == "LPDDR4") + else if (memSpec->MemoryType == "LPDDR4") checker = new CheckerLPDDR4(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); - if (config.ControllerCoreRefDisable) - refreshManager = new RefreshManagerDummy(); - else if (config.BankwiseLogic) - { - refreshManager = new RefreshManagerBankwise(bankMachines); - refreshEvent.notify(refreshManager->getTriggerDelay()); - } - else - { - refreshManager = new RefreshManager(bankMachines); - refreshEvent.notify(refreshManager->getTriggerDelay()); - } - if (config.Scheduler == "FifoStrict") { scheduler = new SchedulerFifo(); @@ -100,12 +89,12 @@ Controller::Controller(sc_module_name name) : { if (config.AdaptivePagePolicy) { - for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) bankMachines.push_back(new BankMachineOpenAdaptive(scheduler, checker, Bank(bankID))); } else { - for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) bankMachines.push_back(new BankMachineOpen(scheduler, checker, Bank(bankID))); } } @@ -113,16 +102,45 @@ Controller::Controller(sc_module_name name) : { if (config.AdaptivePagePolicy) { - for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) bankMachines.push_back(new BankMachineClosedAdaptive(scheduler, checker, Bank(bankID))); } else { - for (unsigned bankID = 0; bankID < config.memSpec->NumberOfBanks; bankID++) + for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) bankMachines.push_back(new BankMachineClosed(scheduler, checker, Bank(bankID))); } } + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + { + bankMachinesOnRank.push_back(std::vector(bankMachines.begin() + rankID * memSpec->BanksPerRank, + bankMachines.begin() + (rankID + 1) * memSpec->BanksPerRank)); + } + + if (config.ControllerCoreRefDisable) + refreshManagers.push_back(new RefreshManagerDummy()); + else if (config.BankwiseLogic) + { + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + { + RefreshManagerIF *manager = new RefreshManagerBankwise + (bankMachinesOnRank[rankID], Rank(rankID), checker); + refreshManagers.push_back(manager); + refreshEvent.notify(manager->startRefreshManager()); + } + } + else + { + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + { + RefreshManagerIF *manager = new RefreshManager + (bankMachinesOnRank[rankID], Rank(rankID), checker); + refreshManagers.push_back(manager); + refreshEvent.notify(manager->startRefreshManager()); + } + } + startBandwidthIdleCollector(); } @@ -130,18 +148,19 @@ Controller::~Controller() { endBandwithIdleCollector(); + for (auto it : refreshManagers) + delete it; for (auto it : bankMachines) delete it; delete commandMux; delete scheduler; - delete refreshManager; delete checker; } void Controller::controllerMethod() { // (1) Release payload if arbiter has accepted the result - if (sc_time_stamp() == timeToRelease /*&& payloadToRelease != nullptr*/) + if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) releasePayload(); // (2) Accept new request from arbiter @@ -170,39 +189,51 @@ void Controller::controllerMethod() it->startBankMachine(); // (5) Choose one request and send it to DRAM - std::pair result; - // (5.1) Check for refresh command (PREA or REFA) - result = refreshManager->getNextCommand(); - refreshEvent.notify(refreshManager->getTriggerDelay()); - if (result.second != nullptr) - sendToDram(result.first, result.second); - // (5.2) Check for other commands (PRE, ACT, RD or WR) - else + std::pair commandPair; + std::vector> readyCommands; + // (5.1) Check for refresh command (PREA/PRE or REFA/REFB) + for (auto it : refreshManagers) { - std::vector> readyCommands; - for (auto it : bankMachines) + commandPair = it->getNextCommand(); + if (commandPair.second != nullptr) + readyCommands.push_back(commandPair); + } + // (5.2) Check for other commands (PRE, ACT, RD or WR) + for (auto it : bankMachines) + { + commandPair = it->getNextCommand(); + if (commandPair.second != nullptr) + readyCommands.push_back(commandPair); + } + if (!readyCommands.empty()) + { + commandPair = commandMux->selectCommand(readyCommands); + if (commandPair.second != nullptr) // TODO: can happen with FIFO strict { - result = it->getNextCommand(); - if (result.second != nullptr) - readyCommands.push_back(result); - } - if (!readyCommands.empty()) - { - result = commandMux->selectCommand(readyCommands); - if (result.second != nullptr) + Rank rank = DramExtension::getRank(commandPair.second); + if (commandPair.first == Command::PREA || commandPair.first == Command::REFA) { - unsigned bankID = DramExtension::getBank(result.second).ID(); - bankMachines[bankID]->updateState(result.first); - sendToDram(result.first, result.second); + for (auto it : bankMachinesOnRank[rank.ID()]) + it->updateState(commandPair.first); } + else + { + Bank bank = DramExtension::getBank(commandPair.second); + bankMachines[bank.ID()]->updateState(commandPair.first); + } + refreshManagers[rank.ID()]->updateState(commandPair.first, commandPair.second); + sendToDram(commandPair.first, commandPair.second); } } - // (6) Restart bank machines to issue new requests for the future + // (6) Restart bank machines and refresh managers to issue new requests for the future + for (auto it : refreshManagers) + bankMachineEvent.notify(it->startRefreshManager()); + for (auto it : bankMachines) { sc_time delay = it->startBankMachine(); - if (delay != SC_ZERO_TIME) // must be checked to avoid livelock + if (delay != SC_ZERO_TIME) // TODO: must be checked to avoid livelock bankMachineEvent.notify(delay); } } diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 64daab41..1ceca538 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -73,6 +73,7 @@ protected: private: unsigned numberOfPayloads = 0; + unsigned maxNumberOfPayloads; tlm_generic_payload *payloadToAcquire = nullptr; sc_time timeToAcquire = SC_ZERO_TIME; tlm_generic_payload *payloadToRelease = nullptr; @@ -80,10 +81,11 @@ private: std::queue> responseQueue; std::vector bankMachines; + std::vector> bankMachinesOnRank; CmdMuxIF *commandMux; SchedulerIF *scheduler; CheckerIF *checker; - RefreshManagerIF *refreshManager; + std::vector refreshManagers; void releasePayload(); void acquirePayload(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index e1c85404..2cf18177 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -41,13 +41,6 @@ CheckerDDR3::CheckerDDR3() if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); - if (config.ControllerCoreRefDisable) - refreshChecker = new RefreshCheckerDDR3Dummy(memSpec); - else if (config.BankwiseLogic) - refreshChecker = new RefreshCheckerDDR3Bankwise(memSpec); - else - refreshChecker = new RefreshCheckerDDR3(memSpec); - lastScheduledByCommandAndBank = std::vector> (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); lastScheduledByCommandAndRank = std::vector> @@ -57,11 +50,6 @@ CheckerDDR3::CheckerDDR3() lastActivates = std::vector>(memSpec->NumberOfRanks); } -CheckerDDR3::~CheckerDDR3() -{ - delete refreshChecker; -} - sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; @@ -75,12 +63,17 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); @@ -93,14 +86,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); if (lastActivates[rank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); - - refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } else if (command == Command::RD || command == Command::RDA) { @@ -117,13 +108,13 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWTR); lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - - refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWTR); } else if (command == Command::WR || command == Command::WRA) { @@ -132,11 +123,13 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->BurstLength / 2 * memSpec->clk + 2 * memSpec->clk - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->BurstLength / 2 * memSpec->clk + 2 * memSpec->clk - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) @@ -145,8 +138,6 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { @@ -159,9 +150,58 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); - refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); } else { @@ -189,75 +229,4 @@ void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) lastActivates[rank.ID()].pop(); lastActivates[rank.ID()].push(sc_time_stamp()); } - else if (command == Command::REFA || command == Command::REFB) - refreshChecker->insert(bank); -} - -// TODO: max(earliestTimeToStart, ...) needed? -void RefreshCheckerDDR3::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR3::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR3::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR3::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= timeForNextPREA) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR3::insert(Bank) -{ - timeForNextREFA += memSpec->tREFI; - timeForNextPREA += memSpec->tREFI; -} - -RefreshCheckerDDR3Bankwise::RefreshCheckerDDR3Bankwise(const MemSpecDDR3 *memSpec) - : RefreshCheckerDDR3Dummy(memSpec) -{ - sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - { - timesForNextREFB.push_back(currentREFB); - timesForNextPRE.push_back(currentPRE); - currentREFB += memSpec->clk; - currentPRE += memSpec->clk; - } -} - -void RefreshCheckerDDR3Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerDDR3Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerDDR3Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerDDR3Bankwise::insert(Bank bank) -{ - timesForNextREFB[bank.ID()] += memSpec->tREFI; - timesForNextPRE[bank.ID()] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 169f5878..b901abf9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -41,13 +41,10 @@ #include "../../configuration/memspec/MemSpecDDR3.h" #include "../../configuration/Configuration.h" -class RefreshCheckerDDR3Dummy; - class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - ~CheckerDDR3(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; void insert(Command, Rank, BankGroup, Bank); @@ -62,58 +59,8 @@ private: // Four activate window std::vector> lastActivates; - RefreshCheckerDDR3Dummy *refreshChecker; - // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; -class RefreshCheckerDDR3Dummy -{ -protected: - friend class CheckerDDR3; - RefreshCheckerDDR3Dummy(const MemSpecDDR3 *memSpec) : memSpec(memSpec) {} - virtual ~RefreshCheckerDDR3Dummy() {} - - virtual void delayToSatisfyACT(Bank, sc_time &) {} - virtual void delayToSatisfyRD(Bank, sc_time &) {} - virtual void delayToSatisfyWR(Bank, sc_time &) {} - virtual void delayToSatisfyPRE(Bank, sc_time &) {} - virtual void insert(Bank) {} - - const MemSpecDDR3 *memSpec; -}; - -class RefreshCheckerDDR3 final : public RefreshCheckerDDR3Dummy -{ -private: - friend class CheckerDDR3; - RefreshCheckerDDR3(const MemSpecDDR3 *memSpec) - : RefreshCheckerDDR3Dummy(memSpec) {} - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void delayToSatisfyPRE(Bank, sc_time &); - void insert(Bank); - - sc_time timeForNextREFA = memSpec->tREFI; - sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; -}; - -class RefreshCheckerDDR3Bankwise final : public RefreshCheckerDDR3Dummy -{ -private: - friend class CheckerDDR3; - RefreshCheckerDDR3Bankwise(const MemSpecDDR3 *); - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void insert(Bank); - - std::vector timesForNextREFB; - std::vector timesForNextPRE; -}; - #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index c640bd64..ff558678 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -39,11 +39,6 @@ std::pair CmdMuxStrict::selectCommand(std::vector> &readyCommands) { - for (auto it : readyCommands) - { - if (it.first == Command::ACT || it.first == Command::PRE) - return it; - } for (auto it : readyCommands) { if (commandIsIn(it.first, {Command::RD, Command::RDA, Command::WR, Command::WRA})) @@ -55,5 +50,11 @@ CmdMuxStrict::selectCommand(std::vector(Command::NOP, nullptr); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 1dad68de..8f64f59c 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -37,41 +37,69 @@ #include "../../configuration/Configuration.h" #include "../../common/utils.h" -RefreshManager::RefreshManager(std::vector &bankMachines) : bankMachines(bankMachines) +RefreshManager::RefreshManager(std::vector &bankMachines, Rank rank, CheckerIF *checker) + : bankMachines(bankMachines), rank(rank), checker(checker) { memSpec = Configuration::getInstance().memSpec; - setUpDummy(refreshPayload); + setUpDummy(refreshPayload, rank); timeForNextTrigger = memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA); } std::pair RefreshManager::getNextCommand() { - if (sc_time_stamp() == timeForNextTrigger) - { - if (state == RmState::IDLE) - { - state = RmState::REFRESHING; - timeForNextTrigger += memSpec->getExecutionTime(Command::PREA); - bool forcedPrecharges = false; - for (auto it : bankMachines) - forcedPrecharges |= it->forcePrecharge(); - if (forcedPrecharges) - return std::pair(Command::PREA, &refreshPayload); - else - return std::pair(Command::NOP, nullptr); - } - else - { - state = RmState::IDLE; - timeForNextTrigger += (memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA)); - return std::pair(Command::REFA, &refreshPayload); - } - } + if (sc_time_stamp() == timeToSchedule) + return std::pair(nextCommand, &refreshPayload); else return std::pair(Command::NOP, nullptr); } -sc_time RefreshManager::getTriggerDelay() +sc_time RefreshManager::startRefreshManager() { - return timeForNextTrigger - sc_time_stamp(); + if (sc_time_stamp() >= timeForNextTrigger) + { + sc_time delay; + if (state == RmState::IDLE) + { + // TODO: If we do not block the bankmachines we have to check this each time + bool doPrecharge = false; + for (auto it : bankMachines) + { + it->block(); + if (it->getState() == BmState::Activated) + doPrecharge = true; + } + + if (doPrecharge) + { + delay = checker->delayToSatisfyConstraints(Command::PREA, rank, BankGroup(0), Bank(0)); + nextCommand = Command::PREA; + } + else + { + delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); + nextCommand = Command::REFA; + state = RmState::PRECHARGED; + } + } + else + { + delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); + nextCommand = Command::REFA; + } + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + else + return timeForNextTrigger - sc_time_stamp(); +} + +void RefreshManager::updateState(Command command, tlm_generic_payload *) +{ + if (command == Command::REFA) + { + state = RmState::IDLE; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + } + else if (command == Command::PREA) + state = RmState::PRECHARGED; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index e18192b4..c3a73988 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -38,23 +38,29 @@ #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" +#include "../checker/CheckerIF.h" using namespace tlm; class RefreshManager final : public RefreshManagerIF { public: - RefreshManager(std::vector &); + RefreshManager(std::vector &, Rank, CheckerIF *); std::pair getNextCommand(); - sc_time getTriggerDelay(); + sc_time startRefreshManager(); + void updateState(Command, tlm_generic_payload *); private: - enum class RmState {IDLE, REFRESHING} state = RmState::IDLE; + enum class RmState {IDLE, PRECHARGED} state = RmState::IDLE; const MemSpec *memSpec; - std::vector &bankMachines; + std::vector bankMachines; tlm_generic_payload refreshPayload; sc_time timeForNextTrigger; + sc_time timeToSchedule = SC_ZERO_TIME; + CheckerIF *checker; + Rank rank; + Command nextCommand; }; #endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 6ebd7d16..39666a69 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -37,8 +37,8 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" -RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines) - : bankMachines(bankMachines) +RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, Rank, CheckerIF *checker) + : bankMachines(bankMachines), checker(checker) { memSpec = Configuration::getInstance().memSpec; // TODO: implement for multiple ranks @@ -70,7 +70,7 @@ std::pair RefreshManagerBankwise::getNextCommand if (states[bank.ID()] == RmState::IDLE) { states[bank.ID()] = RmState::REFRESHING; - bool forcedPrecharge = bankMachines[bank.ID()]->forcePrecharge(); + bool forcedPrecharge = true;/*= bankMachines[bank.ID()]->forcePrecharge();*/ if (forcedPrecharge) return std::pair(Command::PRE, &refreshPayloads[bank.ID()]); else @@ -86,7 +86,12 @@ std::pair RefreshManagerBankwise::getNextCommand return std::pair(Command::NOP, nullptr); } -sc_time RefreshManagerBankwise::getTriggerDelay() +sc_time RefreshManagerBankwise::startRefreshManager() { return timeForNextTrigger - sc_time_stamp(); } + +void RefreshManagerBankwise::updateState(Command, tlm_generic_payload *) +{ + +} diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index b4a9c6da..4e49dddf 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -45,19 +45,21 @@ class RefreshManagerBankwise final : public RefreshManagerIF { public: - RefreshManagerBankwise(std::vector &); + RefreshManagerBankwise(std::vector &, Rank, CheckerIF *); std::pair getNextCommand(); - sc_time getTriggerDelay(); + sc_time startRefreshManager(); + void updateState(Command, tlm_generic_payload *); private: const MemSpec *memSpec; - std::vector &bankMachines; + std::vector bankMachines; std::vector refreshPayloads; std::map triggerTimes; sc_time timeForNextTrigger; enum class RmState {IDLE, REFRESHING}; std::vector states; + CheckerIF *checker; }; #endif // REFRESHMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp index 5f77a543..c35e77af 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -39,7 +39,7 @@ std::pair RefreshManagerDummy::getNextCommand() return std::pair(Command::NOP, nullptr); } -sc_time RefreshManagerDummy::getTriggerDelay() +sc_time RefreshManagerDummy::startRefreshManager() { return sc_max_time() - sc_time_stamp(); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 76ccb6fe..7dac7a23 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -47,7 +47,8 @@ class RefreshManagerDummy final : public RefreshManagerIF { public: std::pair getNextCommand(); - sc_time getTriggerDelay(); + sc_time startRefreshManager(); + void updateState(Command, tlm_generic_payload *) {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index 31601f0a..0449e788 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -48,7 +48,8 @@ public: virtual ~RefreshManagerIF() {} virtual std::pair getNextCommand() = 0; - virtual sc_time getTriggerDelay() = 0; + virtual sc_time startRefreshManager() = 0; + virtual void updateState(Command, tlm_generic_payload *) = 0; }; #endif // REFRESHMANAGERIF_H diff --git a/DRAMSys/traceAnalyzer/scripts/tests.py b/DRAMSys/traceAnalyzer/scripts/tests.py index c82dbc81..dd5c022f 100755 --- a/DRAMSys/traceAnalyzer/scripts/tests.py +++ b/DRAMSys/traceAnalyzer/scripts/tests.py @@ -349,14 +349,18 @@ def timing_constraint(FirstPhase, SecondPhase): return max(dramconfig.tCCD_L, burstlength/dramconfig.dataRate) elif (FirstPhaseName == "RDA"): - if (SecondPhaseName in ["ACT", "PREA", "REFA"]): + if (SecondPhaseName in ["ACT", "REFA"]): return dramconfig.tRTP + dramconfig.tRP + elif (SecondPhaseName == "PREA"): + return dramconfig.tRTP elif (SecondPhaseName in ["PDNA", "PDNP"]): return dramconfig.tRL + dramconfig.getReadAccessTime() + dramconfig.clk elif (FirstPhaseName == "WRA"): - if (SecondPhaseName in ["ACT", "PREA", "REFA"]): + if (SecondPhaseName in ["ACT", "REFA"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR + dramconfig.tRP + elif (SecondPhaseName == "PREA"): + return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR elif (SecondPhaseName in ["PDNA", "PDNP"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR + dramconfig.clk From abb9a37096596c83bc71d2ba0ea9b22eec45d864 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 2 Oct 2019 16:08:10 +0200 Subject: [PATCH 116/183] Added numberOfRanks to database. --- .../resources/scripts/createTraceDB.sql | 1 + DRAMSys/library/src/common/TlmRecorder.cpp | 32 +++++++++++-------- .../businessObjects/generalinfo.h | 15 ++++----- DRAMSys/traceAnalyzer/data/tracedb.cpp | 24 +++++++------- DRAMSys/traceAnalyzer/mainwindow.cpp | 2 +- .../presentation/pornotracescroller.cpp | 4 +-- .../presentation/tracedrawingproperties.h | 9 +++--- .../traceAnalyzer/presentation/traceplot.cpp | 5 +-- 8 files changed, 50 insertions(+), 42 deletions(-) diff --git a/DRAMSys/library/resources/scripts/createTraceDB.sql b/DRAMSys/library/resources/scripts/createTraceDB.sql index e9c71b76..7a127fac 100644 --- a/DRAMSys/library/resources/scripts/createTraceDB.sql +++ b/DRAMSys/library/resources/scripts/createTraceDB.sql @@ -18,6 +18,7 @@ CREATE TABLE Phases( CREATE TABLE GeneralInfo( NumberOfTransactions INTEGER, TraceEnd INTEGER, + NumberOfRanks INTEGER, NumberOfBanks INTEGER, clk INTEGER, UnitOfTime TEXT, diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 8944286e..4b4aba97 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -273,7 +273,8 @@ void TlmRecorder::setUpTransactionTerminatingPhases() void TlmRecorder::prepareSqlStatements() { insertTransactionString = - "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank,:bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; + "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank," + ":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)"; updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id"; updateDataStrobeString = @@ -284,8 +285,9 @@ void TlmRecorder::prepareSqlStatements() updatePhaseString = "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; insertGeneralInfoString = - "INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,clk,UnitOfTime,MCconfig,Memspec,Traces, WindowSize, FlexibleRefresh, MaxRefBurst, ControllerThread) VALUES" - "(:numberOfTransactions,:end,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,:traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread)"; + "INSERT INTO GeneralInfo VALUES" + "(:numberOfTransactions,:end,:numberOfRanks,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec," + ":traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread)"; insertCommandLengthsString = "INSERT INTO CommandLengths VALUES" "(:ACT, :PRE, :PREA, :RD, :RDA, :WR, :WRA, :REFA, :REFB, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)"; @@ -324,33 +326,35 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 2, simulationTimeCoveredByRecording.value()); sqlite3_bind_int(insertGeneralInfoStatement, 3, - Configuration::getInstance().memSpec->NumberOfBanks); + Configuration::getInstance().memSpec->NumberOfRanks); sqlite3_bind_int(insertGeneralInfoStatement, 4, + Configuration::getInstance().memSpec->NumberOfBanks); + sqlite3_bind_int(insertGeneralInfoStatement, 5, Configuration::getInstance().memSpec->clk.value()); - sqlite3_bind_text(insertGeneralInfoStatement, 5, "PS", 2, NULL); - sqlite3_bind_text(insertGeneralInfoStatement, 6, mcconfig.c_str(), + sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL); + sqlite3_bind_text(insertGeneralInfoStatement, 7, mcconfig.c_str(), mcconfig.length(), NULL); - sqlite3_bind_text(insertGeneralInfoStatement, 7, memspec.c_str(), + sqlite3_bind_text(insertGeneralInfoStatement, 8, memspec.c_str(), memspec.length(), NULL); - sqlite3_bind_text(insertGeneralInfoStatement, 8, traces.c_str(), + sqlite3_bind_text(insertGeneralInfoStatement, 9, traces.c_str(), traces.length(), NULL); if (!Configuration::getInstance().EnableWindowing) - sqlite3_bind_int64(insertGeneralInfoStatement, 9, 0); + sqlite3_bind_int64(insertGeneralInfoStatement, 10, 0); else - sqlite3_bind_int64(insertGeneralInfoStatement, 9, + sqlite3_bind_int64(insertGeneralInfoStatement, 10, (Configuration::getInstance().memSpec->clk * Configuration::getInstance().WindowSize).value()); if (Configuration::getInstance().ControllerCoreRefEnablePostpone || Configuration::getInstance().ControllerCoreRefEnablePullIn) { - sqlite3_bind_int(insertGeneralInfoStatement, 10, 1); - sqlite3_bind_int(insertGeneralInfoStatement, 11, + sqlite3_bind_int(insertGeneralInfoStatement, 11, 1); + sqlite3_bind_int(insertGeneralInfoStatement, 12, std::max(Configuration::getInstance().ControllerCoreRefMaxPulledIn, Configuration::getInstance().ControllerCoreRefMaxPostponed)); } else { - sqlite3_bind_int(insertGeneralInfoStatement, 10, 0); sqlite3_bind_int(insertGeneralInfoStatement, 11, 0); + sqlite3_bind_int(insertGeneralInfoStatement, 12, 0); } - sqlite3_bind_int(insertGeneralInfoStatement, 12, UINT_MAX); + sqlite3_bind_int(insertGeneralInfoStatement, 13, UINT_MAX); executeSqlStatement(insertGeneralInfoStatement); } diff --git a/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h b/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h index 883ad0a1..a2858cdb 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h +++ b/DRAMSys/traceAnalyzer/businessObjects/generalinfo.h @@ -44,6 +44,7 @@ struct GeneralInfo { unsigned int numberOfTransactions; unsigned int numberOfPhases; Timespan span; + unsigned int numberOfRanks; unsigned int numberOfBanks; QString description; QString unitOfTime; @@ -53,15 +54,13 @@ struct GeneralInfo { public: GeneralInfo(unsigned int numberOfTransactions, unsigned int numberOfPhases, - Timespan span, unsigned int numberOfBanks, const QString &description, - QString unitOfTime, unsigned int clkPeriod, unsigned int windowSize, - unsigned int controllerThread) : + Timespan span, unsigned int numberOfRanks, unsigned int numberOfBanks, + const QString &description, QString unitOfTime, unsigned int clkPeriod, + unsigned int windowSize, unsigned int controllerThread) : numberOfTransactions(numberOfTransactions) , numberOfPhases(numberOfPhases), - span(span), numberOfBanks(numberOfBanks), description(description), - unitOfTime(unitOfTime), clkPeriod(clkPeriod), windowSize(windowSize), - controllerThread(controllerThread) - { - } + span(span), numberOfRanks(numberOfRanks), numberOfBanks(numberOfBanks), + description(description), unitOfTime(unitOfTime), clkPeriod(clkPeriod), + windowSize(windowSize), controllerThread(controllerThread) {} GeneralInfo() {} }; diff --git a/DRAMSys/traceAnalyzer/data/tracedb.cpp b/DRAMSys/traceAnalyzer/data/tracedb.cpp index 2e99fc07..c3ec15dd 100644 --- a/DRAMSys/traceAnalyzer/data/tracedb.cpp +++ b/DRAMSys/traceAnalyzer/data/tracedb.cpp @@ -238,22 +238,24 @@ ID TraceDB::getTransactionIDFromPhaseID(ID phaseID) GeneralInfo TraceDB::getGeneralInfoFromDB() { QSqlQuery query(database); - query.prepare("SELECT NumberOfTransactions,TraceEnd,NumberOfBanks,Clk,UnitOfTime,Traces,Memspec,MCconfig, WindowSize, ControllerThread FROM GeneralInfo"); + query.prepare("SELECT NumberOfTransactions, TraceEnd, NumberOfRanks, NumberOfBanks, Clk, " + "UnitOfTime, Traces, Memspec, MCconfig, WindowSize, ControllerThread FROM GeneralInfo"); executeQuery(query); if (query.next()) { unsigned int numberOfTransactions = query.value(0).toInt(); traceTime traceEnd = query.value(1).toLongLong(); - unsigned int numberOfBanks = query.value(2).toInt(); - unsigned int clkPeriod = query.value(3).toInt(); - QString unitOfTime = query.value(4).toString(); + unsigned int numberOfRanks = query.value(2).toInt(); + unsigned int numberOfBanks = query.value(3).toInt(); + unsigned int clkPeriod = query.value(4).toInt(); + QString unitOfTime = query.value(5).toString(); unsigned int numberOfPhases = getNumberOfPhases(); - QString traces = "Traces: " + query.value(5).toString(); - QString memspec = "Memspec: " + query.value(6).toString(); - QString mcconfig = "MCconfig: " + query.value(7).toString(); - unsigned int windowSize = query.value(8).toInt(); - unsigned int controllerThread = query.value(9).toUInt(); + QString traces = "Traces: " + query.value(6).toString(); + QString memspec = "Memspec: " + query.value(7).toString(); + QString mcconfig = "MCconfig: " + query.value(8).toString(); + unsigned int windowSize = query.value(9).toInt(); + unsigned int controllerThread = query.value(10).toUInt(); QString description = (traces + "\n"); description += mcconfig + "\n"; @@ -266,8 +268,8 @@ GeneralInfo TraceDB::getGeneralInfoFromDB() description += "Window size:" + QString::number(windowSize) + "\n"; return GeneralInfo(numberOfTransactions, numberOfPhases, Timespan(0, traceEnd), - numberOfBanks, description, unitOfTime, clkPeriod, windowSize, - controllerThread); + numberOfRanks, numberOfBanks, description, unitOfTime, + clkPeriod, windowSize, controllerThread); } else { throw sqlException("Tracefile corrupted. No general info table", this->pathToDB.toStdString()); diff --git a/DRAMSys/traceAnalyzer/mainwindow.cpp b/DRAMSys/traceAnalyzer/mainwindow.cpp index 7155466f..9bdc2565 100644 --- a/DRAMSys/traceAnalyzer/mainwindow.cpp +++ b/DRAMSys/traceAnalyzer/mainwindow.cpp @@ -61,7 +61,7 @@ MainWindow::MainWindow(QWidget *parent) : ui->qwtPlot->setAxisScale(QwtPlot::xBottom, traceNavigator->GeneralTraceInfo().TraceSpan().Begin(), traceNavigator->GeneralTraceInfo().TraceSpan().End()); - unsigned int banksize = traceNavigator -> GeneralTraceInfo().NumberOfBanks(); + unsigned int banksize = traceNavigator->GeneralTraceInfo().NumberOfBanks(); ui->qwtPlot->setAxisScale(QwtPlot::yLeft, 0.0, banksize + 3, 1.0); PhaseCollectionDrawingProperties *drawingProperties = new diff --git a/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp index 9865cd8a..d440f488 100644 --- a/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp +++ b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp @@ -86,7 +86,7 @@ void PornoTraceScroller::setUpTracePlotItem() void PornoTraceScroller::setUpDrawingProperties() { - unsigned int numberOfBanks = navigator -> GeneralTraceInfo().numberOfBanks; + unsigned int numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; drawingProperties.numberOfBanks = numberOfBanks; drawingProperties.yValResponse = numberOfBanks; drawingProperties.yValRequest = numberOfBanks + 1; @@ -97,7 +97,7 @@ void PornoTraceScroller::setUpDrawingProperties() void PornoTraceScroller::setUpAxis() { - setAxisScale(yLeft, -1, navigator -> GeneralTraceInfo().numberOfBanks + 2, 1.0); + setAxisScale(yLeft, -1, navigator->GeneralTraceInfo().numberOfBanks + 2, 1.0); axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Labels, false ); axisScaleDraw(yLeft)->enableComponent(QwtAbstractScaleDraw::Ticks, false ); } diff --git a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h index a2db4a48..ae6150ad 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h +++ b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h @@ -53,6 +53,7 @@ struct TraceDrawingProperties { int yValRequest; int yValCommandBus; int yValDataBus; + unsigned int numberOfRanks; unsigned int numberOfBanks; TraceDrawingProperties() : drawText(true), drawBorder(true), @@ -60,13 +61,13 @@ struct TraceDrawingProperties { TraceDrawingProperties(bool drawText, bool drawBorder, ColorGrouping colorGrouping) : drawText(drawText), drawBorder(drawBorder), colorGrouping(colorGrouping) {} - TraceDrawingProperties(bool drawText, bool drawBorder, - ColorGrouping colorGrouping, int yValResponse, int yValRequest, - int yValCommandBus, int yValDataBus, unsigned int numberOfBanks) : + TraceDrawingProperties(bool drawText, bool drawBorder, ColorGrouping colorGrouping, + int yValResponse, int yValRequest, int yValCommandBus, int yValDataBus, + unsigned int numberOfRanks, unsigned int numberOfBanks) : drawText(drawText), drawBorder(drawBorder), colorGrouping(colorGrouping), yValResponse(yValResponse), yValRequest(yValRequest), yValCommandBus(yValCommandBus), yValDataBus(yValDataBus), - numberOfBanks(numberOfBanks) {} + numberOfRanks(numberOfRanks), numberOfBanks(numberOfBanks) {} QHash getLabels() const { diff --git a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp index 871b3e23..341ecc5c 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp +++ b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp @@ -205,7 +205,8 @@ void TracePlot::connectNavigatorQ_SIGNALS() void TracePlot::setUpDrawingProperties() { - unsigned int numberOfBanks = navigator -> GeneralTraceInfo().numberOfBanks; + drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; + unsigned int numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; drawingProperties.numberOfBanks = numberOfBanks; drawingProperties.yValResponse = numberOfBanks; drawingProperties.yValRequest = numberOfBanks + 1; @@ -252,7 +253,7 @@ void TracePlot::setUpZoom() void TracePlot::setUpAxis() { - int numberOfBanks = navigator -> GeneralTraceInfo().numberOfBanks; + int numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; setAxisScale(yLeft, -5, numberOfBanks + 2, 1.0); setAxisScaleDraw(yLeft, new CustomLabelScaleDraw( From f4a018cfb3458a44b83477a4432d4f860586389a Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 2 Oct 2019 17:46:37 +0200 Subject: [PATCH 117/183] Fixed display of rankwise commands. --- DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp | 8 +++++--- .../traceAnalyzer/presentation/pornotracescroller.cpp | 9 +++++---- .../traceAnalyzer/presentation/tracedrawingproperties.h | 4 +++- DRAMSys/traceAnalyzer/presentation/traceplot.cpp | 8 ++++---- 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp index b72bf9ed..45163619 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp +++ b/DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp @@ -64,7 +64,7 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, } if (!isBankwise()) { - for (unsigned int i = 0; i < drawingProperties.numberOfBanks; i++) + for (int i = getYVal(drawingProperties); i < (int)(getYVal(drawingProperties) + drawingProperties.banksPerRank); i++) drawPhaseSymbol(span.Begin(), span.End(), i, drawingProperties.drawText, getPhaseSymbol(), painter, xMap, yMap); } else @@ -123,8 +123,10 @@ QColor Phase::getColor(const TraceDrawingProperties &drawingProperties) const int Phase::getYVal(const TraceDrawingProperties &drawingProperties) const { - Q_UNUSED(drawingProperties) - return transaction->Bank(); + if (isBankwise()) + return transaction->Bank(); + else + return transaction->Rank() * drawingProperties.banksPerRank; } Qt::BrushStyle Phase::getBrushStyle() const diff --git a/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp index d440f488..8b66efd2 100644 --- a/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp +++ b/DRAMSys/traceAnalyzer/presentation/pornotracescroller.cpp @@ -86,10 +86,11 @@ void PornoTraceScroller::setUpTracePlotItem() void PornoTraceScroller::setUpDrawingProperties() { - unsigned int numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; - drawingProperties.numberOfBanks = numberOfBanks; - drawingProperties.yValResponse = numberOfBanks; - drawingProperties.yValRequest = numberOfBanks + 1; + drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; + drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; + drawingProperties.banksPerRank = drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; + drawingProperties.yValResponse = drawingProperties.numberOfBanks; + drawingProperties.yValRequest = drawingProperties.numberOfBanks + 1; drawingProperties.yValCommandBus = -3; drawingProperties.yValDataBus = -4; } diff --git a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h index ae6150ad..64496973 100644 --- a/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h +++ b/DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h @@ -55,6 +55,7 @@ struct TraceDrawingProperties { int yValDataBus; unsigned int numberOfRanks; unsigned int numberOfBanks; + unsigned int banksPerRank; TraceDrawingProperties() : drawText(true), drawBorder(true), colorGrouping(ColorGrouping::PhaseType) {} @@ -67,7 +68,8 @@ struct TraceDrawingProperties { drawText(drawText), drawBorder(drawBorder), colorGrouping(colorGrouping), yValResponse(yValResponse), yValRequest(yValRequest), yValCommandBus(yValCommandBus), yValDataBus(yValDataBus), - numberOfRanks(numberOfRanks), numberOfBanks(numberOfBanks) {} + numberOfRanks(numberOfRanks), numberOfBanks(numberOfBanks), + banksPerRank(numberOfBanks / numberOfRanks) {} QHash getLabels() const { diff --git a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp index 341ecc5c..27620d4a 100644 --- a/DRAMSys/traceAnalyzer/presentation/traceplot.cpp +++ b/DRAMSys/traceAnalyzer/presentation/traceplot.cpp @@ -206,10 +206,10 @@ void TracePlot::connectNavigatorQ_SIGNALS() void TracePlot::setUpDrawingProperties() { drawingProperties.numberOfRanks = navigator->GeneralTraceInfo().numberOfRanks; - unsigned int numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; - drawingProperties.numberOfBanks = numberOfBanks; - drawingProperties.yValResponse = numberOfBanks; - drawingProperties.yValRequest = numberOfBanks + 1; + drawingProperties.numberOfBanks = navigator->GeneralTraceInfo().numberOfBanks; + drawingProperties.banksPerRank = drawingProperties.numberOfBanks / drawingProperties.numberOfRanks; + drawingProperties.yValResponse = drawingProperties.numberOfBanks; + drawingProperties.yValRequest = drawingProperties.numberOfBanks + 1; drawingProperties.yValCommandBus = -3; drawingProperties.yValDataBus = -4; } From 4328f4550b3e51271f3bd61e3a4c09cd1a645d3a Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 2 Oct 2019 21:54:05 +0200 Subject: [PATCH 118/183] Updated CheckerLPDDR4 for new refresh, some renaming. --- .../src/configuration/memspec/MemSpec.h | 2 +- .../src/configuration/memspec/MemSpecDDR3.cpp | 2 +- .../src/configuration/memspec/MemSpecDDR3.h | 2 +- .../src/configuration/memspec/MemSpecDDR4.cpp | 2 +- .../src/configuration/memspec/MemSpecDDR4.h | 2 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 2 +- .../src/configuration/memspec/MemSpecLPDDR4.h | 2 +- .../configuration/memspec/MemSpecWideIO.cpp | 2 +- .../src/configuration/memspec/MemSpecWideIO.h | 2 +- .../src/controller/checker/CheckerLPDDR4.cpp | 190 +++++++++--------- .../src/controller/checker/CheckerLPDDR4.h | 51 ----- .../refresh/RefreshManagerBankwise.cpp | 4 +- 12 files changed, 110 insertions(+), 153 deletions(-) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index d14f6029..98094d8b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -57,7 +57,7 @@ struct MemSpec sc_time getReadAccessTime() const; virtual sc_time getRefreshIntervalAB() const = 0; - virtual sc_time getRefreshIntervalSB() const = 0; + virtual sc_time getRefreshIntervalPB() const = 0; virtual sc_time getExecutionTime(Command) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 211dff12..16a5a75d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -40,7 +40,7 @@ sc_time MemSpecDDR3::getRefreshIntervalAB() const return tREFI; } -sc_time MemSpecDDR3::getRefreshIntervalSB() const +sc_time MemSpecDDR3::getRefreshIntervalPB() const { SC_REPORT_FATAL("MemSpecDDR3", "Per bank refresh not supported"); return SC_ZERO_TIME; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index dab0eb87..d2345098 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -70,7 +70,7 @@ struct MemSpecDDR3 : public MemSpec double iDD3P1; sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalPB() const override; sc_time getExecutionTime(Command) const override; TimeInterval getIntervalOnDataStrobe(Command) const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 892983cb..7c413340 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -40,7 +40,7 @@ sc_time MemSpecDDR4::getRefreshIntervalAB() const return tREFI; } -sc_time MemSpecDDR4::getRefreshIntervalSB() const +sc_time MemSpecDDR4::getRefreshIntervalPB() const { SC_REPORT_FATAL("MemSpecDDR4", "Per bank refresh not supported"); return SC_ZERO_TIME; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index f7056339..592b864a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -75,7 +75,7 @@ struct MemSpecDDR4 : public MemSpec double iDD62; double vDD2; - sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalPB() const override; sc_time getRefreshIntervalAB() const override; sc_time getExecutionTime(Command) const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 11c3c29d..2de71159 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -55,7 +55,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalAB() const return tREFI; } -sc_time MemSpecLPDDR4::getRefreshIntervalSB() const +sc_time MemSpecLPDDR4::getRefreshIntervalPB() const { return tREFIpb; } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 17edc1a0..2cc80bfe 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -80,7 +80,7 @@ struct MemSpecLPDDR4 : public MemSpec MemSpecLPDDR4(); - sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalPB() const override; sc_time getRefreshIntervalAB() const override; sc_time getExecutionTime(Command) const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index 406b2c0a..c1380122 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -40,7 +40,7 @@ sc_time MemSpecWideIO::getRefreshIntervalAB() const return tREFI; } -sc_time MemSpecWideIO::getRefreshIntervalSB() const +sc_time MemSpecWideIO::getRefreshIntervalPB() const { SC_REPORT_FATAL("MemSpecWideIO", "Per bank refresh not supported"); return SC_ZERO_TIME; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 35fc6b2b..5fe55613 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -78,7 +78,7 @@ struct MemSpecWideIO : public MemSpec double iDD62; double vDD2; - sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalPB() const override; sc_time getRefreshIntervalAB() const override; sc_time getExecutionTime(Command) const override; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 70ceb04d..e2dbd2af 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -41,13 +41,6 @@ CheckerLPDDR4::CheckerLPDDR4() if (memSpec == nullptr) SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); - if (config.ControllerCoreRefDisable) - refreshChecker = new RefreshCheckerLPDDR4Dummy(memSpec); - else if (config.BankwiseLogic) - refreshChecker = new RefreshCheckerLPDDR4Bankwise(memSpec); - else - refreshChecker = new RefreshCheckerLPDDR4(memSpec); - lastScheduledByCommandAndBank = std::vector> (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); lastScheduledByCommandAndRank = std::vector> @@ -57,11 +50,6 @@ CheckerLPDDR4::CheckerLPDDR4() lastActivates = std::vector>(memSpec->NumberOfRanks); } -CheckerLPDDR4::~CheckerLPDDR4() -{ - delete refreshChecker; -} - sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { sc_time lastCommandStart; @@ -82,6 +70,10 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - 2 * memSpec->clk); + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - 2 * memSpec->clk); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb); @@ -98,10 +90,12 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - 2 * memSpec->clk); + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->clk); + if (lastActivates[rank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); - - refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } else if (command == Command::RD || command == Command::RDA) { @@ -123,8 +117,6 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); - - refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) { @@ -146,8 +138,6 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); - - refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { @@ -165,8 +155,97 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->clk); - refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + + memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; // remove this if REFA and REFB are not mixed + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); + } + else if (command == Command::REFB) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + + memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; // remove this + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; // remove this + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); } else { @@ -188,81 +267,10 @@ void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) lastScheduledByCommand[command] = sc_time_stamp(); lastCommandOnBus = sc_time_stamp() + (memSpec->getCommandLength(command) - 1) * memSpec->clk; - if (command == Command::ACT) + if (command == Command::ACT) // TODO: FAW for REFB { if (lastActivates[rank.ID()].size() == 4) lastActivates[rank.ID()].pop(); lastActivates[rank.ID()].push(sc_time_stamp()); } - else if (command == Command::REFA || command == Command::REFB) - refreshChecker->insert(bank); -} - -// TODO: max(earliestTimeToStart, ...) needed? -void RefreshCheckerLPDDR4::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; -} - -void RefreshCheckerLPDDR4::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; -} - -void RefreshCheckerLPDDR4::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; -} - -void RefreshCheckerLPDDR4::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= timeForNextPREA) - earliestTimeToStart = timeForNextREFA + memSpec->tRFCab; -} - -void RefreshCheckerLPDDR4::insert(Bank) -{ - timeForNextREFA += memSpec->tREFI; - timeForNextPREA += memSpec->tREFI; -} - -RefreshCheckerLPDDR4Bankwise::RefreshCheckerLPDDR4Bankwise(const MemSpecLPDDR4 *memSpec) - : RefreshCheckerLPDDR4Dummy(memSpec) -{ - sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRPpb); - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - { - timesForNextREFB.push_back(currentREFB); - timesForNextPRE.push_back(currentPRE); - currentREFB += memSpec->clk; - currentPRE += memSpec->clk; - } -} - -void RefreshCheckerLPDDR4Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFCpb; -} - -void RefreshCheckerLPDDR4Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFCpb; -} - -void RefreshCheckerLPDDR4Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFCpb; -} - -void RefreshCheckerLPDDR4Bankwise::insert(Bank bank) -{ - timesForNextREFB[bank.ID()] += memSpec->tREFI; - timesForNextPRE[bank.ID()] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index 1d8f6ffd..8bd46f3f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -47,7 +47,6 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - ~CheckerLPDDR4(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; void insert(Command, Rank, BankGroup, Bank); @@ -62,58 +61,8 @@ private: // Four activate window std::vector> lastActivates; - RefreshCheckerLPDDR4Dummy *refreshChecker; - // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; -class RefreshCheckerLPDDR4Dummy -{ -protected: - friend class CheckerLPDDR4; - RefreshCheckerLPDDR4Dummy(const MemSpecLPDDR4 *memSpec) : memSpec(memSpec) {} - virtual ~RefreshCheckerLPDDR4Dummy() {} - - virtual void delayToSatisfyACT(Bank, sc_time &) {} - virtual void delayToSatisfyRD(Bank, sc_time &) {} - virtual void delayToSatisfyWR(Bank, sc_time &) {} - virtual void delayToSatisfyPRE(Bank, sc_time &) {} - virtual void insert(Bank) {} - - const MemSpecLPDDR4 *memSpec; -}; - -class RefreshCheckerLPDDR4 final : public RefreshCheckerLPDDR4Dummy -{ -private: - friend class CheckerLPDDR4; - RefreshCheckerLPDDR4(const MemSpecLPDDR4 *memSpec) - : RefreshCheckerLPDDR4Dummy(memSpec) {} - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void delayToSatisfyPRE(Bank, sc_time &); - void insert(Bank); - - sc_time timeForNextREFA = memSpec->tREFI; - sc_time timeForNextPREA = timeForNextREFA - memSpec->tRPpb; -}; - -class RefreshCheckerLPDDR4Bankwise final : public RefreshCheckerLPDDR4Dummy -{ -private: - friend class CheckerLPDDR4; - RefreshCheckerLPDDR4Bankwise(const MemSpecLPDDR4 *); - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void insert(Bank); - - std::vector timesForNextREFB; - std::vector timesForNextPRE; -}; - #endif // CHECKERLPDDR4_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 39666a69..b6c5ed73 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -42,7 +42,7 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM { memSpec = Configuration::getInstance().memSpec; // TODO: implement for multiple ranks - sc_time currentREFB = memSpec->getRefreshIntervalSB() - memSpec->clk * (memSpec->NumberOfBanks - 1); + sc_time currentREFB = memSpec->getRefreshIntervalPB() - memSpec->clk * (memSpec->NumberOfBanks - 1); sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->getExecutionTime(Command::PRE)); timeForNextTrigger = currentPRE; @@ -65,7 +65,7 @@ std::pair RefreshManagerBankwise::getNextCommand auto it = triggerTimes.begin(); Bank bank = it->second; triggerTimes.erase(it); - triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->getRefreshIntervalSB(), bank)); + triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->getRefreshIntervalPB(), bank)); timeForNextTrigger = triggerTimes.begin()->first; if (states[bank.ID()] == RmState::IDLE) { From 6e71e435c5e76422381f6f7d12d57d9eec9547bf Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 2 Oct 2019 21:55:19 +0200 Subject: [PATCH 119/183] Implemented first version of new bankwise refresh. --- .../src/controller/refresh/RefreshManager.cpp | 2 +- .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 81 +++++++++---------- .../refresh/RefreshManagerBankwise.h | 8 +- DRAMSys/library/src/simulation/Dram.cpp | 2 +- 5 files changed, 47 insertions(+), 48 deletions(-) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 8f64f59c..5c17059f 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -41,8 +41,8 @@ RefreshManager::RefreshManager(std::vector &bankMachines, Rank ra : bankMachines(bankMachines), rank(rank), checker(checker) { memSpec = Configuration::getInstance().memSpec; + timeForNextTrigger = memSpec->getRefreshIntervalAB(); setUpDummy(refreshPayload, rank); - timeForNextTrigger = memSpec->getRefreshIntervalAB() - memSpec->getExecutionTime(Command::PREA); } std::pair RefreshManager::getNextCommand() diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index c3a73988..50748fa9 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -58,8 +58,8 @@ private: tlm_generic_payload refreshPayload; sc_time timeForNextTrigger; sc_time timeToSchedule = SC_ZERO_TIME; - CheckerIF *checker; Rank rank; + CheckerIF *checker; Command nextCommand; }; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index b6c5ed73..2e4509fd 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -37,61 +37,58 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" -RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, Rank, CheckerIF *checker) - : bankMachines(bankMachines), checker(checker) +RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, Rank rank, CheckerIF *checker) + : bankMachines(bankMachines), rank(rank), checker(checker) { - memSpec = Configuration::getInstance().memSpec; - // TODO: implement for multiple ranks - sc_time currentREFB = memSpec->getRefreshIntervalPB() - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->getExecutionTime(Command::PRE)); - timeForNextTrigger = currentPRE; + memSpec = Configuration::getInstance().memSpec; + timeForNextTrigger = memSpec->getRefreshIntervalPB(); - refreshPayloads = std::vector(memSpec->NumberOfBanks); - states = std::vector(memSpec->NumberOfBanks, RmState::IDLE); - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - { - setUpDummy(refreshPayloads[bankID], Rank(0), Bank(bankID)); - triggerTimes.insert(std::pair(currentREFB, Bank(bankID))); - triggerTimes.insert(std::pair(currentPRE, Bank(bankID))); - currentREFB += memSpec->clk; - currentPRE += memSpec->clk; - } + refreshPayloads = std::vector(memSpec->BanksPerRank); + //states = std::vector(memSpec->NumberOfBanks, RmState::IDLE); + for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) + setUpDummy(refreshPayloads[bankID], rank, bankMachines[bankID]->getBank()); } std::pair RefreshManagerBankwise::getNextCommand() { - if (sc_time_stamp() == timeForNextTrigger) - { - auto it = triggerTimes.begin(); - Bank bank = it->second; - triggerTimes.erase(it); - triggerTimes.insert(std::pair(timeForNextTrigger + memSpec->getRefreshIntervalPB(), bank)); - timeForNextTrigger = triggerTimes.begin()->first; - if (states[bank.ID()] == RmState::IDLE) - { - states[bank.ID()] = RmState::REFRESHING; - bool forcedPrecharge = true;/*= bankMachines[bank.ID()]->forcePrecharge();*/ - if (forcedPrecharge) - return std::pair(Command::PRE, &refreshPayloads[bank.ID()]); - else - return std::pair(Command::NOP, nullptr); - } - else - { - states[bank.ID()] = RmState::IDLE; - return std::pair(Command::REFB, &refreshPayloads[bank.ID()]); - } - } + if (sc_time_stamp() == timeToSchedule) + return std::pair(nextCommand, &refreshPayloads[nextBankID]); else return std::pair(Command::NOP, nullptr); } sc_time RefreshManagerBankwise::startRefreshManager() { - return timeForNextTrigger - sc_time_stamp(); + if (sc_time_stamp() >= timeForNextTrigger) + { + sc_time delay; + bankMachines[nextBankID]->block(); + if (bankMachines[nextBankID]->getState() == BmState::Activated) + { + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, BankGroup(0), + bankMachines[nextBankID]->getBank()); + nextCommand = Command::PRE; + } + else + { + delay = checker->delayToSatisfyConstraints(Command::REFB, rank, BankGroup(0), + bankMachines[nextBankID]->getBank()); + nextCommand = Command::REFB; + } + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + else + return timeForNextTrigger - sc_time_stamp(); } -void RefreshManagerBankwise::updateState(Command, tlm_generic_payload *) +void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *) { - + if (command == Command::REFB) + { + //state = RmState::IDLE; + nextBankID = (nextBankID + 1) % memSpec->BanksPerRank; + timeForNextTrigger += memSpec->getRefreshIntervalPB(); + } + //else if (command == Command::PRE) do nothing? } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 4e49dddf..158246cc 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -52,14 +52,16 @@ public: void updateState(Command, tlm_generic_payload *); private: + enum class RmState {IDLE, PRECHARGED} state = RmState::IDLE; const MemSpec *memSpec; std::vector bankMachines; std::vector refreshPayloads; - std::map triggerTimes; sc_time timeForNextTrigger; - enum class RmState {IDLE, REFRESHING}; - std::vector states; + sc_time timeToSchedule = SC_ZERO_TIME; + Rank rank; CheckerIF *checker; + Command nextCommand; + unsigned nextBankID = 0; }; #endif // REFRESHMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index 1475747e..bd498d10 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -195,7 +195,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFB)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) From b22cfa4a94ab6d5d4719caee68b916e43f805c9e Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 3 Oct 2019 19:04:34 +0200 Subject: [PATCH 120/183] Improved controller method, some code and output formatting. --- .../library/src/common/XmlAddressDecoder.cpp | 14 +++--- .../src/configuration/Configuration.cpp | 25 +++++----- .../library/src/controller/BankMachine.cpp | 13 ++++-- DRAMSys/library/src/controller/BankMachine.h | 11 +++-- DRAMSys/library/src/controller/Controller.cpp | 46 ++++++++++--------- .../src/controller/refresh/RefreshManager.cpp | 2 +- .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 2 +- .../refresh/RefreshManagerBankwise.h | 2 +- .../refresh/RefreshManagerDummy.cpp | 2 +- .../controller/refresh/RefreshManagerDummy.h | 2 +- .../src/controller/refresh/RefreshManagerIF.h | 2 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 2 +- 13 files changed, 68 insertions(+), 57 deletions(-) diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 39d38d04..06e0c715 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -172,12 +172,12 @@ void XmlAddressDecoder::print() { std::cout << headline << std::endl; std::cout << "Address Mapping:" << std::endl << std::endl; - std::cout << std::setw(11) << "channel: " << std::bitset<64>(masks.channel) << std::endl; - std::cout << std::setw(11) << "rank: " << std::bitset<64>(masks.rank) << std::endl; - std::cout << std::setw(11) << "bankgroup: " << std::bitset<64>(masks.bankgroup) << std::endl; - std::cout << std::setw(11) << "bank: " << std::bitset<64>(masks.bank) << std::endl; - std::cout << std::setw(11) << "row: " << std::bitset<64>(masks.row) << std::endl; - std::cout << std::setw(11) << "column: " << std::bitset<64>(masks.column) << std::endl; - std::cout << std::setw(11) << "bytes: " << std::bitset<64>(masks.bytes) << std::endl; + std::cout << " channel: " << std::bitset<64>(masks.channel) << std::endl; + std::cout << " rank: " << std::bitset<64>(masks.rank) << std::endl; + std::cout << " bankgroup: " << std::bitset<64>(masks.bankgroup) << std::endl; + std::cout << " bank: " << std::bitset<64>(masks.bank) << std::endl; + std::cout << " row: " << std::bitset<64>(masks.row) << std::endl; + std::cout << " column: " << std::bitset<64>(masks.column) << std::endl; + std::cout << " bytes: " << std::bitset<64>(masks.bytes) << std::endl; std::cout << std::endl; } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 5026d578..826343d6 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -337,6 +337,7 @@ void Configuration::setParameters(std::map std::uint64_t Configuration::getSimMemSizeInBytes() { // 1. Get number of banks, rows, columns and data width in bits for one die (or chip) + std::string type = memSpec->MemoryType; std::uint64_t ranks = memSpec->NumberOfRanks; std::uint64_t bankgroups = memSpec->NumberOfBankGroups; std::uint64_t banks = memSpec->NumberOfBanks; @@ -350,17 +351,19 @@ std::uint64_t Configuration::getSimMemSizeInBytes() // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) std::uint64_t memorySize = chipSize * NumberOfDevicesOnDIMM; - std::cout << headline << std::endl << std::endl; - std::cout << std::setw(24) << "Memory size in bytes : " << memorySize << std::endl; - std::cout << std::setw(24) << "Number of ranks : " << ranks << std::endl; - std::cout << std::setw(24) << "Number of bankgroups : " << bankgroups << std::endl; - std::cout << std::setw(24) << "Number of banks : " << banks << std::endl; - std::cout << std::setw(24) << "Number of rows : " << rows << std::endl; - std::cout << std::setw(24) << "Number of columns : " << columns << std::endl; - std::cout << std::setw(24) << "Chip data bus width : " << bitWidth << std::endl; - std::cout << std::setw(24) << "Chip size in bits : " << chipBitSize << std::endl; - std::cout << std::setw(24) << "Chip Size in bytes : " << chipSize << std::endl; - std::cout << std::setw(24) << "Devices/Chips on DIMM: " << NumberOfDevicesOnDIMM << std::endl; + std::cout << headline << std::endl; + std::cout << "Per Channel Configuration:" << std::endl << std::endl; + std::cout << " Memory type: " << type << std::endl; + std::cout << " Memory size in bytes: " << memorySize << std::endl; + std::cout << " Number of ranks: " << ranks << std::endl; + std::cout << " Number of bankgroups: " << bankgroups << std::endl; + std::cout << " Number of banks: " << banks << std::endl; + std::cout << " Number of rows: " << rows << std::endl; + std::cout << " Number of columns: " << columns << std::endl; + std::cout << " Chip data bus width: " << bitWidth << std::endl; + std::cout << " Chip size in bits: " << chipBitSize << std::endl; + std::cout << " Chip Size in bytes: " << chipSize << std::endl; + std::cout << " Devices/Chips on DIMM: " << NumberOfDevicesOnDIMM << std::endl; std::cout << std::endl; assert(memorySize > 0); diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 1953dd30..c3e2688e 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -97,10 +97,15 @@ BmState BankMachine::getState() return currentState; } +bool BankMachine::isIdle() +{ + return (currentPayload == nullptr); +} + BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : BankMachine(scheduler, checker, bank) {} -sc_time BankMachineOpen::startBankMachine() +sc_time BankMachineOpen::start() { if (currentPayload == nullptr) { @@ -147,7 +152,7 @@ sc_time BankMachineOpen::startBankMachine() BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : BankMachine(scheduler, checker, bank) {} -sc_time BankMachineClosed::startBankMachine() +sc_time BankMachineClosed::start() { if (currentPayload == nullptr) { @@ -194,7 +199,7 @@ sc_time BankMachineClosed::startBankMachine() BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : BankMachine(scheduler, checker, bank) {} -sc_time BankMachineOpenAdaptive::startBankMachine() +sc_time BankMachineOpenAdaptive::start() { if (currentPayload == nullptr) { @@ -259,7 +264,7 @@ sc_time BankMachineOpenAdaptive::startBankMachine() BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) : BankMachine(scheduler, checker, bank) {} -sc_time BankMachineClosedAdaptive::startBankMachine() +sc_time BankMachineClosedAdaptive::start() { if (currentPayload == nullptr) { diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index eed17816..bf36ef47 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -59,7 +59,7 @@ class BankMachine { public: virtual ~BankMachine() {} - virtual sc_time startBankMachine() = 0; + virtual sc_time start() = 0; std::pair getNextCommand(); void updateState(Command); void block(); @@ -68,6 +68,7 @@ public: Bank getBank(); Row getOpenRow(); BmState getState(); + bool isIdle(); protected: BankMachine(SchedulerIF *, CheckerIF *, Bank); @@ -89,28 +90,28 @@ class BankMachineOpen final : public BankMachine { public: BankMachineOpen(SchedulerIF *, CheckerIF *, Bank); - sc_time startBankMachine(); + sc_time start(); }; class BankMachineClosed final : public BankMachine { public: BankMachineClosed(SchedulerIF *, CheckerIF *, Bank); - sc_time startBankMachine(); + sc_time start(); }; class BankMachineOpenAdaptive final : public BankMachine { public: BankMachineOpenAdaptive(SchedulerIF *, CheckerIF *, Bank); - sc_time startBankMachine(); + sc_time start(); }; class BankMachineClosedAdaptive final : public BankMachine { public: BankMachineClosedAdaptive(SchedulerIF *, CheckerIF *, Bank); - sc_time startBankMachine(); + sc_time start(); }; #endif // BANKMACHINE_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index ead8b620..35922e48 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -127,7 +127,7 @@ Controller::Controller(sc_module_name name) : RefreshManagerIF *manager = new RefreshManagerBankwise (bankMachinesOnRank[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); - refreshEvent.notify(manager->startRefreshManager()); + refreshEvent.notify(manager->start()); } } else @@ -137,7 +137,7 @@ Controller::Controller(sc_module_name name) : RefreshManagerIF *manager = new RefreshManager (bankMachinesOnRank[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); - refreshEvent.notify(manager->startRefreshManager()); + refreshEvent.notify(manager->start()); } } @@ -163,16 +163,7 @@ void Controller::controllerMethod() if (sc_time_stamp() == timeToRelease && payloadToRelease != nullptr) releasePayload(); - // (2) Accept new request from arbiter - if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) - { - if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) - acquirePayload(); - else - PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); - } - - // (3) Send result to arbiter + // (2) Send next result to arbiter if (payloadToRelease == nullptr && !responseQueue.empty()) { std::pair element = responseQueue.front(); @@ -184,21 +175,32 @@ void Controller::controllerMethod() } } - // (4) Start bank machines to issue new requests for current time - for (auto it : bankMachines) - it->startBankMachine(); + // (3) Accept new request from arbiter and start appropriate BM if necessary + if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) + { + if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) + { + Bank bank = DramExtension::getBank(payloadToAcquire); + acquirePayload(); - // (5) Choose one request and send it to DRAM + if (bankMachines[bank.ID()]->isIdle()) + bankMachines[bank.ID()]->start(); + } + else + PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); + } + + // (4) Choose one request and send it to DRAM std::pair commandPair; std::vector> readyCommands; - // (5.1) Check for refresh command (PREA/PRE or REFA/REFB) + // (4.1) Check for refresh command (PREA/PRE or REFA/REFB) for (auto it : refreshManagers) { commandPair = it->getNextCommand(); if (commandPair.second != nullptr) readyCommands.push_back(commandPair); } - // (5.2) Check for other commands (PRE, ACT, RD or WR) + // (4.2) Check for other commands (PRE, ACT, RD or WR) for (auto it : bankMachines) { commandPair = it->getNextCommand(); @@ -226,13 +228,13 @@ void Controller::controllerMethod() } } - // (6) Restart bank machines and refresh managers to issue new requests for the future + // (5) Restart bank machines and refresh managers to issue new requests for the future for (auto it : refreshManagers) - bankMachineEvent.notify(it->startRefreshManager()); - + bankMachineEvent.notify(it->start()); + // TODO: order, first BM then RM? for (auto it : bankMachines) { - sc_time delay = it->startBankMachine(); + sc_time delay = it->start(); if (delay != SC_ZERO_TIME) // TODO: must be checked to avoid livelock bankMachineEvent.notify(delay); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 5c17059f..3935c7d2 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -53,7 +53,7 @@ std::pair RefreshManager::getNextCommand() return std::pair(Command::NOP, nullptr); } -sc_time RefreshManager::startRefreshManager() +sc_time RefreshManager::start() { if (sc_time_stamp() >= timeForNextTrigger) { diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 50748fa9..9f730d8e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -48,7 +48,7 @@ public: RefreshManager(std::vector &, Rank, CheckerIF *); std::pair getNextCommand(); - sc_time startRefreshManager(); + sc_time start(); void updateState(Command, tlm_generic_payload *); private: diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 2e4509fd..ac6b4158 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -57,7 +57,7 @@ std::pair RefreshManagerBankwise::getNextCommand return std::pair(Command::NOP, nullptr); } -sc_time RefreshManagerBankwise::startRefreshManager() +sc_time RefreshManagerBankwise::start() { if (sc_time_stamp() >= timeForNextTrigger) { diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 158246cc..d3ff44e7 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -48,7 +48,7 @@ public: RefreshManagerBankwise(std::vector &, Rank, CheckerIF *); std::pair getNextCommand(); - sc_time startRefreshManager(); + sc_time start(); void updateState(Command, tlm_generic_payload *); private: diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp index c35e77af..c6c1428c 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -39,7 +39,7 @@ std::pair RefreshManagerDummy::getNextCommand() return std::pair(Command::NOP, nullptr); } -sc_time RefreshManagerDummy::startRefreshManager() +sc_time RefreshManagerDummy::start() { return sc_max_time() - sc_time_stamp(); } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 7dac7a23..2d895cf3 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -47,7 +47,7 @@ class RefreshManagerDummy final : public RefreshManagerIF { public: std::pair getNextCommand(); - sc_time startRefreshManager(); + sc_time start(); void updateState(Command, tlm_generic_payload *) {} }; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index 0449e788..d1e589ca 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -48,7 +48,7 @@ public: virtual ~RefreshManagerIF() {} virtual std::pair getNextCommand() = 0; - virtual sc_time startRefreshManager() = 0; + virtual sc_time start() = 0; virtual void updateState(Command, tlm_generic_payload *) = 0; }; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index ecf8af92..e2d49595 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -169,7 +169,7 @@ void DRAMSys::logo() cout << REDTXT("=| |= ") << BOLDBLUETXT("University of Kaiserslautern") << endl; cout << REDTXT(" +---+ ") << endl; - cout << REDTXT(" ||| ") << "DRAMSys v3.0" << endl; + cout << REDTXT(" ||| ") << "DRAMSys v4.0" << endl; cout << endl; #undef REDTXT #undef BOLDBLUETXT From aa6a2058721d69c4d2c2f1396b0f98e2cf35cc58 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 4 Oct 2019 21:46:29 +0200 Subject: [PATCH 121/183] Implemented first version of flexible refresh (only REFA). --- DRAMSys/library/src/controller/Controller.cpp | 32 ++++++------ DRAMSys/library/src/controller/Controller.h | 2 +- .../src/controller/checker/CheckerDDR3.cpp | 6 +-- .../src/controller/checker/CheckerDDR3.h | 2 +- .../src/controller/checker/CheckerDDR4.cpp | 2 +- .../src/controller/checker/CheckerLPDDR4.cpp | 37 +++++++------- .../src/controller/checker/CheckerWideIO.cpp | 2 +- .../src/controller/refresh/RefreshManager.cpp | 50 +++++++++++++++++-- .../src/controller/refresh/RefreshManager.h | 5 ++ 9 files changed, 94 insertions(+), 44 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 35922e48..8b658d52 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -53,11 +53,10 @@ Controller::Controller(sc_module_name name) : GenericController(name) { SC_METHOD(controllerMethod); - sensitive << beginReqEvent << endRespEvent << bankMachineEvent - << refreshEvent << dataResponseEventQueue; + sensitive << beginReqEvent << endRespEvent << controllerEvent << dataResponseEventQueue; dont_initialize(); - Configuration config = Configuration::getInstance(); + Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; maxNumberOfPayloads = config.MaxNrOfTransactions; @@ -127,7 +126,7 @@ Controller::Controller(sc_module_name name) : RefreshManagerIF *manager = new RefreshManagerBankwise (bankMachinesOnRank[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); - refreshEvent.notify(manager->start()); + controllerEvent.notify(manager->start()); } } else @@ -137,7 +136,7 @@ Controller::Controller(sc_module_name name) : RefreshManagerIF *manager = new RefreshManager (bankMachinesOnRank[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); - refreshEvent.notify(manager->start()); + controllerEvent.notify(manager->start()); } } @@ -190,18 +189,22 @@ void Controller::controllerMethod() PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); } - // (4) Choose one request and send it to DRAM + // (4) Start refresh managers to issue requests for the current time + for (auto it : refreshManagers) + it->start(); + + // (5) Choose one request and send it to DRAM std::pair commandPair; std::vector> readyCommands; - // (4.1) Check for refresh command (PREA/PRE or REFA/REFB) - for (auto it : refreshManagers) + // (5.1) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) + for (auto it : bankMachines) { commandPair = it->getNextCommand(); if (commandPair.second != nullptr) readyCommands.push_back(commandPair); } - // (4.2) Check for other commands (PRE, ACT, RD or WR) - for (auto it : bankMachines) + // (5.2) Check for refresh commands (PREA/PRE or REFA/REFB) + for (auto it : refreshManagers) { commandPair = it->getNextCommand(); if (commandPair.second != nullptr) @@ -228,16 +231,15 @@ void Controller::controllerMethod() } } - // (5) Restart bank machines and refresh managers to issue new requests for the future - for (auto it : refreshManagers) - bankMachineEvent.notify(it->start()); - // TODO: order, first BM then RM? + // (6) Restart bank machines and refresh managers to issue new requests for the future for (auto it : bankMachines) { sc_time delay = it->start(); if (delay != SC_ZERO_TIME) // TODO: must be checked to avoid livelock - bankMachineEvent.notify(delay); + controllerEvent.notify(delay); } + for (auto it : refreshManagers) + controllerEvent.notify(it->start()); } tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 1ceca538..fd08a178 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -91,7 +91,7 @@ private: void acquirePayload(); void controllerMethod(); - sc_event beginReqEvent, endRespEvent, bankMachineEvent, refreshEvent; + sc_event beginReqEvent, endRespEvent, controllerEvent; sc_event_queue dataResponseEventQueue; // Bandwidth related diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 2cf18177..5ac42425 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -36,7 +36,7 @@ CheckerDDR3::CheckerDDR3() { - Configuration config = Configuration::getInstance(); + Configuration &config = Configuration::getInstance(); memSpec = dynamic_cast(config.memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); @@ -208,7 +208,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG reportFatal("CheckerDDR3", "Unknown command!"); } // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); return (earliestTimeToStart - sc_time_stamp()); } @@ -221,7 +221,7 @@ void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - lastScheduled = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp(); if (command == Command::ACT) { diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index b901abf9..10723fa2 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -54,7 +54,7 @@ private: std::vector> lastScheduledByCommandAndBank; std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; - sc_time lastScheduled; + sc_time lastCommandOnBus; // Four activate window std::vector> lastActivates; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index f35bd770..80081016 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -36,7 +36,7 @@ CheckerDDR4::CheckerDDR4() { - Configuration config = Configuration::getInstance(); + Configuration &config = Configuration::getInstance(); memSpec = dynamic_cast(config.memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index e2dbd2af..825087a7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -36,7 +36,7 @@ CheckerLPDDR4::CheckerLPDDR4() { - Configuration config = Configuration::getInstance(); + Configuration &config = Configuration::getInstance(); memSpec = dynamic_cast(config.memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); @@ -94,8 +94,8 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->clk); - if (lastActivates[rank.ID()].size() >= 4) - earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->clk); } else if (command == Command::RD || command == Command::RDA) { @@ -177,9 +177,9 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); +// lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); } else if (command == Command::REFA) { @@ -208,9 +208,9 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; // remove this if REFA and REFB are not mixed - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); +// lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); } else if (command == Command::REFB) { @@ -235,17 +235,20 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); - lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; // remove this - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); +// lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); - lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; // remove this - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); +// lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk); } else { @@ -267,10 +270,10 @@ void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) lastScheduledByCommand[command] = sc_time_stamp(); lastCommandOnBus = sc_time_stamp() + (memSpec->getCommandLength(command) - 1) * memSpec->clk; - if (command == Command::ACT) // TODO: FAW for REFB + if (command == Command::ACT || command == Command::REFB) { if (lastActivates[rank.ID()].size() == 4) lastActivates[rank.ID()].pop(); - lastActivates[rank.ID()].push(sc_time_stamp()); + lastActivates[rank.ID()].push(lastCommandOnBus); } } diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 895bbcb2..065f954a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -36,7 +36,7 @@ CheckerWideIO::CheckerWideIO() { - Configuration config = Configuration::getInstance(); + Configuration &config = Configuration::getInstance(); memSpec = dynamic_cast(config.memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 3935c7d2..962206c2 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -40,9 +40,15 @@ RefreshManager::RefreshManager(std::vector &bankMachines, Rank rank, CheckerIF *checker) : bankMachines(bankMachines), rank(rank), checker(checker) { - memSpec = Configuration::getInstance().memSpec; + Configuration &config = Configuration::getInstance(); + memSpec = config.memSpec; timeForNextTrigger = memSpec->getRefreshIntervalAB(); setUpDummy(refreshPayload, rank); + + if (config.ControllerCoreRefEnablePostpone) + maxPostponed = config.ControllerCoreRefMaxPostponed; + if (config.ControllerCoreRefEnablePullIn) + maxPulledin = -config.ControllerCoreRefMaxPulledIn; } std::pair RefreshManager::getNextCommand() @@ -60,11 +66,30 @@ sc_time RefreshManager::start() sc_time delay; if (state == RmState::IDLE) { + if (flexibleCounter != maxPostponed || isPulledinRefresh) + { + for (auto it : bankMachines) + { + if (!it->isIdle()) + { + if (!isPulledinRefresh) + flexibleCounter++; + isPulledinRefresh = false; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + return timeForNextTrigger - sc_time_stamp(); + } + } + } + else + { + for (auto it : bankMachines) + it->block(); + } + // TODO: If we do not block the bankmachines we have to check this each time bool doPrecharge = false; for (auto it : bankMachines) { - it->block(); if (it->getState() == BmState::Activated) doPrecharge = true; } @@ -78,10 +103,11 @@ sc_time RefreshManager::start() { delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); nextCommand = Command::REFA; - state = RmState::PRECHARGED; + if (flexibleCounter == maxPostponed) + state = RmState::PRECHARGED; } } - else + else // if (state == RmState::PRECHARGED) { delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); nextCommand = Command::REFA; @@ -98,8 +124,22 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) if (command == Command::REFA) { state = RmState::IDLE; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); + + if (isPulledinRefresh) + flexibleCounter--; + else + isPulledinRefresh = true; + + if (flexibleCounter == maxPulledin) + { + isPulledinRefresh = false; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + } } else if (command == Command::PREA) + { + for (auto it : bankMachines) + it->block(); state = RmState::PRECHARGED; + } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 9f730d8e..0bfe6d69 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -61,6 +61,11 @@ private: Rank rank; CheckerIF *checker; Command nextCommand; + + int flexibleCounter = 0; + int maxPostponed = 0; + int maxPulledin = 0; + bool isPulledinRefresh = false; }; #endif // REFRESHMANAGER_H From d1f6bc6233d92ef428a086fb65b314c7688aad93 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 6 Oct 2019 18:56:13 +0200 Subject: [PATCH 122/183] Improved flexible refresh, implemented first version of bankwise flexible refresh. --- .../library/src/controller/BankMachine.cpp | 5 + DRAMSys/library/src/controller/BankMachine.h | 1 + .../src/controller/refresh/RefreshManager.cpp | 83 ++++++---- .../src/controller/refresh/RefreshManager.h | 5 +- .../refresh/RefreshManagerBankwise.cpp | 155 +++++++++++++++--- .../refresh/RefreshManagerBankwise.h | 15 +- 6 files changed, 203 insertions(+), 61 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index c3e2688e..99bd9809 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -82,6 +82,11 @@ Rank BankMachine::getRank() return rank; } +BankGroup BankMachine::getBankGroup() +{ + return bankgroup; +} + Bank BankMachine::getBank() { return bank; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index bf36ef47..bf7ca2f5 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -65,6 +65,7 @@ public: void block(); Rank getRank(); + BankGroup getBankGroup(); Bank getBank(); Row getOpenRow(); BmState getState(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 962206c2..3c8dc00d 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -64,56 +64,68 @@ sc_time RefreshManager::start() if (sc_time_stamp() >= timeForNextTrigger) { sc_time delay; - if (state == RmState::IDLE) + if (state == RmState::Regular) { - if (flexibleCounter != maxPostponed || isPulledinRefresh) + bool forcedRefresh = (flexibilityCounter == maxPostponed); + if (!forcedRefresh) { for (auto it : bankMachines) { if (!it->isIdle()) { - if (!isPulledinRefresh) - flexibleCounter++; - isPulledinRefresh = false; + flexibilityCounter++; timeForNextTrigger += memSpec->getRefreshIntervalAB(); return timeForNextTrigger - sc_time_stamp(); } } } - else + else // regular refresh that cannot be postponed -> force precharge { for (auto it : bankMachines) it->block(); } - // TODO: If we do not block the bankmachines we have to check this each time - bool doPrecharge = false; for (auto it : bankMachines) { if (it->getState() == BmState::Activated) - doPrecharge = true; + { + nextCommand = Command::PREA; + delay = checker->delayToSatisfyConstraints(Command::PREA, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + return delay; + } } - if (doPrecharge) - { - delay = checker->delayToSatisfyConstraints(Command::PREA, rank, BankGroup(0), Bank(0)); - nextCommand = Command::PREA; - } - else - { - delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); - nextCommand = Command::REFA; - if (flexibleCounter == maxPostponed) - state = RmState::PRECHARGED; - } - } - else // if (state == RmState::PRECHARGED) - { - delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); + if (forcedRefresh) // if refresh is forced all banks will remain precharged state + state = RmState::Precharged; nextCommand = Command::REFA; + delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + else if (state == RmState::Pulledin) + { + for (auto it : bankMachines) + { + if (!it->isIdle()) + { + state = RmState::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + return timeForNextTrigger - sc_time_stamp(); + } + } + + delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + else // if (state == RmState::Precharged) + { + nextCommand = Command::REFA; + delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + return delay; } - timeToSchedule = sc_time_stamp() + delay; - return delay; } else return timeForNextTrigger - sc_time_stamp(); @@ -123,23 +135,24 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) { if (command == Command::REFA) { - state = RmState::IDLE; - - if (isPulledinRefresh) - flexibleCounter--; + if (state == RmState::Pulledin) + flexibilityCounter--; else - isPulledinRefresh = true; + state = RmState::Pulledin; - if (flexibleCounter == maxPulledin) + if ((flexibilityCounter == maxPulledin) || + ((sc_time_stamp() + memSpec->getExecutionTime(Command::REFA) + >= (timeForNextTrigger + memSpec->getRefreshIntervalAB())))) { - isPulledinRefresh = false; + state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); } } else if (command == Command::PREA) { + // if PREA was successful we will refresh in any case for (auto it : bankMachines) it->block(); - state = RmState::PRECHARGED; + state = RmState::Precharged; } } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 0bfe6d69..e30ebc83 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -52,7 +52,7 @@ public: void updateState(Command, tlm_generic_payload *); private: - enum class RmState {IDLE, PRECHARGED} state = RmState::IDLE; + enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; std::vector bankMachines; tlm_generic_payload refreshPayload; @@ -62,10 +62,9 @@ private: CheckerIF *checker; Command nextCommand; - int flexibleCounter = 0; + int flexibilityCounter = 0; int maxPostponed = 0; int maxPulledin = 0; - bool isPulledinRefresh = false; }; #endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index ac6b4158..950a153f 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -40,19 +40,27 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, Rank rank, CheckerIF *checker) : bankMachines(bankMachines), rank(rank), checker(checker) { - memSpec = Configuration::getInstance().memSpec; + Configuration &config = Configuration::getInstance(); + memSpec = config.memSpec; timeForNextTrigger = memSpec->getRefreshIntervalPB(); refreshPayloads = std::vector(memSpec->BanksPerRank); - //states = std::vector(memSpec->NumberOfBanks, RmState::IDLE); for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) + { setUpDummy(refreshPayloads[bankID], rank, bankMachines[bankID]->getBank()); + remainingBankMachines.push_back(bankMachines[bankID]); + } + + if (config.ControllerCoreRefEnablePostpone) + maxPostponed = config.ControllerCoreRefMaxPostponed * memSpec->BanksPerRank; + if (config.ControllerCoreRefEnablePullIn) + maxPulledin = -(config.ControllerCoreRefMaxPulledIn * memSpec->BanksPerRank); } std::pair RefreshManagerBankwise::getNextCommand() { if (sc_time_stamp() == timeToSchedule) - return std::pair(nextCommand, &refreshPayloads[nextBankID]); + return std::pair(nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); else return std::pair(Command::NOP, nullptr); } @@ -62,33 +70,140 @@ sc_time RefreshManagerBankwise::start() if (sc_time_stamp() >= timeForNextTrigger) { sc_time delay; - bankMachines[nextBankID]->block(); - if (bankMachines[nextBankID]->getState() == BmState::Activated) + if (state == RmState::Regular) { - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, BankGroup(0), - bankMachines[nextBankID]->getBank()); - nextCommand = Command::PRE; - } - else - { - delay = checker->delayToSatisfyConstraints(Command::REFB, rank, BankGroup(0), - bankMachines[nextBankID]->getBank()); + bool allBanksBusy = true; + currentIterator = remainingBankMachines.begin(); + currentBankMachine = *remainingBankMachines.begin(); + + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + { + if ((*it)->isIdle()) + { + currentIterator = it; + currentBankMachine = *it; + allBanksBusy = false; + break; + } + } + + bool forcedRefresh = (flexibilityCounter == maxPostponed); + if (allBanksBusy && !forcedRefresh) + { + flexibilityCounter++; + timeForNextTrigger += memSpec->getRefreshIntervalPB(); + return timeForNextTrigger - sc_time_stamp(); + } + else if (forcedRefresh) + currentBankMachine->block(); + + if (currentBankMachine->getState() == BmState::Activated) + { + nextCommand = Command::PRE; + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + + if (forcedRefresh) + state = RmState::Precharged; nextCommand = Command::REFB; + delay = checker->delayToSatisfyConstraints(Command::REFB, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + else if (state == RmState::Pulledin) + { + bool allBanksBusy = true; + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + { + if ((*it)->isIdle()) + { + currentIterator = it; + currentBankMachine = *it; + allBanksBusy = false; + break; + } + } + + if (allBanksBusy) + { + state = RmState::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalPB(); + return timeForNextTrigger - sc_time_stamp(); + } + + if (currentBankMachine->getState() == BmState::Activated) + { + nextCommand = Command::PRE; + delay = checker->delayToSatisfyConstraints(Command::PRE, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + } + else + { + nextCommand = Command::REFB; + delay = checker->delayToSatisfyConstraints(Command::REFB, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + } + timeToSchedule = sc_time_stamp() + delay; + return delay; + } + else // if (state == RmState::Precharged) + { + nextCommand = Command::REFB; + delay = checker->delayToSatisfyConstraints(Command::REFB, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = sc_time_stamp() + delay; + return delay; } - timeToSchedule = sc_time_stamp() + delay; - return delay; } else return timeForNextTrigger - sc_time_stamp(); } -void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *) +void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *payload) { + // distinguish between PRE from BM and RM!!!!! if (command == Command::REFB) { - //state = RmState::IDLE; - nextBankID = (nextBankID + 1) % memSpec->BanksPerRank; - timeForNextTrigger += memSpec->getRefreshIntervalPB(); + remainingBankMachines.erase(currentIterator); + if (remainingBankMachines.empty()) + { + for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) + remainingBankMachines.push_back(bankMachines[bankID]); + } + + if (state == RmState::Pulledin) + flexibilityCounter--; + else + state = RmState::Pulledin; + + if ((flexibilityCounter == maxPulledin) || + ((sc_time_stamp() + memSpec->getExecutionTime(Command::REFB) + >= (timeForNextTrigger + memSpec->getRefreshIntervalPB())))) + { + state = RmState::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalPB(); + } + } + else if (command == Command::PRE && nextCommand == Command::PRE) + { + // TODO: remove all this + if (DramExtension::getBank(payload) == currentBankMachine->getBank()) + { + if ((sc_time_stamp() + memSpec->getExecutionTime(Command::PRE) + >= (timeForNextTrigger + memSpec->getRefreshIntervalPB()))) + { + state = RmState::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + } + else + { + currentBankMachine->block(); + state = RmState::Precharged; + } + } } - //else if (command == Command::PRE) do nothing? } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index d3ff44e7..4b176148 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -40,7 +40,9 @@ #include "../BankMachine.h" #include #include -#include +#include + +using namespace tlm; class RefreshManagerBankwise final : public RefreshManagerIF { @@ -52,7 +54,7 @@ public: void updateState(Command, tlm_generic_payload *); private: - enum class RmState {IDLE, PRECHARGED} state = RmState::IDLE; + enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; std::vector bankMachines; std::vector refreshPayloads; @@ -61,7 +63,14 @@ private: Rank rank; CheckerIF *checker; Command nextCommand; - unsigned nextBankID = 0; + + std::list remainingBankMachines; + std::list::iterator currentIterator; + BankMachine *currentBankMachine; + + int flexibilityCounter = 0; + int maxPostponed = 0; + int maxPulledin = 0; }; #endif // REFRESHMANAGERBANKWISE_H From 86d508243474e2a6ceeedfd34670095fb93849ad Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sun, 6 Oct 2019 20:54:30 +0200 Subject: [PATCH 123/183] Further improvements in refresh managers. --- .../src/controller/refresh/RefreshManager.cpp | 20 +++-- .../refresh/RefreshManagerBankwise.cpp | 76 ++++++++++--------- 2 files changed, 52 insertions(+), 44 deletions(-) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 3c8dc00d..220a5f07 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -61,8 +61,15 @@ std::pair RefreshManager::getNextCommand() sc_time RefreshManager::start() { + timeToSchedule = SC_ZERO_TIME; if (sc_time_stamp() >= timeForNextTrigger) { + if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) + { + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + state = RmState::Regular; + } + sc_time delay; if (state == RmState::Regular) { @@ -87,7 +94,7 @@ sc_time RefreshManager::start() for (auto it : bankMachines) { - if (it->getState() == BmState::Activated) + if (it->getState() == BmState::Activated) // at least one bank is active -> do PREA { nextCommand = Command::PREA; delay = checker->delayToSatisfyConstraints(Command::PREA, rank, BankGroup(0), Bank(0)); @@ -96,8 +103,9 @@ sc_time RefreshManager::start() } } - if (forcedRefresh) // if refresh is forced all banks will remain precharged state + if (forcedRefresh) // if refresh is forced all banks will remain in precharged state state = RmState::Precharged; + nextCommand = Command::REFA; delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); timeToSchedule = sc_time_stamp() + delay; @@ -107,7 +115,7 @@ sc_time RefreshManager::start() { for (auto it : bankMachines) { - if (!it->isIdle()) + if (!it->isIdle()) // at least one bank is active -> abort pulling in { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); @@ -140,9 +148,7 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) else state = RmState::Pulledin; - if ((flexibilityCounter == maxPulledin) || - ((sc_time_stamp() + memSpec->getExecutionTime(Command::REFA) - >= (timeForNextTrigger + memSpec->getRefreshIntervalAB())))) + if (flexibilityCounter == maxPulledin) { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); @@ -150,7 +156,7 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) } else if (command == Command::PREA) { - // if PREA was successful we will refresh in any case + // if PREA was successful we will do the refresh in any case for (auto it : bankMachines) it->block(); state = RmState::Precharged; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 950a153f..4934deb7 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -60,21 +60,30 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM std::pair RefreshManagerBankwise::getNextCommand() { if (sc_time_stamp() == timeToSchedule) - return std::pair(nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); + return std::pair + (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); else return std::pair(Command::NOP, nullptr); } sc_time RefreshManagerBankwise::start() { + timeToSchedule = SC_ZERO_TIME; if (sc_time_stamp() >= timeForNextTrigger) { + if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) + { + timeForNextTrigger += memSpec->getRefreshIntervalPB(); + state = RmState::Regular; + } + sc_time delay; if (state == RmState::Regular) { - bool allBanksBusy = true; currentIterator = remainingBankMachines.begin(); currentBankMachine = *remainingBankMachines.begin(); + bool forcedRefresh = (flexibilityCounter == maxPostponed); + bool allBanksBusy = true; for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) { @@ -87,36 +96,40 @@ sc_time RefreshManagerBankwise::start() } } - bool forcedRefresh = (flexibilityCounter == maxPostponed); if (allBanksBusy && !forcedRefresh) { flexibilityCounter++; timeForNextTrigger += memSpec->getRefreshIntervalPB(); return timeForNextTrigger - sc_time_stamp(); } - else if (forcedRefresh) - currentBankMachine->block(); - - if (currentBankMachine->getState() == BmState::Activated) + else if (currentBankMachine->getState() == BmState::Activated) { + if (forcedRefresh) + currentBankMachine->block(); nextCommand = Command::PRE; delay = checker->delayToSatisfyConstraints(Command::PRE, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); timeToSchedule = sc_time_stamp() + delay; return delay; } - - if (forcedRefresh) - state = RmState::Precharged; - nextCommand = Command::REFB; - delay = checker->delayToSatisfyConstraints(Command::REFB, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); - timeToSchedule = sc_time_stamp() + delay; - return delay; + else + { + if (forcedRefresh) + { + currentBankMachine->block(); + state = RmState::Precharged; + } + nextCommand = Command::REFB; + delay = checker->delayToSatisfyConstraints(Command::REFB, rank, + currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = sc_time_stamp() + delay; + return delay; + } } else if (state == RmState::Pulledin) { bool allBanksBusy = true; + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) { if ((*it)->isIdle()) @@ -134,21 +147,22 @@ sc_time RefreshManagerBankwise::start() timeForNextTrigger += memSpec->getRefreshIntervalPB(); return timeForNextTrigger - sc_time_stamp(); } - - if (currentBankMachine->getState() == BmState::Activated) + else if (currentBankMachine->getState() == BmState::Activated) { nextCommand = Command::PRE; delay = checker->delayToSatisfyConstraints(Command::PRE, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = sc_time_stamp() + delay; + return delay; } else { nextCommand = Command::REFB; delay = checker->delayToSatisfyConstraints(Command::REFB, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); + timeToSchedule = sc_time_stamp() + delay; + return delay; } - timeToSchedule = sc_time_stamp() + delay; - return delay; } else // if (state == RmState::Precharged) { @@ -165,7 +179,6 @@ sc_time RefreshManagerBankwise::start() void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *payload) { - // distinguish between PRE from BM and RM!!!!! if (command == Command::REFB) { remainingBankMachines.erase(currentIterator); @@ -180,30 +193,19 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p else state = RmState::Pulledin; - if ((flexibilityCounter == maxPulledin) || - ((sc_time_stamp() + memSpec->getExecutionTime(Command::REFB) - >= (timeForNextTrigger + memSpec->getRefreshIntervalPB())))) + if (flexibilityCounter == maxPulledin) { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalPB(); } } - else if (command == Command::PRE && nextCommand == Command::PRE) + else if (command == Command::PRE) { - // TODO: remove all this - if (DramExtension::getBank(payload) == currentBankMachine->getBank()) + if (nextCommand == Command::PRE && state == RmState::Regular + && DramExtension::getBank(payload) == currentBankMachine->getBank()) { - if ((sc_time_stamp() + memSpec->getExecutionTime(Command::PRE) - >= (timeForNextTrigger + memSpec->getRefreshIntervalPB()))) - { - state = RmState::Regular; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); - } - else - { - currentBankMachine->block(); - state = RmState::Precharged; - } + currentBankMachine->block(); + state = RmState::Precharged; } } } From 932027112e31a9ac5adeb29efbe67074aa3c04a8 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 7 Oct 2019 15:37:23 +0200 Subject: [PATCH 124/183] Adapted timing checkers of DDR4 and WideIO to new refresh. --- .../JEDEC_256Mb_WIDEIO-200_128bit.xml | 4 +- .../JEDEC_256Mb_WIDEIO-266_128bit.xml | 4 +- .../src/configuration/ConfigurationLoader.cpp | 4 +- .../configuration/memspec/MemSpecWideIO.cpp | 16 +- .../src/configuration/memspec/MemSpecWideIO.h | 4 +- .../src/controller/checker/CheckerDDR3.cpp | 3 +- .../src/controller/checker/CheckerDDR4.cpp | 154 ++++++--------- .../src/controller/checker/CheckerDDR4.h | 60 +----- .../src/controller/checker/CheckerLPDDR4.h | 2 - .../src/controller/checker/CheckerWideIO.cpp | 181 ++++++++---------- .../src/controller/checker/CheckerWideIO.h | 53 +---- DRAMSys/library/src/simulation/DramWideIO.cpp | 8 +- 12 files changed, 160 insertions(+), 333 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml index 122ea9af..838ee7f7 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml @@ -28,8 +28,8 @@ - - + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml index aebd11e8..39da583f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml @@ -28,8 +28,8 @@ - - + + diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 36f8ee10..42bf68cf 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -408,12 +408,12 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) memSpec->tRC = clk * queryUIntParameter(timings, "RC"); memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); memSpec->tRL = clk * queryUIntParameter(timings, "RL"); - memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); memSpec->tWL = clk * queryUIntParameter(timings, "WL"); memSpec->tWR = clk * queryUIntParameter(timings, "WR"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tXS = clk * queryUIntParameter(timings, "XS"); - memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tCCD_R = clk * queryUIntParameter(timings, "CCD_R"); + memSpec->tCCD_W = clk * queryUIntParameter(timings, "CCD_W"); memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRP = clk * queryUIntParameter(timings, "RP"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index c1380122..5ea73ad9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -66,19 +66,17 @@ sc_time MemSpecWideIO::getExecutionTime(Command command) const return tRP; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + else if (command == Command::RD || command == Command::RDA) return tRL + getReadAccessTime(); - else if (command == Command::RDA) - // this time is wrong (controller internally waits for tRAS) - return tRTP + tRP; - else if (command == Command::WR) +// else if (command == Command::RDA) +// // this time is wrong (controller internally waits for tRAS) +// return tRTP + tRP; + else if (command == Command::WR || command == Command::WRA) return tWL + getWriteAccessTime(); - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; +// else if (command == Command::WRA) +// return tWL + getWriteAccessTime() + tWR + tRP; else if (command == Command::REFA) return tRFC; - else if (command == Command::REFB) - return tRFC; else { SC_REPORT_FATAL("getExecutionTime", diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 5fe55613..7185b25a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -47,7 +47,6 @@ struct MemSpecWideIO : public MemSpec sc_time tRC; // RAS-cycle-time (min time bw 2 succesive ACT to same bank) sc_time tRCD; // act -> read/write sc_time tRL; // read latency (read command start to data strobe) - sc_time tRTP; // read to precharge sc_time tWL; // write latency sc_time tWR; // write recovery (write to precharge) sc_time tXP; // min delay to row access command after pdnpx pdnax @@ -56,7 +55,8 @@ struct MemSpecWideIO : public MemSpec sc_time tRFC; sc_time tRP; sc_time tDQSCK; - sc_time tCCD; + sc_time tCCD_R; + sc_time tCCD_W; sc_time tRRD; sc_time tTAW; sc_time tWTR; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 5ac42425..14b4caf8 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -204,9 +204,8 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); } else - { reportFatal("CheckerDDR3", "Unknown command!"); - } + // Check if command bus is free earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 80081016..ba999d03 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -41,13 +41,6 @@ CheckerDDR4::CheckerDDR4() if (memSpec == nullptr) SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); - if (config.ControllerCoreRefDisable) - refreshChecker = new RefreshCheckerDDR4Dummy(memSpec); - else if (config.BankwiseLogic) - refreshChecker = new RefreshCheckerDDR4Bankwise(memSpec); - else - refreshChecker = new RefreshCheckerDDR4(memSpec); - lastScheduledByCommandAndBank = std::vector> (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); lastScheduledByCommandAndBankGroup = std::vector> @@ -61,11 +54,6 @@ CheckerDDR4::CheckerDDR4() burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; } -CheckerDDR4::~CheckerDDR4() -{ - delete refreshChecker; -} - sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const { sc_time lastCommandStart; @@ -86,6 +74,10 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); @@ -102,14 +94,8 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - if (lastActivates[rank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); - - refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } else if (command == Command::RD || command == Command::RDA) { @@ -151,8 +137,6 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTR_S); - - refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); } else if (command == Command::WR || command == Command::WRA) { @@ -184,8 +168,6 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S); - - refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); } else if (command == Command::PRE) { @@ -200,15 +182,62 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWR); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); - refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWR); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); } else - { reportFatal("CheckerDDR4", "Unknown command!"); - } + // Check if command bus is free - earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); return (earliestTimeToStart - sc_time_stamp()); } @@ -222,7 +251,7 @@ void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank b lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - lastScheduled = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp(); if (command == Command::ACT) { @@ -230,75 +259,4 @@ void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank b lastActivates[rank.ID()].pop(); lastActivates[rank.ID()].push(sc_time_stamp()); } - else if (command == Command::REFA || command == Command::REFB) - refreshChecker->insert(bank); -} - -// TODO: max(earliestTimeToStart, ...) needed? -void RefreshCheckerDDR4::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR4::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR4::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - burstClocks - memSpec->tWR)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR4::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= timeForNextPREA) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerDDR4::insert(Bank) -{ - timeForNextREFA += memSpec->tREFI; - timeForNextPREA += memSpec->tREFI; -} - -RefreshCheckerDDR4Bankwise::RefreshCheckerDDR4Bankwise(const MemSpecDDR4 *memSpec) - : RefreshCheckerDDR4Dummy(memSpec) -{ - sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - { - timesForNextREFB.push_back(currentREFB); - timesForNextPRE.push_back(currentPRE); - currentREFB += memSpec->clk; - currentPRE += memSpec->clk; - } -} - -void RefreshCheckerDDR4Bankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerDDR4Bankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerDDR4Bankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - burstClocks - memSpec->tWR)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerDDR4Bankwise::insert(Bank bank) -{ - timesForNextREFB[bank.ID()] += memSpec->tREFI; - timesForNextPRE[bank.ID()] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 581c4821..9c1cc8f6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -41,13 +41,10 @@ #include "../../configuration/memspec/MemSpecDDR4.h" #include "../../configuration/Configuration.h" -class RefreshCheckerDDR4Dummy; - class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - ~CheckerDDR4(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; void insert(Command, Rank, BankGroup, Bank); @@ -58,70 +55,15 @@ private: std::vector> lastScheduledByCommandAndBankGroup; std::vector> lastScheduledByCommandAndRank; std::vector lastScheduledByCommand; - sc_time lastScheduled; + sc_time lastCommandOnBus; // Four activate window std::vector> lastActivates; - RefreshCheckerDDR4Dummy *refreshChecker; - sc_time burstClocks; // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; -class RefreshCheckerDDR4Dummy -{ -protected: - friend class CheckerDDR4; - RefreshCheckerDDR4Dummy(const MemSpecDDR4 *memSpec) : memSpec(memSpec) - { - burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; - } - virtual ~RefreshCheckerDDR4Dummy() {} - - virtual void delayToSatisfyACT(Bank, sc_time &) {} - virtual void delayToSatisfyRD(Bank, sc_time &) {} - virtual void delayToSatisfyWR(Bank, sc_time &) {} - virtual void delayToSatisfyPRE(Bank, sc_time &) {} - virtual void insert(Bank) {} - - const MemSpecDDR4 *memSpec; - - sc_time burstClocks; -}; - -class RefreshCheckerDDR4 final : public RefreshCheckerDDR4Dummy -{ -private: - friend class CheckerDDR4; - RefreshCheckerDDR4(const MemSpecDDR4 *memSpec) - : RefreshCheckerDDR4Dummy(memSpec) {} - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void delayToSatisfyPRE(Bank, sc_time &); - void insert(Bank); - - sc_time timeForNextREFA = memSpec->tREFI; - sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; -}; - -class RefreshCheckerDDR4Bankwise final : public RefreshCheckerDDR4Dummy -{ -private: - friend class CheckerDDR4; - RefreshCheckerDDR4Bankwise(const MemSpecDDR4 *); - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void insert(Bank); - - std::vector timesForNextREFB; - std::vector timesForNextPRE; -}; - #endif // CHECKERDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index 8bd46f3f..a8ca0002 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -41,8 +41,6 @@ #include "../../configuration/memspec/MemSpecLPDDR4.h" #include "../../configuration/Configuration.h" -class RefreshCheckerLPDDR4Dummy; - class CheckerLPDDR4 final : public CheckerIF { public: diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 065f954a..c0ac78a7 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -41,13 +41,6 @@ CheckerWideIO::CheckerWideIO() if (memSpec == nullptr) SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); - if (config.ControllerCoreRefDisable) - refreshChecker = new RefreshCheckerWideIODummy(memSpec); - else if (config.BankwiseLogic) - refreshChecker = new RefreshCheckerWideIOBankwise(memSpec); - else - refreshChecker = new RefreshCheckerWideIO(memSpec); - lastScheduledByCommandAndBank = std::vector> (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); lastScheduledByCommandAndRank = std::vector> @@ -55,11 +48,8 @@ CheckerWideIO::CheckerWideIO() lastScheduledByCommand = std::vector(numberOfCommands()); lastActivates = std::vector>(memSpec->NumberOfRanks); -} -CheckerWideIO::~CheckerWideIO() -{ - delete refreshChecker; + burstClocks = memSpec->BurstLength * memSpec->clk; } sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -71,16 +61,21 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban { lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + + burstClocks - memSpec->clk + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); @@ -93,14 +88,8 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); - if (lastActivates[rank.ID()].size() >= 2) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tTAW); - - refreshChecker->delayToSatisfyACT(bank, earliestTimeToStart); } else if (command == Command::RD || command == Command::RDA) { @@ -109,13 +98,21 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR); - refreshChecker->delayToSatisfyRD(bank, earliestTimeToStart); + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR); } else if (command == Command::WR || command == Command::WRA) { @@ -124,13 +121,21 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + burstClocks + memSpec->clk); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + burstClocks + memSpec->clk); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); - refreshChecker->delayToSatisfyWR(bank, earliestTimeToStart); + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); } else if (command == Command::PRE) { @@ -139,13 +144,62 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); - refreshChecker->delayToSatisfyPRE(bank, earliestTimeToStart); + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); } else { @@ -173,75 +227,4 @@ void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) lastActivates[rank.ID()].pop(); lastActivates[rank.ID()].push(sc_time_stamp()); } - else if (command == Command::REFA || command == Command::REFB) - refreshChecker->insert(bank); -} - -// TODO: max(earliestTimeToStart, ...) needed? -void RefreshCheckerWideIO::delayToSatisfyACT(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRAS)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerWideIO::delayToSatisfyRD(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tRTP)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerWideIO::delayToSatisfyWR(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timeForNextPREA - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerWideIO::delayToSatisfyPRE(Bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= timeForNextPREA) - earliestTimeToStart = timeForNextREFA + memSpec->tRFC; -} - -void RefreshCheckerWideIO::insert(Bank) -{ - timeForNextREFA += memSpec->tREFI; - timeForNextPREA += memSpec->tREFI; -} - -RefreshCheckerWideIOBankwise::RefreshCheckerWideIOBankwise(const MemSpecWideIO *memSpec) - : RefreshCheckerWideIODummy(memSpec) -{ - sc_time currentREFB = memSpec->tREFI - memSpec->clk * (memSpec->NumberOfBanks - 1); - sc_time currentPRE = currentREFB - std::max(memSpec->clk * memSpec->NumberOfBanks, memSpec->tRP); - for (unsigned bankID = 0; bankID < memSpec->NumberOfBanks; bankID++) - { - timesForNextREFB.push_back(currentREFB); - timesForNextPRE.push_back(currentPRE); - currentREFB += memSpec->clk; - currentPRE += memSpec->clk; - } -} - -void RefreshCheckerWideIOBankwise::delayToSatisfyACT(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRAS)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerWideIOBankwise::delayToSatisfyRD(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tRTP)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerWideIOBankwise::delayToSatisfyWR(Bank bank, sc_time &earliestTimeToStart) -{ - if (earliestTimeToStart >= (timesForNextPRE[bank.ID()] - memSpec->tWL - memSpec->tCCD - memSpec->tWR)) - earliestTimeToStart = timesForNextREFB[bank.ID()] + memSpec->tRFC; -} - -void RefreshCheckerWideIOBankwise::insert(Bank bank) -{ - timesForNextREFB[bank.ID()] += memSpec->tREFI; - timesForNextPRE[bank.ID()] += memSpec->tREFI; } diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 58fb4560..bb90da75 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -41,13 +41,10 @@ #include "../../configuration/memspec/MemSpecWideIO.h" #include "../../configuration/Configuration.h" -class RefreshCheckerWideIODummy; - class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - ~CheckerWideIO(); sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; void insert(Command, Rank, BankGroup, Bank); @@ -62,58 +59,10 @@ private: // Four activate window std::vector> lastActivates; - RefreshCheckerWideIODummy *refreshChecker; + sc_time burstClocks; // PowerDown TODO: Implement this method? //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; -class RefreshCheckerWideIODummy -{ -protected: - friend class CheckerWideIO; - RefreshCheckerWideIODummy(const MemSpecWideIO *memSpec) : memSpec(memSpec) {} - virtual ~RefreshCheckerWideIODummy() {} - - virtual void delayToSatisfyACT(Bank, sc_time &) {} - virtual void delayToSatisfyRD(Bank, sc_time &) {} - virtual void delayToSatisfyWR(Bank, sc_time &) {} - virtual void delayToSatisfyPRE(Bank, sc_time &) {} - virtual void insert(Bank) {} - - const MemSpecWideIO *memSpec; -}; - -class RefreshCheckerWideIO final : public RefreshCheckerWideIODummy -{ -private: - friend class CheckerWideIO; - RefreshCheckerWideIO(const MemSpecWideIO *memSpec) - : RefreshCheckerWideIODummy(memSpec) {} - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void delayToSatisfyPRE(Bank, sc_time &); - void insert(Bank); - - sc_time timeForNextREFA = memSpec->tREFI; - sc_time timeForNextPREA = timeForNextREFA - memSpec->tRP; -}; - -class RefreshCheckerWideIOBankwise final : public RefreshCheckerWideIODummy -{ -private: - friend class CheckerWideIO; - RefreshCheckerWideIOBankwise(const MemSpecWideIO *); - - void delayToSatisfyACT(Bank, sc_time &); - void delayToSatisfyRD(Bank, sc_time &); - void delayToSatisfyWR(Bank, sc_time &); - void insert(Bank); - - std::vector timesForNextREFB; - std::vector timesForNextPRE; -}; - #endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index 98699d02..1eb2390f 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -77,9 +77,9 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.RRDB_L = memSpec->tRRD / clk; memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = 0; - memTimingSpec.CCD = memSpec->tCCD / clk; - memTimingSpec.CCD_L = memSpec->tCCD / clk; - memTimingSpec.CCD_S = memSpec->tCCD / clk; + memTimingSpec.CCD = memSpec->BurstLength; + memTimingSpec.CCD_L = memSpec->BurstLength; + memTimingSpec.CCD_S = memSpec->BurstLength; memTimingSpec.CKE = memSpec->tCKE / clk; memTimingSpec.CKESR = memSpec->tCKESR / clk; memTimingSpec.clkMhz = memSpec->clkMHz; @@ -97,7 +97,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memTimingSpec.RRD = memSpec->tRRD / clk; memTimingSpec.RRD_L = memSpec->tRRD / clk; memTimingSpec.RRD_S = memSpec->tRRD / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.RTP = memSpec->BurstLength; memTimingSpec.TAW = memSpec->tTAW / clk; memTimingSpec.WL = memSpec->tWL / clk; memTimingSpec.WR = memSpec->tWR / clk; From 65db413a20444ea9fb4a706e10c2b4b849985e97 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 8 Oct 2019 14:14:42 +0200 Subject: [PATCH 125/183] Included MemSpecWideIO2, some adaptions for all memspecs. --- .../amconfigs/am_wideio2_4x64_4x2Gb_brc.xml | 11 ++ .../amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml | 8 +- .../JEDEC_256Mb_WIDEIO-200_128bit.xml | 3 +- .../JEDEC_256Mb_WIDEIO-266_128bit.xml | 3 +- .../JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml | 71 ++++------- .../JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml | 71 ++++------- .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml | 112 +++++------------- .../src/configuration/ConfigurationLoader.cpp | 110 +++++++++++++---- .../src/configuration/ConfigurationLoader.h | 1 + .../src/configuration/memspec/MemSpec.h | 10 -- .../src/configuration/memspec/MemSpecDDR3.h | 9 ++ .../src/configuration/memspec/MemSpecDDR4.h | 9 ++ .../src/configuration/memspec/MemSpecLPDDR4.h | 13 +- .../configuration/memspec/MemSpecWideIO.cpp | 8 +- .../src/configuration/memspec/MemSpecWideIO.h | 10 ++ .../configuration/memspec/MemSpecWideIO2.cpp | 86 ++++++++++++++ .../configuration/memspec/MemSpecWideIO2.h | 79 ++++++++++++ 17 files changed, 386 insertions(+), 228 deletions(-) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml new file mode 100644 index 00000000..cada45b2 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml index 94ac21ae..fc952eba 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml @@ -2,10 +2,10 @@ - - - - + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml index 838ee7f7..99fc35e7 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.xml @@ -21,7 +21,8 @@ - + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml index 39da583f..62abc699 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.xml @@ -21,7 +21,8 @@ - + + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml index 1d4023c3..d2c14626 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.xml @@ -13,54 +13,31 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml index 598303ad..901e0b21 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.xml @@ -13,54 +13,31 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml index 75a2cf67..562e1e07 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.xml @@ -13,88 +13,38 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index 42bf68cf..eaacaf3e 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -41,6 +41,7 @@ #include "memspec/MemSpecDDR4.h" #include "memspec/MemSpecWideIO.h" #include "memspec/MemSpecLPDDR4.h" +#include "memspec/MemSpecWideIO2.h" #include "../common/timingCalculations.h" using namespace tinyxml2; @@ -168,6 +169,12 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, loadCommons(config, memspec); loadWideIO(config, memspec); } + else if (memoryType == "WIDEIO2") + { + Configuration::getInstance().memSpec = new MemSpecWideIO2(); + loadCommons(config, memspec); + loadWideIO2(config, memspec); + } else reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } @@ -191,17 +198,6 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz"); memSpec->clk = FrequencyToClk(memSpec->clkMHz); - - // Currents and voltages - XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); - memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); - memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); - memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); - memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); - memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); - memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); - memSpec->vDD = queryDoubleParameter(powers, "vdd"); } void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) @@ -245,8 +241,16 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - // Currents and Volatages: TODO Check if this is correct. + // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0"); @@ -313,8 +317,16 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL"); - // Currents and Volatages: + // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1"); @@ -324,7 +336,6 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } -// TODO: change timings for LPDDR4 void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) { MemSpecLPDDR4 *memSpec = dynamic_cast(config.memSpec); @@ -372,15 +383,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE"); - // Currents and Volatages: - XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); - memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); - memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p"); - memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p2"); - memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p"); - memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p2"); - memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); - memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); + // Currents and voltages + // TODO: to be completed } void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) @@ -403,7 +407,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) sc_time clk = memSpec->clk; memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); - //memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tAC = clk * queryUIntParameter(timings, "AC"); memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); memSpec->tRC = clk * queryUIntParameter(timings, "RC"); memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); @@ -421,8 +426,16 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) memSpec->tTAW = clk * queryUIntParameter(timings, "TAW"); memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); - // Currents and Volatages: + // Currents and voltages XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec"); + memSpec->iDD0 = queryDoubleParameter(powers, "idd0"); + memSpec->iDD2N = queryDoubleParameter(powers, "idd2n"); + memSpec->iDD3N = queryDoubleParameter(powers, "idd3n"); + memSpec->iDD4R = queryDoubleParameter(powers, "idd4r"); + memSpec->iDD4W = queryDoubleParameter(powers, "idd4w"); + memSpec->iDD5 = queryDoubleParameter(powers, "idd5"); + memSpec->iDD6 = queryDoubleParameter(powers, "idd6"); + memSpec->vDD = queryDoubleParameter(powers, "vdd"); memSpec->iDD02 = queryDoubleParameter(powers, "idd02"); memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0"); memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02"); @@ -440,3 +453,50 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec) memSpec->iDD62 = queryDoubleParameter(powers, "idd62"); memSpec->vDD2 = queryDoubleParameter(powers, "vdd2"); } + +void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecWideIO2 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = 1; + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + + // MemTimings specific for WideIO + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + sc_time clk = memSpec->clk; + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tRCpb = clk * queryUIntParameter(timings, "RCPB"); + memSpec->tRCab = clk * queryUIntParameter(timings, "RCAB"); + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tXSR = clk * queryUIntParameter(timings, "XSR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tCCD = clk * queryUIntParameter(timings, "CCD"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRCD = clk * queryUIntParameter(timings, "RCD"); + memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB"); + memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTR = clk * queryUIntParameter(timings, "WTR"); + memSpec->tRRD = clk * queryUIntParameter(timings, "RRD"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB"); + memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB"); + + // Currents and voltages + // TODO: to be completed +} diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.h b/DRAMSys/library/src/configuration/ConfigurationLoader.h index 142a6918..9bcf77e4 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.h @@ -73,6 +73,7 @@ private: static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec); static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec); static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec); }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 98094d8b..dbb28264 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -87,16 +87,6 @@ struct MemSpec double clkMHz; sc_time clk; - // Currents and Voltages: - double iDD0; - double iDD2N; - double iDD3N; - double iDD4R; - double iDD4W; - double iDD5; - double iDD6; - double vDD; - // Command lengths on bus, standardly one clock cycle std::vector commandLength; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index d2345098..44c972c0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -64,6 +64,15 @@ struct MemSpecDDR3 : public MemSpec sc_time tXSDLL; sc_time tAL; + // Currents and Voltages: + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; double iDD2P0; double iDD2P1; double iDD3P0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 592b864a..ece11a56 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -67,6 +67,15 @@ struct MemSpecDDR4 : public MemSpec sc_time tXPDLL; sc_time tXSDLL; + // Currents and Voltages: + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; double iDD02; double iDD2P0; double iDD2P1; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 2cc80bfe..ed87d516 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -40,6 +40,8 @@ struct MemSpecLPDDR4 : public MemSpec { + MemSpecLPDDR4(); + // Memspec Variables: sc_time tREFI; sc_time tREFIpb; @@ -70,15 +72,8 @@ struct MemSpecLPDDR4 : public MemSpec sc_time tCKE; sc_time tCMDCKE; - double iDD02; - double iDD2P0; - double iDD2P1; - double iDD3P0; - double iDD3P1; - double iDD62; - double vDD2; - - MemSpecLPDDR4(); + // Currents and Voltages: + // TODO: to be completed sc_time getRefreshIntervalPB() const override; sc_time getRefreshIntervalAB() const override; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index 5ea73ad9..b5e9a90f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -49,9 +49,11 @@ sc_time MemSpecWideIO::getRefreshIntervalPB() const TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + return TimeInterval(sc_time_stamp() + tRL + tAC, + sc_time_stamp() + tRL + tAC + getReadAccessTime()); else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + return TimeInterval(sc_time_stamp() + tWL, + sc_time_stamp() + tWL + getWriteAccessTime()); else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); @@ -67,7 +69,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command) const else if (command == Command::ACT) return tRCD; else if (command == Command::RD || command == Command::RDA) - return tRL + getReadAccessTime(); + return tRL + tAC + getReadAccessTime(); // else if (command == Command::RDA) // // this time is wrong (controller internally waits for tRAS) // return tRTP + tRP; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 7185b25a..1f3ce38f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -55,12 +55,22 @@ struct MemSpecWideIO : public MemSpec sc_time tRFC; sc_time tRP; sc_time tDQSCK; + sc_time tAC; sc_time tCCD_R; sc_time tCCD_W; sc_time tRRD; sc_time tTAW; sc_time tWTR; + // Currents and Voltages: + double iDD0; + double iDD2N; + double iDD3N; + double iDD4R; + double iDD4W; + double iDD5; + double iDD6; + double vDD; double iDD02; double iDD2P0; double iDD2P02; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp new file mode 100644 index 00000000..a163acf4 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecWideIO2.h" + +sc_time MemSpecWideIO2::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecWideIO2::getRefreshIntervalPB() const +{ + return tREFIpb; +} + +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tDQSCK, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tDQSS, + sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} + +// Returns the execution time for commands that have a fixed execution time +sc_time MemSpecWideIO2::getExecutionTime(Command command) const +{ + if (command == Command::PRE) + return tRPpb; + else if (command == Command::PREA) + return tRPab; + else if (command == Command::ACT) + return tRCD; + else if (command == Command::RD || command == Command::RDA) + return tRL + tDQSCK + getReadAccessTime(); + else if (command == Command::WR || command == Command::WRA) + return tWL + tDQSS + getWriteAccessTime(); + else if (command == Command::REFA) + return tRFCab; + else if (command == Command::REFB) + return tRFCpb; + else + { + SC_REPORT_FATAL("MemSpecWideIO2::getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h new file mode 100644 index 00000000..d3000da4 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECWIDEIO2_H +#define MEMSPECWIDEIO2_H + +#include "MemSpec.h" + +struct MemSpecWideIO2 : public MemSpec +{ + // Memspec Variables: + sc_time tDQSCK; + sc_time tDQSS; + sc_time tCKE; + sc_time tRL; + sc_time tWL; + sc_time tRCpb; + sc_time tRCab; + sc_time tCKESR; + sc_time tXSR; + sc_time tXP; + sc_time tCCD; + sc_time tRTP; + sc_time tRCD; + sc_time tRPpb; + sc_time tRPab; + sc_time tRAS; + sc_time tWR; + sc_time tWTR; + sc_time tRRD; + sc_time tFAW; + sc_time tREFI; + sc_time tREFIpb; + sc_time tRFCab; + sc_time tRFCpb; + + // Currents and Voltages: + // TODO: to be completed + + sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + + sc_time getExecutionTime(Command) const override; + TimeInterval getIntervalOnDataStrobe(Command) const override; +}; + +#endif // MEMSPECWIDEIO2_H From a5b00ea3be1c48df9ec68b9aeafe7e1c3b3302d0 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 8 Oct 2019 15:27:18 +0200 Subject: [PATCH 126/183] Further inclusion of WideIO2. --- DRAMSys/library/library.pro | 34 +++++---- .../src/configuration/memspec/MemSpec.cpp | 4 +- .../src/configuration/memspec/MemSpecDDR3.h | 10 +-- .../src/configuration/memspec/MemSpecDDR4.h | 10 +-- .../src/configuration/memspec/MemSpecLPDDR4.h | 10 +-- .../src/configuration/memspec/MemSpecWideIO.h | 10 +-- .../configuration/memspec/MemSpecWideIO2.h | 10 +-- DRAMSys/library/src/controller/Controller.cpp | 3 + .../src/controller/checker/CheckerDDR3.h | 4 +- .../src/controller/checker/CheckerDDR4.h | 4 +- .../src/controller/checker/CheckerLPDDR4.h | 4 +- .../src/controller/checker/CheckerWideIO.h | 4 +- .../src/controller/checker/CheckerWideIO2.cpp | 74 +++++++++++++++++++ .../src/controller/checker/CheckerWideIO2.h | 66 +++++++++++++++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 11 +-- DRAMSys/library/src/simulation/DRAMSys.h | 4 +- .../src/simulation/{ => dram}/Dram.cpp | 18 ++--- .../library/src/simulation/{ => dram}/Dram.h | 12 +-- .../src/simulation/{ => dram}/DramDDR3.cpp | 6 +- .../src/simulation/{ => dram}/DramDDR3.h | 4 +- .../src/simulation/{ => dram}/DramDDR4.cpp | 6 +- .../src/simulation/{ => dram}/DramDDR4.h | 4 +- .../src/simulation/{ => dram}/DramLPDDR4.cpp | 2 +- .../src/simulation/{ => dram}/DramLPDDR4.h | 4 +- .../simulation/{ => dram}/DramRecordable.cpp | 11 ++- .../simulation/{ => dram}/DramRecordable.h | 15 ++-- .../src/simulation/{ => dram}/DramWideIO.cpp | 12 +-- .../src/simulation/{ => dram}/DramWideIO.h | 9 +-- .../src/simulation/dram/DramWideIO2.cpp | 59 +++++++++++++++ .../library/src/simulation/dram/DramWideIO2.h | 53 +++++++++++++ 30 files changed, 370 insertions(+), 107 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerWideIO2.h rename DRAMSys/library/src/simulation/{ => dram}/Dram.cpp (96%) rename DRAMSys/library/src/simulation/{ => dram}/Dram.h (91%) rename DRAMSys/library/src/simulation/{ => dram}/DramDDR3.cpp (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramDDR3.h (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramDDR4.cpp (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramDDR4.h (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramLPDDR4.cpp (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramLPDDR4.h (98%) rename DRAMSys/library/src/simulation/{ => dram}/DramRecordable.cpp (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramRecordable.h (90%) rename DRAMSys/library/src/simulation/{ => dram}/DramWideIO.cpp (97%) rename DRAMSys/library/src/simulation/{ => dram}/DramWideIO.h (95%) create mode 100644 DRAMSys/library/src/simulation/dram/DramWideIO2.cpp create mode 100644 DRAMSys/library/src/simulation/dram/DramWideIO2.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 88b450ef..52a33ecd 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -110,17 +110,17 @@ SOURCES += \ src/error/eccbaseclass.cpp \ src/error/ecchamming.cpp \ src/common/AddressDecoder.cpp \ - src/simulation/Dram.cpp \ + src/simulation/dram/Dram.cpp \ src/simulation/Arbiter.cpp \ src/common/CongenAddressDecoder.cpp \ src/common/XmlAddressDecoder.cpp \ src/common/timingCalculations.cpp \ src/common/dramExtensions.cpp \ src/common/utils.cpp \ - src/simulation/DramDDR3.cpp \ - src/simulation/DramDDR4.cpp \ - src/simulation/DramRecordable.cpp \ - src/simulation/DramWideIO.cpp \ + src/simulation/dram/DramDDR3.cpp \ + src/simulation/dram/DramDDR4.cpp \ + src/simulation/dram/DramRecordable.cpp \ + src/simulation/dram/DramWideIO.cpp \ src/configuration/memspec/MemSpec.cpp \ src/controller/BankMachine.cpp \ src/controller/Controller.cpp \ @@ -139,8 +139,11 @@ SOURCES += \ src/configuration/memspec/MemSpecWideIO.cpp \ src/configuration/memspec/MemSpecLPDDR4.cpp \ src/controller/checker/CheckerDDR4.cpp \ - src/simulation/DramLPDDR4.cpp \ - src/controller/checker/CheckerLPDDR4.cpp + src/simulation/dram/DramLPDDR4.cpp \ + src/controller/checker/CheckerLPDDR4.cpp \ + src/configuration/memspec/MemSpecWideIO2.cpp \ + src/simulation/dram/DramWideIO2.cpp \ + src/controller/checker/CheckerWideIO2.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -154,7 +157,7 @@ HEADERS += \ src/controller/core/powerdown/PowerDownManager.h \ src/simulation/TracePlayer.h \ src/simulation/MemoryManager.h \ - src/simulation/Dram.h \ + src/simulation/dram/Dram.h \ src/simulation/Arbiter.h \ src/common/libDRAMPower.h \ src/simulation/ReorderBuffer.h \ @@ -187,10 +190,10 @@ HEADERS += \ src/common/dramExtensions.h \ src/common/utils.h \ src/configuration/TemperatureSimConfig.h \ - src/simulation/DramDDR3.h \ - src/simulation/DramDDR4.h \ - src/simulation/DramRecordable.h \ - src/simulation/DramWideIO.h \ + src/simulation/dram/DramDDR3.h \ + src/simulation/dram/DramDDR4.h \ + src/simulation/dram/DramRecordable.h \ + src/simulation/dram/DramWideIO.h \ src/controller/GenericController.h \ src/controller/BankMachine.h \ src/controller/Controller.h \ @@ -213,8 +216,11 @@ HEADERS += \ src/configuration/memspec/MemSpecDDR4.h \ src/configuration/memspec/MemSpecLPDDR4.h \ src/controller/checker/CheckerDDR4.h \ - src/simulation/DramLPDDR4.h \ - src/controller/checker/CheckerLPDDR4.h + src/simulation/dram/DramLPDDR4.h \ + src/controller/checker/CheckerLPDDR4.h \ + src/configuration/memspec/MemSpecWideIO2.h \ + src/simulation/dram/DramWideIO2.h \ + src/controller/checker/CheckerWideIO2.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index d7e77ab3..6e96ff4a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -35,8 +35,8 @@ #include "MemSpec.h" -#include -#include +#include +#include #include "../../controller/Command.h" #include "../Configuration.h" diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 44c972c0..0d05e964 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -38,7 +38,7 @@ #include "MemSpec.h" -struct MemSpecDDR3 : public MemSpec +struct MemSpecDDR3 final : public MemSpec { // Memspec Variables: sc_time tCKE; // min time in pdna or pdnp @@ -78,11 +78,11 @@ struct MemSpecDDR3 : public MemSpec double iDD3P0; double iDD3P1; - sc_time getRefreshIntervalAB() const override; - sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; + virtual sc_time getRefreshIntervalPB() const override; - sc_time getExecutionTime(Command) const override; - TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index ece11a56..3dd13a1e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -38,7 +38,7 @@ #include "MemSpec.h" -struct MemSpecDDR4 : public MemSpec +struct MemSpecDDR4 final : public MemSpec { // Memspec Variables: sc_time tCKE; // min time in pdna or pdnp @@ -84,11 +84,11 @@ struct MemSpecDDR4 : public MemSpec double iDD62; double vDD2; - sc_time getRefreshIntervalPB() const override; - sc_time getRefreshIntervalAB() const override; + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command) const override; - TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index ed87d516..af42c2ce 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -38,7 +38,7 @@ #include "MemSpec.h" -struct MemSpecLPDDR4 : public MemSpec +struct MemSpecLPDDR4 final : public MemSpec { MemSpecLPDDR4(); @@ -75,11 +75,11 @@ struct MemSpecLPDDR4 : public MemSpec // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalPB() const override; - sc_time getRefreshIntervalAB() const override; + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command) const override; - TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECLPDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 1f3ce38f..3d5715a3 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -38,7 +38,7 @@ #include "MemSpec.h" -struct MemSpecWideIO : public MemSpec +struct MemSpecWideIO final : public MemSpec { // Memspec Variables: sc_time tCKE; // min time in pdna or pdnp @@ -88,11 +88,11 @@ struct MemSpecWideIO : public MemSpec double iDD62; double vDD2; - sc_time getRefreshIntervalPB() const override; - sc_time getRefreshIntervalAB() const override; + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command) const override; - TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index d3000da4..129947d3 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -38,7 +38,7 @@ #include "MemSpec.h" -struct MemSpecWideIO2 : public MemSpec +struct MemSpecWideIO2 final : public MemSpec { // Memspec Variables: sc_time tDQSCK; @@ -69,11 +69,11 @@ struct MemSpecWideIO2 : public MemSpec // Currents and Voltages: // TODO: to be completed - sc_time getRefreshIntervalPB() const override; - sc_time getRefreshIntervalAB() const override; + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; - sc_time getExecutionTime(Command) const override; - TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; #endif // MEMSPECWIDEIO2_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 8b658d52..0c0ea178 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -45,6 +45,7 @@ #include "checker/CheckerDDR4.h" #include "checker/CheckerWideIO.h" #include "checker/CheckerLPDDR4.h" +#include "checker/CheckerWideIO2.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" @@ -68,6 +69,8 @@ Controller::Controller(sc_module_name name) : checker = new CheckerWideIO(); else if (memSpec->MemoryType == "LPDDR4") checker = new CheckerLPDDR4(); + else if (memSpec->MemoryType == "WIDEIO2") + checker = new CheckerWideIO2(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 10723fa2..55f36c9c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -45,8 +45,8 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; - void insert(Command, Rank, BankGroup, Bank); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; private: const MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 9c1cc8f6..ca85a4c3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -45,8 +45,8 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; - void insert(Command, Rank, BankGroup, Bank); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; private: const MemSpecDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index a8ca0002..b925b9e4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -45,8 +45,8 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; - void insert(Command, Rank, BankGroup, Bank); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; private: const MemSpecLPDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index bb90da75..9c0aa038 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -45,8 +45,8 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const; - void insert(Command, Rank, BankGroup, Bank); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; private: const MemSpecWideIO *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp new file mode 100644 index 00000000..b5183814 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerWideIO2.h" + +CheckerWideIO2::CheckerWideIO2() +{ + Configuration &config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen"); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); +} + +sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +{ + return SC_ZERO_TIME; +} + +void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp(); + + if (command == Command::ACT || command == Command::REFB) + { + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(sc_time_stamp()); + } +} diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h new file mode 100644 index 00000000..a909fb59 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERWIDEIO2_H +#define CHECKERWIDEIO2_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecWideIO2.h" +#include "../../configuration/Configuration.h" + +class CheckerWideIO2 final : public CheckerIF +{ +public: + CheckerWideIO2(); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; + +private: + const MemSpecWideIO2 *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastCommandOnBus; + + // Four activate window + std::vector> lastActivates; + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; +}; + +#endif // CHECKERWIDEIO2_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index e2d49595..ed71d28a 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -52,11 +52,12 @@ #include "../common/utils.h" #include "../simulation/TemperatureController.h" #include "../error/ecchamming.h" -#include "DramRecordable.h" -#include "DramDDR3.h" -#include "DramDDR4.h" -#include "DramWideIO.h" -#include "DramLPDDR4.h" +#include "dram/DramRecordable.h" +#include "dram/DramDDR3.h" +#include "dram/DramDDR4.h" +#include "dram/DramWideIO.h" +#include "dram/DramLPDDR4.h" +#include "dram/DramWideIO2.h" #include "../controller/Controller.h" #include "../controller/ControllerRecordable.h" diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index fa04d170..354241f0 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -42,7 +42,7 @@ #include #include -#include "DramRecordable.h" +#include "dram/Dram.h" #include "Arbiter.h" #include "TraceGenerator.h" #include "ReorderBuffer.h" @@ -52,6 +52,7 @@ #include "../common/tlm2_base_protocol_checker.h" #include "../error/eccbaseclass.h" #include "../controller/GenericController.h" +#include "../common/TlmRecorder.h" class DRAMSys : public sc_module { @@ -72,7 +73,6 @@ public: void logo(); - private: std::string traceName; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp similarity index 96% rename from DRAMSys/library/src/simulation/Dram.cpp rename to DRAMSys/library/src/simulation/dram/Dram.cpp index bd498d10..f2244acd 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -40,21 +40,21 @@ #include "Dram.h" #include -#include -#include +#include +#include #include #include #include #include #include #include -#include "../common/DebugManager.h" -#include "../common/dramExtensions.h" -#include "../common/timingCalculations.h" -#include "../configuration/Configuration.h" -#include "../common/protocol.h" -#include "../common/utils.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../common/DebugManager.h" +#include "../../common/dramExtensions.h" +#include "../../common/timingCalculations.h" +#include "../../configuration/Configuration.h" +#include "../../common/protocol.h" +#include "../../common/utils.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace tlm; using namespace Data; diff --git a/DRAMSys/library/src/simulation/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h similarity index 91% rename from DRAMSys/library/src/simulation/Dram.h rename to DRAMSys/library/src/simulation/dram/Dram.h index 7b1bf5e0..119be3a8 100644 --- a/DRAMSys/library/src/simulation/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -40,13 +40,13 @@ #ifndef DRAM_H #define DRAM_H -#include -#include +#include +#include #include -#include "../common/protocol.h" -#include "../configuration/Configuration.h" -#include "../configuration/memspec/MemSpec.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../common/protocol.h" +#include "../../configuration/Configuration.h" +#include "../../configuration/memspec/MemSpec.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace std; using namespace tlm; diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp similarity index 97% rename from DRAMSys/library/src/simulation/DramDDR3.cpp rename to DRAMSys/library/src/simulation/dram/DramDDR3.cpp index 0f507b74..55311aa5 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -36,9 +36,9 @@ #include "DramDDR3.h" #include "Dram.h" -#include "../configuration/Configuration.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/memspec/MemSpecDDR3.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecDDR3.h" DramDDR3::DramDDR3(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR3.h b/DRAMSys/library/src/simulation/dram/DramDDR3.h similarity index 97% rename from DRAMSys/library/src/simulation/DramDDR3.h rename to DRAMSys/library/src/simulation/dram/DramDDR3.h index fef6c7fa..1a51c471 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.h @@ -36,8 +36,8 @@ #ifndef DRAMDDR3_H #define DRAMDDR3_H -#include -#include +#include +#include #include "Dram.h" class DramDDR3 : public Dram diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp similarity index 97% rename from DRAMSys/library/src/simulation/DramDDR4.cpp rename to DRAMSys/library/src/simulation/dram/DramDDR4.cpp index f62eb99c..08bc4b14 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -36,9 +36,9 @@ #include "DramDDR4.h" #include "Dram.h" -#include "../configuration/Configuration.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/memspec/MemSpecDDR4.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecDDR4.h" DramDDR4::DramDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramDDR4.h b/DRAMSys/library/src/simulation/dram/DramDDR4.h similarity index 97% rename from DRAMSys/library/src/simulation/DramDDR4.h rename to DRAMSys/library/src/simulation/dram/DramDDR4.h index 3979c950..9bf17bd7 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.h @@ -36,8 +36,8 @@ #ifndef DRAMDDR4_H #define DRAMDDR4_H -#include -#include +#include +#include #include "Dram.h" class DramDDR4 : public Dram diff --git a/DRAMSys/library/src/simulation/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp similarity index 97% rename from DRAMSys/library/src/simulation/DramLPDDR4.cpp rename to DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp index 3041d406..4b0a9251 100644 --- a/DRAMSys/library/src/simulation/DramLPDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp @@ -35,7 +35,7 @@ #include "DramLPDDR4.h" -#include "../configuration/memspec/MemSpecLPDDR4.h" +#include "../../configuration/memspec/MemSpecLPDDR4.h" DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) { diff --git a/DRAMSys/library/src/simulation/DramLPDDR4.h b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h similarity index 98% rename from DRAMSys/library/src/simulation/DramLPDDR4.h rename to DRAMSys/library/src/simulation/dram/DramLPDDR4.h index 4377ec56..c63561b2 100644 --- a/DRAMSys/library/src/simulation/DramLPDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h @@ -36,8 +36,8 @@ #ifndef DRAMLPDDR4_H #define DRAMLPDDR4_H -#include -#include +#include +#include #include "Dram.h" class DramLPDDR4 : public Dram diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp similarity index 97% rename from DRAMSys/library/src/simulation/DramRecordable.cpp rename to DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 15093d8c..4b60cb6f 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -34,14 +34,16 @@ */ #include "DramRecordable.h" -#include -#include -#include "../common/TlmRecorder.h" + +#include +#include +#include "../../common/TlmRecorder.h" +#include "../../common/utils.h" #include "DramDDR3.h" #include "DramDDR4.h" #include "DramWideIO.h" #include "DramLPDDR4.h" -#include "../common/utils.h" +#include "DramWideIO2.h" using namespace tlm; @@ -144,4 +146,5 @@ template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; +template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h similarity index 90% rename from DRAMSys/library/src/simulation/DramRecordable.h rename to DRAMSys/library/src/simulation/dram/DramRecordable.h index df518bdc..c11f9a81 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -36,11 +36,11 @@ #ifndef DRAMRECORDABLE_H #define DRAMRECORDABLE_H -#include -#include -#include "DramDDR3.h" -#include "DramDDR4.h" -#include "../common/TlmRecorder.h" +#include +#include +#include "../../common/TlmRecorder.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" using namespace tlm; @@ -50,12 +50,11 @@ class DramRecordable final : public BaseDram public: DramRecordable(sc_module_name, TlmRecorder *); SC_HAS_PROCESS(DramRecordable); - ~DramRecordable(); private: - tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay); + virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, + tlm_phase &phase, sc_time &delay) override; TlmRecorder *tlmRecorder; libDRAMPower *DRAMPower; diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp similarity index 97% rename from DRAMSys/library/src/simulation/DramWideIO.cpp rename to DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 1eb2390f..2a320879 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -35,13 +35,13 @@ #include "DramWideIO.h" -#include -#include +#include +#include #include "Dram.h" -#include "../configuration/Configuration.h" -#include "../error/errormodel.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../configuration/memspec/MemSpecWideIO.h" +#include "../../configuration/Configuration.h" +#include "../../error/errormodel.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecWideIO.h" using namespace tlm; diff --git a/DRAMSys/library/src/simulation/DramWideIO.h b/DRAMSys/library/src/simulation/dram/DramWideIO.h similarity index 95% rename from DRAMSys/library/src/simulation/DramWideIO.h rename to DRAMSys/library/src/simulation/dram/DramWideIO.h index 56e0b39a..10aeb629 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.h @@ -36,10 +36,10 @@ #ifndef DRAMWIDEIO_H #define DRAMWIDEIO_H -#include -#include +#include +#include #include "Dram.h" -#include "../error/errormodel.h" +#include "../../error/errormodel.h" using namespace tlm; @@ -48,12 +48,11 @@ class DramWideIO : public Dram public: DramWideIO(sc_module_name); SC_HAS_PROCESS(DramWideIO); - virtual ~DramWideIO(); protected: virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, - tlm_phase &phase, sc_time &delay); + tlm_phase &phase, sc_time &delay) override; private: std::vector ememory; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp new file mode 100644 index 00000000..65299da3 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramWideIO2.h" + +#include "Dram.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecWideIO2.h" + +DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2"); + + // Parameters for DRAMPower + MemSpecWideIO2 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramWideIO2", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + { + SC_REPORT_FATAL("DramWideIO2", "DRAMPower not supported for WideIO2"); + } + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.h b/DRAMSys/library/src/simulation/dram/DramWideIO2.h new file mode 100644 index 00000000..674af83c --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMWIDEIO2_H +#define DRAMWIDEIO2_H + +#include +#include +#include "Dram.h" + +using namespace tlm; + +class DramWideIO2 : public Dram +{ +public: + DramWideIO2(sc_module_name); + SC_HAS_PROCESS(DramWideIO2); + virtual ~DramWideIO2() {} +}; + +#endif // DRAMWIDEIO2_H From 256abe449c942a27abcbcf54ee2190b3b85c3cba Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 9 Oct 2019 09:49:46 +0200 Subject: [PATCH 127/183] Included CheckerWideIO2, tPPD fix in CheckerLPDDR4. --- .../src/controller/checker/CheckerLPDDR4.cpp | 4 + .../src/controller/checker/CheckerWideIO2.cpp | 204 +++++++++++++++++- 2 files changed, 207 insertions(+), 1 deletion(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 825087a7..e8174a65 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -180,6 +180,10 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban // lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; // if (lastCommandStart != SC_ZERO_TIME) // earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); } else if (command == Command::REFA) { diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index b5183814..4a99d98a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -52,7 +52,209 @@ CheckerWideIO2::CheckerWideIO2() sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const { - return SC_ZERO_TIME; + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD + memSpec->clk - memSpec->tWL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD + memSpec->clk - memSpec->tWL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->clk); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab); + } + else if (command == Command::REFB) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb); + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + } + else + { + reportFatal("CheckerWideIO2", "Unknown command!"); + } + // Check if command bus is free + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + + return (earliestTimeToStart - sc_time_stamp()); } void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) From 606d273bee60c0e9cd4ac4c415e32c763d8d44bf Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 10 Oct 2019 15:21:58 +0200 Subject: [PATCH 128/183] Included memspec and dram component for HBM2. --- DRAMSys/library/library.pro | 8 +- .../src/configuration/memspec/MemSpecHBM2.cpp | 88 ++++++++++++++++++ .../src/configuration/memspec/MemSpecHBM2.h | 93 +++++++++++++++++++ .../library/src/simulation/dram/DramHBM2.cpp | 59 ++++++++++++ .../library/src/simulation/dram/DramHBM2.h | 53 +++++++++++ 5 files changed, 299 insertions(+), 2 deletions(-) create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h create mode 100644 DRAMSys/library/src/simulation/dram/DramHBM2.cpp create mode 100644 DRAMSys/library/src/simulation/dram/DramHBM2.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 52a33ecd..e67fc6f1 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -143,7 +143,9 @@ SOURCES += \ src/controller/checker/CheckerLPDDR4.cpp \ src/configuration/memspec/MemSpecWideIO2.cpp \ src/simulation/dram/DramWideIO2.cpp \ - src/controller/checker/CheckerWideIO2.cpp + src/controller/checker/CheckerWideIO2.cpp \ + src/configuration/memspec/MemSpecHBM2.cpp \ + src/simulation/dram/DramHBM2.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -220,7 +222,9 @@ HEADERS += \ src/controller/checker/CheckerLPDDR4.h \ src/configuration/memspec/MemSpecWideIO2.h \ src/simulation/dram/DramWideIO2.h \ - src/controller/checker/CheckerWideIO2.h + src/controller/checker/CheckerWideIO2.h \ + src/configuration/memspec/MemSpecHBM2.h \ + src/simulation/dram/DramHBM2.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp new file mode 100644 index 00000000..1ffc78f5 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecHBM2.h" + +MemSpecHBM2::MemSpecHBM2() +{ + commandLength[Command::ACT] = 2; +} + +sc_time MemSpecHBM2::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecHBM2::getRefreshIntervalPB() const +{ + return tREFISB; +} + +sc_time MemSpecHBM2::getExecutionTime(Command command) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) // TODO: read or write? + return tRCDRD + clk; + else if (command == Command::RD || command == Command::RDA) + return tRL + tDQSCK + getReadAccessTime(); + else if (command == Command::WR || command == Command::WRA) + return tWL + getWriteAccessTime(); + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFCSB; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tDQSCK, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, + sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h new file mode 100644 index 00000000..0448bcaa --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECHBM2_H +#define MEMSPECHBM2_H + +#include "MemSpec.h" + +struct MemSpecHBM2 final : public MemSpec +{ + MemSpecHBM2(); + + // Memspec Variables: + sc_time tDQSCK; +// sc_time tDQSQ; // TODO: check actual value of this parameter + sc_time tRC; + sc_time tRAS; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRRDL; + sc_time tRRDS; + sc_time tFAW; + sc_time tRTPL; + sc_time tRTPS; + sc_time tRP; + sc_time tRL; + sc_time tWL; + sc_time tPL; + sc_time tWR; + sc_time tCCDL; + sc_time tCCDS; +// sc_time tCCDR; // TODO: consecutive reads to different stack IDs + sc_time tWTRL; + sc_time tWTRS; + sc_time tRTW; + sc_time tXP; + sc_time tCKE; + sc_time tPD = tCKE; + sc_time tRDPDE = tRL + tPL + (BurstLength / 2) * clk + clk; + sc_time tWRPDE = tWL + tPL + (BurstLength / 2) * clk + clk + tWR; + sc_time tWRAPDE = tWL + tPL + (BurstLength / 2) * clk + clk + tWR; + sc_time tCKESR = tCKE + clk; + sc_time tRDSRE = tRL + tPL + (BurstLength / 2) * clk + clk; + sc_time tXS; + sc_time tRFC; + sc_time tRFCSB; + sc_time tRREFD; + sc_time tREFI; + sc_time tREFISB; + + // Currents and Voltages: + // TODO: to be completed + + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; + + virtual sc_time getExecutionTime(Command) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; +}; + +#endif // MEMSPECHBM2_H diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp new file mode 100644 index 00000000..cea6f476 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramHBM2.h" + +#include "Dram.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecHBM2.h" + +DramHBM2::DramHBM2(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2"); + + // Parameters for DRAMPower + MemSpecHBM2 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramHBM2", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + { + SC_REPORT_FATAL("DramHBM2", "DRAMPower not supported for HBM2"); + } + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.h b/DRAMSys/library/src/simulation/dram/DramHBM2.h new file mode 100644 index 00000000..84cb5d0b --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMHBM2_H +#define DRAMHBM2_H + +#include +#include +#include "Dram.h" + +using namespace tlm; + +class DramHBM2 : public Dram +{ +public: + DramHBM2(sc_module_name); + SC_HAS_PROCESS(DramHBM2); + virtual ~DramHBM2() {} +}; + +#endif // DRAMHBM2_H From f4803f4b8c0dab58098d3938c28a5596f7fca66a Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 10 Oct 2019 18:17:21 +0200 Subject: [PATCH 129/183] Included checker for HBM2. --- DRAMSys/library/library.pro | 6 +- .../src/configuration/ConfigurationLoader.cpp | 61 ++++ .../src/configuration/ConfigurationLoader.h | 1 + .../src/configuration/memspec/MemSpecHBM2.cpp | 2 +- .../src/configuration/memspec/MemSpecHBM2.h | 3 +- DRAMSys/library/src/controller/Controller.cpp | 3 + .../src/controller/checker/CheckerHBM2.cpp | 337 ++++++++++++++++++ .../src/controller/checker/CheckerHBM2.h | 72 ++++ DRAMSys/library/src/simulation/DRAMSys.cpp | 15 + .../src/simulation/dram/DramRecordable.cpp | 2 + 10 files changed, 497 insertions(+), 5 deletions(-) create mode 100644 DRAMSys/library/src/controller/checker/CheckerHBM2.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerHBM2.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index e67fc6f1..1e09b7ea 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -145,7 +145,8 @@ SOURCES += \ src/simulation/dram/DramWideIO2.cpp \ src/controller/checker/CheckerWideIO2.cpp \ src/configuration/memspec/MemSpecHBM2.cpp \ - src/simulation/dram/DramHBM2.cpp + src/simulation/dram/DramHBM2.cpp \ + src/controller/checker/CheckerHBM2.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -224,7 +225,8 @@ HEADERS += \ src/simulation/dram/DramWideIO2.h \ src/controller/checker/CheckerWideIO2.h \ src/configuration/memspec/MemSpecHBM2.h \ - src/simulation/dram/DramHBM2.h + src/simulation/dram/DramHBM2.h \ + src/controller/checker/CheckerHBM2.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index eaacaf3e..f67af551 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -42,6 +42,7 @@ #include "memspec/MemSpecWideIO.h" #include "memspec/MemSpecLPDDR4.h" #include "memspec/MemSpecWideIO2.h" +#include "memspec/MemSpecHBM2.h" #include "../common/timingCalculations.h" using namespace tinyxml2; @@ -175,6 +176,12 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, loadCommons(config, memspec); loadWideIO2(config, memspec); } + else if (memoryType == "HBM2") + { + Configuration::getInstance().memSpec = new MemSpecHBM2(); + loadCommons(config, memspec); + loadHBM2(config, memspec); + } else reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } @@ -500,3 +507,57 @@ void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec // Currents and voltages // TODO: to be completed } + +void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecHBM2 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + + // MemTimings specific for HBM2 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + sc_time clk = memSpec->clk; + memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); +// memSpec->tDQSQ = clk * queryUIntParameter(timings, "DQSQ"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); + memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); + memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tPL = clk * queryUIntParameter(timings, "PL"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); + memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); +// memSpec->tCCDR = clk * queryUIntParameter(timings, "CCDR"); + memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); + memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); + memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); +// memSpec->tPD = clk * queryUIntParameter(timings, "PD"); +// memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRFCSB = clk * queryUIntParameter(timings, "RFCSB"); + memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFISB = clk * queryUIntParameter(timings, "REFISB"); + + // Currents and voltages + // TODO: to be completed +} diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.h b/DRAMSys/library/src/configuration/ConfigurationLoader.h index 9bcf77e4..add7fc88 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.h @@ -74,6 +74,7 @@ private: static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec); static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec); static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadHBM2(Configuration &config, tinyxml2::XMLElement *memspec); }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 1ffc78f5..190aa56f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -82,7 +82,7 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const sc_time_stamp() + tWL + getWriteAccessTime()); else { - SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); + SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); return TimeInterval(); } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 0448bcaa..5c5d5a8f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -52,8 +52,7 @@ struct MemSpecHBM2 final : public MemSpec sc_time tRRDL; sc_time tRRDS; sc_time tFAW; - sc_time tRTPL; - sc_time tRTPS; + sc_time tRTP; sc_time tRP; sc_time tRL; sc_time tWL; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 0c0ea178..5b0e3269 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -46,6 +46,7 @@ #include "checker/CheckerWideIO.h" #include "checker/CheckerLPDDR4.h" #include "checker/CheckerWideIO2.h" +#include "checker/CheckerHBM2.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" @@ -71,6 +72,8 @@ Controller::Controller(sc_module_name name) : checker = new CheckerLPDDR4(); else if (memSpec->MemoryType == "WIDEIO2") checker = new CheckerWideIO2(); + else if (memSpec->MemoryType == "HBM2") + checker = new CheckerHBM2(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp new file mode 100644 index 00000000..2a960058 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerHBM2.h" + +CheckerHBM2::CheckerHBM2() +{ + Configuration &config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen"); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndBankGroup = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); + + burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; +} + +sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +{ + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRTP + memSpec->tRP - memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP - memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB - memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->clk); + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, + lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + } + else if (command == Command::RD || command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCASBus + memSpec->clk); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->clk); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + burstClocks + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + burstClocks + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCASBus + memSpec->clk); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + } + else if (command == Command::REFB) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + { + if (bankwiseRefreshCounter == 0) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + } + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk); + } + else + { + reportFatal("CheckerHBM2", "Unknown command!"); + } + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + + if (command == Command::RD || command == Command::RDA || command == Command::WR || command == Command::WRA) + lastCommandOnCASBus = sc_time_stamp(); + else if (command == Command::ACT) + lastCommandOnRASBus = sc_time_stamp() + memSpec->clk; + else + lastCommandOnRASBus = sc_time_stamp(); + + if (command == Command::ACT || command == Command::REFB) + { + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(lastCommandOnRASBus); + } + + if (command == Command::REFB) + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h new file mode 100644 index 00000000..d4e2d0ef --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERHBM2_H +#define CHECKERHBM2_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecHBM2.h" +#include "../../configuration/Configuration.h" + +class CheckerHBM2 final : public CheckerIF +{ +public: + CheckerHBM2(); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; + +private: + const MemSpecHBM2 *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastCommandOnRASBus; + sc_time lastCommandOnCASBus; + + // Four activate window + std::vector> lastActivates; + + sc_time burstClocks; + + unsigned bankwiseRefreshCounter = 0; + + // PowerDown TODO: Implement this method? + //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; +}; + +#endif // CHECKERHBM2_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index ed71d28a..b67309e4 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -58,6 +58,7 @@ #include "dram/DramWideIO.h" #include "dram/DramLPDDR4.h" #include "dram/DramWideIO2.h" +#include "dram/DramHBM2.h" #include "../controller/Controller.h" #include "../controller/ControllerRecordable.h" @@ -291,6 +292,20 @@ void DRAMSys::instantiateModules(const string &traceName, else dram = new DramLPDDR4(str.c_str()); } + else if (memoryType == "WIDEIO2") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramWideIO2(str.c_str()); + } + else if (memoryType == "HBM2") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramHBM2(str.c_str()); + } else { SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 4b60cb6f..279ccf1d 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -44,6 +44,7 @@ #include "DramWideIO.h" #include "DramLPDDR4.h" #include "DramWideIO2.h" +#include "DramHBM2.h" using namespace tlm; @@ -147,4 +148,5 @@ template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; +template class DramRecordable; From ed29186adce8beb354213d6d3498633177c88fd0 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 11 Oct 2019 20:35:45 +0200 Subject: [PATCH 130/183] Included HBM2 example, fixed fifo strict issue with HBM2's command buses. --- .../configs/amconfigs/am_hbm2_8Gb_pc_brc.xml | 9 ++++ .../amconfigs/am_lpddr4_8Gbx16_brc.xml | 8 +-- .../amconfigs/am_wideio2_4x64_4x2Gb_brc.xml | 2 +- .../configs/amconfigs/am_wideio_4x1Gb_brc.xml | 12 ++--- .../configs/amconfigs/am_wideio_4x1Gb_rbc.xml | 12 ++--- .../amconfigs/am_wideio_4x256Mb_brc.xml | 14 ++---- .../amconfigs/am_wideio_4x256Mb_rbc.xml | 14 ++---- .../configs/amconfigs/am_wideio_4x2Gb_brc.xml | 12 ++--- .../configs/amconfigs/am_wideio_4x2Gb_rbc.xml | 14 ++---- .../configs/amconfigs/am_wideio_4x4Gb_brc.xml | 4 -- .../configs/amconfigs/am_wideio_4x4Gb_rbc.xml | 12 ++--- .../amconfigs/am_wideio_4x512Mb_brc.xml | 12 ++--- .../amconfigs/am_wideio_4x512Mb_rbc.xml | 14 ++---- .../resources/configs/memspecs/HBM2.xml | 49 +++++++++++++++++++ .../resources/configs/simulator/hbm2.xml | 29 +++++++++++ .../resources/simulations/hbm2-example.xml | 25 ++++++++++ .../library/src/controller/BankMachine.cpp | 8 +-- DRAMSys/library/src/controller/Controller.cpp | 7 ++- 18 files changed, 166 insertions(+), 91 deletions(-) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml create mode 100644 DRAMSys/library/resources/configs/memspecs/HBM2.xml create mode 100644 DRAMSys/library/resources/configs/simulator/hbm2.xml create mode 100644 DRAMSys/library/resources/simulations/hbm2-example.xml diff --git a/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml new file mode 100644 index 00000000..24cf9469 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml @@ -0,0 +1,9 @@ + + + + + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml index efaf9f9b..4844bbf4 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml @@ -1,6 +1,6 @@ - - - - + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml index cada45b2..63c29bfc 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml @@ -1,4 +1,4 @@ - + diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml index ccaecd9c..ffce3d26 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml @@ -1,11 +1,7 @@ - - - - - - + + + + - - \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml index 2daf6367..cbed2266 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml @@ -1,11 +1,7 @@ - - - - - - + + + + - - \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml index 93db07f7..71f71bc8 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml @@ -1,11 +1,7 @@ - - - - - - - - - \ No newline at end of file + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml index 45b5153f..49e1a0ba 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml @@ -1,11 +1,7 @@ - - - - - - - - - \ No newline at end of file + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml index 8d044310..bbf25e41 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml @@ -1,11 +1,7 @@ - - - - - - + + + + - - \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml index 65cbcc32..cd213a33 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml @@ -1,11 +1,7 @@ - - - - - - - - - \ No newline at end of file + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml index ff474639..b330b0cd 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml @@ -1,5 +1,3 @@ - - @@ -7,5 +5,3 @@ - - \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml index 431d6176..7973505e 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml @@ -1,11 +1,7 @@ - - - - - - + + + + - - \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml index 97c6ad9f..b6de91b9 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml @@ -1,11 +1,7 @@ - - - - - - + + + + - - \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml index a2f0141c..52235bd4 100644 --- a/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml +++ b/DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml @@ -1,11 +1,7 @@ - - - - - - - - - \ No newline at end of file + + + + + \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.xml b/DRAMSys/library/resources/configs/memspecs/HBM2.xml new file mode 100644 index 00000000..9760bfbf --- /dev/null +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.xml @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.xml b/DRAMSys/library/resources/configs/simulator/hbm2.xml new file mode 100644 index 00000000..3bf50046 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/hbm2.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/DRAMSys/library/resources/simulations/hbm2-example.xml b/DRAMSys/library/resources/simulations/hbm2-example.xml new file mode 100644 index 00000000..2fac2e74 --- /dev/null +++ b/DRAMSys/library/resources/simulations/hbm2-example.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + ddr3_example.stl + + diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 99bd9809..802b3ad4 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -116,7 +116,7 @@ sc_time BankMachineOpen::start() { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return SC_ZERO_TIME; + return sc_max_time() - sc_time_stamp(); } sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); @@ -163,7 +163,7 @@ sc_time BankMachineClosed::start() { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return SC_ZERO_TIME; + return sc_max_time() - sc_time_stamp(); } sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); @@ -210,7 +210,7 @@ sc_time BankMachineOpenAdaptive::start() { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return SC_ZERO_TIME; + return sc_max_time() - sc_time_stamp(); } sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); @@ -275,7 +275,7 @@ sc_time BankMachineClosedAdaptive::start() { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return SC_ZERO_TIME; + return sc_max_time() - sc_time_stamp(); } sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 5b0e3269..5ddbc4ca 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -202,6 +202,7 @@ void Controller::controllerMethod() // (5) Choose one request and send it to DRAM std::pair commandPair; std::vector> readyCommands; + bool readyCmdBlocked = false; // (5.1) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) for (auto it : bankMachines) { @@ -219,7 +220,7 @@ void Controller::controllerMethod() if (!readyCommands.empty()) { commandPair = commandMux->selectCommand(readyCommands); - if (commandPair.second != nullptr) // TODO: can happen with FIFO strict + if (commandPair.second != nullptr) // can happen with FIFO strict { Rank rank = DramExtension::getRank(commandPair.second); if (commandPair.first == Command::PREA || commandPair.first == Command::REFA) @@ -235,13 +236,15 @@ void Controller::controllerMethod() refreshManagers[rank.ID()]->updateState(commandPair.first, commandPair.second); sendToDram(commandPair.first, commandPair.second); } + else + readyCmdBlocked = true; } // (6) Restart bank machines and refresh managers to issue new requests for the future for (auto it : bankMachines) { sc_time delay = it->start(); - if (delay != SC_ZERO_TIME) // TODO: must be checked to avoid livelock + if (delay != SC_ZERO_TIME || !readyCmdBlocked) // must be checked to avoid livelock controllerEvent.notify(delay); } for (auto it : refreshManagers) From 04a59c8bd23461ba61f03d8b03b678c8f3ee15ed Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 15 Oct 2019 16:03:34 +0200 Subject: [PATCH 131/183] Changed MemSpec::getExecutionTime() for different tRCDs. --- .../src/configuration/memspec/MemSpec.h | 2 +- .../src/configuration/memspec/MemSpecDDR3.cpp | 28 ++++++++-------- .../src/configuration/memspec/MemSpecDDR3.h | 2 +- .../src/configuration/memspec/MemSpecDDR4.cpp | 28 ++++++++-------- .../src/configuration/memspec/MemSpecDDR4.h | 2 +- .../src/configuration/memspec/MemSpecHBM2.cpp | 11 +++++-- .../src/configuration/memspec/MemSpecHBM2.h | 2 +- .../configuration/memspec/MemSpecLPDDR4.cpp | 2 +- .../src/configuration/memspec/MemSpecLPDDR4.h | 2 +- .../configuration/memspec/MemSpecWideIO.cpp | 32 +++++++++---------- .../src/configuration/memspec/MemSpecWideIO.h | 2 +- .../configuration/memspec/MemSpecWideIO2.cpp | 32 +++++++++---------- .../configuration/memspec/MemSpecWideIO2.h | 2 +- DRAMSys/library/src/simulation/dram/Dram.cpp | 18 +++++------ .../src/simulation/dram/DramRecordable.cpp | 6 ++-- .../src/simulation/dram/DramWideIO.cpp | 18 +++++------ 16 files changed, 97 insertions(+), 92 deletions(-) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index dbb28264..0e95ed05 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -59,7 +59,7 @@ struct MemSpec virtual sc_time getRefreshIntervalAB() const = 0; virtual sc_time getRefreshIntervalPB() const = 0; - virtual sc_time getExecutionTime(Command) const = 0; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const = 0; virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; unsigned getCommandLength(Command) const; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 16a5a75d..30e04c29 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -46,21 +46,8 @@ sc_time MemSpecDDR3::getRefreshIntervalPB() const return SC_ZERO_TIME; } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR3::getExecutionTime(Command command) const +sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -86,3 +73,16 @@ sc_time MemSpecDDR3::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 0d05e964..c8c7beac 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -81,7 +81,7 @@ struct MemSpecDDR3 final : public MemSpec virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 7c413340..ca0deeee 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -46,21 +46,8 @@ sc_time MemSpecDDR4::getRefreshIntervalPB() const return SC_ZERO_TIME; } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR4::getExecutionTime(Command command) const +sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -86,3 +73,16 @@ sc_time MemSpecDDR4::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 3dd13a1e..ecadfc18 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -87,7 +87,7 @@ struct MemSpecDDR4 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index 190aa56f..7fa61d1b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -50,12 +50,17 @@ sc_time MemSpecHBM2::getRefreshIntervalPB() const return tREFISB; } -sc_time MemSpecHBM2::getExecutionTime(Command command) const +sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload &payload) const { if (command == Command::PRE || command == Command::PREA) return tRP; - else if (command == Command::ACT) // TODO: read or write? - return tRCDRD + clk; + else if (command == Command::ACT) + { + if (payload.get_command() == TLM_READ_COMMAND) + return tRCDRD + clk; + else + return tRCDWR + clk; + } else if (command == Command::RD || command == Command::RDA) return tRL + tDQSCK + getReadAccessTime(); else if (command == Command::WR || command == Command::WRA) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 5c5d5a8f..d09c31c9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -85,7 +85,7 @@ struct MemSpecHBM2 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 2de71159..50afd825 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -60,7 +60,7 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const return tREFIpb; } -sc_time MemSpecLPDDR4::getExecutionTime(Command command) const +sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE) return tRPpb + clk; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index af42c2ce..67738e4e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -78,7 +78,7 @@ struct MemSpecLPDDR4 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index b5e9a90f..5b4c5316 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -46,23 +46,8 @@ sc_time MemSpecWideIO::getRefreshIntervalPB() const return SC_ZERO_TIME; } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tAC, - sc_time_stamp() + tRL + tAC + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL, - sc_time_stamp() + tWL + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO::getExecutionTime(Command command) const +sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE || command == Command::PREA) return tRP; @@ -86,3 +71,18 @@ sc_time MemSpecWideIO::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tAC, + sc_time_stamp() + tRL + tAC + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL, + sc_time_stamp() + tWL + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index 3d5715a3..e504c63b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -91,7 +91,7 @@ struct MemSpecWideIO final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index a163acf4..7d122e17 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -45,23 +45,8 @@ sc_time MemSpecWideIO2::getRefreshIntervalPB() const return tREFIpb; } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const -{ - if (command == Command::RD || command == Command::RDA) - return TimeInterval(sc_time_stamp() + tRL + tDQSCK, - sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); - else if (command == Command::WR || command == Command::WRA) - return TimeInterval(sc_time_stamp() + tWL + tDQSS, - sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); - else - { - SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); - } -} - // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecWideIO2::getExecutionTime(Command command) const +sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payload &) const { if (command == Command::PRE) return tRPpb; @@ -84,3 +69,18 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command) const return SC_ZERO_TIME; } } + +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tDQSCK, + sc_time_stamp() + tRL + tDQSCK + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tDQSS, + sc_time_stamp() + tWL + tDQSS + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 129947d3..4caff1e4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -72,7 +72,7 @@ struct MemSpecWideIO2 final : public MemSpec virtual sc_time getRefreshIntervalPB() const override; virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command) const override; + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; virtual TimeInterval getIntervalOnDataStrobe(Command) const override; }; diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index f2244acd..9f5cb4ef 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -128,18 +128,18 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); } else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PREA, - delay + memSpec->getExecutionTime(Command::PREA)); + delay + memSpec->getExecutionTime(Command::PREA, payload)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT)); + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); } else if (phase == BEGIN_WR) { @@ -150,7 +150,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR)); + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); } else if (phase == BEGIN_RD) { @@ -161,7 +161,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD)); + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); } else if (phase == BEGIN_WRA) { @@ -172,7 +172,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length()); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA)); + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } else if (phase == BEGIN_RDA) { @@ -183,19 +183,19 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, unsigned char *phyAddr = memory + payload.get_address(); memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length()); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA)); + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } else if (phase == BEGIN_REFB) { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFB)); + delay + memSpec->getExecutionTime(Command::REFB, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 279ccf1d..f52ee002 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -86,11 +86,11 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNAB) - recTime += this->memSpec->getExecutionTime(Command::PDXA); + recTime += this->memSpec->getExecutionTime(Command::PDXA, payload); else if (phase == END_PDNP || phase == END_PDNPB) - recTime += this->memSpec->getExecutionTime(Command::PDXP); + recTime += this->memSpec->getExecutionTime(Command::PDXP, payload); else if (phase == END_SREF || phase == END_SREFB) - recTime += this->memSpec->getExecutionTime(Command::SREFEX); + recTime += this->memSpec->getExecutionTime(Command::SREFEX, payload); unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID(); unsigned int ch __attribute__((unused)) = DramExtension::getExtension(payload).getChannel().ID(); diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 2a320879..232e3224 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -183,18 +183,18 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (phase == BEGIN_PRE) { DRAMPower->doCommand(MemCommand::PRE, bank, cycle); - sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE)); + sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload)); } else if (phase == BEGIN_PREA) { DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PREA, - delay + memSpec->getExecutionTime(Command::PREA)); + delay + memSpec->getExecutionTime(Command::PREA, payload)); } else if (phase == BEGIN_ACT) { DRAMPower->doCommand(MemCommand::ACT, bank, cycle); - sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT)); + sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -213,7 +213,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR)); + sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload)); } else if (phase == BEGIN_RD) { @@ -228,7 +228,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD)); + sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload)); } else if (phase == BEGIN_WRA) { @@ -243,7 +243,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->store(payload); } - sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA)); + sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload)); } else if (phase == BEGIN_RDA) { @@ -258,13 +258,13 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { ememory[bank]->load(payload); } - sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA)); + sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload)); } else if (phase == BEGIN_REFA) { DRAMPower->doCommand(MemCommand::REF, bank, cycle); sendToController(payload, END_REFA, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); if (StoreMode == StorageMode::ErrorModel) @@ -274,7 +274,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, { DRAMPower->doCommand(MemCommand::REFB, bank, cycle); sendToController(payload, END_REFB, - delay + memSpec->getExecutionTime(Command::REFA)); + delay + memSpec->getExecutionTime(Command::REFA, payload)); } // Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) From 2aa5d125c7e4c9b4df7cc5f99424bbb6669811bb Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 15 Oct 2019 16:09:59 +0200 Subject: [PATCH 132/183] Fixed BM deadlock. --- .../library/src/controller/BankMachine.cpp | 20 +++++++++++++++---- .../refresh/RefreshManagerBankwise.cpp | 3 +-- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 802b3ad4..753ebcce 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -112,12 +112,15 @@ BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Ban sc_time BankMachineOpen::start() { - if (currentPayload == nullptr) + if (blocked) + return sc_max_time() - sc_time_stamp(); + else if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } + sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss @@ -159,12 +162,15 @@ BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, sc_time BankMachineClosed::start() { - if (currentPayload == nullptr) + if (blocked) + return sc_max_time() - sc_time_stamp(); + else if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } + sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss @@ -206,12 +212,15 @@ BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, Checker sc_time BankMachineOpenAdaptive::start() { - if (currentPayload == nullptr) + if (blocked) + return sc_max_time() - sc_time_stamp(); + else if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } + sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss @@ -271,12 +280,15 @@ BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, Che sc_time BankMachineClosedAdaptive::start() { - if (currentPayload == nullptr) + if (blocked) + return sc_max_time() - sc_time_stamp(); + else if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } + sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 4934deb7..5ed1f428 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -201,8 +201,7 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p } else if (command == Command::PRE) { - if (nextCommand == Command::PRE && state == RmState::Regular - && DramExtension::getBank(payload) == currentBankMachine->getBank()) + if (nextCommand == Command::PRE && DramExtension::getBank(payload) == currentBankMachine->getBank()) { currentBankMachine->block(); state = RmState::Precharged; From a3fa363a879c2ecbaf45fdacc8a71ea6c471e343 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 15 Oct 2019 20:26:49 +0200 Subject: [PATCH 133/183] Bugfix for triggering controllerMethod() multiple times at the same time. --- DRAMSys/library/src/common/TlmRecorder.cpp | 4 ++-- DRAMSys/library/src/controller/BankMachine.cpp | 12 ++++++++---- DRAMSys/library/src/controller/BankMachine.h | 2 +- DRAMSys/library/src/controller/Controller.cpp | 9 +++++++-- DRAMSys/library/src/controller/Controller.h | 4 ++-- .../src/controller/refresh/RefreshManager.cpp | 3 ++- .../library/src/controller/refresh/RefreshManager.h | 4 ++-- .../controller/refresh/RefreshManagerBankwise.cpp | 3 ++- .../src/controller/refresh/RefreshManagerBankwise.h | 4 ++-- DRAMSys/library/src/simulation/StlPlayer.h | 1 + DRAMSys/library/src/simulation/TraceGenerator.h | 2 +- DRAMSys/library/src/simulation/TracePlayer.cpp | 4 +--- 12 files changed, 31 insertions(+), 21 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 4b4aba97..0a2f0c19 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -205,8 +205,8 @@ void TlmRecorder::Transaction::insertPhase(string name, sc_time begin) void TlmRecorder::Transaction::setPhaseEnd(string name, sc_time end) { // Find the latest recorder phase for that transaction with a matching name and update it - // Note: Transaction have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) only update the latest - // one that has been recorder + // Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) + // only update the latest one that has been recorded for (int i = recordedPhases.size() - 1; i >= 0; i--) { Phase &data = recordedPhases[i]; if (data.name == name) { diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 753ebcce..cf3238b8 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -112,6 +112,8 @@ BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Ban sc_time BankMachineOpen::start() { + timeToSchedule = sc_max_time(); + if (blocked) return sc_max_time() - sc_time_stamp(); else if (currentPayload == nullptr) @@ -120,7 +122,6 @@ sc_time BankMachineOpen::start() if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } - sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss @@ -162,6 +163,8 @@ BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, sc_time BankMachineClosed::start() { + timeToSchedule = sc_max_time(); + if (blocked) return sc_max_time() - sc_time_stamp(); else if (currentPayload == nullptr) @@ -170,7 +173,6 @@ sc_time BankMachineClosed::start() if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } - sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss @@ -212,6 +214,8 @@ BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, Checker sc_time BankMachineOpenAdaptive::start() { + timeToSchedule = sc_max_time(); + if (blocked) return sc_max_time() - sc_time_stamp(); else if (currentPayload == nullptr) @@ -220,7 +224,6 @@ sc_time BankMachineOpenAdaptive::start() if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } - sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss @@ -280,6 +283,8 @@ BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, Che sc_time BankMachineClosedAdaptive::start() { + timeToSchedule = sc_max_time(); + if (blocked) return sc_max_time() - sc_time_stamp(); else if (currentPayload == nullptr) @@ -288,7 +293,6 @@ sc_time BankMachineClosedAdaptive::start() if (currentPayload == nullptr) return sc_max_time() - sc_time_stamp(); } - sc_time delay; DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index bf7ca2f5..1e8e8d2c 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -80,7 +80,7 @@ protected: Row nextRow; BmState currentState = BmState::Precharged; Row currentRow; - sc_time timeToSchedule = SC_ZERO_TIME; + sc_time timeToSchedule = sc_max_time(); Rank rank = Rank(0); BankGroup bankgroup = BankGroup(0); Bank bank; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 5ddbc4ca..f3359a0f 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -124,7 +124,10 @@ Controller::Controller(sc_module_name name) : } if (config.ControllerCoreRefDisable) - refreshManagers.push_back(new RefreshManagerDummy()); + { + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + refreshManagers.push_back(new RefreshManagerDummy()); + } else if (config.BankwiseLogic) { for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) @@ -307,8 +310,9 @@ void Controller::releasePayload() payloadToRelease->release(); numberOfPayloads--; payloadToRelease = nullptr; - + timeToRelease = sc_max_time(); numberOfTransactionsServed++; + if (numberOfPayloads == 0) startBandwidthIdleCollector(); } @@ -327,6 +331,7 @@ void Controller::acquirePayload() payloadToAcquire->set_response_status(TLM_OK_RESPONSE); sendToFrontend(payloadToAcquire, END_REQ); payloadToAcquire = nullptr; + timeToAcquire = sc_max_time(); } void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index fd08a178..11e7e831 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -75,9 +75,9 @@ private: unsigned numberOfPayloads = 0; unsigned maxNumberOfPayloads; tlm_generic_payload *payloadToAcquire = nullptr; - sc_time timeToAcquire = SC_ZERO_TIME; + sc_time timeToAcquire = sc_max_time(); tlm_generic_payload *payloadToRelease = nullptr; - sc_time timeToRelease = SC_ZERO_TIME; + sc_time timeToRelease = sc_max_time(); std::queue> responseQueue; std::vector bankMachines; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 220a5f07..1abdf2ca 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -61,7 +61,8 @@ std::pair RefreshManager::getNextCommand() sc_time RefreshManager::start() { - timeToSchedule = SC_ZERO_TIME; + timeToSchedule = sc_max_time(); + if (sc_time_stamp() >= timeForNextTrigger) { if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index e30ebc83..542108a8 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -56,8 +56,8 @@ private: const MemSpec *memSpec; std::vector bankMachines; tlm_generic_payload refreshPayload; - sc_time timeForNextTrigger; - sc_time timeToSchedule = SC_ZERO_TIME; + sc_time timeForNextTrigger = sc_max_time(); + sc_time timeToSchedule = sc_max_time(); Rank rank; CheckerIF *checker; Command nextCommand; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 5ed1f428..e412d594 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -68,7 +68,8 @@ std::pair RefreshManagerBankwise::getNextCommand sc_time RefreshManagerBankwise::start() { - timeToSchedule = SC_ZERO_TIME; + timeToSchedule = sc_max_time(); + if (sc_time_stamp() >= timeForNextTrigger) { if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 4b176148..5f7b6948 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -58,8 +58,8 @@ private: const MemSpec *memSpec; std::vector bankMachines; std::vector refreshPayloads; - sc_time timeForNextTrigger; - sc_time timeToSchedule = SC_ZERO_TIME; + sc_time timeForNextTrigger = sc_max_time(); + sc_time timeToSchedule = sc_max_time(); Rank rank; CheckerIF *checker; Command nextCommand; diff --git a/DRAMSys/library/src/simulation/StlPlayer.h b/DRAMSys/library/src/simulation/StlPlayer.h index 3f27b624..e45e1233 100644 --- a/DRAMSys/library/src/simulation/StlPlayer.h +++ b/DRAMSys/library/src/simulation/StlPlayer.h @@ -89,6 +89,7 @@ public: } // Allocate a generic payload for this request. gp *payload = this->allocatePayload(); + payload->acquire(); unsigned char *data = payload->get_data_ptr(); // Trace files MUST provide timestamp, command and address for every diff --git a/DRAMSys/library/src/simulation/TraceGenerator.h b/DRAMSys/library/src/simulation/TraceGenerator.h index b96b5456..4631c5a9 100644 --- a/DRAMSys/library/src/simulation/TraceGenerator.h +++ b/DRAMSys/library/src/simulation/TraceGenerator.h @@ -64,7 +64,7 @@ public: } gp *payload = this->allocatePayload(); - + payload->acquire(); unsigned char *dataElement = new unsigned char[16]; // TODO: column / burst breite diff --git a/DRAMSys/library/src/simulation/TracePlayer.cpp b/DRAMSys/library/src/simulation/TracePlayer.cpp index ad727568..f9aa8fb6 100644 --- a/DRAMSys/library/src/simulation/TracePlayer.cpp +++ b/DRAMSys/library/src/simulation/TracePlayer.cpp @@ -77,16 +77,14 @@ void TracePlayer::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) { if (phase == BEGIN_REQ) { - payload.acquire(); sendToTarget(payload, phase, SC_ZERO_TIME); - transactionsSent++; PRINTDEBUGMESSAGE(name(), "Performing request #" + std::to_string(transactionsSent)); } else if (phase == END_REQ) { nextPayload(); } else if (phase == BEGIN_RESP) { - sendToTarget(payload, END_RESP, SC_ZERO_TIME); payload.release(); + sendToTarget(payload, END_RESP, SC_ZERO_TIME); if (Configuration::getInstance().SimulationProgressBar) listener->transactionFinished(); From 5f7cb7a32667986d813f18d1c40bb51a703a14ac Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 17 Oct 2019 15:00:28 +0200 Subject: [PATCH 134/183] Included memspec, dram and checker for GDDR5, GDDR5X and GDDR6. --- DRAMSys/library/library.pro | 22 +- .../src/configuration/ConfigurationLoader.cpp | 216 +++++++++- .../src/configuration/ConfigurationLoader.h | 3 + .../configuration/memspec/MemSpecGDDR5.cpp | 88 ++++ .../src/configuration/memspec/MemSpecGDDR5.h | 90 ++++ .../configuration/memspec/MemSpecGDDR5X.cpp | 88 ++++ .../src/configuration/memspec/MemSpecGDDR5X.h | 90 ++++ .../configuration/memspec/MemSpecGDDR6.cpp | 88 ++++ .../src/configuration/memspec/MemSpecGDDR6.h | 93 +++++ .../src/configuration/memspec/MemSpecHBM2.h | 12 +- DRAMSys/library/src/controller/Controller.cpp | 9 + .../src/controller/checker/CheckerDDR3.h | 3 - .../src/controller/checker/CheckerDDR4.h | 3 - .../src/controller/checker/CheckerGDDR5.cpp | 394 ++++++++++++++++++ .../src/controller/checker/CheckerGDDR5.h | 69 +++ .../src/controller/checker/CheckerGDDR5X.cpp | 394 ++++++++++++++++++ .../src/controller/checker/CheckerGDDR5X.h | 69 +++ .../src/controller/checker/CheckerGDDR6.cpp | 383 +++++++++++++++++ .../src/controller/checker/CheckerGDDR6.h | 68 +++ .../src/controller/checker/CheckerHBM2.h | 3 - .../src/controller/checker/CheckerIF.h | 3 - .../src/controller/checker/CheckerLPDDR4.h | 3 - .../src/controller/checker/CheckerWideIO.h | 3 - .../src/controller/checker/CheckerWideIO2.h | 3 - DRAMSys/library/src/simulation/DRAMSys.cpp | 24 ++ .../library/src/simulation/dram/DramDDR3.h | 1 - .../library/src/simulation/dram/DramDDR4.h | 1 - .../library/src/simulation/dram/DramGDDR5.cpp | 57 +++ .../library/src/simulation/dram/DramGDDR5.h | 50 +++ .../src/simulation/dram/DramGDDR5X.cpp | 57 +++ .../library/src/simulation/dram/DramGDDR5X.h | 50 +++ .../library/src/simulation/dram/DramGDDR6.cpp | 57 +++ .../library/src/simulation/dram/DramGDDR6.h | 51 +++ .../library/src/simulation/dram/DramHBM2.cpp | 2 - .../library/src/simulation/dram/DramHBM2.h | 3 - .../src/simulation/dram/DramLPDDR4.cpp | 5 +- .../library/src/simulation/dram/DramLPDDR4.h | 1 - .../src/simulation/dram/DramRecordable.cpp | 6 + .../src/simulation/dram/DramWideIO2.cpp | 2 - .../library/src/simulation/dram/DramWideIO2.h | 3 - 40 files changed, 2521 insertions(+), 46 deletions(-) create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp create mode 100644 DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h create mode 100644 DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerGDDR5.h create mode 100644 DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerGDDR5X.h create mode 100644 DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp create mode 100644 DRAMSys/library/src/controller/checker/CheckerGDDR6.h create mode 100644 DRAMSys/library/src/simulation/dram/DramGDDR5.cpp create mode 100644 DRAMSys/library/src/simulation/dram/DramGDDR5.h create mode 100644 DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp create mode 100644 DRAMSys/library/src/simulation/dram/DramGDDR5X.h create mode 100644 DRAMSys/library/src/simulation/dram/DramGDDR6.cpp create mode 100644 DRAMSys/library/src/simulation/dram/DramGDDR6.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 1e09b7ea..6ab96b7c 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -146,7 +146,16 @@ SOURCES += \ src/controller/checker/CheckerWideIO2.cpp \ src/configuration/memspec/MemSpecHBM2.cpp \ src/simulation/dram/DramHBM2.cpp \ - src/controller/checker/CheckerHBM2.cpp + src/controller/checker/CheckerHBM2.cpp \ + src/configuration/memspec/MemSpecGDDR5.cpp \ + src/configuration/memspec/MemSpecGDDR5X.cpp \ + src/configuration/memspec/MemSpecGDDR6.cpp \ + src/controller/checker/CheckerGDDR5.cpp \ + src/controller/checker/CheckerGDDR5X.cpp \ + src/controller/checker/CheckerGDDR6.cpp \ + src/simulation/dram/DramGDDR5.cpp \ + src/simulation/dram/DramGDDR5X.cpp \ + src/simulation/dram/DramGDDR6.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -226,7 +235,16 @@ HEADERS += \ src/controller/checker/CheckerWideIO2.h \ src/configuration/memspec/MemSpecHBM2.h \ src/simulation/dram/DramHBM2.h \ - src/controller/checker/CheckerHBM2.h + src/controller/checker/CheckerHBM2.h \ + src/configuration/memspec/MemSpecGDDR5.h \ + src/configuration/memspec/MemSpecGDDR5X.h \ + src/configuration/memspec/MemSpecGDDR6.h \ + src/controller/checker/CheckerGDDR5.h \ + src/controller/checker/CheckerGDDR5X.h \ + src/controller/checker/CheckerGDDR6.h \ + src/simulation/dram/DramGDDR5.h \ + src/simulation/dram/DramGDDR5X.h \ + src/simulation/dram/DramGDDR6.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp index f67af551..29a46b3e 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.cpp @@ -43,6 +43,9 @@ #include "memspec/MemSpecLPDDR4.h" #include "memspec/MemSpecWideIO2.h" #include "memspec/MemSpecHBM2.h" +#include "memspec/MemSpecGDDR5.h" +#include "memspec/MemSpecGDDR5X.h" +#include "memspec/MemSpecGDDR6.h" #include "../common/timingCalculations.h" using namespace tinyxml2; @@ -182,6 +185,24 @@ void ConfigurationLoader::loadMemSpec(Configuration &config, loadCommons(config, memspec); loadHBM2(config, memspec); } + else if (memoryType == "GDDR5") + { + Configuration::getInstance().memSpec = new MemSpecGDDR5(); + loadCommons(config, memspec); + loadGDDR5(config, memspec); + } + else if (memoryType == "GDDR5X") + { + Configuration::getInstance().memSpec = new MemSpecGDDR5X(); + loadCommons(config, memspec); + loadGDDR5X(config, memspec); + } + else if (memoryType == "GDDR6") + { + Configuration::getInstance().memSpec = new MemSpecGDDR6(); + loadCommons(config, memspec); + loadGDDR6(config, memspec); + } else reportFatal("ConfigurationLoader", "Unsupported DRAM type"); } @@ -549,8 +570,16 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); memSpec->tXP = clk * queryUIntParameter(timings, "XP"); memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); -// memSpec->tPD = clk * queryUIntParameter(timings, "PD"); -// memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tPD = memSpec->tCKE; + memSpec->tRDPDE = memSpec->tRL + memSpec->tPL + + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk; + memSpec->tWRPDE = memSpec->tWL + memSpec->tPL + + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR; + memSpec->tWRAPDE = memSpec->tWL + memSpec->tPL + + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk + memSpec->tWR; + memSpec->tCKESR = memSpec->tCKE + memSpec->clk; + memSpec->tRDSRE = memSpec->tRL + memSpec->tPL + + (memSpec->BurstLength / memSpec->DataRate + 1) * memSpec->clk; memSpec->tXS = clk * queryUIntParameter(timings, "XS"); memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); memSpec->tRFCSB = clk * queryUIntParameter(timings, "RFCSB"); @@ -561,3 +590,186 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec) // Currents and voltages // TODO: to be completed } + +void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecGDDR5 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + + // MemTimings specific for GDDR5 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); + memSpec->tCL = clk * queryUIntParameter(timings, "CL"); + memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tXPN = clk * queryUIntParameter(timings, "XPN"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->t32AW = clk * queryUIntParameter(timings, "32AW"); + memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; + memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); + memSpec->tLK = clk * queryUIntParameter(timings, "LK"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecGDDR5X *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + + // MemTimings specific for GDDR5X + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->t32AW = clk * queryUIntParameter(timings, "32AW"); + memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; + memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); + memSpec->tLK = clk * queryUIntParameter(timings, "LK"); + + // Currents and voltages + // TODO: to be completed +} + +void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec) +{ + MemSpecGDDR6 *memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); + + // MemArchitecture + XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->BanksPerRank = queryUIntParameter(architecture, "nbrOfBanks"); + memSpec->GroupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups"); + memSpec->BanksPerGroup = memSpec->BanksPerRank / memSpec->GroupsPerRank; + memSpec->NumberOfBanks = memSpec->BanksPerRank * memSpec->NumberOfRanks; + memSpec->NumberOfBankGroups = memSpec->GroupsPerRank * memSpec->NumberOfRanks; + + // MemTimings specific for GDDR6 + XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec"); + sc_time clk = memSpec->clk; + memSpec->tRP = clk * queryUIntParameter(timings, "RP"); + memSpec->tRAS = clk * queryUIntParameter(timings, "RAS"); + memSpec->tRC = clk * queryUIntParameter(timings, "RC"); + memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD"); + memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR"); + memSpec->tRTP = clk * queryUIntParameter(timings, "RTP"); + memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS"); + memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL"); + memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS"); + memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL"); + memSpec->tRL = clk * queryUIntParameter(timings, "RL"); + memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN"); + memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK"); + memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO"); + memSpec->tRTW = clk * queryUIntParameter(timings, "RTW"); + memSpec->tWL = clk * queryUIntParameter(timings, "WL"); + memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI"); + memSpec->tWR = clk * queryUIntParameter(timings, "WR"); + memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS"); + memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL"); + memSpec->tCKE = clk * queryUIntParameter(timings, "CKE"); + memSpec->tPD = memSpec->tCKE; + memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR"); + memSpec->tXP = clk * queryUIntParameter(timings, "XP"); + memSpec->tREFI = clk * queryUIntParameter(timings, "REFI"); + memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB"); + memSpec->tRFC = clk * queryUIntParameter(timings, "RFC"); + memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB"); + memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD"); + memSpec->tXS = clk * queryUIntParameter(timings, "XS"); + memSpec->tFAW = clk * queryUIntParameter(timings, "FAW"); + memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQO + memSpec->BurstLength / memSpec->DataRate * clk; + memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK + + memSpec->tWCK2DQI + memSpec->BurstLength / memSpec->DataRate * clk; + memSpec->tPPD = clk * queryUIntParameter(timings, "PPD"); + memSpec->tLK = clk * queryUIntParameter(timings, "LK"); + memSpec->tACTPDE = clk * queryUIntParameter(timings, "ACTPDE"); + memSpec->tPREPDE = clk * queryUIntParameter(timings, "PREPDE"); + memSpec->tREFPDE = clk * queryUIntParameter(timings, "REFPDE"); + + // Currents and voltages + // TODO: to be completed +} diff --git a/DRAMSys/library/src/configuration/ConfigurationLoader.h b/DRAMSys/library/src/configuration/ConfigurationLoader.h index add7fc88..b5ea9290 100644 --- a/DRAMSys/library/src/configuration/ConfigurationLoader.h +++ b/DRAMSys/library/src/configuration/ConfigurationLoader.h @@ -75,6 +75,9 @@ private: static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec); static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec); static void loadHBM2(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadGDDR5(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadGDDR5X(Configuration &config, tinyxml2::XMLElement *memspec); + static void loadGDDR6(Configuration &config, tinyxml2::XMLElement *memspec); }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp new file mode 100644 index 00000000..5bcbcbc6 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecGDDR5.h" + +sc_time MemSpecGDDR5::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecGDDR5::getRefreshIntervalPB() const +{ + return tREFIPB; +} + +sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payload &payload) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + { + if (payload.get_command() == TLM_READ_COMMAND) + return tRCDRD + clk; + else + return tRCDWR + clk; + } + else if (command == Command::RD || command == Command::RDA) + return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime(); + else if (command == Command::WR || command == Command::WRA) + return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime(); + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFCPB; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h new file mode 100644 index 00000000..c04bbfd2 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECGDDR5_H +#define MEMSPECGDDR5_H + +#include "MemSpec.h" + +struct MemSpecGDDR5 final : public MemSpec +{ + // Memspec Variables: + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRTP; + sc_time tRRDS; + sc_time tRRDL; + sc_time tCCDS; + sc_time tCCDL; + sc_time tCL; + sc_time tWCK2CKPIN; + sc_time tWCK2CK; + sc_time tWCK2DQO; + sc_time tRTW; + sc_time tWL; + sc_time tWCK2DQI; + sc_time tWR; + sc_time tWTRS; + sc_time tWTRL; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tXPN; + sc_time tREFI; + sc_time tREFIPB; + sc_time tRFC; + sc_time tRFCPB; + sc_time tRREFD; + sc_time tXS; + sc_time tFAW; + sc_time t32AW; + sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + sc_time tPPD; + sc_time tLK; + + // Currents and Voltages: + // TODO: to be completed + + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; + + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; +}; + +#endif // MEMSPECGDDR5_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp new file mode 100644 index 00000000..d7e148f6 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecGDDR5X.h" + +sc_time MemSpecGDDR5X::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecGDDR5X::getRefreshIntervalPB() const +{ + return tREFIPB; +} + +sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_payload &payload) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + { + if (payload.get_command() == TLM_READ_COMMAND) + return tRCDRD + clk; + else + return tRCDWR + clk; + } + else if (command == Command::RD || command == Command::RDA) + return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime(); + else if (command == Command::WR || command == Command::WRA) + return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime(); + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFCPB; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h new file mode 100644 index 00000000..a69d76ce --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECGDDR5X_H +#define MEMSPECGDDR5X_H + +#include "MemSpec.h" + +struct MemSpecGDDR5X final : public MemSpec +{ + // Memspec Variables: + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRTP; + sc_time tRRDS; + sc_time tRRDL; + sc_time tCCDS; + sc_time tCCDL; + sc_time tRL; + sc_time tWCK2CKPIN; + sc_time tWCK2CK; + sc_time tWCK2DQO; + sc_time tRTW; + sc_time tWL; + sc_time tWCK2DQI; + sc_time tWR; + sc_time tWTRS; + sc_time tWTRL; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tXP; + sc_time tREFI; + sc_time tREFIPB; + sc_time tRFC; + sc_time tRFCPB; + sc_time tRREFD; + sc_time tXS; + sc_time tFAW; + sc_time t32AW; + sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + sc_time tPPD; + sc_time tLK; + + // Currents and Voltages: + // TODO: to be completed + + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; + + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; +}; + +#endif // MEMSPECGDDR5X_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp new file mode 100644 index 00000000..9be62f01 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "MemSpecGDDR6.h" + +sc_time MemSpecGDDR6::getRefreshIntervalAB() const +{ + return tREFI; +} + +sc_time MemSpecGDDR6::getRefreshIntervalPB() const +{ + return tREFIPB; +} + +sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payload &payload) const +{ + if (command == Command::PRE || command == Command::PREA) + return tRP; + else if (command == Command::ACT) + { + if (payload.get_command() == TLM_READ_COMMAND) + return tRCDRD + clk; + else + return tRCDWR + clk; + } + else if (command == Command::RD || command == Command::RDA) + return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime(); + else if (command == Command::WR || command == Command::WRA) + return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime(); + else if (command == Command::REFA) + return tRFC; + else if (command == Command::REFB) + return tRFCPB; + else + { + SC_REPORT_FATAL("getExecutionTime", + "command not known or command doesn't have a fixed execution time"); + return SC_ZERO_TIME; + } +} + +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const +{ + if (command == Command::RD || command == Command::RDA) + return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, + sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime()); + else if (command == Command::WR || command == Command::WRA) + return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, + sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime()); + else + { + SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); + return TimeInterval(); + } +} diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h new file mode 100644 index 00000000..43924408 --- /dev/null +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef MEMSPECGDDR6_H +#define MEMSPECGDDR6_H + +#include "MemSpec.h" + +struct MemSpecGDDR6 final : public MemSpec +{ + // Memspec Variables: + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRCDRD; + sc_time tRCDWR; + sc_time tRTP; + sc_time tRRDS; + sc_time tRRDL; + sc_time tCCDS; + sc_time tCCDL; + sc_time tRL; + sc_time tWCK2CKPIN; + sc_time tWCK2CK; + sc_time tWCK2DQO; + sc_time tRTW; + sc_time tWL; + sc_time tWCK2DQI; + sc_time tWR; + sc_time tWTRS; + sc_time tWTRL; + sc_time tCKE; + sc_time tPD; // = tCKE; + sc_time tCKESR; + sc_time tXP; + sc_time tREFI; + sc_time tREFIPB; + sc_time tRFC; + sc_time tRFCPB; + sc_time tRREFD; + sc_time tXS; + sc_time tFAW; + sc_time tRDSRE; // = tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + BurstLength / DataRate * tCK; + sc_time tWRSRE; // = tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + BurstLength / DataRate * tCK; + sc_time tPPD; + sc_time tLK; + sc_time tACTPDE; + sc_time tPREPDE; + sc_time tREFPDE; + + // Currents and Voltages: + // TODO: to be completed + + virtual sc_time getRefreshIntervalPB() const override; + virtual sc_time getRefreshIntervalAB() const override; + + virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command) const override; +}; + +#endif // MEMSPECGDDR6_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index d09c31c9..72b96781 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -66,12 +66,12 @@ struct MemSpecHBM2 final : public MemSpec sc_time tRTW; sc_time tXP; sc_time tCKE; - sc_time tPD = tCKE; - sc_time tRDPDE = tRL + tPL + (BurstLength / 2) * clk + clk; - sc_time tWRPDE = tWL + tPL + (BurstLength / 2) * clk + clk + tWR; - sc_time tWRAPDE = tWL + tPL + (BurstLength / 2) * clk + clk + tWR; - sc_time tCKESR = tCKE + clk; - sc_time tRDSRE = tRL + tPL + (BurstLength / 2) * clk + clk; + sc_time tPD; // = tCKE; + sc_time tRDPDE; // = tRL + tPL + (BurstLength / DataRate) * clk + clk; + sc_time tWRPDE; // = tWL + tPL + (BurstLength / DataRate) * clk + clk + tWR; + sc_time tWRAPDE; // = tWL + tPL + (BurstLength / DataRate) * clk + clk + tWR; + sc_time tCKESR; // = tCKE + clk; + sc_time tRDSRE; // = tRL + tPL + (BurstLength / DataRate) * clk + clk; sc_time tXS; sc_time tRFC; sc_time tRFCSB; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index f3359a0f..11209180 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -47,6 +47,9 @@ #include "checker/CheckerLPDDR4.h" #include "checker/CheckerWideIO2.h" #include "checker/CheckerHBM2.h" +#include "checker/CheckerGDDR5.h" +#include "checker/CheckerGDDR5X.h" +#include "checker/CheckerGDDR6.h" #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" @@ -74,6 +77,12 @@ Controller::Controller(sc_module_name name) : checker = new CheckerWideIO2(); else if (memSpec->MemoryType == "HBM2") checker = new CheckerHBM2(); + else if (memSpec->MemoryType == "GDDR5") + checker = new CheckerGDDR5(); + else if (memSpec->MemoryType == "GDDR5X") + checker = new CheckerGDDR5X(); + else if (memSpec->MemoryType == "GDDR6") + checker = new CheckerGDDR6(); else SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 55f36c9c..12697b3d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -58,9 +58,6 @@ private: // Four activate window std::vector> lastActivates; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index ca85a4c3..2ff961a9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -61,9 +61,6 @@ private: std::vector> lastActivates; sc_time burstClocks; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp new file mode 100644 index 00000000..5f8089fe --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerGDDR5.h" + +CheckerGDDR5::CheckerGDDR5() +{ + Configuration &config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen"); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndBankGroup = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + last4Activates = std::vector>(memSpec->NumberOfRanks); + last32Activates = std::vector>(memSpec->NumberOfRanks); + + burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; +} + +sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +{ + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + + if (last4Activates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + + if (last32Activates[rank.ID()].size() == 32) + earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::RD) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::REFB) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + { + if (bankwiseRefreshCounter == 0) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + } + + if (last4Activates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + + if (last32Activates[rank.ID()].size() == 32) + earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else + { + reportFatal("CheckerGDDR5", "Unknown command!"); + } + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp(); + + if (command == Command::ACT || command == Command::REFB) + { + if (last4Activates[rank.ID()].size() == 4) + last4Activates[rank.ID()].pop(); + last4Activates[rank.ID()].push(lastCommandOnBus); + + if (last32Activates[rank.ID()].size() == 32) + last32Activates[rank.ID()].pop(); + last32Activates[rank.ID()].push(lastCommandOnBus); + } + + if (command == Command::REFB) + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h new file mode 100644 index 00000000..a17b7c28 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERGDDR5_H +#define CHECKERGDDR5_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecGDDR5.h" +#include "../../configuration/Configuration.h" + +class CheckerGDDR5 final : public CheckerIF +{ +public: + CheckerGDDR5(); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; + +private: + const MemSpecGDDR5 *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastCommandOnBus; + + // 4 and 32 activate window + std::vector> last4Activates; + std::vector> last32Activates; + + sc_time burstClocks; + + unsigned bankwiseRefreshCounter = 0; +}; + +#endif // CHECKERGDDR5_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp new file mode 100644 index 00000000..fbc3cbaa --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerGDDR5X.h" + +CheckerGDDR5X::CheckerGDDR5X() +{ + Configuration &config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen"); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndBankGroup = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + last4Activates = std::vector>(memSpec->NumberOfRanks); + last32Activates = std::vector>(memSpec->NumberOfRanks); + + burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; +} + +sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +{ + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + + if (last4Activates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + + if (last32Activates[rank.ID()].size() == 32) + earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::RD) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::REFB) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + { + if (bankwiseRefreshCounter == 0) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + } + + if (last4Activates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW); + + if (last32Activates[rank.ID()].size() == 32) + earliestTimeToStart = std::max(earliestTimeToStart, last32Activates[rank.ID()].front() + memSpec->t32AW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else + { + reportFatal("CheckerGDDR5X", "Unknown command!"); + } + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp(); + + if (command == Command::ACT || command == Command::REFB) + { + if (last4Activates[rank.ID()].size() == 4) + last4Activates[rank.ID()].pop(); + last4Activates[rank.ID()].push(lastCommandOnBus); + + if (last32Activates[rank.ID()].size() == 32) + last32Activates[rank.ID()].pop(); + last32Activates[rank.ID()].push(lastCommandOnBus); + } + + if (command == Command::REFB) + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h new file mode 100644 index 00000000..355ca555 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERGDDR5X_H +#define CHECKERGDDR5X_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecGDDR5X.h" +#include "../../configuration/Configuration.h" + +class CheckerGDDR5X final : public CheckerIF +{ +public: + CheckerGDDR5X(); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; + +private: + const MemSpecGDDR5X *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastCommandOnBus; + + // 4 and 32 activate window + std::vector> last4Activates; + std::vector> last32Activates; + + sc_time burstClocks; + + unsigned bankwiseRefreshCounter = 0; +}; + +#endif // CHECKERGDDR5X_H diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp new file mode 100644 index 00000000..f5aebd85 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "CheckerGDDR6.h" + +CheckerGDDR6::CheckerGDDR6() +{ + Configuration &config = Configuration::getInstance(); + memSpec = dynamic_cast(config.memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen"); + + lastScheduledByCommandAndBank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBanks)); + lastScheduledByCommandAndBankGroup = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfBankGroups)); + lastScheduledByCommandAndRank = std::vector> + (numberOfCommands(), std::vector(memSpec->NumberOfRanks)); + lastScheduledByCommand = std::vector(numberOfCommands()); + + lastActivates = std::vector>(memSpec->NumberOfRanks); + + burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; +} + +sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +{ + sc_time lastCommandStart; + sc_time earliestTimeToStart = sc_time_stamp(); + + if (command == Command::ACT) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::RD) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWTRS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::WR || command == Command::WRA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR); + + lastCommandStart = lastScheduledByCommand[Command::RD]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommand[Command::RDA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WR]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); + + lastCommandStart = lastScheduledByCommand[Command::WRA]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::PRE) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::PREA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::REFA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else if (command == Command::REFB) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC); + + lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL); + + lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS); + + lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + +// lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()]; +// if (lastCommandStart != SC_ZERO_TIME) +// earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + { + if (bankwiseRefreshCounter == 0) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); + } + + if (lastActivates[rank.ID()].size() == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); + + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); + } + else + { + reportFatal("CheckerGDDR6", "Unknown command!"); + } + + return (earliestTimeToStart - sc_time_stamp()); +} + +void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +{ + PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + bank.ID() + + " command is " + commandToString(command)); + + lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); + lastScheduledByCommandAndBankGroup[command][bankgroup.ID()] = sc_time_stamp(); + lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); + lastScheduledByCommand[command] = sc_time_stamp(); + lastCommandOnBus = sc_time_stamp(); + + if (command == Command::ACT || command == Command::REFB) + { + if (lastActivates[rank.ID()].size() == 4) + lastActivates[rank.ID()].pop(); + lastActivates[rank.ID()].push(lastCommandOnBus); + } + + if (command == Command::REFB) + bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; +} diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h new file mode 100644 index 00000000..f61007e6 --- /dev/null +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef CHECKERGDDR6_H +#define CHECKERGDDR6_H + +#include "CheckerIF.h" +#include +#include +#include "../../configuration/memspec/MemSpecGDDR6.h" +#include "../../configuration/Configuration.h" + +class CheckerGDDR6 final : public CheckerIF +{ +public: + CheckerGDDR6(); + virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; + virtual void insert(Command, Rank, BankGroup, Bank) override; + +private: + const MemSpecGDDR6 *memSpec; + + std::vector> lastScheduledByCommandAndBank; + std::vector> lastScheduledByCommandAndBankGroup; + std::vector> lastScheduledByCommandAndRank; + std::vector lastScheduledByCommand; + sc_time lastCommandOnBus; + + // four activate window + std::vector> lastActivates; + + sc_time burstClocks; + + unsigned bankwiseRefreshCounter = 0; +}; + +#endif // CHECKERGDDR6_H diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index d4e2d0ef..31769bb9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -64,9 +64,6 @@ private: sc_time burstClocks; unsigned bankwiseRefreshCounter = 0; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERHBM2_H diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index 2fe47f2a..64e43f5a 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -48,9 +48,6 @@ public: virtual sc_time delayToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; virtual void insert(Command, Rank, BankGroup, Bank) = 0; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERIF_H diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index b925b9e4..fbadc16e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -58,9 +58,6 @@ private: // Four activate window std::vector> lastActivates; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERLPDDR4_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index 9c0aa038..6bcc0796 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -60,9 +60,6 @@ private: std::vector> lastActivates; sc_time burstClocks; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERWIDEIO_H diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index a909fb59..7c27933d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -58,9 +58,6 @@ private: // Four activate window std::vector> lastActivates; - - // PowerDown TODO: Implement this method? - //sc_time getTimeConstraintToEnterPowerDown(Command lastCmd, Command pdnCmd) const; }; #endif // CHECKERWIDEIO2_H diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index b67309e4..f348eaa4 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -59,6 +59,9 @@ #include "dram/DramLPDDR4.h" #include "dram/DramWideIO2.h" #include "dram/DramHBM2.h" +#include "dram/DramGDDR5.h" +#include "dram/DramGDDR5X.h" +#include "dram/DramGDDR6.h" #include "../controller/Controller.h" #include "../controller/ControllerRecordable.h" @@ -306,6 +309,27 @@ void DRAMSys::instantiateModules(const string &traceName, else dram = new DramHBM2(str.c_str()); } + else if (memoryType == "GDDR5") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramGDDR5(str.c_str()); + } + else if (memoryType == "GDDR5X") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramGDDR5X(str.c_str()); + } + else if (memoryType == "GDDR6") + { + if (recordingEnabled) + dram = new DramRecordable(str.c_str(), tlmRecorders[i]); + else + dram = new DramGDDR6(str.c_str()); + } else { SC_REPORT_FATAL("DRAMSys", "Unsupported DRAM type"); diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.h b/DRAMSys/library/src/simulation/dram/DramDDR3.h index 1a51c471..1c1a9ffe 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.h @@ -37,7 +37,6 @@ #define DRAMDDR3_H #include -#include #include "Dram.h" class DramDDR3 : public Dram diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.h b/DRAMSys/library/src/simulation/dram/DramDDR4.h index 9bf17bd7..bb901591 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.h @@ -37,7 +37,6 @@ #define DRAMDDR4_H #include -#include #include "Dram.h" class DramDDR4 : public Dram diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp new file mode 100644 index 00000000..3e580346 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramGDDR5.h" + +#include "Dram.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecGDDR5.h" + +DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5"); + + // Parameters for DRAMPower + MemSpecGDDR5 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramGDDR5", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + SC_REPORT_FATAL("DramGDDR5", "DRAMPower not supported for GDDR5"); + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.h b/DRAMSys/library/src/simulation/dram/DramGDDR5.h new file mode 100644 index 00000000..e35bc380 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMGDDR5_H +#define DRAMGDDR5_H + +#include +#include "Dram.h" + +class DramGDDR5 : public Dram +{ +public: + DramGDDR5(sc_module_name); + SC_HAS_PROCESS(DramGDDR5); + virtual ~DramGDDR5() {} +}; + +#endif // DRAMGDDR5_H diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp new file mode 100644 index 00000000..a3f492e7 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramGDDR5X.h" + +#include "Dram.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecGDDR5X.h" + +DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X"); + + // Parameters for DRAMPower + MemSpecGDDR5X *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramGDDR5X", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + SC_REPORT_FATAL("DramGDDR5X", "DRAMPower not supported for GDDR5X"); + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h new file mode 100644 index 00000000..dedf1f8d --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMGDDR5X_H +#define DRAMGDDR5X_H + +#include +#include "Dram.h" + +class DramGDDR5X : public Dram +{ +public: + DramGDDR5X(sc_module_name); + SC_HAS_PROCESS(DramGDDR5X); + virtual ~DramGDDR5X() {} +}; + +#endif // DRAMGDDR5X_H diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp new file mode 100644 index 00000000..8260db52 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#include "DramGDDR6.h" + +#include "Dram.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../configuration/memspec/MemSpecGDDR6.h" + +DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name) +{ + if (StoreMode == StorageMode::ErrorModel) + SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6"); + + // Parameters for DRAMPower + MemSpecGDDR6 *memSpec = dynamic_cast(this->memSpec); + if (memSpec == nullptr) + SC_REPORT_FATAL("DramGDDR6", "Wrong MemSpec chosen"); + + if (Configuration::getInstance().PowerAnalysis) + SC_REPORT_FATAL("DramGDDR6", "DRAMPower not supported for GDDR6"); + else + DRAMPower = new libDRAMPowerDummy(); +} diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.h b/DRAMSys/library/src/simulation/dram/DramGDDR6.h new file mode 100644 index 00000000..07f586c2 --- /dev/null +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: + * Lukas Steiner + */ + +#ifndef DRAMGDDR6_H +#define DRAMGDDR6_H + +#include +#include "Dram.h" + +class DramGDDR6 : public Dram +{ +public: + DramGDDR6(sc_module_name); + SC_HAS_PROCESS(DramGDDR6); + virtual ~DramGDDR6() {} +}; + + +#endif // DRAMGDDR6_H diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp index cea6f476..3ee73ea0 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp @@ -51,9 +51,7 @@ DramHBM2::DramHBM2(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramHBM2", "Wrong MemSpec chosen"); if (Configuration::getInstance().PowerAnalysis) - { SC_REPORT_FATAL("DramHBM2", "DRAMPower not supported for HBM2"); - } else DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.h b/DRAMSys/library/src/simulation/dram/DramHBM2.h index 84cb5d0b..0b2861fa 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.h +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.h @@ -37,11 +37,8 @@ #define DRAMHBM2_H #include -#include #include "Dram.h" -using namespace tlm; - class DramHBM2 : public Dram { public: diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp index 4b0a9251..38df1da5 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp @@ -35,6 +35,9 @@ #include "DramLPDDR4.h" +#include "Dram.h" +#include "../../configuration/Configuration.h" +#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecLPDDR4.h" DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) @@ -48,9 +51,7 @@ DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramLPDDR4", "Wrong MemSpec chosen"); if (Configuration::getInstance().PowerAnalysis) - { SC_REPORT_FATAL("DramLPDDR4", "DRAMPower not supported for LPDDR4"); - } else DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h index c63561b2..31271928 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h @@ -37,7 +37,6 @@ #define DRAMLPDDR4_H #include -#include #include "Dram.h" class DramLPDDR4 : public Dram diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index f52ee002..97c03e38 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -45,6 +45,9 @@ #include "DramLPDDR4.h" #include "DramWideIO2.h" #include "DramHBM2.h" +#include "DramGDDR5.h" +#include "DramGDDR5X.h" +#include "DramGDDR6.h" using namespace tlm; @@ -149,4 +152,7 @@ template class DramRecordable; template class DramRecordable; template class DramRecordable; template class DramRecordable; +template class DramRecordable; +template class DramRecordable; +template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp index 65299da3..dde791fa 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp @@ -51,9 +51,7 @@ DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name) SC_REPORT_FATAL("DramWideIO2", "Wrong MemSpec chosen"); if (Configuration::getInstance().PowerAnalysis) - { SC_REPORT_FATAL("DramWideIO2", "DRAMPower not supported for WideIO2"); - } else DRAMPower = new libDRAMPowerDummy(); } diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.h b/DRAMSys/library/src/simulation/dram/DramWideIO2.h index 674af83c..d51f7e4f 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.h @@ -37,11 +37,8 @@ #define DRAMWIDEIO2_H #include -#include #include "Dram.h" -using namespace tlm; - class DramWideIO2 : public Dram { public: From e970ad194e10fccbbc90bed593887a6b3591887f Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 17 Oct 2019 15:47:27 +0200 Subject: [PATCH 135/183] Correction of timing dependency WR -<> RDA. --- .../src/configuration/memspec/MemSpecDDR3.cpp | 5 -- .../src/configuration/memspec/MemSpecDDR4.cpp | 9 +-- .../configuration/memspec/MemSpecLPDDR4.cpp | 4 -- .../configuration/memspec/MemSpecWideIO.cpp | 5 -- .../src/controller/checker/CheckerDDR3.cpp | 28 +++++++--- .../src/controller/checker/CheckerDDR3.h | 2 + .../src/controller/checker/CheckerDDR4.cpp | 10 +++- .../src/controller/checker/CheckerGDDR5.cpp | 56 +++---------------- .../src/controller/checker/CheckerGDDR5X.cpp | 56 +++---------------- .../src/controller/checker/CheckerGDDR6.cpp | 56 +++---------------- .../src/controller/checker/CheckerHBM2.cpp | 8 +++ .../src/controller/checker/CheckerLPDDR4.cpp | 8 +++ .../src/controller/checker/CheckerWideIO.cpp | 8 +++ .../src/controller/checker/CheckerWideIO2.cpp | 8 +++ 14 files changed, 88 insertions(+), 175 deletions(-) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 30e04c29..02f83638 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -55,13 +55,8 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload return tRCD; else if (command == Command::RD || command == Command::RDA) return tRL + getReadAccessTime(); -// else if (command == Command::RDA) -// // TODO: this time is wrong (controller internally waits for tRAS) -// return tRTP + tRP; else if (command == Command::WR || command == Command::WRA) return tWL + getWriteAccessTime(); -// else if (command == Command::WRA) -// return tWL + getWriteAccessTime() + tWR + tRP; else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index ca0deeee..0fd8bfb9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -53,15 +53,10 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload return tRP; else if (command == Command::ACT) return tRCD; - else if (command == Command::RD) + else if (command == Command::RD || command == Command::RDA) return tRL + getReadAccessTime(); - else if (command == Command::RDA) - // this time is wrong (controller internally waits for tRAS) - return tRTP + tRP; - else if (command == Command::WR) + else if (command == Command::WR || command == Command::WRA) return tWL + getWriteAccessTime(); - else if (command == Command::WRA) - return tWL + getWriteAccessTime() + tWR + tRP; else if (command == Command::REFA) return tRFC; else if (command == Command::REFB) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index 50afd825..106d3c13 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -70,12 +70,8 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo return tRCD + 3 * clk; else if (command == Command::RD || command == Command::RDA) return tRL + tDQSCK + getReadAccessTime() + 3 * clk; -// else if (command == Command::RDA) -// return getReadAccessTime() - 5 * clk + tRTP + tRPpb; else if (command == Command::WR || command == Command::WRA) return tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk; -// else if (command == Command::WRA) -// return tWL + getWriteAccessTime() + 4 * clk + tWR + tRPpb; else if (command == Command::REFA) return tRFCab + clk; else if (command == Command::REFB) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index 5b4c5316..af3af2b4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -55,13 +55,8 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo return tRCD; else if (command == Command::RD || command == Command::RDA) return tRL + tAC + getReadAccessTime(); -// else if (command == Command::RDA) -// // this time is wrong (controller internally waits for tRAS) -// return tRTP + tRP; else if (command == Command::WR || command == Command::WRA) return tWL + getWriteAccessTime(); -// else if (command == Command::WRA) -// return tWL + getWriteAccessTime() + tWR + tRP; else if (command == Command::REFA) return tRFC; else diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 14b4caf8..74f80b04 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -48,6 +48,8 @@ CheckerDDR3::CheckerDDR3() lastScheduledByCommand = std::vector(numberOfCommands()); lastActivates = std::vector>(memSpec->NumberOfRanks); + + burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; } sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const @@ -64,7 +66,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) @@ -109,12 +111,20 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWTR); + + memSpec->tWL + burstClocks + memSpec->tWTR); + + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWTR); + + memSpec->tWL + burstClocks + memSpec->tWTR); } else if (command == Command::WR || command == Command::WRA) { @@ -124,12 +134,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + memSpec->BurstLength / 2 * memSpec->clk + 2 * memSpec->clk - memSpec->tWL); + + memSpec->tRL + burstClocks + 2 * memSpec->clk - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + memSpec->BurstLength / 2 * memSpec->clk + 2 * memSpec->clk - memSpec->tWL); + + memSpec->tRL + burstClocks + 2 * memSpec->clk - memSpec->tWL); lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) @@ -151,7 +161,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR); + + memSpec->tWL + burstClocks + memSpec->tWR); } else if (command == Command::PREA) { @@ -169,12 +179,12 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR); + + memSpec->tWL + burstClocks + memSpec->tWR); lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR); + + memSpec->tWL + burstClocks + memSpec->tWR); } else if (command == Command::REFA) { @@ -189,7 +199,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + memSpec->BurstLength / 2 * memSpec->clk + memSpec->tWR + memSpec->tRP); + + memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP); lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index 12697b3d..5ee8144b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -58,6 +58,8 @@ private: // Four activate window std::vector> lastActivates; + + sc_time burstClocks; }; #endif // CHECKERDDR3_H diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index ba999d03..e0bab316 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -51,7 +51,7 @@ CheckerDDR4::CheckerDDR4() lastActivates = std::vector>(memSpec->NumberOfRanks); - burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; + burstClocks = (memSpec->BurstLength / memSpec->DataRate) * memSpec->clk; } sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const @@ -123,6 +123,14 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTR_L); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + } + lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 5f8089fe..25107115 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -111,7 +111,7 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } - else if (command == Command::RD) + else if (command == Command::RD || command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); @@ -137,53 +137,13 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTRL); - lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); - } - else if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index fbc3cbaa..c773e8ac 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -111,7 +111,7 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } - else if (command == Command::RD) + else if (command == Command::RD || command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); @@ -137,53 +137,13 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTRL); - lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); - } - else if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index f5aebd85..d37209ad 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -107,7 +107,7 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); } - else if (command == Command::RD) + else if (command == Command::RD || command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); @@ -133,53 +133,13 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTRL); - lastCommandStart = lastScheduledByCommand[Command::WR]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); - - lastCommandStart = lastScheduledByCommand[Command::WRA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRS); - - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk); - } - else if (command == Command::RDA) - { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommand[Command::RD]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL); - - lastCommandStart = lastScheduledByCommand[Command::RDA]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS); - - lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL)); - - lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; - if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tWL + burstClocks + memSpec->tWTRL); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 2a960058..d198e241 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -135,6 +135,14 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTRL); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP); + } + lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index e8174a65..661a3129 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -114,6 +114,14 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWR - memSpec->tRTP); + } + lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index c0ac78a7..9b3f4aa8 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -109,6 +109,14 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->clk + memSpec->tWR); + } + lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 4a99d98a..f91aabda 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -116,6 +116,14 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR); + if (command == Command::RDA) + { + lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWR - memSpec->tRTP); + } + lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart From bddec3022afd6e0b3108534c8f4254c708a7d1bb Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 18 Nov 2019 19:16:42 +0100 Subject: [PATCH 136/183] Some preparations for power down. --- .../library/src/controller/BankMachine.cpp | 3 +- DRAMSys/library/src/controller/Command.cpp | 17 +++++++++ DRAMSys/library/src/controller/Command.h | 7 ++++ DRAMSys/library/src/controller/Controller.cpp | 35 +++++-------------- DRAMSys/library/src/controller/Controller.h | 3 +- .../src/controller/refresh/RefreshManager.cpp | 5 +++ .../src/controller/refresh/RefreshManager.h | 3 ++ .../refresh/RefreshManagerBankwise.cpp | 7 +++- .../refresh/RefreshManagerBankwise.h | 3 ++ .../controller/refresh/RefreshManagerDummy.h | 1 + .../src/controller/refresh/RefreshManagerIF.h | 1 + 11 files changed, 56 insertions(+), 29 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index cf3238b8..7240f0f5 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -66,7 +66,8 @@ void BankMachine::updateState(Command command) currentState = BmState::Precharged; currentPayload = nullptr; } - else if (command == Command::REFA || command == Command::REFB) + else if (command == Command::REFA || command == Command::REFB + || command == Command::PDXA || command == Command::PDXP) blocked = false; else SC_REPORT_FATAL("BankMachine", "Unknown phase"); diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 2890bc36..c9f98bf4 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -135,3 +135,20 @@ bool commandIsIn(Command command, std::vector commands) } return false; } + +std::array phaseOfCommand = {UNINITIALIZED_PHASE, + BEGIN_PRE, + BEGIN_PREA, + BEGIN_ACT, + BEGIN_RD, + BEGIN_WR, + BEGIN_RDA, + BEGIN_WRA, + BEGIN_REFA, + BEGIN_REFB, + BEGIN_PDNA, + END_PDNA, + BEGIN_PDNP, + END_PDNP, + BEGIN_SREF, + END_SREF}; diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 4bb09641..176233fc 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -38,6 +38,11 @@ #include #include +#include +#include +#include "../common/protocol.h" + +using namespace tlm; enum Command { @@ -64,4 +69,6 @@ const std::vector &getAllCommands(); unsigned numberOfCommands(); bool commandIsIn(Command command, std::vector commands); +extern std::array phaseOfCommand; + #endif // COMMAND_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 11209180..08ed05c5 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -64,6 +64,7 @@ Controller::Controller(sc_module_name name) : Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; maxNumberOfPayloads = config.MaxNrOfTransactions; + ranksNumberOfPayloads = std::vector(memSpec->NumberOfRanks, 0); if (memSpec->MemoryType == "DDR3") checker = new CheckerDDR3(); @@ -195,7 +196,7 @@ void Controller::controllerMethod() // (3) Accept new request from arbiter and start appropriate BM if necessary if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) { - if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) + if (totalNumberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) { Bank bank = DramExtension::getBank(payloadToAcquire); acquirePayload(); @@ -316,13 +317,14 @@ void Controller::releasePayload() uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToRelease); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); + totalNumberOfPayloads--; + ranksNumberOfPayloads[DramExtension::getRank(payloadToRelease).ID()]--; payloadToRelease->release(); - numberOfPayloads--; payloadToRelease = nullptr; timeToRelease = sc_max_time(); numberOfTransactionsServed++; - if (numberOfPayloads == 0) + if (totalNumberOfPayloads == 0) startBandwidthIdleCollector(); } @@ -331,12 +333,13 @@ void Controller::acquirePayload() uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToAcquire); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); - if (numberOfPayloads == 0) + if (totalNumberOfPayloads == 0) endBandwithIdleCollector(); scheduler->storeRequest(payloadToAcquire); payloadToAcquire->acquire(); - numberOfPayloads++; + totalNumberOfPayloads++; + ranksNumberOfPayloads[DramExtension::getRank(payloadToAcquire).ID()]++; payloadToAcquire->set_response_status(TLM_OK_RESPONSE); sendToFrontend(payloadToAcquire, END_REQ); payloadToAcquire = nullptr; @@ -355,27 +358,7 @@ void Controller::sendToDram(Command command, tlm_generic_payload *payload) checker->insert(command, extension.getRank(), extension.getBankGroup(), extension.getBank()); sc_time delay = SC_ZERO_TIME; - tlm_phase phase; - if (command == Command::ACT) - phase = BEGIN_ACT; - else if (command == Command::PRE) - phase = BEGIN_PRE; - else if (command == Command::RD) - phase = BEGIN_RD; - else if (command == Command::RDA) - phase = BEGIN_RDA; - else if (command == Command::WR) - phase = BEGIN_WR; - else if (command == Command::WRA) - phase = BEGIN_WRA; - else if (command == Command::PREA) - phase = BEGIN_PREA; - else if (command == Command::REFA) - phase = BEGIN_REFA; - else if (command == Command::REFB) - phase = BEGIN_REFB; - else - SC_REPORT_FATAL("Controller", "Unknown phase"); + tlm_phase phase = phaseOfCommand[command]; iSocket->nb_transport_fw(*payload, phase, delay); } diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 11e7e831..14758071 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -72,7 +72,8 @@ protected: virtual void sendToDram(Command, tlm_generic_payload *); private: - unsigned numberOfPayloads = 0; + unsigned totalNumberOfPayloads = 0; + std::vector ranksNumberOfPayloads; unsigned maxNumberOfPayloads; tlm_generic_payload *payloadToAcquire = nullptr; sc_time timeToAcquire = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 1abdf2ca..906db024 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -59,6 +59,11 @@ std::pair RefreshManager::getNextCommand() return std::pair(Command::NOP, nullptr); } +void RefreshManager::block() +{ + blocked = true; +} + sc_time RefreshManager::start() { timeToSchedule = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 542108a8..a16981d4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -50,6 +50,7 @@ public: std::pair getNextCommand(); sc_time start(); void updateState(Command, tlm_generic_payload *); + void block(); private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; @@ -65,6 +66,8 @@ private: int flexibilityCounter = 0; int maxPostponed = 0; int maxPulledin = 0; + + bool blocked = false; }; #endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index e412d594..7cdc42b7 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -59,13 +59,18 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM std::pair RefreshManagerBankwise::getNextCommand() { - if (sc_time_stamp() == timeToSchedule) + if (sc_time_stamp() == timeToSchedule && !blocked) return std::pair (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); else return std::pair(Command::NOP, nullptr); } +void RefreshManagerBankwise::block() +{ + blocked = true; +} + sc_time RefreshManagerBankwise::start() { timeToSchedule = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 5f7b6948..d986ac74 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -52,6 +52,7 @@ public: std::pair getNextCommand(); sc_time start(); void updateState(Command, tlm_generic_payload *); + void block(); private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; @@ -71,6 +72,8 @@ private: int flexibilityCounter = 0; int maxPostponed = 0; int maxPulledin = 0; + + bool blocked = false; }; #endif // REFRESHMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 2d895cf3..301d724e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -49,6 +49,7 @@ public: std::pair getNextCommand(); sc_time start(); void updateState(Command, tlm_generic_payload *) {} + void block() {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index d1e589ca..d2b78266 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -50,6 +50,7 @@ public: virtual std::pair getNextCommand() = 0; virtual sc_time start() = 0; virtual void updateState(Command, tlm_generic_payload *) = 0; + virtual void block() = 0; }; #endif // REFRESHMANAGERIF_H From 6e6d839bd166c8aa4745a1dcc7919871645ce214 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 20 Nov 2019 00:30:27 +0100 Subject: [PATCH 137/183] First version of power down working, added some helper functions for enum Command. --- DRAMSys/library/library.pro | 17 +- .../src/configuration/memspec/MemSpecDDR3.cpp | 2 + .../library/src/controller/BankMachine.cpp | 2 + DRAMSys/library/src/controller/Command.cpp | 36 ++++- DRAMSys/library/src/controller/Command.h | 12 +- DRAMSys/library/src/controller/Controller.cpp | 49 +++++- DRAMSys/library/src/controller/Controller.h | 3 + .../src/controller/checker/CheckerDDR3.cpp | 145 ++++++++++++++++++ .../src/controller/cmdmux/CmdMuxStrict.cpp | 5 +- .../controller/powerdown/PowerDownManager.cpp | 114 ++++++++++++++ .../controller/powerdown/PowerDownManager.h | 69 +++++++++ .../src/controller/refresh/RefreshManager.cpp | 25 +-- .../src/controller/refresh/RefreshManager.h | 7 +- .../refresh/RefreshManagerBankwise.cpp | 14 +- .../refresh/RefreshManagerBankwise.h | 7 +- .../controller/refresh/RefreshManagerDummy.h | 1 - .../src/controller/refresh/RefreshManagerIF.h | 1 - 17 files changed, 450 insertions(+), 59 deletions(-) create mode 100644 DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp create mode 100644 DRAMSys/library/src/controller/powerdown/PowerDownManager.h diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 6ab96b7c..02051018 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -90,17 +90,12 @@ SOURCES += \ src/common/TlmRecorder.cpp \ src/common/DebugManager.cpp \ src/configuration/Configuration.cpp \ - src/controller/core/powerdown/PowerDownManagerTimeout.cpp \ - src/controller/core/powerdown/PowerDownManagerBankwise.cpp \ - src/controller/core/powerdown/PowerDownManager.cpp \ src/simulation/MemoryManager.cpp \ src/simulation/TemperatureController.cpp \ src/configuration/ConfigurationLoader.cpp \ - src/controller/core/powerdown/NoPowerDown.cpp \ src/controller/Command.cpp \ src/error/errormodel.cpp \ src/simulation/TracePlayer.cpp \ - src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp \ src/simulation/TraceSetup.cpp \ src/simulation/DRAMSys.cpp \ src/simulation/Setup.cpp \ @@ -155,7 +150,8 @@ SOURCES += \ src/controller/checker/CheckerGDDR6.cpp \ src/simulation/dram/DramGDDR5.cpp \ src/simulation/dram/DramGDDR5X.cpp \ - src/simulation/dram/DramGDDR6.cpp + src/simulation/dram/DramGDDR6.cpp \ + src/controller/powerdown/PowerDownManager.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -164,9 +160,6 @@ HEADERS += \ src/common/protocol.h \ src/common/DebugManager.h \ src/configuration/Configuration.h \ - src/controller/core/powerdown/PowerDownManagerTimeout.h \ - src/controller/core/powerdown/PowerDownManagerBankwise.h \ - src/controller/core/powerdown/PowerDownManager.h \ src/simulation/TracePlayer.h \ src/simulation/MemoryManager.h \ src/simulation/dram/Dram.h \ @@ -178,13 +171,10 @@ HEADERS += \ src/simulation/TracePlayerListener.h \ src/simulation/TraceGenerator.h \ src/simulation/TemperatureController.h \ - src/controller/core/powerdown/NoPowerDown.h \ src/controller/Command.h \ - src/controller/core/powerdown/IPowerDownManager.h \ src/configuration/ConfigurationLoader.h \ src/error/errormodel.h \ src/simulation/ExampleInitiator.h \ - src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h \ src/simulation/TraceSetup.h \ src/simulation/DRAMSys.h \ src/simulation/Setup.h \ @@ -244,7 +234,8 @@ HEADERS += \ src/controller/checker/CheckerGDDR6.h \ src/simulation/dram/DramGDDR5.h \ src/simulation/dram/DramGDDR5X.h \ - src/simulation/dram/DramGDDR6.h + src/simulation/dram/DramGDDR6.h \ + src/controller/powerdown/PowerDownManager.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 02f83638..51b21916 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -61,6 +61,8 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload return tRFC; else if (command == Command::REFB) return tRFC; + else if (command == Command::PDXA || command == Command::PDXP || command == Command::SREFEX) + return clk; else { SC_REPORT_FATAL("getExecutionTime", diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 7240f0f5..57ac74f1 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -66,6 +66,8 @@ void BankMachine::updateState(Command command) currentState = BmState::Precharged; currentPayload = nullptr; } + else if (command == Command::PDEA || command == Command::PDEP) + blocked = true; else if (command == Command::REFA || command == Command::REFB || command == Command::PDXA || command == Command::PDXP) blocked = false; diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index c9f98bf4..290f7c44 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -103,15 +103,15 @@ std::string commandToString(Command command) const std::vector &getAllCommands() { static std::vector allCommands( { Command::NOP, - Command::PRE, - Command::PREA, - Command::ACT, Command::RD, Command::WR, Command::RDA, Command::WRA, - Command::REFA, + Command::PRE, + Command::ACT, Command::REFB, + Command::PREA, + Command::REFA, Command::PDEA, Command::PDXA, Command::PDEP, @@ -137,18 +137,38 @@ bool commandIsIn(Command command, std::vector commands) } std::array phaseOfCommand = {UNINITIALIZED_PHASE, - BEGIN_PRE, - BEGIN_PREA, - BEGIN_ACT, BEGIN_RD, BEGIN_WR, BEGIN_RDA, BEGIN_WRA, - BEGIN_REFA, + BEGIN_PRE, + BEGIN_ACT, BEGIN_REFB, + BEGIN_PREA, + BEGIN_REFA, BEGIN_PDNA, END_PDNA, BEGIN_PDNP, END_PDNP, BEGIN_SREF, END_SREF}; + +bool isBankCommand(Command command) +{ + return (command <= 7); +} + +bool isRankCommand(Command command) +{ + return (command >= 8); +} + +bool isCasCommand(Command command) +{ + return (command <= 4); +} + +bool isRasCommand(Command command) +{ + return (command >= 5); +} diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 176233fc..8365ef4d 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -47,15 +47,15 @@ using namespace tlm; enum Command { NOP, - PRE, - PREA, - ACT, RD, WR, RDA, WRA, - REFA, + PRE, + ACT, REFB, + PREA, + REFA, PDEA, PDXA, PDEP, @@ -68,6 +68,10 @@ std::string commandToString(Command command); const std::vector &getAllCommands(); unsigned numberOfCommands(); bool commandIsIn(Command command, std::vector commands); +bool isBankCommand(Command command); +bool isRankCommand(Command command); +bool isCasCommand(Command command); +bool isRasCommand(Command command); extern std::array phaseOfCommand; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 08ed05c5..7f935710 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -133,6 +133,14 @@ Controller::Controller(sc_module_name name) : bankMachines.begin() + (rankID + 1) * memSpec->BanksPerRank)); } + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + { + PowerDownManager *manager = new PowerDownManager(bankMachinesOnRank[rankID], Rank(rankID), checker); + powerDownManagers.push_back(manager); + manager->triggerEntry(); + controllerEvent.notify(manager->start()); + } + if (config.ControllerCoreRefDisable) { for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) @@ -143,7 +151,7 @@ Controller::Controller(sc_module_name name) : for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) { RefreshManagerIF *manager = new RefreshManagerBankwise - (bankMachinesOnRank[rankID], Rank(rankID), checker); + (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); controllerEvent.notify(manager->start()); } @@ -153,7 +161,7 @@ Controller::Controller(sc_module_name name) : for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) { RefreshManagerIF *manager = new RefreshManager - (bankMachinesOnRank[rankID], Rank(rankID), checker); + (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); controllerEvent.notify(manager->start()); } @@ -211,11 +219,14 @@ void Controller::controllerMethod() // (4) Start refresh managers to issue requests for the current time for (auto it : refreshManagers) it->start(); + for (auto it : powerDownManagers) + it->start(); // (5) Choose one request and send it to DRAM std::pair commandPair; std::vector> readyCommands; bool readyCmdBlocked = false; + // TODO: check if all parts have to be called // (5.1) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) for (auto it : bankMachines) { @@ -230,13 +241,21 @@ void Controller::controllerMethod() if (commandPair.second != nullptr) readyCommands.push_back(commandPair); } + // (5.3) Check for power-down commands (...TODO) + for (auto it : powerDownManagers) + { + commandPair = it->getNextCommand(); + if (commandPair.second != nullptr) + readyCommands.push_back(commandPair); + } + if (!readyCommands.empty()) { commandPair = commandMux->selectCommand(readyCommands); if (commandPair.second != nullptr) // can happen with FIFO strict { Rank rank = DramExtension::getRank(commandPair.second); - if (commandPair.first == Command::PREA || commandPair.first == Command::REFA) + if (isRankCommand(commandPair.first)) { for (auto it : bankMachinesOnRank[rank.ID()]) it->updateState(commandPair.first); @@ -247,6 +266,7 @@ void Controller::controllerMethod() bankMachines[bank.ID()]->updateState(commandPair.first); } refreshManagers[rank.ID()]->updateState(commandPair.first, commandPair.second); + powerDownManagers[rank.ID()]->updateState(commandPair.first); sendToDram(commandPair.first, commandPair.second); } else @@ -254,6 +274,7 @@ void Controller::controllerMethod() } // (6) Restart bank machines and refresh managers to issue new requests for the future + // TODO: check if all calls are necessary for (auto it : bankMachines) { sc_time delay = it->start(); @@ -262,6 +283,8 @@ void Controller::controllerMethod() } for (auto it : refreshManagers) controllerEvent.notify(it->start()); + for (auto it : powerDownManagers) + controllerEvent.notify(it->start()); } tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, @@ -317,15 +340,21 @@ void Controller::releasePayload() uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToRelease); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); - totalNumberOfPayloads--; - ranksNumberOfPayloads[DramExtension::getRank(payloadToRelease).ID()]--; + Rank rank = DramExtension::getRank(payloadToRelease); + payloadToRelease->release(); payloadToRelease = nullptr; timeToRelease = sc_max_time(); numberOfTransactionsServed++; + totalNumberOfPayloads--; + ranksNumberOfPayloads[rank.ID()]--; + if (totalNumberOfPayloads == 0) startBandwidthIdleCollector(); + + if (ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerEntry(); } void Controller::acquirePayload() @@ -333,13 +362,19 @@ void Controller::acquirePayload() uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToAcquire); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " entered system."); + Rank rank = DramExtension::getRank(payloadToAcquire); + if (totalNumberOfPayloads == 0) endBandwithIdleCollector(); + if(ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerExit(); + + totalNumberOfPayloads++; + ranksNumberOfPayloads[rank.ID()]++; + scheduler->storeRequest(payloadToAcquire); payloadToAcquire->acquire(); - totalNumberOfPayloads++; - ranksNumberOfPayloads[DramExtension::getRank(payloadToAcquire).ID()]++; payloadToAcquire->set_response_status(TLM_OK_RESPONSE); sendToFrontend(payloadToAcquire, END_REQ); payloadToAcquire = nullptr; diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 14758071..94c36392 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -50,11 +50,13 @@ #include "../common/DebugManager.h" #include "checker/CheckerIF.h" #include "refresh/RefreshManagerIF.h" +#include "powerdown/PowerDownManager.h" using namespace tlm; class BankMachine; class SchedulerIF; +class PowerDownManager; class Controller : public GenericController { @@ -87,6 +89,7 @@ private: SchedulerIF *scheduler; CheckerIF *checker; std::vector refreshManagers; + std::vector powerDownManagers; void releasePayload(); void acquirePayload(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 74f80b04..d1a72fbe 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -92,6 +92,18 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG // if (lastCommandStart != SC_ZERO_TIME) // earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + if (lastActivates[rank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW); } @@ -125,6 +137,14 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWTR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL); } else if (command == Command::WR || command == Command::WRA) { @@ -148,6 +168,14 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXSDLL); } else if (command == Command::PRE) { @@ -162,6 +190,10 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); } else if (command == Command::PREA) { @@ -185,6 +217,10 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + burstClocks + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); } else if (command == Command::REFA) { @@ -212,6 +248,115 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + } + else if (command == Command::PDEA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + 4 * memSpec->clk + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); + } + else if (command == Command::PDXA) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); + } + else if (command == Command::PDEP) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tRL + 5 * memSpec->clk); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + memSpec->tWL + 5 * memSpec->clk + memSpec->tWR); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + } + else if (command == Command::PDXP) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE); + } + else if (command == Command::SREFEN) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + std::max(memSpec->tRL + 5 * memSpec->clk, memSpec->tAL + memSpec->tRTP + memSpec->tRP)); + + lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + + std::max(memSpec->tWL + 5 * memSpec->clk + memSpec->tWR, memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP)); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP); + + lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC); + + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS); + } + else if (command == Command::SREFEX) + { + lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()]; + if (lastCommandStart != SC_ZERO_TIME) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR); } else reportFatal("CheckerDDR3", "Unknown command!"); diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index ff558678..6e2d623e 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -41,7 +41,7 @@ CmdMuxStrict::selectCommand(std::vector(Command::NOP, nullptr); diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp new file mode 100644 index 00000000..b0fadef6 --- /dev/null +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "PowerDownManager.h" +#include "../../common/utils.h" + +PowerDownManager::PowerDownManager(std::vector &bankMachines, Rank rank, CheckerIF *checker) + : bankMachines(bankMachines), rank(rank), checker(checker) +{ + setUpDummy(powerDownPayload, rank); +} + +void PowerDownManager::triggerEntry() +{ + if (state == PdmState::Idle) + triggered = true; +} + +void PowerDownManager::triggerExit() +{ + if (state == PdmState::Idle) + triggered = false; + else + triggered = true; +} + +std::pair PowerDownManager::getNextCommand() +{ + if (sc_time_stamp() == timeToSchedule) + return std::pair(nextCommand, &powerDownPayload); + else + return std::pair(Command::NOP, nullptr); +} + +sc_time PowerDownManager::start() +{ + timeToSchedule = sc_max_time(); + sc_time delay = sc_max_time() - sc_time_stamp(); + + if (triggered) + { + if (state == PdmState::Idle) + { + nextCommand = Command::PDEP; + for (auto it : bankMachines) + { + if(it->getState() == BmState::Activated) + { + nextCommand = Command::PDEA; + break; + } + } + } + else if (state == PdmState::ActivePd) + nextCommand = Command::PDXA; + else if (state == PdmState::PrechargePd) + nextCommand = Command::PDXP; + // TODO: add self refresh + delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + } + + return delay; +} + +void PowerDownManager::updateState(Command command) +{ + if (command == Command::PDEA) + { + state = PdmState::ActivePd; + triggered = false; + } + else if (command == Command::PDEP) + { + state = PdmState::PrechargePd; + triggered = false; + } + else if (command == Command::PDXA || command == Command::PDXP) + { + state = PdmState::Idle; + triggered = false; + } +} diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.h b/DRAMSys/library/src/controller/powerdown/PowerDownManager.h new file mode 100644 index 00000000..50692f3a --- /dev/null +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManager.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef POWERDOWNMANAGER_H +#define POWERDOWNMANAGER_H + +#include "../BankMachine.h" +#include "../checker/CheckerIF.h" + +using namespace tlm; + +class BankMachine; + +class PowerDownManager +{ +public: + PowerDownManager(std::vector &, Rank, CheckerIF *); + + void triggerEntry(); + void triggerExit(); + + std::pair getNextCommand(); + void updateState(Command); + sc_time start(); + +private: + enum class PdmState {Idle, ActivePd, PrechargePd, SelfRefresh} state = PdmState::Idle; + bool triggered = false; + std::vector &bankMachines; + tlm_generic_payload powerDownPayload; + Rank rank; + CheckerIF *checker; + + sc_time timeToSchedule; + Command nextCommand; +}; + +#endif // POWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 906db024..8f32a3b9 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -37,8 +37,9 @@ #include "../../configuration/Configuration.h" #include "../../common/utils.h" -RefreshManager::RefreshManager(std::vector &bankMachines, Rank rank, CheckerIF *checker) - : bankMachines(bankMachines), rank(rank), checker(checker) +RefreshManager::RefreshManager(std::vector &bankMachines, + PowerDownManager *powerDownManager, Rank rank, CheckerIF *checker) + : bankMachines(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; @@ -53,23 +54,22 @@ RefreshManager::RefreshManager(std::vector &bankMachines, Rank ra std::pair RefreshManager::getNextCommand() { - if (sc_time_stamp() == timeToSchedule) + if (sc_time_stamp() == timeToSchedule && !blocked) return std::pair(nextCommand, &refreshPayload); else return std::pair(Command::NOP, nullptr); } -void RefreshManager::block() -{ - blocked = true; -} - sc_time RefreshManager::start() { timeToSchedule = sc_max_time(); if (sc_time_stamp() >= timeForNextTrigger) { + powerDownManager->triggerExit(); + if (blocked) + return sc_max_time() - sc_time_stamp(); + if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) { timeForNextTrigger += memSpec->getRefreshIntervalAB(); @@ -121,7 +121,7 @@ sc_time RefreshManager::start() { for (auto it : bankMachines) { - if (!it->isIdle()) // at least one bank is active -> abort pulling in + if (!it->isIdle()) // at least one bank has a payload -> abort pulling in { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); @@ -158,6 +158,8 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalAB(); + // TODO: is only allowed if all banks are still idle + //powerDownManager->triggerEntry(); } } else if (command == Command::PREA) @@ -165,6 +167,11 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) // if PREA was successful we will do the refresh in any case for (auto it : bankMachines) it->block(); + // TODO: remove for and insert blocking directly into BM state = RmState::Precharged; } + else if (command == Command::PDEA || command == Command::PDEP) + blocked = true; + else if (command == Command::PDXA || command == Command::PDXP) + blocked = false; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index a16981d4..36dca117 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -38,6 +38,7 @@ #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" +#include "../powerdown/PowerDownManager.h" #include "../checker/CheckerIF.h" using namespace tlm; @@ -45,17 +46,17 @@ using namespace tlm; class RefreshManager final : public RefreshManagerIF { public: - RefreshManager(std::vector &, Rank, CheckerIF *); + RefreshManager(std::vector &, PowerDownManager *, Rank, CheckerIF *); std::pair getNextCommand(); sc_time start(); void updateState(Command, tlm_generic_payload *); - void block(); private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; - std::vector bankMachines; + std::vector &bankMachines; + PowerDownManager *powerDownManager; tlm_generic_payload refreshPayload; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 7cdc42b7..874d877e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -37,8 +37,9 @@ #include "../../common/utils.h" #include "../../common/dramExtensions.h" -RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, Rank rank, CheckerIF *checker) - : bankMachines(bankMachines), rank(rank), checker(checker) +RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, + PowerDownManager *powerDownManager, Rank rank, CheckerIF *checker) + : bankMachines(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) { Configuration &config = Configuration::getInstance(); memSpec = config.memSpec; @@ -66,11 +67,6 @@ std::pair RefreshManagerBankwise::getNextCommand return std::pair(Command::NOP, nullptr); } -void RefreshManagerBankwise::block() -{ - blocked = true; -} - sc_time RefreshManagerBankwise::start() { timeToSchedule = sc_max_time(); @@ -213,4 +209,8 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p state = RmState::Precharged; } } + else if (command == Command::PDEA || command == Command::PDEP) + blocked = true; + else if (command == Command::PDXA || command == Command::PDXP) + blocked = false; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index d986ac74..169f4719 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -38,6 +38,7 @@ #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" +#include "../powerdown/PowerDownManager.h" #include #include #include @@ -47,17 +48,17 @@ using namespace tlm; class RefreshManagerBankwise final : public RefreshManagerIF { public: - RefreshManagerBankwise(std::vector &, Rank, CheckerIF *); + RefreshManagerBankwise(std::vector &, PowerDownManager *, Rank, CheckerIF *); std::pair getNextCommand(); sc_time start(); void updateState(Command, tlm_generic_payload *); - void block(); private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; - std::vector bankMachines; + std::vector &bankMachines; + PowerDownManager *powerDownManager; std::vector refreshPayloads; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 301d724e..2d895cf3 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -49,7 +49,6 @@ public: std::pair getNextCommand(); sc_time start(); void updateState(Command, tlm_generic_payload *) {} - void block() {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index d2b78266..d1e589ca 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -50,7 +50,6 @@ public: virtual std::pair getNextCommand() = 0; virtual sc_time start() = 0; virtual void updateState(Command, tlm_generic_payload *) = 0; - virtual void block() = 0; }; #endif // REFRESHMANAGERIF_H From 9d7f17451a460379c3de5e87aa74ef603e61e700 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 21 Nov 2019 00:03:15 +0100 Subject: [PATCH 138/183] Included interface and dummy for power-down manager. --- .../library/src/controller/BankMachine.cpp | 4 +- DRAMSys/library/src/controller/Controller.cpp | 42 +++++++--- DRAMSys/library/src/controller/Controller.h | 4 +- .../controller/powerdown/PowerDownManager.cpp | 78 ++++++++++++++----- .../controller/powerdown/PowerDownManager.h | 26 ++++--- .../powerdown/PowerDownManagerDummy.cpp | 45 +++++++++++ .../powerdown/PowerDownManagerDummy.h | 55 +++++++++++++ .../controller/powerdown/PowerDownManagerIF.h | 60 ++++++++++++++ .../src/controller/refresh/RefreshManager.cpp | 39 +++++++--- .../src/controller/refresh/RefreshManager.h | 10 +-- .../refresh/RefreshManagerBankwise.cpp | 2 +- .../refresh/RefreshManagerBankwise.h | 12 +-- .../controller/refresh/RefreshManagerDummy.h | 6 +- 13 files changed, 310 insertions(+), 73 deletions(-) create mode 100644 DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp create mode 100644 DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h create mode 100644 DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 57ac74f1..543fec2c 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -66,13 +66,11 @@ void BankMachine::updateState(Command command) currentState = BmState::Precharged; currentPayload = nullptr; } - else if (command == Command::PDEA || command == Command::PDEP) + else if (command == Command::PDEA || command == Command::PDEP || command == Command::SREFEN) blocked = true; else if (command == Command::REFA || command == Command::REFB || command == Command::PDXA || command == Command::PDXP) blocked = false; - else - SC_REPORT_FATAL("BankMachine", "Unknown phase"); } void BankMachine::block() diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 7f935710..a4a7ac90 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -53,6 +53,8 @@ #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" +#include "powerdown/PowerDownManager.h" +#include "powerdown/PowerDownManagerDummy.h" Controller::Controller(sc_module_name name) : GenericController(name) @@ -66,6 +68,7 @@ Controller::Controller(sc_module_name name) : maxNumberOfPayloads = config.MaxNrOfTransactions; ranksNumberOfPayloads = std::vector(memSpec->NumberOfRanks, 0); + // instantiate timing checker if (memSpec->MemoryType == "DDR3") checker = new CheckerDDR3(); else if (memSpec->MemoryType == "DDR4") @@ -85,8 +88,9 @@ Controller::Controller(sc_module_name name) : else if (memSpec->MemoryType == "GDDR6") checker = new CheckerGDDR6(); else - SC_REPORT_FATAL("Controller", "Unsupported DRAM type"); + SC_REPORT_FATAL("Controller", "Unsupported DRAM type!"); + // instantiate scheduler and command mux if (config.Scheduler == "FifoStrict") { scheduler = new SchedulerFifo(); @@ -98,8 +102,9 @@ Controller::Controller(sc_module_name name) : commandMux = new CmdMuxOldest(); } else - SC_REPORT_FATAL("Controller", "Selected scheduler not supported"); + SC_REPORT_FATAL("Controller", "Selected scheduler not supported!"); + // instantiate bank machines (one per bank) if (config.OpenPagePolicy) { if (config.AdaptivePagePolicy) @@ -133,14 +138,29 @@ Controller::Controller(sc_module_name name) : bankMachines.begin() + (rankID + 1) * memSpec->BanksPerRank)); } - for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + // instantiate power-down managers (one per rank) + if (config.PowerDownMode == EPowerDownMode::NoPowerDown) { - PowerDownManager *manager = new PowerDownManager(bankMachinesOnRank[rankID], Rank(rankID), checker); - powerDownManagers.push_back(manager); - manager->triggerEntry(); - controllerEvent.notify(manager->start()); + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + { + PowerDownManagerIF *manager = new PowerDownManagerDummy(); + powerDownManagers.push_back(manager); + } } + else if (config.PowerDownMode == EPowerDownMode::Staggered) + { + for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) + { + PowerDownManagerIF *manager = new PowerDownManager(Rank(rankID), checker); + powerDownManagers.push_back(manager); + manager->triggerEntry(TriggerSource::Constructor); + controllerEvent.notify(manager->start()); + } + } + else + SC_REPORT_FATAL("Controller", "Selected power-down mode not supported!"); + // instantiate refresh managers (one per rank) if (config.ControllerCoreRefDisable) { for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) @@ -176,6 +196,8 @@ Controller::~Controller() for (auto it : refreshManagers) delete it; + for (auto it : powerDownManagers) + delete it; for (auto it : bankMachines) delete it; delete commandMux; @@ -216,7 +238,7 @@ void Controller::controllerMethod() PRINTDEBUGMESSAGE(name(), "Total number of payloads exceeded, backpressure!"); } - // (4) Start refresh managers to issue requests for the current time + // (4) Start refresh and power-down managers to issue requests for the current time for (auto it : refreshManagers) it->start(); for (auto it : powerDownManagers) @@ -354,7 +376,7 @@ void Controller::releasePayload() startBandwidthIdleCollector(); if (ranksNumberOfPayloads[rank.ID()] == 0) - powerDownManagers[rank.ID()]->triggerEntry(); + powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); } void Controller::acquirePayload() @@ -368,7 +390,7 @@ void Controller::acquirePayload() endBandwithIdleCollector(); if(ranksNumberOfPayloads[rank.ID()] == 0) - powerDownManagers[rank.ID()]->triggerExit(); + powerDownManagers[rank.ID()]->triggerExit(TriggerSource::Controller); totalNumberOfPayloads++; ranksNumberOfPayloads[rank.ID()]++; diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 94c36392..ed04c5e9 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -50,7 +50,7 @@ #include "../common/DebugManager.h" #include "checker/CheckerIF.h" #include "refresh/RefreshManagerIF.h" -#include "powerdown/PowerDownManager.h" +#include "powerdown/PowerDownManagerIF.h" using namespace tlm; @@ -89,7 +89,7 @@ private: SchedulerIF *scheduler; CheckerIF *checker; std::vector refreshManagers; - std::vector powerDownManagers; + std::vector powerDownManagers; void releasePayload(); void acquirePayload(); diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp index b0fadef6..35c47376 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp @@ -35,24 +35,39 @@ #include "PowerDownManager.h" #include "../../common/utils.h" -PowerDownManager::PowerDownManager(std::vector &bankMachines, Rank rank, CheckerIF *checker) - : bankMachines(bankMachines), rank(rank), checker(checker) +PowerDownManager::PowerDownManager(Rank rank, CheckerIF *checker) + : rank(rank), checker(checker) { setUpDummy(powerDownPayload, rank); } -void PowerDownManager::triggerEntry() +void PowerDownManager::triggerEntry(TriggerSource source) { - if (state == PdmState::Idle) + if (source == TriggerSource::Controller) + controllerIdle = true; + + // TODO: check if state is always idle here + if (state == PdmState::Idle && controllerIdle) triggered = true; } -void PowerDownManager::triggerExit() +void PowerDownManager::triggerExit(TriggerSource source) { - if (state == PdmState::Idle) + if (source == TriggerSource::Controller) + controllerIdle = false; + + if (state == PdmState::Idle) // Controller triggered entry, refresh triggers exit triggered = false; - else + else if (state == PdmState::PrechargePd && source == TriggerSource::RefreshManager && !triggered) + { // last !triggered has to be checked that normal trigger is not overwritten triggered = true; + enterSelfRefresh = true; + } + else + { + triggered = true; + enterSelfRefresh = false; + } } std::pair PowerDownManager::getNextCommand() @@ -72,21 +87,25 @@ sc_time PowerDownManager::start() { if (state == PdmState::Idle) { - nextCommand = Command::PDEP; - for (auto it : bankMachines) - { - if(it->getState() == BmState::Activated) - { - nextCommand = Command::PDEA; - break; - } - } + if (activatedBanks == 0) + nextCommand = Command::PDEP; + else + nextCommand = Command::PDEA; } else if (state == PdmState::ActivePd) nextCommand = Command::PDXA; else if (state == PdmState::PrechargePd) - nextCommand = Command::PDXP; - // TODO: add self refresh + { + if (enterSelfRefresh) + nextCommand = Command::SREFEN; + else + nextCommand = Command::PDXP; + } + else if (state == PdmState::SelfRefresh) + nextCommand = Command::SREFEX; + else // if (state == PdmState::Refresh) + nextCommand = Command::REFA; + delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); timeToSchedule = sc_time_stamp() + delay; } @@ -96,7 +115,13 @@ sc_time PowerDownManager::start() void PowerDownManager::updateState(Command command) { - if (command == Command::PDEA) + if (command == Command::ACT) + activatedBanks++; + else if (command == Command::PRE) + activatedBanks--; + else if (command == Command::PREA) + activatedBanks = 0; + else if (command == Command::PDEA) { state = PdmState::ActivePd; triggered = false; @@ -106,9 +131,24 @@ void PowerDownManager::updateState(Command command) state = PdmState::PrechargePd; triggered = false; } + else if (command == Command::SREFEN) + { + state = PdmState::SelfRefresh; + triggered = false; + enterSelfRefresh = false; + } else if (command == Command::PDXA || command == Command::PDXP) { state = PdmState::Idle; triggered = false; } + else if (command == Command::SREFEX) + { + state = PdmState::Refresh; + } + else if (command == Command::REFA && state == PdmState::Refresh) + { + state = PdmState::Idle; + triggered = false; + } } diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.h b/DRAMSys/library/src/controller/powerdown/PowerDownManager.h index 50692f3a..1394e6ea 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManager.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManager.h @@ -35,35 +35,37 @@ #ifndef POWERDOWNMANAGER_H #define POWERDOWNMANAGER_H +#include "PowerDownManagerIF.h" #include "../BankMachine.h" #include "../checker/CheckerIF.h" using namespace tlm; -class BankMachine; - -class PowerDownManager +class PowerDownManager final : public PowerDownManagerIF { public: - PowerDownManager(std::vector &, Rank, CheckerIF *); + PowerDownManager(Rank, CheckerIF *); - void triggerEntry(); - void triggerExit(); + virtual void triggerEntry(TriggerSource) override; + virtual void triggerExit(TriggerSource) override; - std::pair getNextCommand(); - void updateState(Command); - sc_time start(); + virtual std::pair getNextCommand() override; + virtual void updateState(Command) override; + virtual sc_time start() override; private: - enum class PdmState {Idle, ActivePd, PrechargePd, SelfRefresh} state = PdmState::Idle; - bool triggered = false; - std::vector &bankMachines; + enum class PdmState {Idle, ActivePd, PrechargePd, SelfRefresh, Refresh} state = PdmState::Idle; tlm_generic_payload powerDownPayload; Rank rank; CheckerIF *checker; sc_time timeToSchedule; Command nextCommand; + + bool triggered = false; + bool enterSelfRefresh = false; + bool controllerIdle = true; + unsigned activatedBanks = 0; }; #endif // POWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp new file mode 100644 index 00000000..b24db7fb --- /dev/null +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#include "PowerDownManagerDummy.h" + +std::pair PowerDownManagerDummy::getNextCommand() +{ + return std::pair(Command::NOP, nullptr); +} + +sc_time PowerDownManagerDummy::start() +{ + return sc_max_time() - sc_time_stamp(); +} diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h new file mode 100644 index 00000000..8aef3f54 --- /dev/null +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef POWERDOWNMANAGERDUMMY_H +#define POWERDOWNMANAGERDUMMY_H + +#include "PowerDownManagerIF.h" + +using namespace tlm; + +class PowerDownManagerDummy final : public PowerDownManagerIF +{ +public: + PowerDownManagerDummy() {} + + virtual void triggerEntry(TriggerSource) override {} + virtual void triggerExit(TriggerSource) override {} + + virtual std::pair getNextCommand() override; + virtual void updateState(Command) override {} + virtual sc_time start() override; +}; + +#endif // POWERDOWNMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h new file mode 100644 index 00000000..3a584e29 --- /dev/null +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2019, University of Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Lukas Steiner + */ + +#ifndef POWERDOWNMANAGERIF_H +#define POWERDOWNMANAGERIF_H + +#include +#include +#include +#include "../Command.h" + +using namespace tlm; + +enum class TriggerSource {Constructor, Controller, RefreshManager}; + +class PowerDownManagerIF +{ +public: + virtual ~PowerDownManagerIF() {} + + virtual void triggerEntry(TriggerSource) = 0; + virtual void triggerExit(TriggerSource) = 0; + + virtual std::pair getNextCommand() = 0; + virtual void updateState(Command) = 0; + virtual sc_time start() = 0; +}; + +#endif // POWERDOWNMANAGERIF_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 8f32a3b9..773fae5a 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -38,7 +38,7 @@ #include "../../common/utils.h" RefreshManager::RefreshManager(std::vector &bankMachines, - PowerDownManager *powerDownManager, Rank rank, CheckerIF *checker) + PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) : bankMachines(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) { Configuration &config = Configuration::getInstance(); @@ -66,7 +66,7 @@ sc_time RefreshManager::start() if (sc_time_stamp() >= timeForNextTrigger) { - powerDownManager->triggerExit(); + powerDownManager->triggerExit(TriggerSource::RefreshManager); if (blocked) return sc_max_time() - sc_time_stamp(); @@ -147,19 +147,29 @@ sc_time RefreshManager::start() void RefreshManager::updateState(Command command, tlm_generic_payload *) { + // TODO: first ask if RAS command, otherwise ignore it if (command == Command::REFA) { - if (state == RmState::Pulledin) - flexibilityCounter--; - else - state = RmState::Pulledin; - - if (flexibilityCounter == maxPulledin) + if (blocked) { - state = RmState::Regular; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); - // TODO: is only allowed if all banks are still idle - //powerDownManager->triggerEntry(); + // Refresh command after SREFEX + state = RmState::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalAB(); + blocked = false; + } + else + { + if (state == RmState::Pulledin) + flexibilityCounter--; + else + state = RmState::Pulledin; + + if (flexibilityCounter == maxPulledin) + { + state = RmState::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + powerDownManager->triggerEntry(TriggerSource::RefreshManager); + } } } else if (command == Command::PREA) @@ -172,6 +182,11 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) } else if (command == Command::PDEA || command == Command::PDEP) blocked = true; + else if (command == Command::SREFEN) + { + blocked = true; + timeForNextTrigger = sc_max_time(); + } else if (command == Command::PDXA || command == Command::PDXP) blocked = false; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 36dca117..5c24c0a3 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -46,17 +46,17 @@ using namespace tlm; class RefreshManager final : public RefreshManagerIF { public: - RefreshManager(std::vector &, PowerDownManager *, Rank, CheckerIF *); + RefreshManager(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - std::pair getNextCommand(); - sc_time start(); - void updateState(Command, tlm_generic_payload *); + virtual std::pair getNextCommand() override; + virtual sc_time start() override; + virtual void updateState(Command, tlm_generic_payload *) override; private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; std::vector &bankMachines; - PowerDownManager *powerDownManager; + PowerDownManagerIF *powerDownManager; tlm_generic_payload refreshPayload; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 874d877e..22af8665 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -38,7 +38,7 @@ #include "../../common/dramExtensions.h" RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankMachines, - PowerDownManager *powerDownManager, Rank rank, CheckerIF *checker) + PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker) : bankMachines(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker) { Configuration &config = Configuration::getInstance(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 169f4719..63f8f210 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -38,7 +38,7 @@ #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" -#include "../powerdown/PowerDownManager.h" +#include "../powerdown/PowerDownManagerIF.h" #include #include #include @@ -48,17 +48,17 @@ using namespace tlm; class RefreshManagerBankwise final : public RefreshManagerIF { public: - RefreshManagerBankwise(std::vector &, PowerDownManager *, Rank, CheckerIF *); + RefreshManagerBankwise(std::vector &, PowerDownManagerIF *, Rank, CheckerIF *); - std::pair getNextCommand(); - sc_time start(); - void updateState(Command, tlm_generic_payload *); + virtual std::pair getNextCommand() override; + virtual sc_time start() override; + virtual void updateState(Command, tlm_generic_payload *) override; private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; std::vector &bankMachines; - PowerDownManager *powerDownManager; + PowerDownManagerIF *powerDownManager; std::vector refreshPayloads; sc_time timeForNextTrigger = sc_max_time(); sc_time timeToSchedule = sc_max_time(); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 2d895cf3..3a62916a 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -46,9 +46,9 @@ using namespace tlm; class RefreshManagerDummy final : public RefreshManagerIF { public: - std::pair getNextCommand(); - sc_time start(); - void updateState(Command, tlm_generic_payload *) {} + virtual std::pair getNextCommand() override; + virtual sc_time start() override; + virtual void updateState(Command, tlm_generic_payload *) override {} }; #endif // REFRESHMANAGERDUMMY_H From 4bd9987c9c241f9561a23b044124b7b93e4d302d Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 21 Nov 2019 17:21:54 +0100 Subject: [PATCH 139/183] Staggered power-down with all-bank refresh is working. --- DRAMSys/library/library.pro | 7 ++- DRAMSys/library/src/controller/Controller.cpp | 44 +++++++++------- .../controller/powerdown/PowerDownManager.cpp | 50 +++++++++++-------- .../controller/powerdown/PowerDownManagerIF.h | 2 +- 4 files changed, 60 insertions(+), 43 deletions(-) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 02051018..917ee599 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -151,7 +151,8 @@ SOURCES += \ src/simulation/dram/DramGDDR5.cpp \ src/simulation/dram/DramGDDR5X.cpp \ src/simulation/dram/DramGDDR6.cpp \ - src/controller/powerdown/PowerDownManager.cpp + src/controller/powerdown/PowerDownManager.cpp \ + src/controller/powerdown/PowerDownManagerDummy.cpp HEADERS += \ src/common/third_party/tinyxml2/tinyxml2.h \ @@ -235,7 +236,9 @@ HEADERS += \ src/simulation/dram/DramGDDR5.h \ src/simulation/dram/DramGDDR5X.h \ src/simulation/dram/DramGDDR6.h \ - src/controller/powerdown/PowerDownManager.h + src/controller/powerdown/PowerDownManager.h \ + src/controller/powerdown/PowerDownManagerIF.h \ + src/controller/powerdown/PowerDownManagerDummy.h #src/common/third_party/json/include/nlohmann/json.hpp \ thermalsim = $$(THERMALSIM) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index a4a7ac90..0a63fa41 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -153,7 +153,7 @@ Controller::Controller(sc_module_name name) : { PowerDownManagerIF *manager = new PowerDownManager(Rank(rankID), checker); powerDownManagers.push_back(manager); - manager->triggerEntry(TriggerSource::Constructor); + manager->triggerEntry(TriggerSource::Controller); controllerEvent.notify(manager->start()); } } @@ -239,6 +239,7 @@ void Controller::controllerMethod() } // (4) Start refresh and power-down managers to issue requests for the current time + // TODO: check if the order of start() matters for (auto it : refreshManagers) it->start(); for (auto it : powerDownManagers) @@ -246,31 +247,36 @@ void Controller::controllerMethod() // (5) Choose one request and send it to DRAM std::pair commandPair; - std::vector> readyCommands; - bool readyCmdBlocked = false; - // TODO: check if all parts have to be called - // (5.1) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachines) - { - commandPair = it->getNextCommand(); - if (commandPair.second != nullptr) - readyCommands.push_back(commandPair); - } - // (5.2) Check for refresh commands (PREA/PRE or REFA/REFB) - for (auto it : refreshManagers) - { - commandPair = it->getNextCommand(); - if (commandPair.second != nullptr) - readyCommands.push_back(commandPair); - } - // (5.3) Check for power-down commands (...TODO) + std::vector> readyCommands; + // (5.1) Check for power-down commands (PDEA/PDEP/SREFEN or PDXA/PDXP/SREFEX) for (auto it : powerDownManagers) { commandPair = it->getNextCommand(); if (commandPair.second != nullptr) readyCommands.push_back(commandPair); } + if (readyCommands.empty()) + { + // (5.2) Check for refresh commands (PREA/PRE or REFA/REFB) + for (auto it : refreshManagers) + { + commandPair = it->getNextCommand(); + if (commandPair.second != nullptr) + readyCommands.push_back(commandPair); + } + if (readyCommands.empty()) + { + // (5.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) + for (auto it : bankMachines) + { + commandPair = it->getNextCommand(); + if (commandPair.second != nullptr) + readyCommands.push_back(commandPair); + } + } + } + bool readyCmdBlocked = false; if (!readyCommands.empty()) { commandPair = commandMux->selectCommand(readyCommands); diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp index 35c47376..c81efa30 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp @@ -54,19 +54,26 @@ void PowerDownManager::triggerEntry(TriggerSource source) void PowerDownManager::triggerExit(TriggerSource source) { if (source == TriggerSource::Controller) - controllerIdle = false; - - if (state == PdmState::Idle) // Controller triggered entry, refresh triggers exit - triggered = false; - else if (state == PdmState::PrechargePd && source == TriggerSource::RefreshManager && !triggered) - { // last !triggered has to be checked that normal trigger is not overwritten - triggered = true; - enterSelfRefresh = true; - } - else { - triggered = true; + controllerIdle = false; enterSelfRefresh = false; + + if (state == PdmState::Idle) + triggered = false; + else + triggered = true; + } + else // if (source == TriggerSource::RefreshManager) + { + if (state == PdmState::Idle && !enterSelfRefresh) + triggered = false; + else if (state == PdmState::PrechargePd && !triggered) + { + triggered = true; + enterSelfRefresh = true; + } + else if (state == PdmState::ActivePd) // TODO: check if normal else is also ok here + triggered = true; } } @@ -87,7 +94,9 @@ sc_time PowerDownManager::start() { if (state == PdmState::Idle) { - if (activatedBanks == 0) + if (enterSelfRefresh) + nextCommand = Command::SREFEN; + else if (activatedBanks == 0) nextCommand = Command::PDEP; else nextCommand = Command::PDEA; @@ -95,12 +104,7 @@ sc_time PowerDownManager::start() else if (state == PdmState::ActivePd) nextCommand = Command::PDXA; else if (state == PdmState::PrechargePd) - { - if (enterSelfRefresh) - nextCommand = Command::SREFEN; - else - nextCommand = Command::PDXP; - } + nextCommand = Command::PDXP; else if (state == PdmState::SelfRefresh) nextCommand = Command::SREFEX; else // if (state == PdmState::Refresh) @@ -137,15 +141,19 @@ void PowerDownManager::updateState(Command command) triggered = false; enterSelfRefresh = false; } - else if (command == Command::PDXA || command == Command::PDXP) + else if (command == Command::PDXA) { state = PdmState::Idle; triggered = false; } - else if (command == Command::SREFEX) + else if (command == Command::PDXP) { - state = PdmState::Refresh; + state = PdmState::Idle; + if (!enterSelfRefresh) + triggered = false; } + else if (command == Command::SREFEX) + state = PdmState::Refresh; else if (command == Command::REFA && state == PdmState::Refresh) { state = PdmState::Idle; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h index 3a584e29..d6a12ac4 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h @@ -42,7 +42,7 @@ using namespace tlm; -enum class TriggerSource {Constructor, Controller, RefreshManager}; +enum class TriggerSource {Controller, RefreshManager}; class PowerDownManagerIF { From 037cd4f334e47afbdef789ddfaf433b992c53d8b Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 21 Nov 2019 21:38:52 +0100 Subject: [PATCH 140/183] Removed old controller core files. --- DRAMSys/library/library.pro | 4 +- DRAMSys/library/src/controller/Controller.cpp | 4 +- DRAMSys/library/src/controller/Controller.h | 2 +- .../core/powerdown/IPowerDownManager.h | 129 ---------- .../controller/core/powerdown/NoPowerDown.cpp | 63 ----- .../controller/core/powerdown/NoPowerDown.h | 65 ------ .../core/powerdown/PowerDownManager.cpp | 220 ------------------ .../core/powerdown/PowerDownManager.h | 71 ------ .../powerdown/PowerDownManagerBankwise.cpp | 216 ----------------- .../core/powerdown/PowerDownManagerBankwise.h | 86 ------- .../powerdown/PowerDownManagerTimeout.cpp | 142 ----------- .../core/powerdown/PowerDownManagerTimeout.h | 63 ----- .../PowerDownManagerTimeoutBankwise.cpp | 135 ----------- .../PowerDownManagerTimeoutBankwise.h | 63 ----- ...ager.cpp => PowerDownManagerStaggered.cpp} | 14 +- ...nManager.h => PowerDownManagerStaggered.h} | 10 +- .../src/controller/refresh/RefreshManager.h | 2 +- 17 files changed, 18 insertions(+), 1271 deletions(-) delete mode 100644 DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h delete mode 100644 DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp delete mode 100644 DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp delete mode 100644 DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h rename DRAMSys/library/src/controller/powerdown/{PowerDownManager.cpp => PowerDownManagerStaggered.cpp} (91%) rename DRAMSys/library/src/controller/powerdown/{PowerDownManager.h => PowerDownManagerStaggered.h} (91%) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 917ee599..36c5861b 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -151,7 +151,7 @@ SOURCES += \ src/simulation/dram/DramGDDR5.cpp \ src/simulation/dram/DramGDDR5X.cpp \ src/simulation/dram/DramGDDR6.cpp \ - src/controller/powerdown/PowerDownManager.cpp \ + src/controller/powerdown/PowerDownManagerStaggered.cpp \ src/controller/powerdown/PowerDownManagerDummy.cpp HEADERS += \ @@ -236,7 +236,7 @@ HEADERS += \ src/simulation/dram/DramGDDR5.h \ src/simulation/dram/DramGDDR5X.h \ src/simulation/dram/DramGDDR6.h \ - src/controller/powerdown/PowerDownManager.h \ + src/controller/powerdown/PowerDownManagerStaggered.h \ src/controller/powerdown/PowerDownManagerIF.h \ src/controller/powerdown/PowerDownManagerDummy.h #src/common/third_party/json/include/nlohmann/json.hpp \ diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 0a63fa41..b097d268 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -53,7 +53,7 @@ #include "refresh/RefreshManager.h" #include "refresh/RefreshManagerDummy.h" #include "refresh/RefreshManagerBankwise.h" -#include "powerdown/PowerDownManager.h" +#include "powerdown/PowerDownManagerStaggered.h" #include "powerdown/PowerDownManagerDummy.h" Controller::Controller(sc_module_name name) : @@ -151,7 +151,7 @@ Controller::Controller(sc_module_name name) : { for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) { - PowerDownManagerIF *manager = new PowerDownManager(Rank(rankID), checker); + PowerDownManagerIF *manager = new PowerDownManagerStaggered(Rank(rankID), checker); powerDownManagers.push_back(manager); manager->triggerEntry(TriggerSource::Controller); controllerEvent.notify(manager->start()); diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index ed04c5e9..02a93b92 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -56,7 +56,7 @@ using namespace tlm; class BankMachine; class SchedulerIF; -class PowerDownManager; +class PowerDownManagerStaggered; class Controller : public GenericController { diff --git a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h deleted file mode 100644 index 047cb407..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/IPowerDownManager.h +++ /dev/null @@ -1,129 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// */ - -//#ifndef IPOWERDOWNMANAGER_H -//#define IPOWERDOWNMANAGER_H - -//#include -//#include "../../../common/dramExtensions.h" -//#include "../../Command.h" - - -//enum class PowerDownState { -// Awake, AwakeForRefresh, PDNActive, PDNPrecharge, PDNSelfRefresh -//}; - -//class IPowerDownManager -//{ -//public: -// virtual ~IPowerDownManager() {} - -// virtual void sleep(Bank bank, sc_time time) = 0; -// virtual void triggerSleep(Bank bank, sc_time time) = 0; - -// virtual void wakeUp(Bank bank, sc_time time) = 0; -// virtual void wakeUpForRefresh(Bank bank, sc_time time) = 0; - -// virtual bool isInSelfRefresh(Bank bank) = 0; - -//protected: -// Command getSleepCommand(PowerDownState state); -// Command getWakeUpCommand(PowerDownState state); - -//}; - -//inline Command IPowerDownManager::getSleepCommand(PowerDownState state) -//{ -// Command cmd(Command::NOP); -// switch (state) { -// case PowerDownState::PDNActive: -// cmd = Command::PDEA; -// break; -// case PowerDownState::PDNPrecharge: -// cmd = Command::PDEP; -// break; -// case PowerDownState::PDNSelfRefresh: -// cmd = Command::SREFEN; -// break; -// default: -// SC_REPORT_FATAL("In PowerDownManager sendPowerdownBegin", -// "invalid powerDownState"); -// break; -// } -// return cmd; -//} - -//inline Command IPowerDownManager::getWakeUpCommand(PowerDownState state) - -//{ -// Command cmd(Command::NOP); -// switch (state) { -// case PowerDownState::PDNActive: -// cmd = Command::PDXA; -// break; -// case PowerDownState::PDNPrecharge: -// cmd = Command::PDXP; -// break; -// case PowerDownState::PDNSelfRefresh: -// cmd = Command::SREFEX; -// break; -// default: -// SC_REPORT_FATAL("In PowerDownManager sendPowerdownEnd", -// "invalid powerDownState"); -// } -// return cmd; -//} - -//inline std::string powerDownStateToString(PowerDownState powerDownState) -//{ -// switch (powerDownState) { -// case PowerDownState::Awake: -// return "Awake"; -// case PowerDownState::AwakeForRefresh: -// return "Awake for refresh"; -// case PowerDownState::PDNActive: -// return "PDN Active"; -// case PowerDownState::PDNPrecharge: -// return "PDN Precharged"; -// case PowerDownState::PDNSelfRefresh: -// return "PDN Self refresh"; -// default: -// return "unknown state"; -// } -//} - - -//#endif // IPOWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp deleted file mode 100644 index 97c8bd30..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.cpp +++ /dev/null @@ -1,63 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// */ - -//#include "NoPowerDown.h" - -//void NoPowerDown::triggerSleep(Bank /*bank*/, sc_time /*time*/) -//{ -// return; -//} - -//void NoPowerDown::sleep(Bank /*bank*/, sc_time /*time*/) -//{ -// return; -//} - -//void NoPowerDown::wakeUp(Bank /*bank*/, sc_time /*time*/) -//{ -// return; -//} - -//void NoPowerDown::wakeUpForRefresh(Bank /*bank*/, sc_time /*time*/) -//{ -// return; -//} - -//bool NoPowerDown::isInSelfRefresh(Bank /*bank*/) -//{ -// return false; -//} diff --git a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h b/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h deleted file mode 100644 index 4dd70adc..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/NoPowerDown.h +++ /dev/null @@ -1,65 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// */ - -//#ifndef NOPOWERDOWN_H -//#define NOPOWERDOWN_H - -//#include "PowerDownManager.h" -//#include -//#include "../../../common/dramExtensions.h" -//#include "../scheduling/ScheduledCommand.h" - - - -//class NoPowerDown : public IPowerDownManager -//{ -//public: -// NoPowerDown() {} -// virtual ~NoPowerDown() {} - -// virtual void triggerSleep(Bank bank, sc_time time) override; -// virtual void sleep(Bank bank, sc_time time) override; - -// virtual void wakeUp(Bank bank, sc_time time) override; -// virtual void wakeUpForRefresh(Bank bank, sc_time time) override; - -// virtual bool isInSelfRefresh(Bank bank) override; -//}; - - - -//#endif // NOPOWERDOWN_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp deleted file mode 100644 index 15ddf00a..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.cpp +++ /dev/null @@ -1,220 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// * Felipe S. Prado -// */ - -//#include -//#include -//#include "PowerDownManager.h" -//#include "../ControllerCore.h" -//#include "../timingCalculations.h" -//#include "../../../common/DebugManager.h" -//#include -//#include "../../../common/utils.h" - -//using namespace tlm; -//using namespace std; - - -//PowerDownManager::PowerDownManager(sc_module_name /*name*/, -// ControllerCore &controller) : -// controllerCore(controller) -//{ -// powerDownState = PowerDownState::Awake; -// for (Bank bank : controller.getBanks()) { -// setUpDummy(powerDownPayloads[bank], bank); -// } -// //controllerCore.controller.send(PDNTrigger, sc_time_stamp(), powerDownPayloads[Bank(0)]); -//} - -//PowerDownManager::~PowerDownManager() -//{ - -//} - -//void PowerDownManager::sleep(Bank /*bank*/, sc_time time) -//{ -// if (!canSleep() || isInPowerDown()) -// return; - -// PowerDownState state = powerDownState; - -// if (state == PowerDownState::Awake) { //coming from active -// state = controllerCore.state->rowBufferStates->allRowBuffersAreClosed() ? -// PowerDownState::PDNPrecharge : PowerDownState::PDNActive; -// } else if (state == -// PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down -// sc_assert(controllerCore.state->rowBufferStates->allRowBuffersAreClosed()); - -// if (controllerCore.state->getLastCommand(Command::PDEA).getStart() -// >= controllerCore.state->getLastCommand(Command::PDEP).getStart()) -// state = PowerDownState::PDNPrecharge; -// else { -// state = PowerDownState::PDNSelfRefresh; -// } -// } - -// Command cmd = IPowerDownManager::getSleepCommand(state); -// ScheduledCommand pdn(cmd, time, -// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), -// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - -// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - -// if (state != PowerDownState::PDNSelfRefresh -// && controllerCore.refreshManager->hasCollision(pdn)) { -// return; -// } else { -// setPowerDownState(state); -// sendPowerDownPayload(pdn); -// } -//} - -//void PowerDownManager::wakeUp(Bank bank, sc_time time) -//{ -// printDebugMessage("Waking up at " + time.to_string() + -// " current power down state is " + powerDownStateToString(powerDownState)); - -// if (isAwakeForRefresh()) { //Request enters system during Refresh -// setPowerDownState(PowerDownState::Awake); -// } else if (isInPowerDown()) { //Request wakes up power down -// Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); -// ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, -// powerDownPayloads[Bank(0)]), -// DramExtension::getExtension(powerDownPayloads[Bank(0)])); -// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - -// if (cmd == Command::SREFEX) { -// // Leaving Self Refresh. Plan the next refresh. -// controllerCore.refreshManager->reInitialize(bank, pdn.getEnd()); -// printDebugMessage("Waking up. Leaving Self Refresh at " + time.to_string() + -// " next refresh planned to " + pdn.getEnd().to_string()); -// } - -// setPowerDownState(PowerDownState::Awake); - -// printDebugMessage("Sending power down exit command " + commandToString( -// cmd) + " on all banks"); -// sendPowerDownPayload(pdn); -// } - -// printDebugMessage("Awaken at " + time.to_string() + -// " current power down state is " + powerDownStateToString(powerDownState)); -//} - -//void PowerDownManager::wakeUpForRefresh(Bank /*bank*/, sc_time time) -//{ -// printDebugMessage("Waking up for refresh at " + time.to_string() + -// " current power down state is " + powerDownStateToString(powerDownState)); - -// if (isInPowerDown()) { -// Command cmd = IPowerDownManager::getWakeUpCommand(powerDownState); -// ScheduledCommand pdn(cmd, time, Configuration::getInstance().memSpec->getExecutionTime(cmd, -// powerDownPayloads[Bank(0)]), -// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - -// setPowerDownState(PowerDownState::AwakeForRefresh); - -// printDebugMessage("Sending power down exit command " + commandToString( -// cmd) + " on all banks"); -// sendPowerDownPayload(pdn); -// } - -// printDebugMessage("Awaken for refresh at " + time.to_string() + -// " current power down state is " + powerDownStateToString(powerDownState)); -//} - -//void PowerDownManager::sendPowerDownPayload(ScheduledCommand &pdnToSend) -//{ -// controllerCore.state->bus.moveCommandToNextFreeSlot(pdnToSend); -// for (size_t bank = 1; bank < controllerCore.getBanks().size(); bank++) { -// tlm_generic_payload &payloadToSend = powerDownPayloads[bank]; - -// ScheduledCommand pdn(pdnToSend.getCommand(), pdnToSend.getStart(), -// pdnToSend.getExecutionTime(), DramExtension::getExtension(payloadToSend)); -// controllerCore.state->change(pdn); - -// } -// controllerCore.state->change(pdnToSend); -// controllerCore.controller.send(pdnToSend, powerDownPayloads[Bank(0)]); -// printDebugMessage("Sending power down command " + commandToString( -// pdnToSend.getCommand()) + " on bank " + to_string(pdnToSend.getBank().ID()) + -// " start time " + pdnToSend.getStart().to_string() + " end time " + -// pdnToSend.getEnd().to_string()); -//} - -//void PowerDownManager::setPowerDownState(PowerDownState state) -//{ -// powerDownState = state; -// printDebugMessage("Is now in state " + powerDownStateToString( -// powerDownState) + " on all banks"); -//} - -//bool PowerDownManager::isInPowerDown() -//{ -// return (powerDownState == PowerDownState::PDNActive -// || powerDownState == PowerDownState::PDNPrecharge -// || powerDownState == PowerDownState::PDNSelfRefresh); -//} - -//bool PowerDownManager::canSleep() -//{ -// for (Bank bank : controllerCore.getBanks()) { -// if (!controllerCore.numberOfPayloads[bank] == 0) -// return false; -// } -// return true; -//} - -//bool PowerDownManager::isInSelfRefresh(Bank /*bank*/) -//{ -// return powerDownState == PowerDownState::PDNSelfRefresh; -//} - -//bool PowerDownManager::isAwakeForRefresh() -//{ -// return powerDownState == PowerDownState::AwakeForRefresh; -//} - -//void PowerDownManager::triggerSleep(Bank bank, sc_time time) -//{ -// sleep(bank, time); -//} - -//void PowerDownManager::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage(this->name(), message); -//} - diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h deleted file mode 100644 index bd7ffd3d..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManager.h +++ /dev/null @@ -1,71 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// */ - -//#ifndef POWERDOWNMANAGER_H -//#define POWERDOWNMANAGER_H - -//#include "PowerDownManagerBankwise.h" - - -//class ControllerCore; - -//class PowerDownManager: public IPowerDownManager, public sc_module -//{ -//public: -// PowerDownManager(sc_module_name /*name*/, ControllerCore &controllerCore); -// virtual ~PowerDownManager(); - -// virtual void triggerSleep(Bank bank, sc_time time) override; -// virtual void sleep(Bank /*bank*/, sc_time time) override; -// virtual void wakeUp(Bank bank, sc_time time) override; -// virtual void wakeUpForRefresh(Bank bank, sc_time time) override; -// virtual bool isInSelfRefresh(Bank bank) override; - -//protected: -// void sendPowerDownPayload(ScheduledCommand &pdnToSend); -// bool isInPowerDown(); -// void setPowerDownState(PowerDownState state); -// bool canSleep(); -// bool isAwakeForRefresh(); - -// PowerDownState powerDownState; -// std::map powerDownPayloads; -// ControllerCore &controllerCore; -// void printDebugMessage(std::string message); -//}; - - -//#endif // POWERDOWNMANAGER_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp deleted file mode 100644 index 4b9e125c..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.cpp +++ /dev/null @@ -1,216 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// */ - -//#include "PowerDownManager.h" -//#include "../ControllerCore.h" -//#include "../../../common/utils.h" -//#include "../../../common/DebugManager.h" -//#include "../timingCalculations.h" - -//using namespace tlm; - -//PowerDownManagerBankwise::PowerDownManagerBankwise(sc_module_name /*name*/, -// ControllerCore &controllerCore) : controllerCore(controllerCore) -//{ -// for (Bank bank : controllerCore.getBanks()) { -// setUpDummy(powerDownPayloads[bank], bank); -// powerDownStates[bank] = PowerDownState::Awake; -// //controllerCore.controller.send(PDNTrigger, sc_time_stamp(), powerDownPayloads[bank]); -// } -//} - -//void PowerDownManagerBankwise::sleep(Bank bank, sc_time time) -//{ -// if (!canSleep(bank) || isInPowerDown(bank)) -// return; - -// tlm_generic_payload &payload = powerDownPayloads[bank]; - -// PowerDownState state = powerDownStates[bank]; -// if (state == PowerDownState::Awake) { //coming from active -// state = controllerCore.state->rowBufferStates->rowBufferIsOpen( -// bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; -// } else if (state == -// PowerDownState::AwakeForRefresh) { //coming from refresh interrupting power down -// sc_assert(!controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)); - -// if (controllerCore.state->getLastCommand(Command::PDEA, bank).getStart() -// >= controllerCore.state->getLastCommand(Command::PDEP, bank).getStart()) -// state = PowerDownState::PDNPrecharge; -// else { -// state = PowerDownState::PDNSelfRefresh; -// } -// } - -// Command cmd = IPowerDownManager::getSleepCommand(state); -// ScheduledCommand pdn(cmd, time, -// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), -// DramExtension::getExtension(payload)); -// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - -// if (state != PowerDownState::PDNSelfRefresh -// && controllerCore.refreshManager->hasCollision(pdn)) { -// return; -// } else { -// setPowerDownState(state, bank); -// sendPowerDownPayload(pdn); -// } -//} - -//void PowerDownManagerBankwise::wakeUp(Bank bank, sc_time time) -//{ -// printDebugMessage("Waking up on bank " + to_string(bank.ID()) + " at " + -// time.to_string() + " current power down state is " + powerDownStateToString( -// powerDownStates[bank])); - -// if (isAwakeForRefresh(bank)) { -// printDebugMessage("It was already awake for refresh on bank " + to_string( -// bank.ID()) + " at " + time.to_string()); -// setPowerDownState(PowerDownState::Awake, bank); -// } else if (isInPowerDown(bank)) { -// // Request wake up from power down. A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). -// Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); -// // Mount the command to be scheduled -// ScheduledCommand pdnExit(pdnExitCmd, time, Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, -// powerDownPayloads[bank]), DramExtension::getExtension(powerDownPayloads[bank])); -// // Ensure that time constraints are respected -// controllerCore.getCommandChecker(pdnExitCmd).delayToSatisfyConstraints(pdnExit); - -// if (pdnExitCmd == Command::SREFEX) { -// // Leaving Self Refresh. Plan the next refresh. -// controllerCore.refreshManager->reInitialize(bank, pdnExit.getEnd()); -// printDebugMessage("Waking up. Leaving Self Refresh on Bank " + to_string( -// bank.ID()) + " at " + time.to_string() + " next refresh planned to " + -// pdnExit.getEnd().to_string()); -// } - -// setPowerDownState(PowerDownState::Awake, bank); - -// printDebugMessage("Sending power down exit command " + commandToString( -// pdnExitCmd) + " on bank " + to_string(bank.ID()) + " at " + time.to_string() + -// " start time " + pdnExit.getStart().to_string() + " end time " + -// pdnExit.getEnd().to_string()); -// sendPowerDownPayload(pdnExit); -// } - -// printDebugMessage("Awaken on bank " + to_string(bank.ID()) + " at " + -// time.to_string() + " current power down state is " + powerDownStateToString( -// powerDownStates[bank])); -//} - -//void PowerDownManagerBankwise::wakeUpForRefresh(Bank bank, sc_time time) -//{ -// printDebugMessage("Waking up for refresh on bank " + to_string( -// bank.ID()) + " at " + time.to_string() + " current power down state is " + -// powerDownStateToString(powerDownStates[bank])); - -// if (isInPowerDown(bank)) { -// // A Power Down Exit request will be generated (PDNAX, PDNPX, SREFX). -// Command pdnExitCmd = IPowerDownManager::getWakeUpCommand(powerDownStates[bank]); -// // Get the execution time for this request -// sc_time executionTime = Configuration::getInstance().memSpec->getExecutionTime(pdnExitCmd, powerDownPayloads[bank]); -// // Mount the command to be scheduled -// ScheduledCommand pdnExit(pdnExitCmd, time, executionTime, -// DramExtension::getExtension(powerDownPayloads[bank])); - -// setPowerDownState(PowerDownState::AwakeForRefresh, bank); - -// printDebugMessage("Sending power down exit command " + commandToString( -// pdnExitCmd) + " on bank " + to_string(bank.ID()) + " at " + time.to_string() + -// " start time " + pdnExit.getStart().to_string() + " end time " + -// pdnExit.getEnd().to_string()); -// sendPowerDownPayload(pdnExit); -// } - -// printDebugMessage("Awaken for refresh on bank " + to_string( -// bank.ID()) + " at " + time.to_string() + " current power down state is " + -// powerDownStateToString(powerDownStates[bank])); -//} - -//bool PowerDownManagerBankwise::isInPowerDown(Bank bank) -//{ -// return isIn(powerDownStates[bank], { PowerDownState::PDNActive, PowerDownState::PDNPrecharge, PowerDownState::PDNSelfRefresh }); -//} - -//bool PowerDownManagerBankwise::isInSelfRefresh(Bank bank) -//{ -// return powerDownStates[bank] == PowerDownState::PDNSelfRefresh; -//} - -//bool PowerDownManagerBankwise::isAwakeForRefresh(Bank bank) -//{ -// return powerDownStates[bank] == PowerDownState::AwakeForRefresh; -//} - -//bool PowerDownManagerBankwise::isAwake(Bank bank) -//{ -// return powerDownStates[bank] == PowerDownState::Awake; -//} - -//void PowerDownManagerBankwise::setPowerDownState(PowerDownState state, -// Bank bank) -//{ -// PowerDownState &bankstate = powerDownStates[bank]; -// bankstate = state; -// printDebugMessage("Is now in state " + powerDownStateToString( -// state) + " on Bank " + to_string(bank.ID())); -//} - -//void PowerDownManagerBankwise::sendPowerDownPayload(ScheduledCommand &pdn) -//{ -// controllerCore.state->bus.moveCommandToNextFreeSlot(pdn); -// controllerCore.state->change(pdn); -// printDebugMessage("Sending power down command " + commandToString( -// pdn.getCommand()) + " on bank " + to_string(pdn.getBank().ID()) + " start time " -// + pdn.getStart().to_string() + " end time " + pdn.getEnd().to_string()); -// controllerCore.controller.send(pdn, powerDownPayloads[pdn.getBank()]); -//} - -//bool PowerDownManagerBankwise::canSleep(Bank bank) -//{ -// return controllerCore.numberOfPayloads[bank] == 0; -//} - -//void PowerDownManagerBankwise::triggerSleep(Bank bank, sc_time time) -//{ -// sleep(bank, time); -//} - -//void PowerDownManagerBankwise::printDebugMessage(std::string message) -//{ -// DebugManager::getInstance().printDebugMessage(this->name(), message); -//} - diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h deleted file mode 100644 index 07d32ba1..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerBankwise.h +++ /dev/null @@ -1,86 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Matthias Jung -// */ - -//#ifndef POWERDOWNMANAGERBANKWISE_H -//#define POWERDOWNMANAGERBANKWISE_H - -//#include -//#include -//#include -//#include -//#include "../../Command.h" -//#include "../../../common/dramExtensions.h" -//#include "../scheduling/ScheduledCommand.h" -//#include "IPowerDownManager.h" - - -//class ControllerCore; - -//class PowerDownManagerBankwise : public sc_module, public IPowerDownManager -//{ -//public: -// PowerDownManagerBankwise(sc_module_name /*name*/, -// ControllerCore &controllerCore); -// virtual ~PowerDownManagerBankwise() {} -// virtual void triggerSleep(Bank bank, sc_time time) override; -// virtual void sleep(Bank bank, sc_time time) override; -// virtual void wakeUp(Bank bank, sc_time time) override; -// virtual void wakeUpForRefresh(Bank bank, sc_time time) override; -// virtual bool isInSelfRefresh(Bank bank) override; - -//protected: -// virtual bool isInPowerDown(Bank bank); -// virtual bool isAwake(Bank bank); -// virtual bool isAwakeForRefresh(Bank bank); - -// ControllerCore &controllerCore; -// std::map powerDownPayloads; -// std::map powerDownStates; - -// virtual bool canSleep(Bank bank); - -// void setPowerDownState(PowerDownState state, Bank bank); - -// Command getWakeUpCommand(PowerDownState state); -// Command getSleepCommand(PowerDownState state); - -// void sendPowerDownPayload(ScheduledCommand &pdn); - -// void printDebugMessage(std::string message); -//}; - -//#endif // POWERDOWNMANAGERBANKWISE_H - diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp deleted file mode 100644 index 65a9a45d..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.cpp +++ /dev/null @@ -1,142 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// * Felipe S. Prado -// */ - -//#include "PowerDownManagerTimeout.h" -//#include "../ControllerCore.h" -//#include "../../../common/utils.h" -//#include "../../../common/DebugManager.h" -//#include "../timingCalculations.h" - -//using namespace tlm; - -//PowerDownManagerTimeout::PowerDownManagerTimeout(sc_module_name name, -// ControllerCore &controllerCore): -// PowerDownManager(name, controllerCore) -//{ -// //controllerCore.controller.send(PDNTrigger, Configuration::getInstance().getPowerDownTimeout(), powerDownPayloads[Bank(0)]); -//} - -//PowerDownManagerTimeout::~PowerDownManagerTimeout() -//{ -// // TODO Auto-generated destructor stub -//} - -//void PowerDownManagerTimeout::sleep(Bank /*bank*/, sc_time time) -//{ -// bool timeoutTest; -// if (!isAwakeForRefresh()) { -// sc_time lastReadScheduled; -// sc_time lastWriteScheduled; -// if (Configuration::getInstance().OpenPagePolicy) { -// lastReadScheduled = controllerCore.state->getLastCommand( -// Command::RD).getEnd(); -// lastWriteScheduled = controllerCore.state->getLastCommand( -// Command::WR).getEnd(); -// } else { -// lastReadScheduled = controllerCore.state->getLastCommand( -// Command::RDA).getEnd(); -// lastWriteScheduled = controllerCore.state->getLastCommand( -// Command::WRA).getEnd(); -// } -// sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); -// timeoutTest = (time - lastScheduledCommand) >= -// Configuration::getInstance().getPowerDownTimeout(); -// } else { -// timeoutTest = true; -// } - -// //test_awakeForRefresh = false; - -// if ( canSleep() && !isInPowerDown() && timeoutTest) { - -// PowerDownState newState; -// if (Configuration::getInstance().PowerDownMode == EPowerDownMode::TimeoutPDN) { -// newState = controllerCore.state->rowBufferStates->allRowBuffersAreClosed() ? -// PowerDownState::PDNPrecharge : PowerDownState::PDNActive; -// } else { // PowerDownMode == TimeoutSREF -// if (!controllerCore.state->rowBufferStates->allRowBuffersAreClosed()) { -// ScheduledCommand prechargeAllMaster(Command::PREA, time, -// Configuration::getInstance().memSpec->getExecutionTime( -// Command::PREA, powerDownPayloads[Bank(0)]), -// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - -// controllerCore.getCommandChecker( -// Command::PREA).delayToSatisfyConstraints(prechargeAllMaster); - -// if (controllerCore.refreshManager->hasCollision(prechargeAllMaster)) { -// return; -// } else { -// for (size_t i = 1; i < controllerCore.getBanks().size(); i++) { -// ScheduledCommand prechargeAll(Command::PREA, -// prechargeAllMaster.getStart(), prechargeAllMaster.getExecutionTime(), -// powerDownPayloads[Bank(i)]); -// controllerCore.state->change(prechargeAll); -// } -// controllerCore.state->change(prechargeAllMaster); -// controllerCore.controller.send(prechargeAllMaster, powerDownPayloads[Bank(0)]); -// } - -// } - -// newState = PowerDownState::PDNSelfRefresh; -// } - -// Command cmd = IPowerDownManager::getSleepCommand(newState); -// ScheduledCommand pdn(cmd, time, -// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), -// DramExtension::getExtension(powerDownPayloads[Bank(0)])); - -// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - -// if (controllerCore.refreshManager->hasCollision(pdn)) { -// return; -// } else { -// setPowerDownState(newState); -// sendPowerDownPayload(pdn); -// } -// } -//} - -//void PowerDownManagerTimeout::triggerSleep(Bank /*bank*/, sc_time time) -//{ -// if (canSleep() && !isInPowerDown()) { -// controllerCore.controller.send(PDNTrigger, -// time + controllerCore.config.getPowerDownTimeout(), powerDownPayloads[Bank(0)]); -// } -//} - diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h deleted file mode 100644 index 48b36b0b..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeout.h +++ /dev/null @@ -1,63 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// * Felipe S. Prado -// */ - -//#ifndef POWERDOWNMANAGERTIMEOUT_H -//#define POWERDOWNMANAGERTIMEOUT_H - -//#include "PowerDownManager.h" -//#include -//#include "../../../common/dramExtensions.h" -//#include "../scheduling/ScheduledCommand.h" -//#include - -//class ControllerCore; - -//class PowerDownManagerTimeout: public PowerDownManager -//{ -//public: -// PowerDownManagerTimeout(sc_module_name /*name*/, -// ControllerCore &controllerCore); -// virtual ~PowerDownManagerTimeout(); - -// virtual void triggerSleep(Bank /*bank*/, sc_time time); -// virtual void sleep(Bank /*bank*/, sc_time time); -//}; - - - -//#endif // POWERDOWNMANAGERTIMEOUT_H diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp deleted file mode 100644 index 83535fc6..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp +++ /dev/null @@ -1,135 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// * Felipe S. Prado -// */ - -//#include "PowerDownManagerTimeoutBankwise.h" -//#include "../ControllerCore.h" -//#include "../../../common/utils.h" -//#include "../../../common/DebugManager.h" -//#include "../timingCalculations.h" - -//using namespace tlm; - -//PowerDownManagerTimeoutBankwise::PowerDownManagerTimeoutBankwise( -// sc_module_name name, ControllerCore &controllerCore): -// PowerDownManagerBankwise(name, controllerCore) -//{ -// /*for (Bank bank : controllerCore.getBanks()) -// { -// controllerCore.controller.send(PDNTrigger, controllerCore.config.getPowerDownTimeout(), powerDownPayloads[bank]); -// }*/ -//} - -//PowerDownManagerTimeoutBankwise::~PowerDownManagerTimeoutBankwise() -//{ -// // TODO Auto-generated destructor stub -//} - -//void PowerDownManagerTimeoutBankwise::sleep(Bank bank, sc_time time) -//{ -// bool timeoutTest; -// if (!isAwakeForRefresh(bank)) { -// sc_time lastReadScheduled; -// sc_time lastWriteScheduled; -// if (Configuration::getInstance().OpenPagePolicy) { -// lastReadScheduled = controllerCore.state->getLastCommand(Command::RD, -// bank).getEnd(); -// lastWriteScheduled = controllerCore.state->getLastCommand(Command::WR, -// bank).getEnd(); -// } else { -// lastReadScheduled = controllerCore.state->getLastCommand(Command::RDA, -// bank).getEnd(); -// lastWriteScheduled = controllerCore.state->getLastCommand(Command::WRA, -// bank).getEnd(); -// } -// sc_time lastScheduledCommand = max(lastReadScheduled, lastWriteScheduled); -// timeoutTest = (time - lastScheduledCommand) >= -// Configuration::getInstance().getPowerDownTimeout(); -// } else { -// timeoutTest = true; -// } - -// if ( canSleep(bank) && !isInPowerDown(bank) && timeoutTest) { -// PowerDownState newState; -// if (Configuration::getInstance().PowerDownMode == EPowerDownMode::TimeoutPDN) { -// newState = controllerCore.state->rowBufferStates->rowBufferIsOpen( -// bank) ? PowerDownState::PDNActive : PowerDownState::PDNPrecharge; -// } else { // PowerDownMode == TimeoutSREF -// if (controllerCore.state->rowBufferStates->rowBufferIsOpen(bank)) { -// ScheduledCommand precharge(Command::PRE, time, -// Configuration::getInstance().memSpec->getExecutionTime(Command::PRE, powerDownPayloads[bank]), -// DramExtension::getExtension(powerDownPayloads[bank])); - -// controllerCore.getCommandChecker(Command::PRE).delayToSatisfyConstraints( -// precharge); - -// if (controllerCore.refreshManager->hasCollision(precharge)) { -// return; -// } else { -// controllerCore.state->change(precharge); -// controllerCore.controller.send(precharge, powerDownPayloads[bank]); -// } - -// } - -// newState = PowerDownState::PDNSelfRefresh; -// } - - -// Command cmd = IPowerDownManager::getSleepCommand(newState); -// ScheduledCommand pdn(cmd, time, -// Configuration::getInstance().memSpec->getMinExecutionTimeForPowerDownCmd(cmd), -// DramExtension::getExtension(powerDownPayloads[bank])); - -// controllerCore.getCommandChecker(cmd).delayToSatisfyConstraints(pdn); - -// if (controllerCore.refreshManager->hasCollision(pdn)) { -// return; -// } else { -// setPowerDownState(newState, bank); -// sendPowerDownPayload(pdn); -// } -// } -//} - -//void PowerDownManagerTimeoutBankwise::triggerSleep(Bank bank, sc_time time) -//{ -// if (canSleep(bank) && !isInPowerDown(bank)) { -// controllerCore.controller.send(PDNTrigger, -// time + controllerCore.config.getPowerDownTimeout(), powerDownPayloads[bank]); -// } -//} diff --git a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h b/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h deleted file mode 100644 index 440a482d..00000000 --- a/DRAMSys/library/src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h +++ /dev/null @@ -1,63 +0,0 @@ -///* -// * Copyright (c) 2015, University of Kaiserslautern -// * All rights reserved. -// * -// * Redistribution and use in source and binary forms, with or without -// * modification, are permitted provided that the following conditions are -// * met: -// * -// * 1. Redistributions of source code must retain the above copyright notice, -// * this list of conditions and the following disclaimer. -// * -// * 2. Redistributions in binary form must reproduce the above copyright -// * notice, this list of conditions and the following disclaimer in the -// * documentation and/or other materials provided with the distribution. -// * -// * 3. Neither the name of the copyright holder nor the names of its -// * contributors may be used to endorse or promote products derived from -// * this software without specific prior written permission. -// * -// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -// * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// * -// * Authors: -// * Janik Schlemminger -// * Robert Gernhardt -// * Matthias Jung -// * Felipe S. Prado -// */ - -//#ifndef POWERDOWNMANAGERTIMEOUTBANKWISE_H -//#define POWERDOWNMANAGERTIMEOUTBANKWISE_H - -//#include "PowerDownManager.h" -//#include -//#include "../../../common/dramExtensions.h" -//#include "../scheduling/ScheduledCommand.h" -//#include - -//class ControllerCore; - -//class PowerDownManagerTimeoutBankwise: public PowerDownManagerBankwise -//{ -//public: -// PowerDownManagerTimeoutBankwise(sc_module_name /*name*/, -// ControllerCore &controllerCore); -// virtual ~PowerDownManagerTimeoutBankwise(); - -// virtual void triggerSleep(Bank bank, sc_time time); -// virtual void sleep(Bank bank, sc_time time); -//}; - - - -//#endif // POWERDOWNMANAGERTIMEOUTBANKWISE_H diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp similarity index 91% rename from DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp rename to DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp index c81efa30..cf3cc839 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManager.cpp +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp @@ -32,16 +32,16 @@ * Author: Lukas Steiner */ -#include "PowerDownManager.h" +#include "PowerDownManagerStaggered.h" #include "../../common/utils.h" -PowerDownManager::PowerDownManager(Rank rank, CheckerIF *checker) +PowerDownManagerStaggered::PowerDownManagerStaggered(Rank rank, CheckerIF *checker) : rank(rank), checker(checker) { setUpDummy(powerDownPayload, rank); } -void PowerDownManager::triggerEntry(TriggerSource source) +void PowerDownManagerStaggered::triggerEntry(TriggerSource source) { if (source == TriggerSource::Controller) controllerIdle = true; @@ -51,7 +51,7 @@ void PowerDownManager::triggerEntry(TriggerSource source) triggered = true; } -void PowerDownManager::triggerExit(TriggerSource source) +void PowerDownManagerStaggered::triggerExit(TriggerSource source) { if (source == TriggerSource::Controller) { @@ -77,7 +77,7 @@ void PowerDownManager::triggerExit(TriggerSource source) } } -std::pair PowerDownManager::getNextCommand() +std::pair PowerDownManagerStaggered::getNextCommand() { if (sc_time_stamp() == timeToSchedule) return std::pair(nextCommand, &powerDownPayload); @@ -85,7 +85,7 @@ std::pair PowerDownManager::getNextCommand() return std::pair(Command::NOP, nullptr); } -sc_time PowerDownManager::start() +sc_time PowerDownManagerStaggered::start() { timeToSchedule = sc_max_time(); sc_time delay = sc_max_time() - sc_time_stamp(); @@ -117,7 +117,7 @@ sc_time PowerDownManager::start() return delay; } -void PowerDownManager::updateState(Command command) +void PowerDownManagerStaggered::updateState(Command command) { if (command == Command::ACT) activatedBanks++; diff --git a/DRAMSys/library/src/controller/powerdown/PowerDownManager.h b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h similarity index 91% rename from DRAMSys/library/src/controller/powerdown/PowerDownManager.h rename to DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h index 1394e6ea..350e38b5 100644 --- a/DRAMSys/library/src/controller/powerdown/PowerDownManager.h +++ b/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h @@ -32,8 +32,8 @@ * Author: Lukas Steiner */ -#ifndef POWERDOWNMANAGER_H -#define POWERDOWNMANAGER_H +#ifndef POWERDOWNMANAGERSTAGGERED_H +#define POWERDOWNMANAGERSTAGGERED_H #include "PowerDownManagerIF.h" #include "../BankMachine.h" @@ -41,10 +41,10 @@ using namespace tlm; -class PowerDownManager final : public PowerDownManagerIF +class PowerDownManagerStaggered final : public PowerDownManagerIF { public: - PowerDownManager(Rank, CheckerIF *); + PowerDownManagerStaggered(Rank, CheckerIF *); virtual void triggerEntry(TriggerSource) override; virtual void triggerExit(TriggerSource) override; @@ -68,4 +68,4 @@ private: unsigned activatedBanks = 0; }; -#endif // POWERDOWNMANAGER_H +#endif // POWERDOWNMANAGERSTAGGERED_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 5c24c0a3..b718b243 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -38,7 +38,7 @@ #include "RefreshManagerIF.h" #include "../../configuration/memspec/MemSpec.h" #include "../BankMachine.h" -#include "../powerdown/PowerDownManager.h" +#include "../powerdown/PowerDownManagerIF.h" #include "../checker/CheckerIF.h" using namespace tlm; From 79976485212d30c70c52db309f5043a492919a92 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 21 Nov 2019 23:29:55 +0100 Subject: [PATCH 141/183] Fixed position of power-down entry trigger. --- DRAMSys/library/src/controller/Controller.cpp | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index b097d268..56a1754c 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -353,6 +353,12 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, // TODO: check this part (order of responses) responseQueue.push({(sc_time_stamp() + delay), &trans}); dataResponseEventQueue.notify(delay); + + Rank rank = DramExtension::getRank(trans); + ranksNumberOfPayloads[rank.ID()]--; + if (ranksNumberOfPayloads[rank.ID()] == 0) + powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); + } return TLM_ACCEPTED; } @@ -368,21 +374,14 @@ void Controller::releasePayload() uint64_t id __attribute__((unused)) = DramExtension::getPayloadID(payloadToRelease); PRINTDEBUGMESSAGE(name(), "Payload " + std::to_string(id) + " left system."); - Rank rank = DramExtension::getRank(payloadToRelease); - payloadToRelease->release(); payloadToRelease = nullptr; timeToRelease = sc_max_time(); numberOfTransactionsServed++; totalNumberOfPayloads--; - ranksNumberOfPayloads[rank.ID()]--; - if (totalNumberOfPayloads == 0) startBandwidthIdleCollector(); - - if (ranksNumberOfPayloads[rank.ID()] == 0) - powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); } void Controller::acquirePayload() @@ -394,11 +393,10 @@ void Controller::acquirePayload() if (totalNumberOfPayloads == 0) endBandwithIdleCollector(); + totalNumberOfPayloads++; if(ranksNumberOfPayloads[rank.ID()] == 0) powerDownManagers[rank.ID()]->triggerExit(TriggerSource::Controller); - - totalNumberOfPayloads++; ranksNumberOfPayloads[rank.ID()]++; scheduler->storeRequest(payloadToAcquire); From fa301d2bb4f7933c2f8e6f430e2422a514c52517 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 22 Nov 2019 01:01:08 +0100 Subject: [PATCH 142/183] Staggered power-down working, adapt per-bank refresh. --- DRAMSys/library/src/controller/Controller.cpp | 7 ++ .../src/controller/refresh/RefreshManager.cpp | 100 +++++++----------- .../src/controller/refresh/RefreshManager.h | 8 +- .../refresh/RefreshManagerBankwise.h | 3 + .../controller/refresh/RefreshManagerDummy.h | 3 + .../src/controller/refresh/RefreshManagerIF.h | 3 + 6 files changed, 63 insertions(+), 61 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 56a1754c..f0af873c 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -170,6 +170,7 @@ Controller::Controller(sc_module_name name) : { for (unsigned rankID = 0; rankID < memSpec->NumberOfRanks; rankID++) { + // TODO: remove bankMachines in constructor RefreshManagerIF *manager = new RefreshManagerBankwise (bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker); refreshManagers.push_back(manager); @@ -357,7 +358,10 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, Rank rank = DramExtension::getRank(trans); ranksNumberOfPayloads[rank.ID()]--; if (ranksNumberOfPayloads[rank.ID()] == 0) + { + refreshManagers[rank.ID()]->messageIdle(); powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); + } } return TLM_ACCEPTED; @@ -396,7 +400,10 @@ void Controller::acquirePayload() totalNumberOfPayloads++; if(ranksNumberOfPayloads[rank.ID()] == 0) + { + refreshManagers[rank.ID()]->messageActive(); powerDownManagers[rank.ID()]->triggerExit(TriggerSource::Controller); + } ranksNumberOfPayloads[rank.ID()]++; scheduler->storeRequest(payloadToAcquire); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 773fae5a..ccc836d4 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -52,6 +52,16 @@ RefreshManager::RefreshManager(std::vector &bankMachines, maxPulledin = -config.ControllerCoreRefMaxPulledIn; } +void RefreshManager::messageActive() +{ + controllerIdle = false; +} + +void RefreshManager::messageIdle() +{ + controllerIdle = true; +} + std::pair RefreshManager::getNextCommand() { if (sc_time_stamp() == timeToSchedule && !blocked) @@ -80,65 +90,38 @@ sc_time RefreshManager::start() if (state == RmState::Regular) { bool forcedRefresh = (flexibilityCounter == maxPostponed); - if (!forcedRefresh) + if (!forcedRefresh && !controllerIdle) { - for (auto it : bankMachines) - { - if (!it->isIdle()) - { - flexibilityCounter++; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); - return timeForNextTrigger - sc_time_stamp(); - } - } + flexibilityCounter++; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + return timeForNextTrigger - sc_time_stamp(); } - else // regular refresh that cannot be postponed -> force precharge + else { - for (auto it : bankMachines) - it->block(); - } - - for (auto it : bankMachines) - { - if (it->getState() == BmState::Activated) // at least one bank is active -> do PREA - { + if (activatedBanks > 0) nextCommand = Command::PREA; - delay = checker->delayToSatisfyConstraints(Command::PREA, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; - return delay; - } + else + nextCommand = Command::REFA; + delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + return delay; } - - if (forcedRefresh) // if refresh is forced all banks will remain in precharged state - state = RmState::Precharged; - - nextCommand = Command::REFA; - delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; - return delay; } - else if (state == RmState::Pulledin) + else // if (state == RmState::Pulledin) { - for (auto it : bankMachines) + if (!controllerIdle) { - if (!it->isIdle()) // at least one bank has a payload -> abort pulling in - { - state = RmState::Regular; - timeForNextTrigger += memSpec->getRefreshIntervalAB(); - return timeForNextTrigger - sc_time_stamp(); - } + state = RmState::Regular; + timeForNextTrigger += memSpec->getRefreshIntervalAB(); + return timeForNextTrigger - sc_time_stamp(); + } + else + { + // nextCommand stays Command::REFA + delay = checker->delayToSatisfyConstraints(nextCommand, rank, BankGroup(0), Bank(0)); + timeToSchedule = sc_time_stamp() + delay; + return delay; } - - delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; - return delay; - } - else // if (state == RmState::Precharged) - { - nextCommand = Command::REFA; - delay = checker->delayToSatisfyConstraints(Command::REFA, rank, BankGroup(0), Bank(0)); - timeToSchedule = sc_time_stamp() + delay; - return delay; } } else @@ -147,8 +130,13 @@ sc_time RefreshManager::start() void RefreshManager::updateState(Command command, tlm_generic_payload *) { - // TODO: first ask if RAS command, otherwise ignore it - if (command == Command::REFA) + if (command == Command::ACT) + activatedBanks++; + else if (command == Command::PRE) + activatedBanks--; + else if (command == Command::PREA) + activatedBanks = 0; + else if (command == Command::REFA) { if (blocked) { @@ -172,14 +160,6 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) } } } - else if (command == Command::PREA) - { - // if PREA was successful we will do the refresh in any case - for (auto it : bankMachines) - it->block(); - // TODO: remove for and insert blocking directly into BM - state = RmState::Precharged; - } else if (command == Command::PDEA || command == Command::PDEP) blocked = true; else if (command == Command::SREFEN) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index b718b243..44f85fe0 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -52,8 +52,11 @@ public: virtual sc_time start() override; virtual void updateState(Command, tlm_generic_payload *) override; + virtual void messageActive() override; + virtual void messageIdle() override; + private: - enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; + enum class RmState {Regular, Pulledin} state = RmState::Regular; const MemSpec *memSpec; std::vector &bankMachines; PowerDownManagerIF *powerDownManager; @@ -64,6 +67,9 @@ private: CheckerIF *checker; Command nextCommand; + bool controllerIdle = true; + unsigned activatedBanks = 0; + int flexibilityCounter = 0; int maxPostponed = 0; int maxPulledin = 0; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 63f8f210..cdf457c1 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -54,6 +54,9 @@ public: virtual sc_time start() override; virtual void updateState(Command, tlm_generic_payload *) override; + virtual void messageActive() override {} + virtual void messageIdle() override {} + private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; const MemSpec *memSpec; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index 3a62916a..a59a5112 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -49,6 +49,9 @@ public: virtual std::pair getNextCommand() override; virtual sc_time start() override; virtual void updateState(Command, tlm_generic_payload *) override {} + + virtual void messageActive() override {} + virtual void messageIdle() override {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index d1e589ca..fd428a37 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -50,6 +50,9 @@ public: virtual std::pair getNextCommand() = 0; virtual sc_time start() = 0; virtual void updateState(Command, tlm_generic_payload *) = 0; + + virtual void messageIdle() = 0; + virtual void messageActive() = 0; }; #endif // REFRESHMANAGERIF_H From 7380edfac29c23718f600568f46bd550b56e53bf Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 25 Nov 2019 00:18:51 +0100 Subject: [PATCH 143/183] Small code refactoring. --- DRAMSys/library/src/controller/Controller.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index f0af873c..240c0d5f 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -284,18 +284,21 @@ void Controller::controllerMethod() if (commandPair.second != nullptr) // can happen with FIFO strict { Rank rank = DramExtension::getRank(commandPair.second); + BankGroup bankgroup = DramExtension::getBankGroup(commandPair.second); + Bank bank = DramExtension::getBank(commandPair.second); + if (isRankCommand(commandPair.first)) { for (auto it : bankMachinesOnRank[rank.ID()]) it->updateState(commandPair.first); } else - { - Bank bank = DramExtension::getBank(commandPair.second); bankMachines[bank.ID()]->updateState(commandPair.first); - } + refreshManagers[rank.ID()]->updateState(commandPair.first, commandPair.second); powerDownManagers[rank.ID()]->updateState(commandPair.first); + checker->insert(commandPair.first, rank, bankgroup, bank); + sendToDram(commandPair.first, commandPair.second); } else @@ -422,9 +425,6 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) void Controller::sendToDram(Command command, tlm_generic_payload *payload) { - DramExtension extension = DramExtension::getExtension(payload); - checker->insert(command, extension.getRank(), extension.getBankGroup(), extension.getBank()); - sc_time delay = SC_ZERO_TIME; tlm_phase phase = phaseOfCommand[command]; From ccfe1f45af9d3ea0b45689a26f255b084764d331 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 25 Nov 2019 23:44:54 +0100 Subject: [PATCH 144/183] Small bugfix in LPDDR4 checker, some method renaming. --- DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp | 2 +- DRAMSys/library/src/controller/refresh/RefreshManager.cpp | 4 ++-- DRAMSys/library/src/controller/refresh/RefreshManager.h | 4 ++-- .../library/src/controller/refresh/RefreshManagerBankwise.h | 4 ++-- DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h | 4 ++-- DRAMSys/library/src/controller/refresh/RefreshManagerIF.h | 4 ++-- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 661a3129..ea2deb12 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -175,7 +175,7 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + 2 * memSpec->clk); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk); lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index ccc836d4..3035418e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -52,12 +52,12 @@ RefreshManager::RefreshManager(std::vector &bankMachines, maxPulledin = -config.ControllerCoreRefMaxPulledIn; } -void RefreshManager::messageActive() +void RefreshManager::notifyActive() { controllerIdle = false; } -void RefreshManager::messageIdle() +void RefreshManager::notifyIdle() { controllerIdle = true; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index 44f85fe0..aa7acd03 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -52,8 +52,8 @@ public: virtual sc_time start() override; virtual void updateState(Command, tlm_generic_payload *) override; - virtual void messageActive() override; - virtual void messageIdle() override; + virtual void notifyActive() override; + virtual void notifyIdle() override; private: enum class RmState {Regular, Pulledin} state = RmState::Regular; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index cdf457c1..4054c0e2 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -54,8 +54,8 @@ public: virtual sc_time start() override; virtual void updateState(Command, tlm_generic_payload *) override; - virtual void messageActive() override {} - virtual void messageIdle() override {} + virtual void notifyActive() override {} + virtual void notifyIdle() override {} private: enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h index a59a5112..e9c2cabe 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h @@ -50,8 +50,8 @@ public: virtual sc_time start() override; virtual void updateState(Command, tlm_generic_payload *) override {} - virtual void messageActive() override {} - virtual void messageIdle() override {} + virtual void notifyActive() override {} + virtual void notifyIdle() override {} }; #endif // REFRESHMANAGERDUMMY_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index fd428a37..cedf94c9 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -51,8 +51,8 @@ public: virtual sc_time start() = 0; virtual void updateState(Command, tlm_generic_payload *) = 0; - virtual void messageIdle() = 0; - virtual void messageActive() = 0; + virtual void notifyIdle() = 0; + virtual void notifyActive() = 0; }; #endif // REFRESHMANAGERIF_H From 5111973983dd7888427858d7d8fc23c3c64df600 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Sat, 30 Nov 2019 00:13:08 +0100 Subject: [PATCH 145/183] Small bugfixes in controller and HBM2 checker. --- DRAMSys/library/src/controller/Controller.cpp | 4 ++-- DRAMSys/library/src/controller/checker/CheckerHBM2.cpp | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 240c0d5f..1b086ce6 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -362,7 +362,7 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, ranksNumberOfPayloads[rank.ID()]--; if (ranksNumberOfPayloads[rank.ID()] == 0) { - refreshManagers[rank.ID()]->messageIdle(); + refreshManagers[rank.ID()]->notifyIdle(); powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); } @@ -404,7 +404,7 @@ void Controller::acquirePayload() if(ranksNumberOfPayloads[rank.ID()] == 0) { - refreshManagers[rank.ID()]->messageActive(); + refreshManagers[rank.ID()]->notifyActive(); powerDownManagers[rank.ID()]->triggerExit(TriggerSource::Controller); } ranksNumberOfPayloads[rank.ID()]++; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index d198e241..d1ecaeb0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -167,13 +167,11 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + burstClocks + memSpec->tRTW); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != SC_ZERO_TIME) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart - + memSpec->tRL + burstClocks + memSpec->tRTW); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW); lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != SC_ZERO_TIME) From 10f577c38f49f45a8852dfc0644cfda6788e12fb Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Wed, 11 Dec 2019 11:11:21 +0100 Subject: [PATCH 146/183] Adapted bankwise refresh manager to new controller functionality. --- .../refresh/RefreshManagerBankwise.cpp | 76 +++++++------------ .../refresh/RefreshManagerBankwise.h | 3 +- 2 files changed, 31 insertions(+), 48 deletions(-) diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 22af8665..53955547 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -49,8 +49,9 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) { setUpDummy(refreshPayloads[bankID], rank, bankMachines[bankID]->getBank()); - remainingBankMachines.push_back(bankMachines[bankID]); + allBankMachines.push_back(bankMachines[bankID]); } + remainingBankMachines = allBankMachines; if (config.ControllerCoreRefEnablePostpone) maxPostponed = config.ControllerCoreRefMaxPostponed * memSpec->BanksPerRank; @@ -73,6 +74,10 @@ sc_time RefreshManagerBankwise::start() if (sc_time_stamp() >= timeForNextTrigger) { + powerDownManager->triggerExit(TriggerSource::RefreshManager); + if (blocked) + return sc_max_time() - sc_time_stamp(); + if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) { timeForNextTrigger += memSpec->getRefreshIntervalPB(); @@ -104,31 +109,19 @@ sc_time RefreshManagerBankwise::start() timeForNextTrigger += memSpec->getRefreshIntervalPB(); return timeForNextTrigger - sc_time_stamp(); } - else if (currentBankMachine->getState() == BmState::Activated) - { - if (forcedRefresh) - currentBankMachine->block(); - nextCommand = Command::PRE; - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); - timeToSchedule = sc_time_stamp() + delay; - return delay; - } else { - if (forcedRefresh) - { - currentBankMachine->block(); - state = RmState::Precharged; - } - nextCommand = Command::REFB; - delay = checker->delayToSatisfyConstraints(Command::REFB, rank, + if (currentBankMachine->getState() == BmState::Activated) + nextCommand = Command::PRE; + else + nextCommand = Command::REFB; + delay = checker->delayToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); timeToSchedule = sc_time_stamp() + delay; return delay; } } - else if (state == RmState::Pulledin) + else // if (state == RmState::Pulledin) { bool allBanksBusy = true; @@ -149,31 +142,18 @@ sc_time RefreshManagerBankwise::start() timeForNextTrigger += memSpec->getRefreshIntervalPB(); return timeForNextTrigger - sc_time_stamp(); } - else if (currentBankMachine->getState() == BmState::Activated) - { - nextCommand = Command::PRE; - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); - timeToSchedule = sc_time_stamp() + delay; - return delay; - } else { - nextCommand = Command::REFB; - delay = checker->delayToSatisfyConstraints(Command::REFB, rank, + if (currentBankMachine->getState() == BmState::Activated) + nextCommand = Command::PRE; + else + nextCommand = Command::REFB; + delay = checker->delayToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); timeToSchedule = sc_time_stamp() + delay; return delay; } } - else // if (state == RmState::Precharged) - { - nextCommand = Command::REFB; - delay = checker->delayToSatisfyConstraints(Command::REFB, rank, - currentBankMachine->getBankGroup(), currentBankMachine->getBank()); - timeToSchedule = sc_time_stamp() + delay; - return delay; - } } else return timeForNextTrigger - sc_time_stamp(); @@ -185,10 +165,7 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p { remainingBankMachines.erase(currentIterator); if (remainingBankMachines.empty()) - { - for (unsigned bankID = 0; bankID < memSpec->BanksPerRank; bankID++) - remainingBankMachines.push_back(bankMachines[bankID]); - } + remainingBankMachines = allBankMachines; if (state == RmState::Pulledin) flexibilityCounter--; @@ -199,18 +176,23 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p { state = RmState::Regular; timeForNextTrigger += memSpec->getRefreshIntervalPB(); + powerDownManager->triggerEntry(TriggerSource::RefreshManager); } } - else if (command == Command::PRE) + else if (command == Command::REFA) { - if (nextCommand == Command::PRE && DramExtension::getBank(payload) == currentBankMachine->getBank()) - { - currentBankMachine->block(); - state = RmState::Precharged; - } + // Refresh command after SREFEX + state = RmState::Regular; // TODO: check if this assignment is necessary + timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalPB(); + blocked = false; } else if (command == Command::PDEA || command == Command::PDEP) blocked = true; + else if (command == Command::SREFEN) + { + blocked = true; + timeForNextTrigger = sc_max_time(); + } else if (command == Command::PDXA || command == Command::PDXP) blocked = false; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 4054c0e2..8963e36d 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -58,7 +58,7 @@ public: virtual void notifyIdle() override {} private: - enum class RmState {Regular, Precharged, Pulledin} state = RmState::Regular; + enum class RmState {Regular, Pulledin} state = RmState::Regular; const MemSpec *memSpec; std::vector &bankMachines; PowerDownManagerIF *powerDownManager; @@ -70,6 +70,7 @@ private: Command nextCommand; std::list remainingBankMachines; + std::list allBankMachines; std::list::iterator currentIterator; BankMachine *currentBankMachine; From 705729dee01534fc304e84745aaf5efc68ada34d Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 17 Dec 2019 23:25:22 +0100 Subject: [PATCH 147/183] Fix of memory leak in controllerMethod. --- DRAMSys/library/src/controller/Controller.cpp | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 1b086ce6..dc0f9840 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -310,13 +310,21 @@ void Controller::controllerMethod() for (auto it : bankMachines) { sc_time delay = it->start(); - if (delay != SC_ZERO_TIME || !readyCmdBlocked) // must be checked to avoid livelock + if (delay != (sc_max_time() - sc_time_stamp()) && (delay != SC_ZERO_TIME || !readyCmdBlocked)) // must be checked to avoid livelock controllerEvent.notify(delay); } for (auto it : refreshManagers) - controllerEvent.notify(it->start()); + { + sc_time delay = it->start(); + if (delay != (sc_max_time() - sc_time_stamp())) + controllerEvent.notify(delay); + } for (auto it : powerDownManagers) - controllerEvent.notify(it->start()); + { + sc_time delay = it->start(); + if (delay != (sc_max_time() - sc_time_stamp())) + controllerEvent.notify(delay); + } } tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, From e39d182f050a0b8591fad7ffa17afb2363c0350b Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 3 Feb 2020 08:54:51 +0100 Subject: [PATCH 148/183] New address mapping for bosch. --- .../resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml diff --git a/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml new file mode 100644 index 00000000..c4ae7d76 --- /dev/null +++ b/DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file From 9f5616c8dd41f6ecaa57879ddd1e114117f1b844 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 3 Feb 2020 10:26:06 +0100 Subject: [PATCH 149/183] Included chrono clock for higher precision. --- DRAMSys/simulator/main.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index ca6e6ead..5d6403f8 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -39,7 +39,7 @@ #include #include #include -#include +#include #include "DRAMSys.h" #include "TraceSetup.h" @@ -53,6 +53,11 @@ string pathOfFile(string file) return file.substr(0, file.find_last_of('/')); } +int main(int argc, char **argv) +{ + return sc_main(argc, argv); +} + int sc_main(int argc, char **argv) { sc_set_time_resolution(1, SC_PS); @@ -105,7 +110,7 @@ int sc_main(int argc, char **argv) } // Store the starting of the simulation in wallclock time: - clock_t simStartTime = clock(); + auto start = std::chrono::high_resolution_clock::now(); // Kickstart the players: for (auto &p : players) { @@ -116,8 +121,9 @@ int sc_main(int argc, char **argv) sc_set_stop_mode(SC_STOP_FINISH_DELTA); sc_start(); - double elapsed_secs = double(clock() - simStartTime) / CLOCKS_PER_SEC; - cout << "Simulation took " + to_string(elapsed_secs) + " seconds" << endl; + auto finish = std::chrono::high_resolution_clock::now(); + std::chrono::duration elapsed = finish - start; + std::cout << "Simulation took " + std::to_string(elapsed.count()) + " seconds." << std::endl; delete dramSys; delete ts; From bb783837ba1a82a5d65a6333f539e8a13edc30e8 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Tue, 4 Feb 2020 15:42:54 +0100 Subject: [PATCH 150/183] Removed nextRow in BankMachine. --- .../library/src/controller/BankMachine.cpp | 22 +++++-------------- DRAMSys/library/src/controller/BankMachine.h | 1 - 2 files changed, 5 insertions(+), 18 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 543fec2c..714abe2d 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -55,7 +55,7 @@ void BankMachine::updateState(Command command) if (command == Command::ACT) { currentState = BmState::Activated; - currentRow = nextRow; + currentRow = DramExtension::getRow(currentPayload); } else if (command == Command::PRE || command == Command::PREA) currentState = BmState::Precharged; @@ -124,16 +124,14 @@ sc_time BankMachineOpen::start() return sc_max_time() - sc_time_stamp(); } sc_time delay; - DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; - nextRow = extension.getRow(); } else if (currentState == BmState::Activated) { - if (extension.getRow() == currentRow) // row hit + if (DramExtension::getRow(currentPayload) == currentRow) // row hit { if (currentPayload->get_command() == TLM_READ_COMMAND) { @@ -152,7 +150,6 @@ sc_time BankMachineOpen::start() { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; - nextRow = extension.getRow(); } } timeToSchedule = sc_time_stamp() + delay; @@ -175,16 +172,14 @@ sc_time BankMachineClosed::start() return sc_max_time() - sc_time_stamp(); } sc_time delay; - DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; - nextRow = extension.getRow(); } else if (currentState == BmState::Activated) { - if (extension.getRow() == currentRow) // row hit + if (DramExtension::getRow(currentPayload) == currentRow) // row hit { if (currentPayload->get_command() == TLM_READ_COMMAND) { @@ -203,7 +198,6 @@ sc_time BankMachineClosed::start() { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; - nextRow = extension.getRow(); } } timeToSchedule = sc_time_stamp() + delay; @@ -226,16 +220,14 @@ sc_time BankMachineOpenAdaptive::start() return sc_max_time() - sc_time_stamp(); } sc_time delay; - DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; - nextRow = extension.getRow(); } else if (currentState == BmState::Activated) { - if (extension.getRow() == currentRow) // row hit + if (DramExtension::getRow(currentPayload) == currentRow) // row hit { if (scheduler->hasRequest(bank) && !scheduler->hasRowHit(bank, currentRow)) { @@ -272,7 +264,6 @@ sc_time BankMachineOpenAdaptive::start() { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; - nextRow = extension.getRow(); } } timeToSchedule = sc_time_stamp() + delay; @@ -295,16 +286,14 @@ sc_time BankMachineClosedAdaptive::start() return sc_max_time() - sc_time_stamp(); } sc_time delay; - DramExtension extension = DramExtension::getExtension(currentPayload); if (currentState == BmState::Precharged) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; - nextRow = extension.getRow(); } else if (currentState == BmState::Activated) { - if (extension.getRow() == currentRow) // row hit + if (DramExtension::getRow(currentPayload) == currentRow) // row hit { if (scheduler->hasRowHit(bank, currentRow)) { @@ -341,7 +330,6 @@ sc_time BankMachineClosedAdaptive::start() { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; - nextRow = extension.getRow(); SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); } } diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index 1e8e8d2c..e7f0e4b1 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -77,7 +77,6 @@ protected: SchedulerIF *scheduler; CheckerIF *checker; Command nextCommand; - Row nextRow; BmState currentState = BmState::Precharged; Row currentRow; sc_time timeToSchedule = sc_max_time(); From 26b2893def0edd9789a970cab3f114bf137b0067 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 6 Feb 2020 17:21:49 +0100 Subject: [PATCH 151/183] Improved placement of refresh commands. --- .../library/src/controller/BankMachine.cpp | 69 +++++++++++-------- DRAMSys/library/src/controller/BankMachine.h | 1 + .../src/controller/refresh/RefreshManager.cpp | 8 ++- 3 files changed, 49 insertions(+), 29 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 714abe2d..383f4554 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -44,7 +44,7 @@ BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank) std::pair BankMachine::getNextCommand() { - if (sc_time_stamp() == timeToSchedule && !blocked) + if (sc_time_stamp() == timeToSchedule) return std::pair(nextCommand, currentPayload); else return std::pair(Command::NOP, nullptr); @@ -67,10 +67,14 @@ void BankMachine::updateState(Command command) currentPayload = nullptr; } else if (command == Command::PDEA || command == Command::PDEP || command == Command::SREFEN) - blocked = true; - else if (command == Command::REFA || command == Command::REFB - || command == Command::PDXA || command == Command::PDXP) + sleeping = true; + else if (command == Command::REFA || command == Command::REFB) + { + sleeping = false; blocked = false; + } + else if (command == Command::PDXA || command == Command::PDXP) + sleeping = false; } void BankMachine::block() @@ -114,17 +118,19 @@ BankMachineOpen::BankMachineOpen(SchedulerIF *scheduler, CheckerIF *checker, Ban sc_time BankMachineOpen::start() { timeToSchedule = sc_max_time(); + sc_time delay = sc_max_time() - sc_time_stamp(); - if (blocked) - return sc_max_time() - sc_time_stamp(); - else if (currentPayload == nullptr) + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return sc_max_time() - sc_time_stamp(); + return delay; } - sc_time delay; - if (currentState == BmState::Precharged) // row miss + + if (sleeping) + return delay; + + if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; @@ -152,6 +158,7 @@ sc_time BankMachineOpen::start() nextCommand = Command::PRE; } } + timeToSchedule = sc_time_stamp() + delay; return delay; } @@ -162,17 +169,19 @@ BankMachineClosed::BankMachineClosed(SchedulerIF *scheduler, CheckerIF *checker, sc_time BankMachineClosed::start() { timeToSchedule = sc_max_time(); + sc_time delay = sc_max_time() - sc_time_stamp(); - if (blocked) - return sc_max_time() - sc_time_stamp(); - else if (currentPayload == nullptr) + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return sc_max_time() - sc_time_stamp(); + return delay; } - sc_time delay; - if (currentState == BmState::Precharged) // row miss + + if (sleeping) + return delay; + + if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; @@ -210,17 +219,19 @@ BankMachineOpenAdaptive::BankMachineOpenAdaptive(SchedulerIF *scheduler, Checker sc_time BankMachineOpenAdaptive::start() { timeToSchedule = sc_max_time(); + sc_time delay = sc_max_time() - sc_time_stamp(); - if (blocked) - return sc_max_time() - sc_time_stamp(); - else if (currentPayload == nullptr) + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return sc_max_time() - sc_time_stamp(); + return delay; } - sc_time delay; - if (currentState == BmState::Precharged) // row miss + + if (sleeping) + return delay; + + if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; @@ -276,17 +287,19 @@ BankMachineClosedAdaptive::BankMachineClosedAdaptive(SchedulerIF *scheduler, Che sc_time BankMachineClosedAdaptive::start() { timeToSchedule = sc_max_time(); + sc_time delay = sc_max_time() - sc_time_stamp(); - if (blocked) - return sc_max_time() - sc_time_stamp(); - else if (currentPayload == nullptr) + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); if (currentPayload == nullptr) - return sc_max_time() - sc_time_stamp(); + return delay; } - sc_time delay; - if (currentState == BmState::Precharged) // row miss + + if (sleeping) + return delay; + + if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); nextCommand = Command::ACT; diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h index e7f0e4b1..49fce270 100644 --- a/DRAMSys/library/src/controller/BankMachine.h +++ b/DRAMSys/library/src/controller/BankMachine.h @@ -84,6 +84,7 @@ protected: BankGroup bankgroup = BankGroup(0); Bank bank; bool blocked = false; + bool sleeping = false; }; class BankMachineOpen final : public BankMachine diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 3035418e..9fbcadaf 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -90,7 +90,7 @@ sc_time RefreshManager::start() if (state == RmState::Regular) { bool forcedRefresh = (flexibilityCounter == maxPostponed); - if (!forcedRefresh && !controllerIdle) + if (!forcedRefresh && !controllerIdle) // no forced refresh & controller is busy -> postpone { flexibilityCounter++; timeForNextTrigger += memSpec->getRefreshIntervalAB(); @@ -98,6 +98,12 @@ sc_time RefreshManager::start() } else { + if (forcedRefresh) + { + for (auto it : bankMachines) + it->block(); + } + if (activatedBanks > 0) nextCommand = Command::PREA; else From 7611163bc317715f09cf4280cb01cad9ea523b18 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Mon, 10 Feb 2020 15:45:23 +0100 Subject: [PATCH 152/183] Re-included blocking mechanism into BM, small bugfix in HBM2 timing checker. --- .../library/src/controller/BankMachine.cpp | 54 ++++++++----------- .../src/controller/checker/CheckerHBM2.cpp | 5 +- .../src/controller/checker/CheckerHBM2.h | 3 +- .../src/controller/refresh/RefreshManager.cpp | 14 ++--- .../src/controller/refresh/RefreshManager.h | 2 +- .../refresh/RefreshManagerBankwise.cpp | 12 ++--- .../refresh/RefreshManagerBankwise.h | 2 +- 7 files changed, 42 insertions(+), 50 deletions(-) diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 383f4554..c0aaa913 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -120,6 +120,9 @@ sc_time BankMachineOpen::start() timeToSchedule = sc_max_time(); sc_time delay = sc_max_time() - sc_time_stamp(); + if (sleeping) + return delay; + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); @@ -127,9 +130,6 @@ sc_time BankMachineOpen::start() return delay; } - if (sleeping) - return delay; - if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); @@ -152,7 +152,7 @@ sc_time BankMachineOpen::start() else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - else // row miss + else if (!blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; @@ -171,6 +171,9 @@ sc_time BankMachineClosed::start() timeToSchedule = sc_max_time(); sc_time delay = sc_max_time() - sc_time_stamp(); + if (sleeping) + return delay; + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); @@ -178,9 +181,6 @@ sc_time BankMachineClosed::start() return delay; } - if (sleeping) - return delay; - if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); @@ -188,26 +188,18 @@ sc_time BankMachineClosed::start() } else if (currentState == BmState::Activated) { - if (DramExtension::getRow(currentPayload) == currentRow) // row hit + if (currentPayload->get_command() == TLM_READ_COMMAND) { - if (currentPayload->get_command() == TLM_READ_COMMAND) - { - delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); - nextCommand = Command::RDA; - } - else if (currentPayload->get_command() == TLM_WRITE_COMMAND) - { - delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); - nextCommand = Command::WRA; - } - else - SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); + delay = checker->delayToSatisfyConstraints(Command::RDA, rank, bankgroup, bank); + nextCommand = Command::RDA; } - else // row miss + else if (currentPayload->get_command() == TLM_WRITE_COMMAND) { - delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); - nextCommand = Command::PRE; + delay = checker->delayToSatisfyConstraints(Command::WRA, rank, bankgroup, bank); + nextCommand = Command::WRA; } + else + SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } timeToSchedule = sc_time_stamp() + delay; return delay; @@ -221,6 +213,9 @@ sc_time BankMachineOpenAdaptive::start() timeToSchedule = sc_max_time(); sc_time delay = sc_max_time() - sc_time_stamp(); + if (sleeping) + return delay; + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); @@ -228,9 +223,6 @@ sc_time BankMachineOpenAdaptive::start() return delay; } - if (sleeping) - return delay; - if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); @@ -271,7 +263,7 @@ sc_time BankMachineOpenAdaptive::start() SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } } - else // row miss + else if (!blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; @@ -289,6 +281,9 @@ sc_time BankMachineClosedAdaptive::start() timeToSchedule = sc_max_time(); sc_time delay = sc_max_time() - sc_time_stamp(); + if (sleeping) + return delay; + if (currentPayload == nullptr) { currentPayload = scheduler->getNextRequest(this); @@ -296,9 +291,6 @@ sc_time BankMachineClosedAdaptive::start() return delay; } - if (sleeping) - return delay; - if (currentState == BmState::Precharged && !blocked) // row miss { delay = checker->delayToSatisfyConstraints(Command::ACT, rank, bankgroup, bank); @@ -339,7 +331,7 @@ sc_time BankMachineClosedAdaptive::start() SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } } - else // row miss TODO: remove this, can never happen + else if (!blocked) // row miss TODO: remove this, can never happen { delay = checker->delayToSatisfyConstraints(Command::PRE, rank, bankgroup, bank); nextCommand = Command::PRE; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index d1ecaeb0..e20b5254 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -50,6 +50,7 @@ CheckerHBM2::CheckerHBM2() lastScheduledByCommand = std::vector(numberOfCommands()); lastActivates = std::vector>(memSpec->NumberOfRanks); + bankwiseRefreshCounter = std::vector(memSpec->NumberOfRanks); burstClocks = (memSpec->BurstLength / 2) * memSpec->clk; } @@ -295,7 +296,7 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()]; if (lastCommandStart != SC_ZERO_TIME) { - if (bankwiseRefreshCounter == 0) + if (bankwiseRefreshCounter[rank.ID()] == 0) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB); else earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD); @@ -339,5 +340,5 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b } if (command == Command::REFB) - bankwiseRefreshCounter = (bankwiseRefreshCounter + 1) % memSpec->BanksPerRank; + bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->BanksPerRank; } diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 31769bb9..06c688b2 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -60,10 +60,9 @@ private: // Four activate window std::vector> lastActivates; + std::vector bankwiseRefreshCounter; sc_time burstClocks; - - unsigned bankwiseRefreshCounter = 0; }; #endif // CHECKERHBM2_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp index 9fbcadaf..148c8828 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.cpp @@ -64,7 +64,7 @@ void RefreshManager::notifyIdle() std::pair RefreshManager::getNextCommand() { - if (sc_time_stamp() == timeToSchedule && !blocked) + if (sc_time_stamp() == timeToSchedule) return std::pair(nextCommand, &refreshPayload); else return std::pair(Command::NOP, nullptr); @@ -77,7 +77,7 @@ sc_time RefreshManager::start() if (sc_time_stamp() >= timeForNextTrigger) { powerDownManager->triggerExit(TriggerSource::RefreshManager); - if (blocked) + if (sleeping) return sc_max_time() - sc_time_stamp(); if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalAB()) @@ -144,12 +144,12 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) activatedBanks = 0; else if (command == Command::REFA) { - if (blocked) + if (sleeping) { // Refresh command after SREFEX state = RmState::Regular; // TODO: check if this assignment is necessary timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalAB(); - blocked = false; + sleeping = false; } else { @@ -167,12 +167,12 @@ void RefreshManager::updateState(Command command, tlm_generic_payload *) } } else if (command == Command::PDEA || command == Command::PDEP) - blocked = true; + sleeping = true; else if (command == Command::SREFEN) { - blocked = true; + sleeping = true; timeForNextTrigger = sc_max_time(); } else if (command == Command::PDXA || command == Command::PDXP) - blocked = false; + sleeping = false; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManager.h b/DRAMSys/library/src/controller/refresh/RefreshManager.h index aa7acd03..e6a2942a 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManager.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManager.h @@ -74,7 +74,7 @@ private: int maxPostponed = 0; int maxPulledin = 0; - bool blocked = false; + bool sleeping = false; }; #endif // REFRESHMANAGER_H diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 53955547..0475ec6b 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -61,7 +61,7 @@ RefreshManagerBankwise::RefreshManagerBankwise(std::vector &bankM std::pair RefreshManagerBankwise::getNextCommand() { - if (sc_time_stamp() == timeToSchedule && !blocked) + if (sc_time_stamp() == timeToSchedule) return std::pair (nextCommand, &refreshPayloads[currentBankMachine->getBank().ID() % memSpec->BanksPerRank]); else @@ -75,7 +75,7 @@ sc_time RefreshManagerBankwise::start() if (sc_time_stamp() >= timeForNextTrigger) { powerDownManager->triggerExit(TriggerSource::RefreshManager); - if (blocked) + if (sleeping) return sc_max_time() - sc_time_stamp(); if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalPB()) @@ -184,15 +184,15 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p // Refresh command after SREFEX state = RmState::Regular; // TODO: check if this assignment is necessary timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalPB(); - blocked = false; + sleeping = false; } else if (command == Command::PDEA || command == Command::PDEP) - blocked = true; + sleeping = true; else if (command == Command::SREFEN) { - blocked = true; + sleeping = true; timeForNextTrigger = sc_max_time(); } else if (command == Command::PDXA || command == Command::PDXP) - blocked = false; + sleeping = false; } diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 8963e36d..e92cc08f 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -78,7 +78,7 @@ private: int maxPostponed = 0; int maxPulledin = 0; - bool blocked = false; + bool sleeping = false; }; #endif // REFRESHMANAGERBANKWISE_H From fbc0a3d7e664c761699d0a28f3d6aa1baf727d70 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 13 Feb 2020 16:47:51 +0100 Subject: [PATCH 153/183] Moved buffer mechanism to scheduler. --- .../src/controller/scheduler/SchedulerFifo.cpp | 12 ++++++++++-- .../src/controller/scheduler/SchedulerFifo.h | 10 ++++++---- .../controller/scheduler/SchedulerFrFcfs.cpp | 18 +++++++++++++----- .../src/controller/scheduler/SchedulerFrFcfs.h | 14 ++++++++------ .../src/controller/scheduler/SchedulerIF.h | 1 + 5 files changed, 38 insertions(+), 17 deletions(-) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp index 9f0eb5ae..ce31bc50 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp @@ -38,12 +38,20 @@ SchedulerFifo::SchedulerFifo() { buffer = std::vector> (Configuration::getInstance().memSpec->NumberOfBanks); + maxNumberOfRequests = Configuration::getInstance().MaxNrOfTransactions; +} + +bool SchedulerFifo::hasBufferSpace(tlm_generic_payload *payload) +{ + if (buffer[DramExtension::getBank(payload).ID()].size() < maxNumberOfRequests) + return true; + else + return false; } void SchedulerFifo::storeRequest(tlm_generic_payload *payload) { - unsigned bankID = DramExtension::getBank(payload).ID(); - buffer[bankID].push(payload); + buffer[DramExtension::getBank(payload).ID()].push(payload); } tlm_generic_payload *SchedulerFifo::getNextRequest(BankMachine *bankMachine) diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h index eac15127..f2d9f8be 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h @@ -48,12 +48,14 @@ class SchedulerFifo : public SchedulerIF { public: SchedulerFifo(); - void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(BankMachine *); - bool hasRowHit(Bank, Row); - bool hasRequest(Bank); + virtual bool hasBufferSpace(tlm_generic_payload *) override; + virtual void storeRequest(tlm_generic_payload *) override; + virtual tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual bool hasRowHit(Bank, Row) override; + virtual bool hasRequest(Bank) override; private: std::vector> buffer; + unsigned maxNumberOfRequests; }; #endif // SCHEDULERFIFO_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp index c9f2df18..eb784508 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp @@ -38,14 +38,22 @@ SchedulerFrFcfs::SchedulerFrFcfs() { - buffer = std::vector> + buffer = std::vector> (Configuration::getInstance().memSpec->NumberOfBanks); + maxNumberOfRequests = Configuration::getInstance().MaxNrOfTransactions; +} + +bool SchedulerFrFcfs::hasBufferSpace(tlm_generic_payload *payload) +{ + if (buffer[DramExtension::getBank(payload).ID()].size() < maxNumberOfRequests) + return true; + else + return false; } void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload) { - unsigned bankID = DramExtension::getBank(payload).ID(); - buffer[bankID].push_back(payload); + buffer[DramExtension::getBank(payload).ID()].push_back(payload); } tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) @@ -57,7 +65,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) if (currentState == BmState::Precharged) { tlm_generic_payload *result = buffer[bankID].front(); - buffer[bankID].erase(buffer[bankID].begin()); + buffer[bankID].pop_front(); return result; } else if (currentState == BmState::Activated) @@ -75,7 +83,7 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) } // No row hit found tlm_generic_payload *result = buffer[bankID].front(); - buffer[bankID].erase(buffer[bankID].begin()); + buffer[bankID].pop_front(); return result; } else diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h index 9946e39f..5bf4f264 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h @@ -37,7 +37,7 @@ #include #include -#include +#include #include "SchedulerIF.h" #include "../../common/dramExtensions.h" #include "../BankMachine.h" @@ -48,12 +48,14 @@ class SchedulerFrFcfs : public SchedulerIF { public: SchedulerFrFcfs(); - void storeRequest(tlm_generic_payload *); - tlm_generic_payload *getNextRequest(BankMachine *); - bool hasRowHit(Bank, Row); - bool hasRequest(Bank); + virtual bool hasBufferSpace(tlm_generic_payload *) override; + virtual void storeRequest(tlm_generic_payload *) override; + virtual tlm_generic_payload *getNextRequest(BankMachine *) override; + virtual bool hasRowHit(Bank, Row) override; + virtual bool hasRequest(Bank) override; private: - std::vector> buffer; + std::vector> buffer; + unsigned maxNumberOfRequests; }; #endif // SCHEDULERFRFCFS_H diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h index 8568773b..c882a3b0 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h +++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h @@ -49,6 +49,7 @@ class SchedulerIF { public: virtual ~SchedulerIF() {} + virtual bool hasBufferSpace(tlm_generic_payload *) = 0; virtual void storeRequest(tlm_generic_payload *) = 0; virtual tlm_generic_payload *getNextRequest(BankMachine *) = 0; virtual bool hasRowHit(Bank, Row) = 0; From e3c4a923cf98f6adc12afe84a51437741406d6ec Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Thu, 13 Feb 2020 16:51:24 +0100 Subject: [PATCH 154/183] getNextCommand() mechanism is now working rankwise. --- DRAMSys/library/src/controller/Controller.cpp | 63 ++++++++----------- DRAMSys/library/src/controller/Controller.h | 1 - 2 files changed, 26 insertions(+), 38 deletions(-) diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index dc0f9840..d4ded163 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -65,8 +65,7 @@ Controller::Controller(sc_module_name name) : Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - maxNumberOfPayloads = config.MaxNrOfTransactions; - ranksNumberOfPayloads = std::vector(memSpec->NumberOfRanks, 0); + ranksNumberOfPayloads = std::vector(memSpec->NumberOfRanks); // instantiate timing checker if (memSpec->MemoryType == "DDR3") @@ -227,7 +226,7 @@ void Controller::controllerMethod() // (3) Accept new request from arbiter and start appropriate BM if necessary if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr) { - if (totalNumberOfPayloads < Configuration::getInstance().MaxNrOfTransactions) + if (scheduler->hasBufferSpace(payloadToAcquire)) { Bank bank = DramExtension::getBank(payloadToAcquire); acquirePayload(); @@ -240,7 +239,7 @@ void Controller::controllerMethod() } // (4) Start refresh and power-down managers to issue requests for the current time - // TODO: check if the order of start() matters + // TODO: check if the order of start() matters, do I always need to start them at this point? No, only if something happened in steps 1-3!!! for (auto it : refreshManagers) it->start(); for (auto it : powerDownManagers) @@ -248,31 +247,28 @@ void Controller::controllerMethod() // (5) Choose one request and send it to DRAM std::pair commandPair; - std::vector> readyCommands; + std::vector> readyCommands; // (5.1) Check for power-down commands (PDEA/PDEP/SREFEN or PDXA/PDXP/SREFEX) - for (auto it : powerDownManagers) + for (unsigned rankID = 0; rankID < Configuration::getInstance().memSpec->NumberOfRanks; rankID++) { - commandPair = it->getNextCommand(); + commandPair = powerDownManagers[rankID]->getNextCommand(); if (commandPair.second != nullptr) readyCommands.push_back(commandPair); - } - if (readyCommands.empty()) - { - // (5.2) Check for refresh commands (PREA/PRE or REFA/REFB) - for (auto it : refreshManagers) + else { - commandPair = it->getNextCommand(); + // (5.2) Check for refresh commands (PREA/PRE or REFA/REFB) + commandPair = refreshManagers[rankID]->getNextCommand(); if (commandPair.second != nullptr) readyCommands.push_back(commandPair); - } - if (readyCommands.empty()) - { - // (5.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) - for (auto it : bankMachines) + else { - commandPair = it->getNextCommand(); - if (commandPair.second != nullptr) - readyCommands.push_back(commandPair); + // (5.3) Check for bank commands (PRE, ACT, RD/RDA or WR/WRA) + for (auto it : bankMachinesOnRank[rankID]) + { + commandPair = it->getNextCommand(); + if (commandPair.second != nullptr) + readyCommands.push_back(commandPair); + } } } } @@ -307,24 +303,18 @@ void Controller::controllerMethod() // (6) Restart bank machines and refresh managers to issue new requests for the future // TODO: check if all calls are necessary + sc_time delayForNextTrigger = sc_max_time(); for (auto it : bankMachines) - { - sc_time delay = it->start(); - if (delay != (sc_max_time() - sc_time_stamp()) && (delay != SC_ZERO_TIME || !readyCmdBlocked)) // must be checked to avoid livelock - controllerEvent.notify(delay); - } + delayForNextTrigger = std::min(delayForNextTrigger, it->start()); + if (payloadToAcquire != nullptr && sc_time_stamp() >= timeToAcquire && scheduler->hasBufferSpace(payloadToAcquire)) + acquirePayload(); for (auto it : refreshManagers) - { - sc_time delay = it->start(); - if (delay != (sc_max_time() - sc_time_stamp())) - controllerEvent.notify(delay); - } + delayForNextTrigger = std::min(delayForNextTrigger, it->start()); for (auto it : powerDownManagers) - { - sc_time delay = it->start(); - if (delay != (sc_max_time() - sc_time_stamp())) - controllerEvent.notify(delay); - } + delayForNextTrigger = std::min(delayForNextTrigger, it->start()); + + if (!((delayForNextTrigger == SC_ZERO_TIME && readyCmdBlocked) || (delayForNextTrigger == (sc_max_time() - sc_time_stamp())))) + controllerEvent.notify(delayForNextTrigger); } tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans, @@ -373,7 +363,6 @@ tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &trans, refreshManagers[rank.ID()]->notifyIdle(); powerDownManagers[rank.ID()]->triggerEntry(TriggerSource::Controller); } - } return TLM_ACCEPTED; } diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index 02a93b92..6200bb69 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -76,7 +76,6 @@ protected: private: unsigned totalNumberOfPayloads = 0; std::vector ranksNumberOfPayloads; - unsigned maxNumberOfPayloads; tlm_generic_payload *payloadToAcquire = nullptr; sc_time timeToAcquire = sc_max_time(); tlm_generic_payload *payloadToRelease = nullptr; From 169627de2e8da1c9e7c95e08b2f8e2a7d442cad5 Mon Sep 17 00:00:00 2001 From: "Lukas Steiner (2)" Date: Fri, 21 Feb 2020 14:55:06 +0100 Subject: [PATCH 155/183] Included address range check. Fixed bug with FIFO Strict in controllerMethod(). --- DRAMSys/library/src/common/XmlAddressDecoder.cpp | 5 +++++ DRAMSys/library/src/common/XmlAddressDecoder.h | 1 + DRAMSys/library/src/controller/Controller.cpp | 8 ++++++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.cpp b/DRAMSys/library/src/common/XmlAddressDecoder.cpp index 06e0c715..0dcc2d5d 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.cpp +++ b/DRAMSys/library/src/common/XmlAddressDecoder.cpp @@ -119,6 +119,8 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) bankgroupsPerRank = amount.bankgroup; amount.bankgroup = bankgroupsPerRank * amount.rank; + maximumAddress = amount.bytes * amount.column * amount.row * banksPerGroup * bankgroupsPerRank * amount.rank * amount.channel - 1; + Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; @@ -132,6 +134,9 @@ void XmlAddressDecoder::setConfiguration(std::string addressConfigURI) DecodedAddress XmlAddressDecoder::decodeAddress(uint64_t addr) { + if (addr > maximumAddress) + SC_REPORT_WARNING("XmlAddressDecoder", ("Address " + std::to_string(addr) + " out of range (maximum address is " + std::to_string(maximumAddress) + ")").c_str()); + DecodedAddress result; result.channel = (addr & masks.channel) >> shifts.channel; result.rank = (addr & masks.rank) >> shifts.rank; diff --git a/DRAMSys/library/src/common/XmlAddressDecoder.h b/DRAMSys/library/src/common/XmlAddressDecoder.h index 85a9c0ca..21befb9f 100644 --- a/DRAMSys/library/src/common/XmlAddressDecoder.h +++ b/DRAMSys/library/src/common/XmlAddressDecoder.h @@ -78,6 +78,7 @@ private: unsigned bankgroupsPerRank; tinyxml2::XMLElement *addressmapping; + uint64_t maximumAddress; public: XmlAddressDecoder(); diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index d4ded163..54811455 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -305,7 +305,11 @@ void Controller::controllerMethod() // TODO: check if all calls are necessary sc_time delayForNextTrigger = sc_max_time(); for (auto it : bankMachines) - delayForNextTrigger = std::min(delayForNextTrigger, it->start()); + { + sc_time localDelay = it->start(); + if (!(localDelay == SC_ZERO_TIME && readyCmdBlocked)) + delayForNextTrigger = std::min(delayForNextTrigger, localDelay); + } if (payloadToAcquire != nullptr && sc_time_stamp() >= timeToAcquire && scheduler->hasBufferSpace(payloadToAcquire)) acquirePayload(); for (auto it : refreshManagers) @@ -313,7 +317,7 @@ void Controller::controllerMethod() for (auto it : powerDownManagers) delayForNextTrigger = std::min(delayForNextTrigger, it->start()); - if (!((delayForNextTrigger == SC_ZERO_TIME && readyCmdBlocked) || (delayForNextTrigger == (sc_max_time() - sc_time_stamp())))) + if (!(delayForNextTrigger == (sc_max_time() - sc_time_stamp()))) controllerEvent.notify(delayForNextTrigger); } From a56b39d3442eedf241b73b2440c9f09fc978e9a0 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:34:04 +0100 Subject: [PATCH 156/183] New Script for wget SystemC and build with CMAKE --- utils/getsysc_cmake.sh | 63 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 utils/getsysc_cmake.sh diff --git a/utils/getsysc_cmake.sh b/utils/getsysc_cmake.sh new file mode 100644 index 00000000..df9bc1ef --- /dev/null +++ b/utils/getsysc_cmake.sh @@ -0,0 +1,63 @@ +#!/usr/bin/env bash + +# Copyright (c) 2020, University of Kaiserslautern +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Author: Éder F. Zulian +# Matthias Jung + +sysc=systemc-2.3.3 +sysctarball=$sysc.tar.gz +builddir=build + +function getnumprocs { + local __retvar=$1; + local __nprocs=$(cat /proc/cpuinfo | grep processor | wc -l) + if [[ "$__retvar" ]]; then + eval $__retvar="'$__nprocs'" + else + echo "$__nprocs" + fi +} + +# Get the code +wget -nc http://accellera.org/images/downloads/standards/systemc/$sysctarball +tar -xaf $sysctarball +rm $sysctarball +cd $sysc + +# Build the library +mkdir $builddir +cd $builddir +cmake -DCMAKE_INSTALL_PREFIX=/opt/$sysc/ -DCMAKE_CXX_STANDARD=11 .. +getnumprocs np +nj=`expr $np - 1` +make -j$nj +sudo make install From 4f4b88936fa1592b88ba9a4bbe154d6a109c7c45 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:38:12 +0100 Subject: [PATCH 157/183] Trance Analyser pro-file simplified --- DRAMSys/traceAnalyzer/traceAnalyzer.pro | 62 ++----------------------- 1 file changed, 4 insertions(+), 58 deletions(-) diff --git a/DRAMSys/traceAnalyzer/traceAnalyzer.pro b/DRAMSys/traceAnalyzer/traceAnalyzer.pro index 9db5fe69..42817173 100644 --- a/DRAMSys/traceAnalyzer/traceAnalyzer.pro +++ b/DRAMSys/traceAnalyzer/traceAnalyzer.pro @@ -1,47 +1,12 @@ -#------------------------------------------------- -# -# Project created by QtCreator 2013-11-26T20:21:15 -# -#------------------------------------------------- - QT += core gui QT += sql CONFIG += no_keywords +CONFIG += python +CONFIG += link_pkgconfig +PKGCONFIG += python3 -CONFIG += python - - -unix:!macx { - # Python library and header files - python_home = $$(PYTHON_HOME) - isEmpty(python_home) { - python_home = /opt/python/lib - } - message(Python home is $${python_home}) - - python_headers = $$(PYTHON_HEADERS) - isEmpty(python_headers) { - python_headers = /opt/python/include/python3.5m - } - message(Getting python headers from $${python_headers}) - - QMAKE_CXXFLAGS += -std=c++11 - CONFIG += qwt - QMAKE_CXXFLAGS += -Xlinker -export-dynamic - QMAKE_RPATHDIR += $${libqwt_home} - message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR}) - - CONFIG(python){ - libpython_vers = $$(LIBPYTHON_VERSION) - isEmpty(libpython_vers) { - libpython_vers = 3.5m - } - message(Lib Python version is $${libpython_vers}) - LIBS += -L$${python_home} -lpython$${libpython_vers} - INCLUDEPATH += $${python_headers} - } -} +CONFIG+=qwt macx: { message(Building on a MAC) @@ -60,25 +25,6 @@ macx: { CONFIG-=app_bundle } -# QWT library and header files -libqwt_home = $$(LIBQWT_HOME) -isEmpty(libqwt_home) { - libqwt_home = /opt/qwt/lib -} -message(LIBQWT path is $${libqwt_home}) - - -libqwt_headers = $$(LIBQWT_HEADERS) -isEmpty(libqwt_headers) { - libqwt_headers = /opt/qwt/include -} -message(Getting LIBQWT headers from $${libqwt_headers}) - -CONFIG(qwt){ - LIBS += -L$${libqwt_home}/ -lqwt -lutil - INCLUDEPATH += $${libqwt_headers} -} - greaterThan(QT_MAJOR_VERSION, 4): QT += widgets TARGET = traceAnalyzer From 8a7ad0c7b9c66cc8d0258d18be61d99a62badb78 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:40:36 +0100 Subject: [PATCH 158/183] Simulator pro file simplified --- DRAMSys/simulator/simulator.pro | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/DRAMSys/simulator/simulator.pro b/DRAMSys/simulator/simulator.pro index a0b27493..de259186 100644 --- a/DRAMSys/simulator/simulator.pro +++ b/DRAMSys/simulator/simulator.pro @@ -11,13 +11,6 @@ isEmpty(systemc_home) { } message(SystemC home is $${systemc_home}) -systemc_target_arch = $$(SYSTEMC_TARGET_ARCH) -isEmpty(systemc_target_arch) { - systemc_target_arch = linux64 -} - -message(SystemC target architecture is $${systemc_target_arch}) - dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) isEmpty(dramsys_disable_coverage_check) { coverage_check = true @@ -29,16 +22,16 @@ isEmpty(dramsys_disable_coverage_check) { unix:!macx { message(Building on a GNU/Linux) - QMAKE_RPATHDIR += $${systemc_home}/lib-$${systemc_target_arch} - message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR}) + QMAKE_RPATHDIR += $${systemc_home}/lib + message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR}) } DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES unix:!macx { - QMAKE_CXXFLAGS += -std=c++11 -O0 -g - $$eval(coverage_check) { + QMAKE_CXXFLAGS += -std=c++0x -O0 -g + $$eval(coverage_check) { QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0 QMAKE_LFLAGS += -lgcov --coverage } @@ -59,7 +52,7 @@ INCLUDEPATH += $${systemc_home}/include INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src/libdrampower -LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc +LIBS += -L$${systemc_home}/lib -lsystemc LIBS += ../library/libDRAMSys.a LIBS += ../../DRAMSys/library/src/common/third_party/DRAMPower/src/libdrampower.a LIBS += -lsqlite3 From bd11d34abcb15c630aa7005ef8ae791d61da974b Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:41:23 +0100 Subject: [PATCH 159/183] Library pro file simplified --- DRAMSys/library/library.pro | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro index 36c5861b..8043e99e 100644 --- a/DRAMSys/library/library.pro +++ b/DRAMSys/library/library.pro @@ -10,7 +10,7 @@ system(cd ../../DRAMSys/library/src/common/third_party/DRAMPower; make src/libdr systemc_home = $$(SYSTEMC_HOME) isEmpty(systemc_home) { - systemc_home = /opt/systemc + systemc_home = /opt/systemc/ } # Check if PCT's SystemC should be used? @@ -41,12 +41,6 @@ isEmpty(gem5) { message(SystemC home is $${systemc_home}) -systemc_target_arch = $$(SYSTEMC_TARGET_ARCH) -isEmpty(systemc_target_arch) { - systemc_target_arch = linux64 -} -message(SystemC target architecture is $${systemc_target_arch}) - INCLUDEPATH += $${systemc_home}/include INCLUDEPATH += src/common/third_party/DRAMPower/src @@ -66,8 +60,8 @@ isEmpty(dramsys_disable_coverage_check) { } unix:!macx { - QMAKE_CXXFLAGS += -std=c++11 -O0 -g - $$eval(coverage_check) { + QMAKE_CXXFLAGS += -std=c++11 -O0 -g + $$eval(coverage_check) { QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0 QMAKE_LFLAGS += -lgcov --coverage } From 3eb406f0b12eacf040d01fa31e0320a2f2be3af3 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:42:09 +0100 Subject: [PATCH 160/183] Added missing include in Utils.cpp --- DRAMSys/library/src/common/utils.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index af4890f0..3b9cdc1e 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -40,6 +40,7 @@ #include #include #include "dramExtensions.h" +#include using namespace std; using namespace tinyxml2; From 369db7f2897e056bba80e6970c14d78d66fc344d Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:42:57 +0100 Subject: [PATCH 161/183] install_deb.sh updated --- utils/install_deb.sh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/utils/install_deb.sh b/utils/install_deb.sh index 31afe9e7..e08baca9 100755 --- a/utils/install_deb.sh +++ b/utils/install_deb.sh @@ -53,8 +53,8 @@ subversion astyle uncrustify clang-format -python3.5 -python3.5-dev +python3 +python3-dev python3-matplotlib sqlite3 sqlitebrowser @@ -72,6 +72,7 @@ libqt5sql5 libqt5widgets5 libqt5core5a lsb-core +libqwt-qt5-dev gedit sublime-text vim-gtk @@ -81,6 +82,8 @@ gtkwave openssh-server nautilus telnet +dpkg-dev +pkg-config " for d in $deplist; do sudo apt-get -y install $d From 1bc4914d9f561adb8b12fa977155e8878270ce5b Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 19:56:39 +0100 Subject: [PATCH 162/183] Updated DRAMPower to head --- DRAMSys/library/src/common/third_party/DRAMPower | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/common/third_party/DRAMPower b/DRAMSys/library/src/common/third_party/DRAMPower index e65a108c..f9ac6fa0 160000 --- a/DRAMSys/library/src/common/third_party/DRAMPower +++ b/DRAMSys/library/src/common/third_party/DRAMPower @@ -1 +1 @@ -Subproject commit e65a108c385d7964410364cdaedad56f0db96e1b +Subproject commit f9ac6fa0102ad73331b04620935bca6b80416752 From cc9f436e1366d92e9d69e288cf6eb693371ecc68 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 22:05:25 +0100 Subject: [PATCH 163/183] Updated to newest DRAMPower --- DRAMSys/library/src/common/third_party/DRAMPower | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/common/third_party/DRAMPower b/DRAMSys/library/src/common/third_party/DRAMPower index f9ac6fa0..9f9f8db0 160000 --- a/DRAMSys/library/src/common/third_party/DRAMPower +++ b/DRAMSys/library/src/common/third_party/DRAMPower @@ -1 +1 @@ -Subproject commit f9ac6fa0102ad73331b04620935bca6b80416752 +Subproject commit 9f9f8db0bdd0864bc7bb14e7c3d197a9473942c0 From f4a0e9fdede95b580d2f2aa5e3035d865f949e69 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 25 Feb 2020 23:58:47 +0100 Subject: [PATCH 164/183] Added first CMAKE configuration A first CMAKE configuration was added. Right now it was just tested under Debian linux in the WSL context. Further tests on native Windows, Linux and macOS have to be performed. --- DRAMSys/CMakeLists.txt | 23 ++++++ DRAMSys/library/CMakeLists.txt | 102 +++++++++++++++++++++++++++ DRAMSys/traceAnalyzer/CMakeLists.txt | 80 +++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 DRAMSys/CMakeLists.txt create mode 100644 DRAMSys/library/CMakeLists.txt create mode 100644 DRAMSys/traceAnalyzer/CMakeLists.txt diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt new file mode 100644 index 00000000..b796dcb6 --- /dev/null +++ b/DRAMSys/CMakeLists.txt @@ -0,0 +1,23 @@ +cmake_minimum_required(VERSION 3.10) + +# Project Name +project(DRAMSys) + +# Add SystemC Dependency: +find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") + +# Add sqlite3 Dependency: +FIND_LIBRARY(SQLITE3_LIBRARY NAMES sqlite3) + +# Add DRAMSysLibrary: +add_subdirectory(library) + +# Add TraceAnalyzer: +add_subdirectory(traceAnalyzer) + +set (CMAKE_CXX_STANDARD 11) + +add_executable(DRAMSys simulator/main.cpp) +target_include_directories(DRAMSys PUBLIC DRAMSysLibrary library/src/simulation) +target_link_libraries(DRAMSys SystemC::systemc sqlite3 DRAMSysLibrary) + diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt new file mode 100644 index 00000000..ff924707 --- /dev/null +++ b/DRAMSys/library/CMakeLists.txt @@ -0,0 +1,102 @@ +cmake_minimum_required(VERSION 3.10) + +# Project Name +project(DRAMSysLibrary) + +# Add SystemC Dependency: +find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") + +set (CMAKE_CXX_STANDARD 11) + +add_subdirectory(src/common/third_party/DRAMPower) + +include_directories( + src/simulation + src/simulation/dram + src/controller + src/controller/checker + src/controller/cmdmux + src/controller/powerdown + src/controller/refresh + src/controller/scheduler + src/common + src/common/third_party/DRAMPower/src + src/configuration + src/configuration/memspec + src/error + src/error/ECC +) + +add_library(DRAMSysLibrary + src/common/third_party/tinyxml2/tinyxml2.cpp + src/common/TlmRecorder.cpp + src/common/DebugManager.cpp + src/configuration/Configuration.cpp + src/simulation/MemoryManager.cpp + src/simulation/TemperatureController.cpp + src/configuration/ConfigurationLoader.cpp + src/controller/Command.cpp + src/error/errormodel.cpp + src/simulation/TracePlayer.cpp + src/simulation/TraceSetup.cpp + src/simulation/DRAMSys.cpp + src/simulation/Setup.cpp + src/error/ECC/Bit.cpp + src/error/ECC/ECC.cpp + src/error/ECC/Word.cpp + src/error/eccbaseclass.cpp + src/error/ecchamming.cpp + src/common/AddressDecoder.cpp + src/simulation/dram/Dram.cpp + src/simulation/Arbiter.cpp + src/common/CongenAddressDecoder.cpp + src/common/XmlAddressDecoder.cpp + src/common/timingCalculations.cpp + src/common/dramExtensions.cpp + src/common/utils.cpp + src/simulation/dram/DramDDR3.cpp + src/simulation/dram/DramDDR4.cpp + src/simulation/dram/DramRecordable.cpp + src/simulation/dram/DramWideIO.cpp + src/configuration/memspec/MemSpec.cpp + src/controller/BankMachine.cpp + src/controller/Controller.cpp + src/controller/scheduler/SchedulerFifo.cpp + src/controller/scheduler/SchedulerFrFcfs.cpp + src/controller/cmdmux/CmdMuxStrict.cpp + src/controller/cmdmux/CmdMuxOldest.cpp + src/controller/ControllerRecordable.cpp + src/controller/checker/CheckerDDR3.cpp + src/controller/refresh/RefreshManager.cpp + src/controller/refresh/RefreshManagerDummy.cpp + src/controller/refresh/RefreshManagerBankwise.cpp + src/controller/checker/CheckerWideIO.cpp + src/configuration/memspec/MemSpecDDR3.cpp + src/configuration/memspec/MemSpecDDR4.cpp + src/configuration/memspec/MemSpecWideIO.cpp + src/configuration/memspec/MemSpecLPDDR4.cpp + src/controller/checker/CheckerDDR4.cpp + src/simulation/dram/DramLPDDR4.cpp + src/controller/checker/CheckerLPDDR4.cpp + src/configuration/memspec/MemSpecWideIO2.cpp + src/simulation/dram/DramWideIO2.cpp + src/controller/checker/CheckerWideIO2.cpp + src/configuration/memspec/MemSpecHBM2.cpp + src/simulation/dram/DramHBM2.cpp + src/controller/checker/CheckerHBM2.cpp + src/configuration/memspec/MemSpecGDDR5.cpp + src/configuration/memspec/MemSpecGDDR5X.cpp + src/configuration/memspec/MemSpecGDDR6.cpp + src/controller/checker/CheckerGDDR5.cpp + src/controller/checker/CheckerGDDR5X.cpp + src/controller/checker/CheckerGDDR6.cpp + src/simulation/dram/DramGDDR5.cpp + src/simulation/dram/DramGDDR5X.cpp + src/simulation/dram/DramGDDR6.cpp + src/controller/powerdown/PowerDownManagerStaggered.cpp + src/controller/powerdown/PowerDownManagerDummy.cpp +) + +target_include_directories(DRAMSysLibrary PUBLIC src/common/third_party/DRAMPower/src) +target_link_libraries(DRAMSysLibrary DRAMPower SystemC::systemc) + diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt new file mode 100644 index 00000000..f489ad94 --- /dev/null +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -0,0 +1,80 @@ +cmake_minimum_required(VERSION 3.10) + +# Project Name +project(TraceAnalyzer) + +# Add SystemC Dependency: +find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") + +# Add Python Dependency: +find_library(PYTHON3_LIBRARY NAMES Python3) + +# Add sqlite3 Dependency: +find_package(PythonLibs REQUIRED) + +# Add QWT Dependency: +find_library(QWT_LIBRARY NAMES "qwt-qt5" "qwt") +find_path (QWT_INCLUDE_DIRS NAMES "qwt_plot.h" PATHS "/usr/include/qwt-qt5" "/usr/include/qwt") + +message(${QWT_LIBRARY}) + +# Add QT Library +find_package(Qt5 COMPONENTS Core Gui Widgets Sql REQUIRED) +set(CMAKE_AUTOMOC ON) +set(CMAKE_AUTOUIC ON) +set(CMAKE_AUTORCC ON) +set(CMAKE_INCLUDE_CURRENT_DIR ON) + +set (CMAKE_CXX_STANDARD 11) + +include_directories( + ${QWT_INCLUDE_DIRS} + ${PYTHON_INCLUDE_DIRS} + ./ + businessObjects/ + businessObjects/phases/ + data/ + presentation/ + presentation/util/ +) + + +add_executable(TraceAnalyzer + main.cpp + businessObjects/transaction.cpp + businessObjects/timespan.cpp + data/tracedb.cpp + presentation/tracenavigator.cpp + presentation/util/colorgenerator.cpp + presentation/tracedrawing.cpp + presentation/traceplotitem.cpp + gototimedialog.cpp + presentation/traceplot.cpp + tracefiletab.cpp + presentation/pornotracescroller.cpp + traceanalyzer.cpp + presentation/transactiontreewidget.cpp + presentation/commenttreewidget.cpp + presentation/util/clkgrid.cpp + queryeditor.cpp + presentation/selectedtransactiontreewidget.cpp + businessObjects/phases/phasefactory.cpp + presentation/debugmessagetreewidget.cpp + presentation/tracePlotMouseLabel.cpp + evaluationtool.cpp + selectmetrics.cpp + presentation/util/testlight.cpp + presentation/tracetesttreewidget.cpp + businessObjects/pythoncaller.cpp + businessObjects/tracetestresults.cpp + presentation/tracemetrictreewidget.cpp + businessObjects/phases/phase.cpp +) + +#target_include_directories(TraceAnalyzer PUBLIC qwt-qt5) +target_link_libraries(TraceAnalyzer + ${PYTHON_LIBRARIES} + ${QWT_LIBRARY} +) +qt5_use_modules(TraceAnalyzer Widgets Sql) + From d96e8c316aff8bfb9957a9358a4c3a46014e0391 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 00:00:05 +0100 Subject: [PATCH 165/183] CMAKE: Workaround for python --- DRAMSys/traceAnalyzer/businessObjects/pythoncaller.h | 6 ++++++ DRAMSys/traceAnalyzer/evaluationtool.h | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/DRAMSys/traceAnalyzer/businessObjects/pythoncaller.h b/DRAMSys/traceAnalyzer/businessObjects/pythoncaller.h index 17ff8819..9eceec38 100644 --- a/DRAMSys/traceAnalyzer/businessObjects/pythoncaller.h +++ b/DRAMSys/traceAnalyzer/businessObjects/pythoncaller.h @@ -38,6 +38,12 @@ #ifndef PYTHONCALLER_H #define PYTHONCALLER_H + +// Workaround for CMAKE and Python +#ifdef slots +#undef slots +#endif + #include #include #include diff --git a/DRAMSys/traceAnalyzer/evaluationtool.h b/DRAMSys/traceAnalyzer/evaluationtool.h index 32977f5b..81364e07 100644 --- a/DRAMSys/traceAnalyzer/evaluationtool.h +++ b/DRAMSys/traceAnalyzer/evaluationtool.h @@ -41,7 +41,13 @@ #define EVALUATIONTOOL_H #include "selectmetrics.h" + +// Workaround for CMAKE and Python +#ifdef slots +#undef slots +#endif #include + #include #include #include From 757ec296cf916c7fc8d4dd17eecc1d47f07bd130 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 00:01:27 +0100 Subject: [PATCH 166/183] FIXME: workaround for bankwise parameters. --- DRAMSys/library/src/simulation/dram/Dram.cpp | 3 ++- DRAMSys/library/src/simulation/dram/Dram.h | 2 +- DRAMSys/library/src/simulation/dram/DramDDR3.cpp | 14 +++++++------- DRAMSys/library/src/simulation/dram/DramDDR4.cpp | 14 +++++++------- DRAMSys/library/src/simulation/dram/DramWideIO.cpp | 14 +++++++------- 5 files changed, 24 insertions(+), 23 deletions(-) diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 9f5cb4ef..93877ee1 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -55,9 +55,10 @@ #include "../../common/protocol.h" #include "../../common/utils.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../common/third_party/DRAMPower/src/MemCommand.h" using namespace tlm; -using namespace Data; +using namespace DRAMPower; Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") { diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 119be3a8..e317768c 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -50,7 +50,7 @@ using namespace std; using namespace tlm; -using namespace Data; +using namespace DRAMPower; class Dram : public sc_module { diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index 55311aa5..bcdb03eb 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -67,13 +67,13 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memArchSpec.dll = true; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = memSpec->tFAW / clk; - memTimingSpec.RASB = memSpec->tRAS / clk; - memTimingSpec.RCB = memSpec->tRC / clk; - memTimingSpec.RPB = memSpec->tRP / clk; - memTimingSpec.RRDB = memSpec->tRRD / clk; - memTimingSpec.RRDB_L = memSpec->tRRD / clk; - memTimingSpec.RRDB_S = memSpec->tRRD / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; + //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; + //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD / clk; memTimingSpec.CCD_L = memSpec->tCCD / clk; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 08bc4b14..7fb03743 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -67,13 +67,13 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memArchSpec.dll = true; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = memSpec->tFAW / clk; - memTimingSpec.RASB = memSpec->tRAS / clk; - memTimingSpec.RCB = memSpec->tRC / clk; - memTimingSpec.RPB = memSpec->tRP / clk; - memTimingSpec.RRDB = memSpec->tRRD_S / clk; - memTimingSpec.RRDB_L = memSpec->tRRD_L / clk; - memTimingSpec.RRDB_S = memSpec->tRRD_S / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; + //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; + //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / clk; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / clk; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD_S / clk; memTimingSpec.CCD_L = memSpec->tCCD_L / clk; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 232e3224..1ee85597 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -69,13 +69,13 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memArchSpec.dll = false; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = memSpec->tTAW / clk; - memTimingSpec.RASB = memSpec->tRAS / clk; - memTimingSpec.RCB = memSpec->tRC / clk; - memTimingSpec.RPB = memSpec->tRP / clk; - memTimingSpec.RRDB = memSpec->tRRD / clk; - memTimingSpec.RRDB_L = memSpec->tRRD / clk; - memTimingSpec.RRDB_S = memSpec->tRRD / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tTAW / clk; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; + //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; + //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = 0; memTimingSpec.CCD = memSpec->BurstLength; memTimingSpec.CCD_L = memSpec->BurstLength; From ac7567741699c2f497bf16e96a3cade1c4bc6260 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 11:34:35 +0100 Subject: [PATCH 167/183] Simplified SystemC Download Script --- utils/getsysc_cmake.sh | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) mode change 100644 => 100755 utils/getsysc_cmake.sh diff --git a/utils/getsysc_cmake.sh b/utils/getsysc_cmake.sh old mode 100644 new mode 100755 index df9bc1ef..f67b206d --- a/utils/getsysc_cmake.sh +++ b/utils/getsysc_cmake.sh @@ -36,20 +36,11 @@ sysc=systemc-2.3.3 sysctarball=$sysc.tar.gz builddir=build - -function getnumprocs { - local __retvar=$1; - local __nprocs=$(cat /proc/cpuinfo | grep processor | wc -l) - if [[ "$__retvar" ]]; then - eval $__retvar="'$__nprocs'" - else - echo "$__nprocs" - fi -} +cores=4 # Get the code wget -nc http://accellera.org/images/downloads/standards/systemc/$sysctarball -tar -xaf $sysctarball +tar xfv $sysctarball rm $sysctarball cd $sysc @@ -57,7 +48,5 @@ cd $sysc mkdir $builddir cd $builddir cmake -DCMAKE_INSTALL_PREFIX=/opt/$sysc/ -DCMAKE_CXX_STANDARD=11 .. -getnumprocs np -nj=`expr $np - 1` -make -j$nj +make -j$cores sudo make install From eee04e897b3158bf0da4e813c968b225a6318b2b Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 12:20:22 +0100 Subject: [PATCH 168/183] Small syntactic change --- .gitmodules | 3 +++ DRAMSys/CMakeLists.txt | 2 +- DRAMSys/library/src/common/third_party/systemc | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) create mode 160000 DRAMSys/library/src/common/third_party/systemc diff --git a/.gitmodules b/.gitmodules index 14883ec7..cd634d8d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,3 +8,6 @@ [submodule "DRAMSys/unitTests/googletest"] path = DRAMSys/unitTests/googletest url = https://github.com/google/googletest.git +[submodule "DRAMSys/library/src/common/third_party/systemc"] + path = DRAMSys/library/src/common/third_party/systemc + url = https://github.com/accellera-official/systemc.git diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index b796dcb6..3212c071 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -7,7 +7,7 @@ project(DRAMSys) find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") # Add sqlite3 Dependency: -FIND_LIBRARY(SQLITE3_LIBRARY NAMES sqlite3) +find_library(SQLITE3_LIBRARY NAMES sqlite3) # Add DRAMSysLibrary: add_subdirectory(library) diff --git a/DRAMSys/library/src/common/third_party/systemc b/DRAMSys/library/src/common/third_party/systemc new file mode 160000 index 00000000..60418250 --- /dev/null +++ b/DRAMSys/library/src/common/third_party/systemc @@ -0,0 +1 @@ +Subproject commit 604182509559ae42c34e878f508bae7c18abbbd6 From 7faccaa02bdff87a67ea03c65176e9ba022bdb32 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 14:44:59 +0100 Subject: [PATCH 169/183] Included SystemC in CMAKE Build process --- DRAMSys/CMakeLists.txt | 11 +++++------ DRAMSys/library/CMakeLists.txt | 15 ++++++++++----- DRAMSys/traceAnalyzer/CMakeLists.txt | 13 ++++--------- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 3212c071..8fb9b18d 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -1,10 +1,10 @@ cmake_minimum_required(VERSION 3.10) -# Project Name +# Project Name: project(DRAMSys) -# Add SystemC Dependency: -find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") +# Configuration: +set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") # Add sqlite3 Dependency: find_library(SQLITE3_LIBRARY NAMES sqlite3) @@ -15,9 +15,8 @@ add_subdirectory(library) # Add TraceAnalyzer: add_subdirectory(traceAnalyzer) -set (CMAKE_CXX_STANDARD 11) - +# Build: add_executable(DRAMSys simulator/main.cpp) target_include_directories(DRAMSys PUBLIC DRAMSysLibrary library/src/simulation) -target_link_libraries(DRAMSys SystemC::systemc sqlite3 DRAMSysLibrary) +target_link_libraries(DRAMSys systemc sqlite3 DRAMSysLibrary) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index ff924707..dc1e62f2 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -3,13 +3,17 @@ cmake_minimum_required(VERSION 3.10) # Project Name project(DRAMSysLibrary) -# Add SystemC Dependency: -find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") - -set (CMAKE_CXX_STANDARD 11) +#set (CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") +# Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) +# Add SystemC: +set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs") +add_subdirectory(src/common/third_party/systemc) + +# Configuration: include_directories( src/simulation src/simulation/dram @@ -97,6 +101,7 @@ add_library(DRAMSysLibrary src/controller/powerdown/PowerDownManagerDummy.cpp ) +# Build: target_include_directories(DRAMSysLibrary PUBLIC src/common/third_party/DRAMPower/src) -target_link_libraries(DRAMSysLibrary DRAMPower SystemC::systemc) +target_link_libraries(DRAMSysLibrary SystemC::systemc DRAMPower) diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index f489ad94..7ec09045 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -1,11 +1,8 @@ cmake_minimum_required(VERSION 3.10) -# Project Name +# Project Name: project(TraceAnalyzer) -# Add SystemC Dependency: -find_package(SystemCLanguage CONFIG REQUIRED PATHS "/opt/systemc/lib/cmake") - # Add Python Dependency: find_library(PYTHON3_LIBRARY NAMES Python3) @@ -16,15 +13,14 @@ find_package(PythonLibs REQUIRED) find_library(QWT_LIBRARY NAMES "qwt-qt5" "qwt") find_path (QWT_INCLUDE_DIRS NAMES "qwt_plot.h" PATHS "/usr/include/qwt-qt5" "/usr/include/qwt") -message(${QWT_LIBRARY}) - -# Add QT Library +# Add QT Library: find_package(Qt5 COMPONENTS Core Gui Widgets Sql REQUIRED) set(CMAKE_AUTOMOC ON) set(CMAKE_AUTOUIC ON) set(CMAKE_AUTORCC ON) set(CMAKE_INCLUDE_CURRENT_DIR ON) +# Configure: set (CMAKE_CXX_STANDARD 11) include_directories( @@ -71,10 +67,9 @@ add_executable(TraceAnalyzer businessObjects/phases/phase.cpp ) -#target_include_directories(TraceAnalyzer PUBLIC qwt-qt5) +# Build: target_link_libraries(TraceAnalyzer ${PYTHON_LIBRARIES} ${QWT_LIBRARY} ) qt5_use_modules(TraceAnalyzer Widgets Sql) - From af3a3ab0bea43ba248b1b523218824434b3a3d25 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 14:51:53 +0100 Subject: [PATCH 170/183] Removed unecessary SystemC Download Scripts --- utils/getsysc.sh | 88 ------------------------------------------ utils/getsysc_cmake.sh | 63 ------------------------------ 2 files changed, 151 deletions(-) delete mode 100755 utils/getsysc.sh delete mode 100644 utils/getsysc_cmake.sh diff --git a/utils/getsysc.sh b/utils/getsysc.sh deleted file mode 100755 index 0dc300cb..00000000 --- a/utils/getsysc.sh +++ /dev/null @@ -1,88 +0,0 @@ -#!/usr/bin/env bash - -# Copyright (c) 2017, University of Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Author: Éder F. Zulian - -dest=$HOME -sysc=systemc-2.3.1a -sysctarball=$sysc.tar.gz -builddir=objdir - -function getnumprocs { - local __retvar=$1; - local __nprocs=$(cat /proc/cpuinfo | grep processor | wc -l) - if [[ "$__retvar" ]]; then - eval $__retvar="'$__nprocs'" - else - echo "$__nprocs" - fi -} - -# Get the code -cd $dest -wget -nc http://accellera.org/images/downloads/standards/systemc/$sysctarball -tar -xaf $sysctarball -rm $sysctarball - -# Create a git repo to keep track of local changes -cd $sysc -git init -git add . -git commit -m "Adding files to repository" - -# Build the library -mkdir $builddir -cd $builddir - -# Patch needed for building systemc-2.3.1a -if [[ $sysc == 'systemc-2.3.1a' ]]; then - printf "Patching $sysc\n" - sedfile="../src/systemc.h" - sed -i "s@using\ std::gets;@//using\ std::gets;@g" $sedfile -fi - -export SYSTEMC_HOME=$dest/$sysc -../configure $cfgopts -getnumprocs np -nj=`expr $np - 1` -make -j$nj -make check -j$nj -make install - -# Add env. variables to ~/.bashrc -arch=$(uname -m | sed 's/x86_//;s/i[3-6]86/32/') -echo "# SystemC home" >> ~/.bashrc -echo "export SYSTEMC_HOME=$dest/$sysc" >> ~/.bashrc -echo "# SystemC target architecture" >> ~/.bashrc -echo "export SYSTEMC_TARGET_ARCH=linux$arch" >> ~/.bashrc -echo "export LD_LIBRARY_PATH=\${LD_LIBRARY_PATH}:\${SYSTEMC_HOME}/lib-linux$arch" >> ~/.bashrc -echo "Done." diff --git a/utils/getsysc_cmake.sh b/utils/getsysc_cmake.sh deleted file mode 100644 index df9bc1ef..00000000 --- a/utils/getsysc_cmake.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/usr/bin/env bash - -# Copyright (c) 2020, University of Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Author: Éder F. Zulian -# Matthias Jung - -sysc=systemc-2.3.3 -sysctarball=$sysc.tar.gz -builddir=build - -function getnumprocs { - local __retvar=$1; - local __nprocs=$(cat /proc/cpuinfo | grep processor | wc -l) - if [[ "$__retvar" ]]; then - eval $__retvar="'$__nprocs'" - else - echo "$__nprocs" - fi -} - -# Get the code -wget -nc http://accellera.org/images/downloads/standards/systemc/$sysctarball -tar -xaf $sysctarball -rm $sysctarball -cd $sysc - -# Build the library -mkdir $builddir -cd $builddir -cmake -DCMAKE_INSTALL_PREFIX=/opt/$sysc/ -DCMAKE_CXX_STANDARD=11 .. -getnumprocs np -nj=`expr $np - 1` -make -j$nj -sudo make install From 79d6582387c30fe5b17fc1fcc6aebf484f931ee4 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 14:52:14 +0100 Subject: [PATCH 171/183] Added license to CMAKE Files --- DRAMSys/CMakeLists.txt | 32 ++++++++++++++++++++++++++++ DRAMSys/library/CMakeLists.txt | 32 ++++++++++++++++++++++++++++ DRAMSys/traceAnalyzer/CMakeLists.txt | 32 ++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 8fb9b18d..75ac6330 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -1,3 +1,35 @@ +# Copyright (c) 2020, Fraunhofer IESE +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Author: Matthias Jung + cmake_minimum_required(VERSION 3.10) # Project Name: diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index dc1e62f2..7094e300 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -1,3 +1,35 @@ +# Copyright (c) 2020, Fraunhofer IESE +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Author: Matthias Jung + cmake_minimum_required(VERSION 3.10) # Project Name diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 7ec09045..13567b43 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -1,3 +1,35 @@ +# Copyright (c) 2020, Fraunhofer IESE +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Author: Matthias Jung + cmake_minimum_required(VERSION 3.10) # Project Name: From 372f383664fdb7587e357e60900bf8c1a590c90a Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 14:57:31 +0100 Subject: [PATCH 172/183] Updated DRAMPower Submodule --- DRAMSys/library/src/common/third_party/DRAMPower | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/library/src/common/third_party/DRAMPower b/DRAMSys/library/src/common/third_party/DRAMPower index 9f9f8db0..1ddc48a3 160000 --- a/DRAMSys/library/src/common/third_party/DRAMPower +++ b/DRAMSys/library/src/common/third_party/DRAMPower @@ -1 +1 @@ -Subproject commit 9f9f8db0bdd0864bc7bb14e7c3d197a9473942c0 +Subproject commit 1ddc48a3872d93e2a60fc8c53348e0c2ed95fae1 From b21574c70d21ec61db396c9f1effcac822ded345 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 15:51:37 +0100 Subject: [PATCH 173/183] Readme updated w.r.t CMAKE --- README.md | 216 ++++++------------------------------------------------ 1 file changed, 21 insertions(+), 195 deletions(-) diff --git a/README.md b/README.md index 42b094de..bc1c6595 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -DRAMSys 3.0 +DRAMSys 4.0 =========== **DRAMSys** [1] is a flexible DRAM subsystem design space exploration @@ -9,40 +9,21 @@ Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sy [![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master) ## Basic Setup -Open a terminal window, go to your home directory, create a directory for your -projects and change to it. - -```bash -$ cd -$ mkdir projects -$ cd projects -``` - -Configure git on your machine. Some basic configurations follow. - -```bash -$ git config --global user.name "FirstName OtherNames LastName" -$ git config --global user.email user@email -$ git config --global credential.helper 'cache --timeout=3600' -$ git config --global color.ui auto -``` - -Now clone the repository into a local folder on your computer. +Start using DRAMSys by cloning the current stable master branch: ```bash $ git clone --recursive https://git.eit.uni-kl.de/ems/astdm/dram.sys.git ``` The *--recursive* flag tells git to initialize all submodules within the -repository. **DRAMPower** [2] and **tinyxml** are examples third party -repositories that were embedded within the source tree as submodules. +repository, namely **DRAMPower** [2], **SystemC** and **tinyxml**. Now you can implement, test, commit and push features into a **branch**. When you consider your work stable enough to be merged into the master branch it is time to open a **merge request** using the web interface. -Your changes will be reviewed and finally integrated into the master branch. +Your changes will be reviewed and might be integrated into the master branch. After cloning go to the project directory. @@ -66,87 +47,12 @@ $ ls ``` You can use [utils/install_deb.sh](./utils/install_deb.sh) in order to install -dependencies. First read and understand the script, then execute it. Type your -password if required. +dependencies. Type your password if required. ```bash $ ./install_deb.sh ``` -- **SystemC 2.3.1a and TLM-2.0** - -You can use [utils/getsysc.sh](./utils/getsysc.sh) to download and install SystemC 2.3.1a -and TLM-2.0. First read and understand the script then execute it. - -```bash -$ ./getsysc.sh -``` - -Alternatively, the sources can be downloaded from -[here](http://accellera.org/downloads/standards/systemc). For installation -instructions see the installation notes file contained in the release package. - -- **qwt-6.1** - -You can use [utils/getqwt.sh](./utils/getqwt.sh) in order to install qwt-6.1. First read -and understand the script then execute it. - -```bash -$ ./getqwt.sh -$ cd ~/qwt-6.1 -``` - -After that add environment variables to your ~/.bashrc. Open the file with a -text editor (e.g., nano, gedit, kate, notepad++, subl, atom, ultraedit, emacs, -vim, etc.). - -```bash -$ nano ~/.bashrc -``` - - -```bash -export LIBQWT_HOME=${HOME}/qwt-6.1/lib -export LIBQWT_HEADERS=${HOME}/qwt-6.1/src -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH:+${LD_LIBRARY_PATH}:}${LIBQWT_HOME} -``` - -Remember to verify that the library was created and the header files are -located in the paths you specify. You can use the **ls** command to accomplish -that. - -```bash -$ ls ${HOME}/qwt-6.1/lib -$ ls ${HOME}/qwt-6.1/src -``` - -Further information about Qwt can be found [here](http://qwt.sourceforge.net/). - -To grant flexibility to the user the paths where to find some essential -libraries and headers can be specified with environment variables. Make sure -you have the environment variables below defined in your ~/.bashrc file. - -**Note that some of the variables are automatically generated by the scripts. If -you install the libraries in custom paths in your system you have to adapt the -environment variables accordingly**. - -```bash -# SystemC home and target architecture -export SYSTEMC_HOME=$HOME/systemc-2.3.1a -export SYSTEMC_TARGET_ARCH=linux64 -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${SYSTEMC_HOME}/lib-$SYSTEMC_TARGET_ARCH - -# DRAMSys libraries and headers -export LIBPYTHON_VERSION="3.5m" -export PYTHON_HOME=/usr/lib/python3.5 -export PYTHON_HEADERS=/usr/include/python3.5m - -export LIBQWT_HOME=${HOME}/qwt-6.1/lib -export LIBQWT_HEADERS=${HOME}/qwt-6.1/src -export LD_LIBRARY_PATH=${LD_LIBRARY_PATH:+${LD_LIBRARY_PATH}:}${LIBQWT_HOME} - -``` - ### Coding Style Please read the [coding-style document](coding-style.md) before starting to @@ -167,15 +73,15 @@ $ qtcreator & Use the menu bar and open the DRAMSys project. -**File -> Open Project -> dram.sys/DRAMSys/DRAMSys.pro** +**File -> Open Project -> dram.sys/DRAMSys/CMakeLists.txt** When you open the project for the first time a configuration window pops-up. Then click in **Configure Project** and after that **Build** the project. To speedup the building process one can use the additional **make** option -**-j[jobs]**. The command line below returns a good number to be passed to -make as the number of jobs that can run simultaneously to improve the building -time. +**-j[jobs]**. The command line below returns the number of CPUs on a Debian +Linux to be passed to make as the number of jobs that can run simultaneously to +improve the building time. ```bash $ cat /proc/cpuinfo | grep processor | wc -l @@ -193,17 +99,18 @@ version** configuration shown in the image below. ### Building without QTCreator In case you prefer a command line interface to the QTCreator GUI you can also -use **qmake** to generate a Makefile and then compile the project. +use **cmake** to generate a Makefile and then compile the project. ```bash +$ cd dram.sys $ mkdir build $ cd build -$ qmake ../DRAMSys/DRAMSys.pro +$ cmake ../DRAMSys/ $ make -j4 ``` The compilation generates executable binary files **DRAMSys** and -**traceAnalyzer** that can be found inside sub-directories. +**TraceAnalyzer** that can be found inside sub-directories. From the build directory use the commands below to execute DRAMSys. @@ -231,50 +138,13 @@ $ ./traceAnalyzer ``` ### Building on MacOS (Formerly OSX) -- Install XCode - -- Install SystemC manually in /opt: - -```bash -$ ./configure --prefix=/opt/systemc -$ make -$ sudo make install -``` - -Or you can install via homebrew: - -```bash -$ brew install systemc -``` - -in this case, systemc will be installed, e.g. in: -``` -/usr/local/Cellar/systemc/2.3.1 -``` -and make a simlink of the lib directory: -``` -ln -s lib/ lib-macosx64 -``` - - -- Install the required python 3 over homebrew: +- Install XCode as a Compiler (or any other via Homebrew) +- Install the required python3 over homebrew: ```bash $ brew install python3 ``` -Python3 (via homebrew) will be installed in -``` -/usr/local/Cellar/python3/3.5.2_2/Frameworks/Python.framework -``` - -or you can install manually using official package provided in [link](https://www.python.org/downloads/) - -**Note:** Official Python Package will be installed in -``` -/Library/Frameworks/Python.framework -``` - - Install the QtCreator using offical setup file from [link](https://www.qt.io/download-open-source/#section-2) **Note:** You have later setup PATH for Qt5 and its tool if you install QtCreator manually, e.g: @@ -291,61 +161,17 @@ export PATH $ cd /Library/Frameworks $ sudo ln -s /opt/qwt-6.1.2/lib/qwt.framework/ . ``` -- Export correct Environment Variables in your terminal's profile, e.g: -```bash -# Setting for DRAMSys -# SystemC via official source -export SYSTEMC_HOME=/opt/systemc -export SYSTEMC_TARGET_ARCH=macosx64 -# SystemC via Homebrew -#export SYSTEMC_HOME=/usr/local/Cellar/systemc/2.3.1 -#export SYSTEMC_TARGET_ARCH=macosx64 - -# Python via official pkg -export PYTHON_HOME=/Library/Frameworks/Python.framework/Versions/3.5/lib -export PYTHON_HEADERS=/Library/Frameworks/Python.framework/Versions/3.5/Headers - -# Python3 via Homebrew -#export PYTHON_HOME=/usr/local/Cellar/python3/3.5.2_2/Frameworks/Python.framework/Versions/3.5/lib -#export PYTHON_HEADERS=/usr/local/Cellar/python3/3.5.2_2/Frameworks/Python.framework/Versions/3.5/Headers - -export LIBQWT_HOME=/opt/qwt-6.1.4/lib -export LIBQWT_HEADERS=/opt/qwt-6.1.4/lib/qwt.framework/Headers -``` - -- For the trace analyzer the file: -``` -/opt/local/Library/Frameworks/Python.framework/Versions/3.5/include/python3.4m/pyport.h -``` -has to be changed like [this](https://trac.macports.org/attachment/ticket/44288/issue10910-workaround.txt) - -- Install package [xerces](http://xerces.apache.org/mirrors.cgi) if your system does not have. - -- Type following command inside your dram.sys folder: - -```bash -$ mkdir build -$ qmake ../DRAMSys/DRAMSys.pro -$ make -j -``` - -Now you can try to run DRAMSys and traceAnalyzer App inside folder simulator and traceAnalyzer, respectively +You compile DRAMSys also with QtCreator or CMAKE as described in the Linux +section. ### Building on Windows 10 -DRAMSys can also run on Windows 10 with the *Windows Subsystem for Linux* (WSL) feature. You can install a linux distribution like Debian over the windows app store. -We refer to the following example [website](https://docs.microsoft.com/en-us/windows/wsl/install-win10). +- DRAMSys can also run on Windows 10 with the *Windows Subsystem for Linux* (WSL) feature. You can install a linux distribution like Debian over the windows app store. + We refer to the following example [website](https://docs.microsoft.com/en-us/windows/wsl/install-win10). + Then DRAMSys can be installed as described above for Linux. -Then DRAMSys can be installed as described above for Linux. However it might be advisable to install Qt, SystemC and qwt by hand. Qt should be downloaded from the Qt website. -The install systemc.sh script can be used to install SystemC and for QWT the version 6.1.3 should be used. - -Also the build configuration for SystemC should be configured as static with pthreads in the ```simulator.pro``` file: - -```qmake - #LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc - LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -Wl,-Bstatic -lsystemc -Wl,-Bdynamic -pthread -``` +- Native Windows 10 Implementation is currently under investigation ### DRAMSys Configuration From 3d0edbfc2cec4548745e8bb12c9a4772b4e8a8fe Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 18:08:15 +0100 Subject: [PATCH 174/183] Fix bug in DRAMSys Simulator Because of the transition process to CMAKE the main simulator file was adjusted for the paths of the simulation files. --- DRAMSys/simulator/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 5d6403f8..0cd387ac 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -68,14 +68,14 @@ int sc_main(int argc, char **argv) if (argc == 1) { // Get path of resources: resources = pathOfFile(argv[0]) - + string("/../../DRAMSys/library/resources/"); + + string("/../DRAMSys/library/resources/"); SimulationXML = resources + "simulations/ddr3-example.xml"; } // Run with specific config but default resource folders: else if (argc == 2) { // Get path of resources: resources = pathOfFile(argv[0]) - + string("/../../DRAMSys/library/resources/"); + + string("/../DRAMSys/library/resources/"); SimulationXML = argv[1]; } // Run with spefific config and specific resource folder: From 33546cabf434a7eb89cf40efcc3193f0e2401bf6 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 18:09:47 +0100 Subject: [PATCH 175/183] QMAKE files removed --- DRAMSys/DRAMSys.pro | 58 ----- DRAMSys/library/library.pro | 278 ------------------------ DRAMSys/traceAnalyzer/traceAnalyzer.pro | 121 ----------- 3 files changed, 457 deletions(-) delete mode 100644 DRAMSys/DRAMSys.pro delete mode 100644 DRAMSys/library/library.pro delete mode 100644 DRAMSys/traceAnalyzer/traceAnalyzer.pro diff --git a/DRAMSys/DRAMSys.pro b/DRAMSys/DRAMSys.pro deleted file mode 100644 index 6070fb7b..00000000 --- a/DRAMSys/DRAMSys.pro +++ /dev/null @@ -1,58 +0,0 @@ -TEMPLATE = subdirs - -thermalsim = $$(THERMALSIM) -isEmpty(thermalsim) { - thermalsim = false -} - -$$eval(thermalsim) { - message(Thermal Simulation Feature Enabled) -} else { - message(Thermal Simulation Feature Disabled) -} - -dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) -isEmpty(dramsys_disable_coverage_check) { - message(Coverage check ENABLED) -} else { - message(Coverage check DISABLED) -} - -systemc_home = $$(SYSTEMC_HOME) -isEmpty(systemc_home) { - systemc_home = /opt/systemc -} -message(SystemC home is $${systemc_home}) - -SUBDIRS += library -#SUBDIRS += unitTests -SUBDIRS += simulator -SUBDIRS += traceAnalyzer - -library.subdir = library -#unitTests.subdir = unitTests -simulator.subdir = simulator -traceAnalyzer.subdir = traceAnalyzer - -# Check if gem5 is installed: -gem5 = $$(GEM5) -isEmpty(gem5) { - message(GEM5 environment variable not found) - message(Gem5 Simulation Disabled) -} else { - message(Gem5 Simulation Feature Enabled) - message(Gem5 home is $${gem5}) - DEFINES += DRAMSYS_GEM5 - SUBDIRS += gem5 - gem5.subdir = gem5 - gem5.depends = library simulator -} - -# Define Build Order -simulator.depends = library - -# Additional Files: -# tests folder (DRAMSys/tests) -include(tests/tests.pri) - -DISTFILES += ../README.md diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro deleted file mode 100644 index 8043e99e..00000000 --- a/DRAMSys/library/library.pro +++ /dev/null @@ -1,278 +0,0 @@ -TARGET = DRAMSys - -TEMPLATE = lib -CONFIG += staticlib -CONFIG += console -CONFIG -= app_bundle -CONFIG -= qt - -system(cd ../../DRAMSys/library/src/common/third_party/DRAMPower; make src/libdrampower.a;) - -systemc_home = $$(SYSTEMC_HOME) -isEmpty(systemc_home) { - systemc_home = /opt/systemc/ -} - -# Check if PCT's SystemC should be used? -dramsys_pct = $$(DRAMSYS_PCT) -isEmpty(dramsys_pct) { - dramsys_pct = false -} - -$$eval(dramsys_pct) { - # PCT: - message(PCT Simulation Feature Enabled) - systemc_home = /software/Synopsys_CoWare/K-2015.12-SP1/SLS/linux/common - INCLUDEPATH += $${systemc_home}/include/tlm - - DEFINES += DRAMSYS_PCT -} - -# Check if gem5 should be used -gem5 = $$(GEM5) -isEmpty(gem5) { - message(GEM5 environment variable not found) - message(Gem5 Simulation Disabled) -} else { - message(Gem5 Simulation Feature Enabled) - message(Gem5 home is $${gem5}) - DEFINES += DRAMSYS_GEM5 -} - -message(SystemC home is $${systemc_home}) - -INCLUDEPATH += $${systemc_home}/include - -INCLUDEPATH += src/common/third_party/DRAMPower/src -INCLUDEPATH += src/common/third_party/DRAMPower/src/libdrampower -INCLUDEPATH += src/common/third_party/json/include - -DEFINES += TIXML_USE_STL -DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES - -dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) -isEmpty(dramsys_disable_coverage_check) { - coverage_check = true - message(Coverage check ENABLED) -} else { - coverage_check = false - message(Coverage check DISABLED) -} - -unix:!macx { - QMAKE_CXXFLAGS += -std=c++11 -O0 -g - $$eval(coverage_check) { - QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0 - QMAKE_LFLAGS += -lgcov --coverage - } -} - -macx: { - CONFIG += c++11 - QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g - QMAKE_MACOSX_DEPLOYMENT_TARGET=10.14 - $$eval(coverage_check) { - QMAKE_CXXFLAGS += --coverage - QMAKE_LFLAGS += --coverage - } -} - -QMAKE_CXXFLAGS += -isystem $${systemc_home}/include - -SOURCES += \ - src/common/third_party/tinyxml2/tinyxml2.cpp \ - src/common/TlmRecorder.cpp \ - src/common/DebugManager.cpp \ - src/configuration/Configuration.cpp \ - src/simulation/MemoryManager.cpp \ - src/simulation/TemperatureController.cpp \ - src/configuration/ConfigurationLoader.cpp \ - src/controller/Command.cpp \ - src/error/errormodel.cpp \ - src/simulation/TracePlayer.cpp \ - src/simulation/TraceSetup.cpp \ - src/simulation/DRAMSys.cpp \ - src/simulation/Setup.cpp \ - src/error/ECC/Bit.cpp \ - src/error/ECC/ECC.cpp \ - src/error/ECC/Word.cpp \ - src/error/eccbaseclass.cpp \ - src/error/ecchamming.cpp \ - src/common/AddressDecoder.cpp \ - src/simulation/dram/Dram.cpp \ - src/simulation/Arbiter.cpp \ - src/common/CongenAddressDecoder.cpp \ - src/common/XmlAddressDecoder.cpp \ - src/common/timingCalculations.cpp \ - src/common/dramExtensions.cpp \ - src/common/utils.cpp \ - src/simulation/dram/DramDDR3.cpp \ - src/simulation/dram/DramDDR4.cpp \ - src/simulation/dram/DramRecordable.cpp \ - src/simulation/dram/DramWideIO.cpp \ - src/configuration/memspec/MemSpec.cpp \ - src/controller/BankMachine.cpp \ - src/controller/Controller.cpp \ - src/controller/scheduler/SchedulerFifo.cpp \ - src/controller/scheduler/SchedulerFrFcfs.cpp \ - src/controller/cmdmux/CmdMuxStrict.cpp \ - src/controller/cmdmux/CmdMuxOldest.cpp \ - src/controller/ControllerRecordable.cpp \ - src/controller/checker/CheckerDDR3.cpp \ - src/controller/refresh/RefreshManager.cpp \ - src/controller/refresh/RefreshManagerDummy.cpp \ - src/controller/refresh/RefreshManagerBankwise.cpp \ - src/controller/checker/CheckerWideIO.cpp \ - src/configuration/memspec/MemSpecDDR3.cpp \ - src/configuration/memspec/MemSpecDDR4.cpp \ - src/configuration/memspec/MemSpecWideIO.cpp \ - src/configuration/memspec/MemSpecLPDDR4.cpp \ - src/controller/checker/CheckerDDR4.cpp \ - src/simulation/dram/DramLPDDR4.cpp \ - src/controller/checker/CheckerLPDDR4.cpp \ - src/configuration/memspec/MemSpecWideIO2.cpp \ - src/simulation/dram/DramWideIO2.cpp \ - src/controller/checker/CheckerWideIO2.cpp \ - src/configuration/memspec/MemSpecHBM2.cpp \ - src/simulation/dram/DramHBM2.cpp \ - src/controller/checker/CheckerHBM2.cpp \ - src/configuration/memspec/MemSpecGDDR5.cpp \ - src/configuration/memspec/MemSpecGDDR5X.cpp \ - src/configuration/memspec/MemSpecGDDR6.cpp \ - src/controller/checker/CheckerGDDR5.cpp \ - src/controller/checker/CheckerGDDR5X.cpp \ - src/controller/checker/CheckerGDDR6.cpp \ - src/simulation/dram/DramGDDR5.cpp \ - src/simulation/dram/DramGDDR5X.cpp \ - src/simulation/dram/DramGDDR6.cpp \ - src/controller/powerdown/PowerDownManagerStaggered.cpp \ - src/controller/powerdown/PowerDownManagerDummy.cpp - -HEADERS += \ - src/common/third_party/tinyxml2/tinyxml2.h \ - src/common/TlmRecorder.h \ - src/common/tlm2_base_protocol_checker.h \ - src/common/protocol.h \ - src/common/DebugManager.h \ - src/configuration/Configuration.h \ - src/simulation/TracePlayer.h \ - src/simulation/MemoryManager.h \ - src/simulation/dram/Dram.h \ - src/simulation/Arbiter.h \ - src/common/libDRAMPower.h \ - src/simulation/ReorderBuffer.h \ - src/configuration/memspec/MemSpec.h \ - src/simulation/StlPlayer.h \ - src/simulation/TracePlayerListener.h \ - src/simulation/TraceGenerator.h \ - src/simulation/TemperatureController.h \ - src/controller/Command.h \ - src/configuration/ConfigurationLoader.h \ - src/error/errormodel.h \ - src/simulation/ExampleInitiator.h \ - src/simulation/TraceSetup.h \ - src/simulation/DRAMSys.h \ - src/simulation/Setup.h \ - src/error/ECC/Bit.h \ - src/error/ECC/ECC.h \ - src/error/ECC/Word.h \ - src/error/eccbaseclass.h \ - src/error/ecchamming.h \ - src/simulation/IArbiter.h \ - src/simulation/SimpleArbiter.h \ - src/common/AddressDecoder.h \ - src/common/CongenAddressDecoder.h \ - src/common/XmlAddressDecoder.h \ - src/common/timingCalculations.h \ - src/common/dramExtensions.h \ - src/common/utils.h \ - src/configuration/TemperatureSimConfig.h \ - src/simulation/dram/DramDDR3.h \ - src/simulation/dram/DramDDR4.h \ - src/simulation/dram/DramRecordable.h \ - src/simulation/dram/DramWideIO.h \ - src/controller/GenericController.h \ - src/controller/BankMachine.h \ - src/controller/Controller.h \ - src/controller/scheduler/SchedulerIF.h \ - src/controller/scheduler/SchedulerFifo.h \ - src/controller/scheduler/SchedulerFrFcfs.h \ - src/controller/cmdmux/CmdMuxIF.h \ - src/controller/cmdmux/CmdMuxStrict.h \ - src/controller/cmdmux/CmdMuxOldest.h \ - src/controller/ControllerRecordable.h \ - src/controller/checker/CheckerIF.h \ - src/controller/checker/CheckerDDR3.h \ - src/controller/refresh/RefreshManagerIF.h \ - src/controller/refresh/RefreshManager.h \ - src/controller/refresh/RefreshManagerDummy.h \ - src/controller/refresh/RefreshManagerBankwise.h \ - src/controller/checker/CheckerWideIO.h \ - src/configuration/memspec/MemSpecDDR3.h \ - src/configuration/memspec/MemSpecWideIO.h \ - src/configuration/memspec/MemSpecDDR4.h \ - src/configuration/memspec/MemSpecLPDDR4.h \ - src/controller/checker/CheckerDDR4.h \ - src/simulation/dram/DramLPDDR4.h \ - src/controller/checker/CheckerLPDDR4.h \ - src/configuration/memspec/MemSpecWideIO2.h \ - src/simulation/dram/DramWideIO2.h \ - src/controller/checker/CheckerWideIO2.h \ - src/configuration/memspec/MemSpecHBM2.h \ - src/simulation/dram/DramHBM2.h \ - src/controller/checker/CheckerHBM2.h \ - src/configuration/memspec/MemSpecGDDR5.h \ - src/configuration/memspec/MemSpecGDDR5X.h \ - src/configuration/memspec/MemSpecGDDR6.h \ - src/controller/checker/CheckerGDDR5.h \ - src/controller/checker/CheckerGDDR5X.h \ - src/controller/checker/CheckerGDDR6.h \ - src/simulation/dram/DramGDDR5.h \ - src/simulation/dram/DramGDDR5X.h \ - src/simulation/dram/DramGDDR6.h \ - src/controller/powerdown/PowerDownManagerStaggered.h \ - src/controller/powerdown/PowerDownManagerIF.h \ - src/controller/powerdown/PowerDownManagerDummy.h - #src/common/third_party/json/include/nlohmann/json.hpp \ - -thermalsim = $$(THERMALSIM) -isEmpty(thermalsim) { - thermalsim = false -} - -$$eval(thermalsim) { - message(Thermal Simulation Feature Enabled) - - libthreed_ice_home = $$(LIBTHREED_ICE_HOME) - isEmpty(libthreed_ice_home) { - libthreed_ice_home = /opt/3D-ICE/ - } - message(LIBTHREED_ICE_HOME path is $${libthreed_ice_home}) - - libsuperlu_home = $$(LIBSUPERLU_HOME) - isEmpty(libsuperlu_home) { - libsuperlu_home = /opt/SuperLU_4.3/ - } - message(LIBSUPERLU_HOME path is $${libthreed_ice_home}) - - LIBS += -L$${libthreed_ice_home}/lib -lthreed-ice-2.2.4 - LIBS += -L$${libsuperlu_home}/lib -lsuperlu_4.3 - LIBS += -lblas - message(Libraries: $${LIBS}) - - INCLUDEPATH += $${libthreed_ice_home}/include - INCLUDEPATH += $${libsuperlu_home}/SRC - INCLUDEPATH += $${systemc_home}/include - message(Include paths: $${INCLUDEPATH}) - - QMAKE_CXXFLAGS += -DTHERMALSIM - message(Compiler flags: $${QMAKE_CXXFLAGS}) - -} else { - message(Thermal Simulation Feature Disabled) -} - -# Additional Files: -include(resources/resources.pri) - -DISTFILES += ../DRAMSys.astylerc diff --git a/DRAMSys/traceAnalyzer/traceAnalyzer.pro b/DRAMSys/traceAnalyzer/traceAnalyzer.pro deleted file mode 100644 index 42817173..00000000 --- a/DRAMSys/traceAnalyzer/traceAnalyzer.pro +++ /dev/null @@ -1,121 +0,0 @@ -QT += core gui -QT += sql -CONFIG += no_keywords - -CONFIG += python -CONFIG += link_pkgconfig -PKGCONFIG += python3 - -CONFIG+=qwt - -macx: { - message(Building on a MAC) - - CONFIG += c++11 - QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ - - QMAKE_LFLAGS += -F$$(LIBQWT_HOME) - LIBS += -F$$(LIBQWT_HOME) -framework qwt - INCLUDEPATH += $$(LIBQWT_HEADERS) - DEPENDPATH += $$replace(LIBQWT_HOME, lib, ) - - INCLUDEPATH += /usr/local/Cellar/python3/3.6.4_2/Frameworks/Python.framework/Versions/3.6/Headers/ - LIBS += -L/usr/local/Cellar/python3/3.6.4_2/Frameworks/Python.framework/Versions/3.6/lib/ -lpython3.6 - - CONFIG-=app_bundle -} - -greaterThan(QT_MAJOR_VERSION, 4): QT += widgets - -TARGET = traceAnalyzer -TEMPLATE = app - -#copy python scripts -config.path = $${OUT_PWD}/scripts -config.files = scripts/* -INSTALLS += config - -SOURCES += main.cpp\ - businessObjects/transaction.cpp \ - businessObjects/timespan.cpp \ - data/tracedb.cpp \ - presentation/tracenavigator.cpp \ - presentation/util/colorgenerator.cpp \ - presentation/tracedrawing.cpp \ - presentation/traceplotitem.cpp \ - gototimedialog.cpp \ - presentation/traceplot.cpp \ - tracefiletab.cpp \ - presentation/pornotracescroller.cpp \ - traceanalyzer.cpp \ - presentation/transactiontreewidget.cpp \ - presentation/commenttreewidget.cpp \ - presentation/util/clkgrid.cpp \ - queryeditor.cpp \ - presentation/selectedtransactiontreewidget.cpp \ - businessObjects/phases/phasefactory.cpp \ - presentation/debugmessagetreewidget.cpp \ - presentation/tracePlotMouseLabel.cpp \ - evaluationtool.cpp \ - selectmetrics.cpp \ - presentation/util/testlight.cpp \ - presentation/tracetesttreewidget.cpp \ - businessObjects/pythoncaller.cpp \ - businessObjects/tracetestresults.cpp \ - presentation/tracemetrictreewidget.cpp \ - businessObjects/phases/phase.cpp - -HEADERS += businessObjects/transaction.h \ - businessObjects/timespan.h \ - businessObjects/generalinfo.h \ - data/tracedb.h \ - presentation/tracenavigator.h \ - presentation/util/colorgenerator.h \ - presentation/util/engineeringScaleDraw.h \ - presentation/tracedrawingproperties.h \ - presentation/tracedrawing.h \ - presentation/traceplotitem.h \ - gototimedialog.h \ - presentation/traceplot.h \ - tracefiletab.h \ - presentation/pornotracescroller.h \ - traceanalyzer.h \ - presentation/transactiontreewidget.h \ - businessObjects/comment.h \ - presentation/commenttreewidget.h \ - businessObjects/tracetime.h \ - presentation/util/clkgrid.h \ - presentation/util/customlabelscaledraw.h \ - data/QueryTexts.h \ - queryeditor.h \ - presentation/selectedtransactiontreewidget.h \ - businessObjects/phases/phasefactory.h \ - presentation/debugmessagetreewidget.h \ - presentation/tracePlotMouseLabel.h \ - evaluationtool.h \ - selectmetrics.h \ - presentation/util/testlight.h \ - presentation/tracetesttreewidget.h \ - businessObjects/pythoncaller.h \ - businessObjects/testresult.h \ - businessObjects/tracetestresults.h \ - presentation/tracemetrictreewidget.h \ - businessObjects/calculatedMetric.h \ - businessObjects/tracecalculatedmetrics.h \ - businessObjects/phases/phase.h \ - businessObjects/commandlengths.h - - -FORMS += \ - gototimedialog.ui \ - tracefiletab.ui \ - traceanalyzer.ui \ - queryeditor.ui \ - preferences.ui \ - selectmetrics.ui \ - evaluationtool.ui - -# Additional Files: -include(scripts/scripts.pri) - -DISTFILES += ../DRAMSys.astylerc From 746b685677f95eee40fbe0b9d572b1193e228242 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 18:09:47 +0100 Subject: [PATCH 176/183] QMAKE files removed --- DRAMSys/DRAMSys.pro | 58 ----- DRAMSys/library/library.pro | 278 ------------------------ DRAMSys/simulator/simulator.pro | 64 ------ DRAMSys/traceAnalyzer/traceAnalyzer.pro | 121 ----------- 4 files changed, 521 deletions(-) delete mode 100644 DRAMSys/DRAMSys.pro delete mode 100644 DRAMSys/library/library.pro delete mode 100644 DRAMSys/simulator/simulator.pro delete mode 100644 DRAMSys/traceAnalyzer/traceAnalyzer.pro diff --git a/DRAMSys/DRAMSys.pro b/DRAMSys/DRAMSys.pro deleted file mode 100644 index 6070fb7b..00000000 --- a/DRAMSys/DRAMSys.pro +++ /dev/null @@ -1,58 +0,0 @@ -TEMPLATE = subdirs - -thermalsim = $$(THERMALSIM) -isEmpty(thermalsim) { - thermalsim = false -} - -$$eval(thermalsim) { - message(Thermal Simulation Feature Enabled) -} else { - message(Thermal Simulation Feature Disabled) -} - -dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) -isEmpty(dramsys_disable_coverage_check) { - message(Coverage check ENABLED) -} else { - message(Coverage check DISABLED) -} - -systemc_home = $$(SYSTEMC_HOME) -isEmpty(systemc_home) { - systemc_home = /opt/systemc -} -message(SystemC home is $${systemc_home}) - -SUBDIRS += library -#SUBDIRS += unitTests -SUBDIRS += simulator -SUBDIRS += traceAnalyzer - -library.subdir = library -#unitTests.subdir = unitTests -simulator.subdir = simulator -traceAnalyzer.subdir = traceAnalyzer - -# Check if gem5 is installed: -gem5 = $$(GEM5) -isEmpty(gem5) { - message(GEM5 environment variable not found) - message(Gem5 Simulation Disabled) -} else { - message(Gem5 Simulation Feature Enabled) - message(Gem5 home is $${gem5}) - DEFINES += DRAMSYS_GEM5 - SUBDIRS += gem5 - gem5.subdir = gem5 - gem5.depends = library simulator -} - -# Define Build Order -simulator.depends = library - -# Additional Files: -# tests folder (DRAMSys/tests) -include(tests/tests.pri) - -DISTFILES += ../README.md diff --git a/DRAMSys/library/library.pro b/DRAMSys/library/library.pro deleted file mode 100644 index 8043e99e..00000000 --- a/DRAMSys/library/library.pro +++ /dev/null @@ -1,278 +0,0 @@ -TARGET = DRAMSys - -TEMPLATE = lib -CONFIG += staticlib -CONFIG += console -CONFIG -= app_bundle -CONFIG -= qt - -system(cd ../../DRAMSys/library/src/common/third_party/DRAMPower; make src/libdrampower.a;) - -systemc_home = $$(SYSTEMC_HOME) -isEmpty(systemc_home) { - systemc_home = /opt/systemc/ -} - -# Check if PCT's SystemC should be used? -dramsys_pct = $$(DRAMSYS_PCT) -isEmpty(dramsys_pct) { - dramsys_pct = false -} - -$$eval(dramsys_pct) { - # PCT: - message(PCT Simulation Feature Enabled) - systemc_home = /software/Synopsys_CoWare/K-2015.12-SP1/SLS/linux/common - INCLUDEPATH += $${systemc_home}/include/tlm - - DEFINES += DRAMSYS_PCT -} - -# Check if gem5 should be used -gem5 = $$(GEM5) -isEmpty(gem5) { - message(GEM5 environment variable not found) - message(Gem5 Simulation Disabled) -} else { - message(Gem5 Simulation Feature Enabled) - message(Gem5 home is $${gem5}) - DEFINES += DRAMSYS_GEM5 -} - -message(SystemC home is $${systemc_home}) - -INCLUDEPATH += $${systemc_home}/include - -INCLUDEPATH += src/common/third_party/DRAMPower/src -INCLUDEPATH += src/common/third_party/DRAMPower/src/libdrampower -INCLUDEPATH += src/common/third_party/json/include - -DEFINES += TIXML_USE_STL -DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES - -dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) -isEmpty(dramsys_disable_coverage_check) { - coverage_check = true - message(Coverage check ENABLED) -} else { - coverage_check = false - message(Coverage check DISABLED) -} - -unix:!macx { - QMAKE_CXXFLAGS += -std=c++11 -O0 -g - $$eval(coverage_check) { - QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0 - QMAKE_LFLAGS += -lgcov --coverage - } -} - -macx: { - CONFIG += c++11 - QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g - QMAKE_MACOSX_DEPLOYMENT_TARGET=10.14 - $$eval(coverage_check) { - QMAKE_CXXFLAGS += --coverage - QMAKE_LFLAGS += --coverage - } -} - -QMAKE_CXXFLAGS += -isystem $${systemc_home}/include - -SOURCES += \ - src/common/third_party/tinyxml2/tinyxml2.cpp \ - src/common/TlmRecorder.cpp \ - src/common/DebugManager.cpp \ - src/configuration/Configuration.cpp \ - src/simulation/MemoryManager.cpp \ - src/simulation/TemperatureController.cpp \ - src/configuration/ConfigurationLoader.cpp \ - src/controller/Command.cpp \ - src/error/errormodel.cpp \ - src/simulation/TracePlayer.cpp \ - src/simulation/TraceSetup.cpp \ - src/simulation/DRAMSys.cpp \ - src/simulation/Setup.cpp \ - src/error/ECC/Bit.cpp \ - src/error/ECC/ECC.cpp \ - src/error/ECC/Word.cpp \ - src/error/eccbaseclass.cpp \ - src/error/ecchamming.cpp \ - src/common/AddressDecoder.cpp \ - src/simulation/dram/Dram.cpp \ - src/simulation/Arbiter.cpp \ - src/common/CongenAddressDecoder.cpp \ - src/common/XmlAddressDecoder.cpp \ - src/common/timingCalculations.cpp \ - src/common/dramExtensions.cpp \ - src/common/utils.cpp \ - src/simulation/dram/DramDDR3.cpp \ - src/simulation/dram/DramDDR4.cpp \ - src/simulation/dram/DramRecordable.cpp \ - src/simulation/dram/DramWideIO.cpp \ - src/configuration/memspec/MemSpec.cpp \ - src/controller/BankMachine.cpp \ - src/controller/Controller.cpp \ - src/controller/scheduler/SchedulerFifo.cpp \ - src/controller/scheduler/SchedulerFrFcfs.cpp \ - src/controller/cmdmux/CmdMuxStrict.cpp \ - src/controller/cmdmux/CmdMuxOldest.cpp \ - src/controller/ControllerRecordable.cpp \ - src/controller/checker/CheckerDDR3.cpp \ - src/controller/refresh/RefreshManager.cpp \ - src/controller/refresh/RefreshManagerDummy.cpp \ - src/controller/refresh/RefreshManagerBankwise.cpp \ - src/controller/checker/CheckerWideIO.cpp \ - src/configuration/memspec/MemSpecDDR3.cpp \ - src/configuration/memspec/MemSpecDDR4.cpp \ - src/configuration/memspec/MemSpecWideIO.cpp \ - src/configuration/memspec/MemSpecLPDDR4.cpp \ - src/controller/checker/CheckerDDR4.cpp \ - src/simulation/dram/DramLPDDR4.cpp \ - src/controller/checker/CheckerLPDDR4.cpp \ - src/configuration/memspec/MemSpecWideIO2.cpp \ - src/simulation/dram/DramWideIO2.cpp \ - src/controller/checker/CheckerWideIO2.cpp \ - src/configuration/memspec/MemSpecHBM2.cpp \ - src/simulation/dram/DramHBM2.cpp \ - src/controller/checker/CheckerHBM2.cpp \ - src/configuration/memspec/MemSpecGDDR5.cpp \ - src/configuration/memspec/MemSpecGDDR5X.cpp \ - src/configuration/memspec/MemSpecGDDR6.cpp \ - src/controller/checker/CheckerGDDR5.cpp \ - src/controller/checker/CheckerGDDR5X.cpp \ - src/controller/checker/CheckerGDDR6.cpp \ - src/simulation/dram/DramGDDR5.cpp \ - src/simulation/dram/DramGDDR5X.cpp \ - src/simulation/dram/DramGDDR6.cpp \ - src/controller/powerdown/PowerDownManagerStaggered.cpp \ - src/controller/powerdown/PowerDownManagerDummy.cpp - -HEADERS += \ - src/common/third_party/tinyxml2/tinyxml2.h \ - src/common/TlmRecorder.h \ - src/common/tlm2_base_protocol_checker.h \ - src/common/protocol.h \ - src/common/DebugManager.h \ - src/configuration/Configuration.h \ - src/simulation/TracePlayer.h \ - src/simulation/MemoryManager.h \ - src/simulation/dram/Dram.h \ - src/simulation/Arbiter.h \ - src/common/libDRAMPower.h \ - src/simulation/ReorderBuffer.h \ - src/configuration/memspec/MemSpec.h \ - src/simulation/StlPlayer.h \ - src/simulation/TracePlayerListener.h \ - src/simulation/TraceGenerator.h \ - src/simulation/TemperatureController.h \ - src/controller/Command.h \ - src/configuration/ConfigurationLoader.h \ - src/error/errormodel.h \ - src/simulation/ExampleInitiator.h \ - src/simulation/TraceSetup.h \ - src/simulation/DRAMSys.h \ - src/simulation/Setup.h \ - src/error/ECC/Bit.h \ - src/error/ECC/ECC.h \ - src/error/ECC/Word.h \ - src/error/eccbaseclass.h \ - src/error/ecchamming.h \ - src/simulation/IArbiter.h \ - src/simulation/SimpleArbiter.h \ - src/common/AddressDecoder.h \ - src/common/CongenAddressDecoder.h \ - src/common/XmlAddressDecoder.h \ - src/common/timingCalculations.h \ - src/common/dramExtensions.h \ - src/common/utils.h \ - src/configuration/TemperatureSimConfig.h \ - src/simulation/dram/DramDDR3.h \ - src/simulation/dram/DramDDR4.h \ - src/simulation/dram/DramRecordable.h \ - src/simulation/dram/DramWideIO.h \ - src/controller/GenericController.h \ - src/controller/BankMachine.h \ - src/controller/Controller.h \ - src/controller/scheduler/SchedulerIF.h \ - src/controller/scheduler/SchedulerFifo.h \ - src/controller/scheduler/SchedulerFrFcfs.h \ - src/controller/cmdmux/CmdMuxIF.h \ - src/controller/cmdmux/CmdMuxStrict.h \ - src/controller/cmdmux/CmdMuxOldest.h \ - src/controller/ControllerRecordable.h \ - src/controller/checker/CheckerIF.h \ - src/controller/checker/CheckerDDR3.h \ - src/controller/refresh/RefreshManagerIF.h \ - src/controller/refresh/RefreshManager.h \ - src/controller/refresh/RefreshManagerDummy.h \ - src/controller/refresh/RefreshManagerBankwise.h \ - src/controller/checker/CheckerWideIO.h \ - src/configuration/memspec/MemSpecDDR3.h \ - src/configuration/memspec/MemSpecWideIO.h \ - src/configuration/memspec/MemSpecDDR4.h \ - src/configuration/memspec/MemSpecLPDDR4.h \ - src/controller/checker/CheckerDDR4.h \ - src/simulation/dram/DramLPDDR4.h \ - src/controller/checker/CheckerLPDDR4.h \ - src/configuration/memspec/MemSpecWideIO2.h \ - src/simulation/dram/DramWideIO2.h \ - src/controller/checker/CheckerWideIO2.h \ - src/configuration/memspec/MemSpecHBM2.h \ - src/simulation/dram/DramHBM2.h \ - src/controller/checker/CheckerHBM2.h \ - src/configuration/memspec/MemSpecGDDR5.h \ - src/configuration/memspec/MemSpecGDDR5X.h \ - src/configuration/memspec/MemSpecGDDR6.h \ - src/controller/checker/CheckerGDDR5.h \ - src/controller/checker/CheckerGDDR5X.h \ - src/controller/checker/CheckerGDDR6.h \ - src/simulation/dram/DramGDDR5.h \ - src/simulation/dram/DramGDDR5X.h \ - src/simulation/dram/DramGDDR6.h \ - src/controller/powerdown/PowerDownManagerStaggered.h \ - src/controller/powerdown/PowerDownManagerIF.h \ - src/controller/powerdown/PowerDownManagerDummy.h - #src/common/third_party/json/include/nlohmann/json.hpp \ - -thermalsim = $$(THERMALSIM) -isEmpty(thermalsim) { - thermalsim = false -} - -$$eval(thermalsim) { - message(Thermal Simulation Feature Enabled) - - libthreed_ice_home = $$(LIBTHREED_ICE_HOME) - isEmpty(libthreed_ice_home) { - libthreed_ice_home = /opt/3D-ICE/ - } - message(LIBTHREED_ICE_HOME path is $${libthreed_ice_home}) - - libsuperlu_home = $$(LIBSUPERLU_HOME) - isEmpty(libsuperlu_home) { - libsuperlu_home = /opt/SuperLU_4.3/ - } - message(LIBSUPERLU_HOME path is $${libthreed_ice_home}) - - LIBS += -L$${libthreed_ice_home}/lib -lthreed-ice-2.2.4 - LIBS += -L$${libsuperlu_home}/lib -lsuperlu_4.3 - LIBS += -lblas - message(Libraries: $${LIBS}) - - INCLUDEPATH += $${libthreed_ice_home}/include - INCLUDEPATH += $${libsuperlu_home}/SRC - INCLUDEPATH += $${systemc_home}/include - message(Include paths: $${INCLUDEPATH}) - - QMAKE_CXXFLAGS += -DTHERMALSIM - message(Compiler flags: $${QMAKE_CXXFLAGS}) - -} else { - message(Thermal Simulation Feature Disabled) -} - -# Additional Files: -include(resources/resources.pri) - -DISTFILES += ../DRAMSys.astylerc diff --git a/DRAMSys/simulator/simulator.pro b/DRAMSys/simulator/simulator.pro deleted file mode 100644 index de259186..00000000 --- a/DRAMSys/simulator/simulator.pro +++ /dev/null @@ -1,64 +0,0 @@ -TARGET = DRAMSys - -TEMPLATE = app -CONFIG += console -CONFIG -= app_bundle -CONFIG -= qt - -systemc_home = $$(SYSTEMC_HOME) -isEmpty(systemc_home) { - systemc_home = /opt/systemc -} -message(SystemC home is $${systemc_home}) - -dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK) -isEmpty(dramsys_disable_coverage_check) { - coverage_check = true - message(Coverage check ENABLED) -} else { - coverage_check = false - message(Coverage check DISABLED) -} - -unix:!macx { - message(Building on a GNU/Linux) - QMAKE_RPATHDIR += $${systemc_home}/lib - message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR}) -} - -DEFINES += TIXML_USE_STL -DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES - -unix:!macx { - QMAKE_CXXFLAGS += -std=c++0x -O0 -g - $$eval(coverage_check) { - QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0 - QMAKE_LFLAGS += -lgcov --coverage - } -} - -macx: { - CONFIG += c++11 - QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g - QMAKE_MACOSX_DEPLOYMENT_TARGET=10.14 - $$eval(coverage_check) { - QMAKE_CXXFLAGS += --coverage - QMAKE_LFLAGS += --coverage - } -} - -INCLUDEPATH += ../library/src/simulation/ -INCLUDEPATH += $${systemc_home}/include -INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src -INCLUDEPATH += ../library/src/common/third_party/DRAMPower/src/libdrampower - -LIBS += -L$${systemc_home}/lib -lsystemc -LIBS += ../library/libDRAMSys.a -LIBS += ../../DRAMSys/library/src/common/third_party/DRAMPower/src/libdrampower.a -LIBS += -lsqlite3 - -PRE_TARGETDEPS += ../library/libDRAMSys.a - -SOURCES += main.cpp - -DISTFILES += ../DRAMSys.astylerc diff --git a/DRAMSys/traceAnalyzer/traceAnalyzer.pro b/DRAMSys/traceAnalyzer/traceAnalyzer.pro deleted file mode 100644 index 42817173..00000000 --- a/DRAMSys/traceAnalyzer/traceAnalyzer.pro +++ /dev/null @@ -1,121 +0,0 @@ -QT += core gui -QT += sql -CONFIG += no_keywords - -CONFIG += python -CONFIG += link_pkgconfig -PKGCONFIG += python3 - -CONFIG+=qwt - -macx: { - message(Building on a MAC) - - CONFIG += c++11 - QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ - - QMAKE_LFLAGS += -F$$(LIBQWT_HOME) - LIBS += -F$$(LIBQWT_HOME) -framework qwt - INCLUDEPATH += $$(LIBQWT_HEADERS) - DEPENDPATH += $$replace(LIBQWT_HOME, lib, ) - - INCLUDEPATH += /usr/local/Cellar/python3/3.6.4_2/Frameworks/Python.framework/Versions/3.6/Headers/ - LIBS += -L/usr/local/Cellar/python3/3.6.4_2/Frameworks/Python.framework/Versions/3.6/lib/ -lpython3.6 - - CONFIG-=app_bundle -} - -greaterThan(QT_MAJOR_VERSION, 4): QT += widgets - -TARGET = traceAnalyzer -TEMPLATE = app - -#copy python scripts -config.path = $${OUT_PWD}/scripts -config.files = scripts/* -INSTALLS += config - -SOURCES += main.cpp\ - businessObjects/transaction.cpp \ - businessObjects/timespan.cpp \ - data/tracedb.cpp \ - presentation/tracenavigator.cpp \ - presentation/util/colorgenerator.cpp \ - presentation/tracedrawing.cpp \ - presentation/traceplotitem.cpp \ - gototimedialog.cpp \ - presentation/traceplot.cpp \ - tracefiletab.cpp \ - presentation/pornotracescroller.cpp \ - traceanalyzer.cpp \ - presentation/transactiontreewidget.cpp \ - presentation/commenttreewidget.cpp \ - presentation/util/clkgrid.cpp \ - queryeditor.cpp \ - presentation/selectedtransactiontreewidget.cpp \ - businessObjects/phases/phasefactory.cpp \ - presentation/debugmessagetreewidget.cpp \ - presentation/tracePlotMouseLabel.cpp \ - evaluationtool.cpp \ - selectmetrics.cpp \ - presentation/util/testlight.cpp \ - presentation/tracetesttreewidget.cpp \ - businessObjects/pythoncaller.cpp \ - businessObjects/tracetestresults.cpp \ - presentation/tracemetrictreewidget.cpp \ - businessObjects/phases/phase.cpp - -HEADERS += businessObjects/transaction.h \ - businessObjects/timespan.h \ - businessObjects/generalinfo.h \ - data/tracedb.h \ - presentation/tracenavigator.h \ - presentation/util/colorgenerator.h \ - presentation/util/engineeringScaleDraw.h \ - presentation/tracedrawingproperties.h \ - presentation/tracedrawing.h \ - presentation/traceplotitem.h \ - gototimedialog.h \ - presentation/traceplot.h \ - tracefiletab.h \ - presentation/pornotracescroller.h \ - traceanalyzer.h \ - presentation/transactiontreewidget.h \ - businessObjects/comment.h \ - presentation/commenttreewidget.h \ - businessObjects/tracetime.h \ - presentation/util/clkgrid.h \ - presentation/util/customlabelscaledraw.h \ - data/QueryTexts.h \ - queryeditor.h \ - presentation/selectedtransactiontreewidget.h \ - businessObjects/phases/phasefactory.h \ - presentation/debugmessagetreewidget.h \ - presentation/tracePlotMouseLabel.h \ - evaluationtool.h \ - selectmetrics.h \ - presentation/util/testlight.h \ - presentation/tracetesttreewidget.h \ - businessObjects/pythoncaller.h \ - businessObjects/testresult.h \ - businessObjects/tracetestresults.h \ - presentation/tracemetrictreewidget.h \ - businessObjects/calculatedMetric.h \ - businessObjects/tracecalculatedmetrics.h \ - businessObjects/phases/phase.h \ - businessObjects/commandlengths.h - - -FORMS += \ - gototimedialog.ui \ - tracefiletab.ui \ - traceanalyzer.ui \ - queryeditor.ui \ - preferences.ui \ - selectmetrics.ui \ - evaluationtool.ui - -# Additional Files: -include(scripts/scripts.pri) - -DISTFILES += ../DRAMSys.astylerc From 175454a64e505573f5d9a4dc4692c8b9dbfde96c Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Fri, 28 Feb 2020 13:55:56 +0100 Subject: [PATCH 177/183] Utilscript for QWT deleted --- utils/getqwt.sh | 45 --------------------------------------------- 1 file changed, 45 deletions(-) delete mode 100755 utils/getqwt.sh diff --git a/utils/getqwt.sh b/utils/getqwt.sh deleted file mode 100755 index b3f43208..00000000 --- a/utils/getqwt.sh +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env bash - -# Copyright (c) 2017, University of Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Author: Éder F. Zulian - -dest=$HOME/qwt-6.1 -svn checkout svn://svn.code.sf.net/p/qwt/code/branches/qwt-6.1 $dest -cd $dest -svn up -r 2481 -if [[ $(hostname -s) =~ ^head[0-9]+$ ]] || [[ $(hostname -s) =~ ^node[0-9]+$ ]]; then - # Elwetritsch cluster - heads or nodes - module load qt/5.5 -fi -qmake qwt.pro -make -echo "Done." From f2a563539d20f1a416ebf5387d2123c6372e7860 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Sun, 1 Mar 2020 21:46:36 +0100 Subject: [PATCH 178/183] Modified CMAKE files for WIN32 --- .gitmodules | 3 +++ DRAMSys/CMakeLists.txt | 12 +++++++++--- DRAMSys/library/CMakeLists.txt | 17 ++++++++++++----- .../src/common/third_party/sqlite-amalgamation | 1 + DRAMSys/library/src/simulation/dram/Dram.cpp | 13 +++++++++++-- DRAMSys/traceAnalyzer/CMakeLists.txt | 9 ++++++++- 6 files changed, 44 insertions(+), 11 deletions(-) create mode 160000 DRAMSys/library/src/common/third_party/sqlite-amalgamation diff --git a/.gitmodules b/.gitmodules index cd634d8d..13b67848 100644 --- a/.gitmodules +++ b/.gitmodules @@ -11,3 +11,6 @@ [submodule "DRAMSys/library/src/common/third_party/systemc"] path = DRAMSys/library/src/common/third_party/systemc url = https://github.com/accellera-official/systemc.git +[submodule "DRAMSys/library/src/common/third_party/sqlite-amalgamation"] + path = DRAMSys/library/src/common/third_party/sqlite-amalgamation + url = https://github.com/azadkuh/sqlite-amalgamation.git diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 75ac6330..9ce35df7 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -37,9 +37,12 @@ project(DRAMSys) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") +set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") # Add sqlite3 Dependency: -find_library(SQLITE3_LIBRARY NAMES sqlite3) +set(BUILD_ENABLE_RTREE ON CACHE BOOL "Enable R-Tree Feature") +set(BUILD_ENABLE_RTREE ON) +add_subdirectory(library/src/common/third_party/sqlite-amalgamation) # Add DRAMSysLibrary: add_subdirectory(library) @@ -49,6 +52,9 @@ add_subdirectory(traceAnalyzer) # Build: add_executable(DRAMSys simulator/main.cpp) -target_include_directories(DRAMSys PUBLIC DRAMSysLibrary library/src/simulation) -target_link_libraries(DRAMSys systemc sqlite3 DRAMSysLibrary) +target_include_directories(DRAMSys + PUBLIC library/src/simulation/ + PUBLIC library/src/common/third_party/sqlite-amalgamation/ +) +target_link_libraries(DRAMSys sqlite3::sqlite3 systemc DRAMSysLibrary) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 7094e300..e43b84a8 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -35,9 +35,6 @@ cmake_minimum_required(VERSION 3.10) # Project Name project(DRAMSysLibrary) -#set (CMAKE_CXX_STANDARD 11) -set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") - # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) @@ -46,6 +43,9 @@ set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Shared Libs") add_subdirectory(src/common/third_party/systemc) # Configuration: +set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") +set(DCMAKE_SH="CMAKE_SH-NOTFOUND") + include_directories( src/simulation src/simulation/dram @@ -134,6 +134,13 @@ add_library(DRAMSysLibrary ) # Build: -target_include_directories(DRAMSysLibrary PUBLIC src/common/third_party/DRAMPower/src) -target_link_libraries(DRAMSysLibrary SystemC::systemc DRAMPower) +target_include_directories(DRAMSysLibrary + PUBLIC src/common/third_party/DRAMPower/src + PUBLIC src/common/third_party/sqlite-amalgamation/ +) +target_link_libraries(DRAMSysLibrary + SystemC::systemc + sqlite3::sqlite3 + DRAMPower +) diff --git a/DRAMSys/library/src/common/third_party/sqlite-amalgamation b/DRAMSys/library/src/common/third_party/sqlite-amalgamation new file mode 160000 index 00000000..9be05e13 --- /dev/null +++ b/DRAMSys/library/src/common/third_party/sqlite-amalgamation @@ -0,0 +1 @@ +Subproject commit 9be05e13408dd8cf8dafe8f11b1700a28194e07e diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 93877ee1..b23e9c58 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -39,7 +39,11 @@ #include "Dram.h" -#include +#ifdef _WIN32 + #include +#else + #include +#endif #include #include #include @@ -78,7 +82,12 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") else { // allocate and model storage of one DRAM channel using memory map - memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + #ifdef _WIN32 + SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported"); + memory = 0; // FIXME + #else + memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + #endif } } diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 13567b43..d4cc7b5a 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -43,7 +43,13 @@ find_package(PythonLibs REQUIRED) # Add QWT Dependency: find_library(QWT_LIBRARY NAMES "qwt-qt5" "qwt") -find_path (QWT_INCLUDE_DIRS NAMES "qwt_plot.h" PATHS "/usr/include/qwt-qt5" "/usr/include/qwt") +find_path (QWT_INCLUDE_DIRS NAMES "qwt_plot.h" PATHS + "/usr/include/qwt-qt5" + "/usr/include/qwt" + "C:\\Qwt\\" + "C:\\Qwt-6.1.4\\" + "C:\\Users\\jung\\Zeugs\\qwt\\qwt-614-install\\include" +) # Add QT Library: find_package(Qt5 COMPONENTS Core Gui Widgets Sql REQUIRED) @@ -54,6 +60,7 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON) # Configure: set (CMAKE_CXX_STANDARD 11) +set(DCMAKE_SH="CMAKE_SH-NOTFOUND") include_directories( ${QWT_INCLUDE_DIRS} From d739fc71f443df4b369dd5e79c180d6fd89f6cae Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Sun, 1 Mar 2020 21:47:11 +0100 Subject: [PATCH 179/183] Added CMAKE to deb_install file --- utils/install_deb.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/install_deb.sh b/utils/install_deb.sh index e08baca9..c7db3eac 100755 --- a/utils/install_deb.sh +++ b/utils/install_deb.sh @@ -73,6 +73,7 @@ libqt5widgets5 libqt5core5a lsb-core libqwt-qt5-dev +cmake gedit sublime-text vim-gtk From 0f586888ba7e506f3b06a8431c44a7812fcdea69 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Sun, 1 Mar 2020 21:47:32 +0100 Subject: [PATCH 180/183] Changed Paths in DRAMSys Standalone Simulator Due to the new CMAKE compile system, the hard-coded paths in the software did not fit. This error was now corrected. --- DRAMSys/simulator/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 5d6403f8..0cd387ac 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -68,14 +68,14 @@ int sc_main(int argc, char **argv) if (argc == 1) { // Get path of resources: resources = pathOfFile(argv[0]) - + string("/../../DRAMSys/library/resources/"); + + string("/../DRAMSys/library/resources/"); SimulationXML = resources + "simulations/ddr3-example.xml"; } // Run with specific config but default resource folders: else if (argc == 2) { // Get path of resources: resources = pathOfFile(argv[0]) - + string("/../../DRAMSys/library/resources/"); + + string("/../DRAMSys/library/resources/"); SimulationXML = argv[1]; } // Run with spefific config and specific resource folder: From b6f6ae0037f8c16f096378069c58d87189f1dadb Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Sun, 1 Mar 2020 22:03:38 +0100 Subject: [PATCH 181/183] Added ui Files in Trace Analyzer's CMAKE --- DRAMSys/traceAnalyzer/CMakeLists.txt | 65 +++++++++++++++------------- 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/DRAMSys/traceAnalyzer/CMakeLists.txt b/DRAMSys/traceAnalyzer/CMakeLists.txt index 13567b43..ddc3b13d 100644 --- a/DRAMSys/traceAnalyzer/CMakeLists.txt +++ b/DRAMSys/traceAnalyzer/CMakeLists.txt @@ -68,35 +68,42 @@ include_directories( add_executable(TraceAnalyzer - main.cpp - businessObjects/transaction.cpp - businessObjects/timespan.cpp - data/tracedb.cpp - presentation/tracenavigator.cpp - presentation/util/colorgenerator.cpp - presentation/tracedrawing.cpp - presentation/traceplotitem.cpp - gototimedialog.cpp - presentation/traceplot.cpp - tracefiletab.cpp - presentation/pornotracescroller.cpp - traceanalyzer.cpp - presentation/transactiontreewidget.cpp - presentation/commenttreewidget.cpp - presentation/util/clkgrid.cpp - queryeditor.cpp - presentation/selectedtransactiontreewidget.cpp - businessObjects/phases/phasefactory.cpp - presentation/debugmessagetreewidget.cpp - presentation/tracePlotMouseLabel.cpp - evaluationtool.cpp - selectmetrics.cpp - presentation/util/testlight.cpp - presentation/tracetesttreewidget.cpp - businessObjects/pythoncaller.cpp - businessObjects/tracetestresults.cpp - presentation/tracemetrictreewidget.cpp - businessObjects/phases/phase.cpp + main.cpp + businessObjects/transaction.cpp + businessObjects/timespan.cpp + data/tracedb.cpp + presentation/tracenavigator.cpp + presentation/util/colorgenerator.cpp + presentation/tracedrawing.cpp + presentation/traceplotitem.cpp + gototimedialog.cpp + presentation/traceplot.cpp + tracefiletab.cpp + presentation/pornotracescroller.cpp + traceanalyzer.cpp + presentation/transactiontreewidget.cpp + presentation/commenttreewidget.cpp + presentation/util/clkgrid.cpp + queryeditor.cpp + presentation/selectedtransactiontreewidget.cpp + businessObjects/phases/phasefactory.cpp + presentation/debugmessagetreewidget.cpp + presentation/tracePlotMouseLabel.cpp + evaluationtool.cpp + selectmetrics.cpp + presentation/util/testlight.cpp + presentation/tracetesttreewidget.cpp + businessObjects/pythoncaller.cpp + businessObjects/tracetestresults.cpp + presentation/tracemetrictreewidget.cpp + businessObjects/phases/phase.cpp + selectmetrics.ui + preferences.ui + evaluationtool.ui + gototimedialog.ui + tracefiletab.ui + queryeditor.ui + traceanalyzer.ui ) # Build: From 400846505f2434a1deec35188955776d50e0e4c7 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Thu, 19 Mar 2020 15:06:57 +0100 Subject: [PATCH 182/183] Bugfix for the creation of debug messages. --- DRAMSys/library/src/common/TlmRecorder.cpp | 75 +++++++++---------- DRAMSys/library/src/common/TlmRecorder.h | 41 +++++----- .../src/controller/checker/CheckerDDR3.cpp | 2 +- .../src/controller/checker/CheckerDDR4.cpp | 2 +- .../src/controller/checker/CheckerGDDR5.cpp | 2 +- .../src/controller/checker/CheckerGDDR5X.cpp | 2 +- .../src/controller/checker/CheckerGDDR6.cpp | 2 +- .../src/controller/checker/CheckerHBM2.cpp | 2 +- .../src/controller/checker/CheckerLPDDR4.cpp | 2 +- .../src/controller/checker/CheckerWideIO.cpp | 2 +- .../src/controller/checker/CheckerWideIO2.cpp | 2 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 10 +-- 12 files changed, 71 insertions(+), 73 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 0a2f0c19..d917d47c 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -45,11 +45,10 @@ #include "XmlAddressDecoder.h" #include "../configuration/Configuration.h" -using namespace std; +using namespace tlm; - -TlmRecorder::TlmRecorder(sc_module_name name, string uri, string dbname) : - sc_module(name), sqlScriptURI(uri), dbName(dbname), +TlmRecorder::TlmRecorder(std::string name, std::string uri, std::string dbname) : + name(name), sqlScriptURI(uri), dbName(dbname), totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME) { recordedData.reserve(transactionCommitRate); @@ -65,7 +64,7 @@ TlmRecorder::TlmRecorder(sc_module_name name, string uri, string dbname) : createTables(TlmRecorder::sqlScriptURI); prepareSqlStatements(); - PRINTDEBUGMESSAGE(this->name(), "Starting new database transaction"); + PRINTDEBUGMESSAGE(name, "Starting new database transaction"); } TlmRecorder::~TlmRecorder() @@ -91,15 +90,15 @@ void TlmRecorder::recordPower(double timeInSeconds, double averagePower) executeSqlStatement(insertPowerStatement); } -void TlmRecorder::recordPhase(tlm::tlm_generic_payload &trans, - tlm::tlm_phase phase, sc_time time) +void TlmRecorder::recordPhase(tlm_generic_payload &trans, + tlm_phase phase, sc_time time) { if (currentTransactionsInSystem.count(&trans) == 0) introduceTransactionSystem(trans); - string phaseName = phaseNameToString(phase); - string phaseBeginPrefix = "BEGIN_"; - string phaseEndPrefix = "END_"; + std::string phaseName = phaseNameToString(phase); + std::string phaseBeginPrefix = "BEGIN_"; + std::string phaseEndPrefix = "END_"; if (phaseName.find(phaseBeginPrefix) != string::npos) { phaseName.erase(0, phaseBeginPrefix.length()); @@ -111,7 +110,7 @@ void TlmRecorder::recordPhase(tlm::tlm_generic_payload &trans, currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time); } - bool phaseTerminatesTransaction = count(transactionTerminatingPhases.begin(), + bool phaseTerminatesTransaction = std::count(transactionTerminatingPhases.begin(), transactionTerminatingPhases.end(), phase) == 1; if (phaseTerminatesTransaction) removeTransactionFromSystem(trans); @@ -121,7 +120,7 @@ void TlmRecorder::recordPhase(tlm::tlm_generic_payload &trans, void TlmRecorder::updateDataStrobe(const sc_time &begin, const sc_time &end, - tlm::tlm_generic_payload &trans) + tlm_generic_payload &trans) { assert(currentTransactionsInSystem.count(&trans) != 0); currentTransactionsInSystem[&trans].timeOnDataStrobe.start = begin; @@ -137,7 +136,7 @@ void TlmRecorder::recordDebugMessage(std::string message, sc_time time) // ------------- internal ----------------------- -void TlmRecorder::introduceTransactionSystem(tlm::tlm_generic_payload &trans) +void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) { unsigned int id = totalNumTransactions++; currentTransactionsInSystem[&trans].id = id; @@ -154,21 +153,21 @@ void TlmRecorder::introduceTransactionSystem(tlm::tlm_generic_payload &trans) currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getExtension(&trans).TimeOfGeneration(); - PRINTDEBUGMESSAGE(name(), "New transaction #" + to_string(id) + " generation time " + + PRINTDEBUGMESSAGE(name, "New transaction #" + to_string(id) + " generation time " + currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); if (id % transactionCommitRate == 0) { - PRINTDEBUGMESSAGE(name(), "Committing transactions " + + PRINTDEBUGMESSAGE(name, "Committing transactions " + to_string(id - transactionCommitRate + 1) + " - " + to_string(id)); commitRecordedDataToDB(); } } -void TlmRecorder::removeTransactionFromSystem(tlm::tlm_generic_payload &trans) +void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) { assert(currentTransactionsInSystem.count(&trans) != 0); - PRINTDEBUGMESSAGE(name(), "Removing transaction #" + + PRINTDEBUGMESSAGE(name, "Removing transaction #" + to_string(currentTransactionsInSystem[&trans].id)); Transaction &recordingData = currentTransactionsInSystem[&trans]; @@ -197,12 +196,12 @@ void TlmRecorder::commitRecordedDataToDB() } -void TlmRecorder::Transaction::insertPhase(string name, sc_time begin) +void TlmRecorder::Transaction::insertPhase(std::string name, sc_time begin) { recordedPhases.push_back(Phase(name, begin)); } -void TlmRecorder::Transaction::setPhaseEnd(string name, sc_time end) +void TlmRecorder::Transaction::setPhaseEnd(std::string name, sc_time end) { // Find the latest recorder phase for that transaction with a matching name and update it // Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) @@ -221,7 +220,7 @@ void TlmRecorder::Transaction::setPhaseEnd(string name, sc_time end) void TlmRecorder::openDB(std::string name) { - ifstream f(name.c_str()); + std::ifstream f(name.c_str()); if (f.good()) { if (remove(name.c_str()) != 0) { SC_REPORT_FATAL("TlmRecorder", "Error deleting file" ); @@ -235,38 +234,38 @@ void TlmRecorder::openDB(std::string name) } -void TlmRecorder::createTables(string pathToURI) +void TlmRecorder::createTables(std::string pathToURI) { - string initial = loadTextFileContents(pathToURI); + std::string initial = loadTextFileContents(pathToURI); executeSqlCommand(initial); } void TlmRecorder::setUpTransactionTerminatingPhases() { - transactionTerminatingPhases.push_back(tlm::END_RESP); + transactionTerminatingPhases.push_back(END_RESP); // Refresh All - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_REFA)); // Refresh Bank - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_REFB)); // Phases for Power Down - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_PDNA)); - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_PDNP)); - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_SREF)); // Phases for Power Down Bankwise - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_PDNAB)); - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_PDNPB)); - transactionTerminatingPhases.push_back(static_cast + transactionTerminatingPhases.push_back(static_cast (END_SREFB)); } @@ -312,7 +311,7 @@ void TlmRecorder::prepareSqlStatements() sqlite3_prepare_v2(db, insertPowerString.c_str(), -1, &insertPowerStatement, 0); } -void TlmRecorder::insertDebugMessageInDB(string message, const sc_time &time) +void TlmRecorder::insertDebugMessageInDB(std::string message, const sc_time &time) { sqlite3_bind_int64(insertDebugMessageStatement, 1, time.value()); sqlite3_bind_text(insertDebugMessageStatement, 2, message.c_str(), @@ -422,7 +421,7 @@ void TlmRecorder::insertRangeInDB(unsigned int id, const sc_time &begin, sqlite3_bind_int64(insertRangeStatement, 3, end.value()); executeSqlStatement(insertRangeStatement); } -void TlmRecorder::insertPhaseInDB(string phaseName, const sc_time &begin, +void TlmRecorder::insertPhaseInDB(std::string phaseName, const sc_time &begin, const sc_time &end, unsigned int transactionID) { @@ -445,9 +444,9 @@ void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement) sqlite3_reset(statement); } -void TlmRecorder::executeSqlCommand(string command) +void TlmRecorder::executeSqlCommand(std::string command) { - PRINTDEBUGMESSAGE(name(), "Creating database by running provided sql script"); + PRINTDEBUGMESSAGE(name, "Creating database by running provided sql script"); char *errMsg = 0; int rc = sqlite3_exec(db, command.c_str(), NULL, 0, &errMsg); @@ -456,7 +455,7 @@ void TlmRecorder::executeSqlCommand(string command) sqlite3_free(errMsg); } - PRINTDEBUGMESSAGE(name(), "Database created successfully"); + PRINTDEBUGMESSAGE(name, "Database created successfully"); } void TlmRecorder::closeConnection() @@ -464,9 +463,9 @@ void TlmRecorder::closeConnection() commitRecordedDataToDB(); insertGeneralInfo(); insertCommandLengths(); - PRINTDEBUGMESSAGE(name(), "Number of transactions written to DB: " + PRINTDEBUGMESSAGE(name, "Number of transactions written to DB: " + std::to_string(totalNumTransactions - 1)); - PRINTDEBUGMESSAGE(name(), "tlmPhaseRecorder:\tEnd Recording"); + PRINTDEBUGMESSAGE(name, "tlmPhaseRecorder:\tEnd Recording"); sqlite3_close(db); db = NULL; } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 122678b5..9c6e75e3 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -53,40 +53,39 @@ #include "DebugManager.h" #include "utils.h" -using namespace std; +using namespace tlm; -class TlmRecorder : public sc_module +class TlmRecorder { public: std::string sqlScriptURI; std::string dbName; - TlmRecorder(sc_module_name name, string uri, string dbname); + TlmRecorder(std::string name, std::string uri, std::string dbname); ~TlmRecorder(); - void recordMCconfig(string mcconfig) + void recordMCconfig(std::string mcconfig) { this->mcconfig = mcconfig; } - void recordMemspec(string memspec) + void recordMemspec(std::string memspec) { this->memspec = memspec; } - void recordTracenames(string traces) + void recordTracenames(std::string traces) { this->traces = traces; } - void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, + void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time time); void recordPower(double timeInSeconds, double averagePower); void recordDebugMessage(std::string message, sc_time time); void updateDataStrobe(const sc_time &begin, const sc_time &end, - tlm::tlm_generic_payload &trans); + tlm_generic_payload &trans); void closeConnection(); private: - struct Transaction { Transaction() {} Transaction(unsigned int id): id(id) {} @@ -100,16 +99,18 @@ private: TimeInterval timeOnDataStrobe; struct Phase { - Phase(string name, sc_time begin): name(name), interval(begin, SC_ZERO_TIME) {} - string name; + Phase(std::string name, sc_time begin): name(name), interval(begin, SC_ZERO_TIME) {} + std::string name; TimeInterval interval; }; std::vector recordedPhases; - void insertPhase(string name, sc_time begin); - void setPhaseEnd(string name, sc_time end); + void insertPhase(std::string name, sc_time begin); + void setPhaseEnd(std::string name, sc_time end); }; + std::string name; + std::string mcconfig, memspec, traces; void prepareSqlStatements(); @@ -120,26 +121,26 @@ private: void createTables(std::string pathToURI); void setUpTransactionTerminatingPhases(); - void introduceTransactionSystem(tlm::tlm_generic_payload &trans); - void removeTransactionFromSystem(tlm::tlm_generic_payload &trans); + void introduceTransactionSystem(tlm_generic_payload &trans); + void removeTransactionFromSystem(tlm_generic_payload &trans); void commitRecordedDataToDB(); void insertGeneralInfo(); void insertCommandLengths(); void insertTransactionInDB(Transaction &recordingData); void insertRangeInDB(unsigned int id, const sc_time &begin, const sc_time &end); - void insertPhaseInDB(string phaseName, const sc_time &begin, const sc_time &end, + void insertPhaseInDB(std::string phaseName, const sc_time &begin, const sc_time &end, unsigned int transactionID); - void insertDebugMessageInDB(string message, const sc_time &time); + void insertDebugMessageInDB(std::string message, const sc_time &time); static const int transactionCommitRate = 1000; - vector recordedData; - map currentTransactionsInSystem; + std::vector recordedData; + std::map currentTransactionsInSystem; unsigned int totalNumTransactions; sc_time simulationTimeCoveredByRecording; - std::vector transactionTerminatingPhases; + std::vector transactionTerminatingPhases; sqlite3 *db = NULL; sqlite3_stmt *insertTransactionStatement, *insertRangeStatement, *updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement, diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index d1a72fbe..ad58c159 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -369,7 +369,7 @@ sc_time CheckerDDR3::delayToSatisfyConstraints(Command command, Rank rank, BankG void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index e0bab316..8576d1b6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -252,7 +252,7 @@ sc_time CheckerDDR4::delayToSatisfyConstraints(Command command, Rank rank, BankG void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 25107115..f607942f 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -329,7 +329,7 @@ sc_time CheckerGDDR5::delayToSatisfyConstraints(Command command, Rank rank, Bank void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index c773e8ac..1f1aee32 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -329,7 +329,7 @@ sc_time CheckerGDDR5X::delayToSatisfyConstraints(Command command, Rank rank, Ban void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index d37209ad..1a1ae3ae 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -322,7 +322,7 @@ sc_time CheckerGDDR6::delayToSatisfyConstraints(Command command, Rank rank, Bank void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index e20b5254..31d028e9 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -317,7 +317,7 @@ sc_time CheckerHBM2::delayToSatisfyConstraints(Command command, Rank rank, BankG void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index ea2deb12..ed7b9116 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -274,7 +274,7 @@ sc_time CheckerLPDDR4::delayToSatisfyConstraints(Command command, Rank rank, Ban void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 9b3f4aa8..118abc31 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -221,7 +221,7 @@ sc_time CheckerWideIO::delayToSatisfyConstraints(Command command, Rank rank, Ban void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index f91aabda..463e3eb8 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -267,7 +267,7 @@ sc_time CheckerWideIO2::delayToSatisfyConstraints(Command command, Rank rank, Ba void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) { - PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + bank.ID() + PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index f348eaa4..f705a6fc 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -133,6 +133,9 @@ DRAMSys::DRAMSys(sc_module_name name, AddressDecoder::getInstance().print(); + // Setup the debug manager: + setupDebugManager(Configuration::getInstance().SimulationName); + // If a simulation file is passed as argument to DRAMSys the simulation ID // is prepended to the simulation name if found. std::string simName; @@ -157,9 +160,6 @@ DRAMSys::DRAMSys(sc_module_name name, // Connect all internal DRAMSys modules: bindSockets(); - // Setup the debug manager: - setupDebugManager(Configuration::getInstance().SimulationName); - report(headline); } @@ -209,9 +209,7 @@ void DRAMSys::setupTlmRecorders(const string &traceName, std::string recorderName = "tlmRecorder" + std::to_string(i); TlmRecorder *tlmRecorder = - new TlmRecorder(recorderName.c_str(), - sqlScriptURI.c_str(), - dbName.c_str()); + new TlmRecorder(recorderName, sqlScriptURI.c_str(), dbName.c_str()); tlmRecorder->recordMCconfig(Configuration::getInstance().mcconfigUri); tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri); From 89221c53a7084192fe9f9f706986c8889e47d537 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 24 Mar 2020 15:04:39 +0100 Subject: [PATCH 183/183] Gitignore updated to cmake. --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index c7425d6f..99b20805 100644 --- a/.gitignore +++ b/.gitignore @@ -3,7 +3,7 @@ /dram/debug /dram/release /dram/build -*pro.user* +*.user *.tdb *.tdb-journal *.out