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sim config files to json

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This commit is contained in:
scorrea
2020-05-14 10:21:55 +02:00
parent 587ecbd2a7
commit 85aab3ded9
42 changed files with 532 additions and 665 deletions
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22
DRAMSys/library/resources/configs/simulator/ddr3-single-device.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "ddr3_single_dev"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "ddr3_single_dev",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

24
DRAMSys/library/resources/configs/simulator/ddr3-single-device.xml
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@@ -1,24 +0,0 @@
<simconfig>
<SimulationName value="ddr3_single_dev" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/ddr3.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

29
DRAMSys/library/resources/configs/simulator/ddr3.xml
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@@ -1,29 +0,0 @@
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "AddressOffset": {"@value": "2147483648"}, "UseMalloc": {"@value": "1"}}}
{
"simconfig": {
"AddressOffset": "2147483648",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"StoreMode": "Store",
"ThermalSimulation": "0",
"UseMalloc": "1",
"WindowSize": "1000"
}
}

28
DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.xml
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@@ -1,28 +0,0 @@
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="Store" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
-->
<AddressOffset value = "2147483648" />
<UseMalloc value="1" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/ddr3_ecc.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Hamming"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "ErrorModel"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Hamming",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"StoreMode": "ErrorModel",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

24
DRAMSys/library/resources/configs/simulator/ddr3_ecc.xml
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@@ -1,24 +0,0 @@
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Hamming" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="ErrorModel" />
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "ddr3",
"SimulationProgressBar": "1",
"StoreMode": "Store",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

29
DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.xml
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@@ -1,29 +0,0 @@
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="Store" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/ddr4.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "ddr4"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "8",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"SimulationName": "ddr4",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

29
DRAMSys/library/resources/configs/simulator/ddr4.xml
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@@ -1,29 +0,0 @@
<simconfig>
<SimulationName value="ddr4" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/hbm2.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "hbm2"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"SimulationName": "hbm2",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

29
DRAMSys/library/resources/configs/simulator/hbm2.xml
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@@ -1,29 +0,0 @@
<simconfig>
<SimulationName value="hbm2" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/lpddr4.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "lpddr4"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "0",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "1",
"PowerAnalysis": "0",
"SimulationName": "lpddr4",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

29
DRAMSys/library/resources/configs/simulator/lpddr4.xml
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@@ -1,29 +0,0 @@
<simconfig>
<SimulationName value="lpddr4" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

41
DRAMSys/library/resources/configs/simulator/orgr.json
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@@ -1 +1,40 @@
{"simconfig": {"SimulationName": {"@value": "orgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": [{"@value": "1"}, {"@value": "1"}], "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "20"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "8"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "27"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "27"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "1"}, "ControllerCoreRGRB5": {"@value": "1"}, "ControllerCoreRGRB6": {"@value": "1"}, "ControllerCoreRGRB7": {"@value": "1"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"ControllerCoreRGR": "1",
"ControllerCoreRGRB0": "1",
"ControllerCoreRGRB1": "1",
"ControllerCoreRGRB10": "0",
"ControllerCoreRGRB11": "0",
"ControllerCoreRGRB12": "0",
"ControllerCoreRGRB13": "0",
"ControllerCoreRGRB14": "0",
"ControllerCoreRGRB15": "0",
"ControllerCoreRGRB2": "1",
"ControllerCoreRGRB3": "1",
"ControllerCoreRGRB4": "1",
"ControllerCoreRGRB5": "1",
"ControllerCoreRGRB6": "1",
"ControllerCoreRGRB7": "1",
"ControllerCoreRGRB8": "0",
"ControllerCoreRGRB9": "0",
"ControllerCoreRGRtFAWBInClkCycles": "27",
"ControllerCoreRGRtRASBInClkCycles": "20",
"ControllerCoreRGRtRCBInClkCycles": "27",
"ControllerCoreRGRtRPBInClkCycles": "8",
"ControllerCoreRGRtRRDB_LInClkCycles": "6",
"ControllerCoreRGRtRRDB_SInClkCycles": "6",
"ControllerCoreRefDisable": "0",
"ControllerCoreRefNumARCmdsIntREFI": "8192",
"DatabaseRecording": "1",
"Debug": "0",
"EnableWindowing": "1",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

52
DRAMSys/library/resources/configs/simulator/orgr.xml
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@@ -1,52 +0,0 @@
<simconfig>
<SimulationName value="orgr" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<NumberOfMemChannels value="1"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- NEW COMMANDS USING STARNDARD TIMING VALUES -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
<!-- NEW COMMANDS USING OPTIMAL TIMING VALUES -->
<!--
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
-->
<!-- SELECT THE BANKS YOU WANT TO REFRESH 1 YES 0 NO (max. 16 banks!) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<UseMalloc value="0" />
</simconfig>

41
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json
View File

@@ -1 +1,40 @@
{"simconfig": {"SimulationName": {"@value": "orgr_4b_opt_timings"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": {"@value": "1"}, "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "11"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "5"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "16"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "0"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "0"}, "ControllerCoreRGRB5": {"@value": "0"}, "ControllerCoreRGRB6": {"@value": "0"}, "ControllerCoreRGRB7": {"@value": "0"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"ControllerCoreRGR": "1",
"ControllerCoreRGRB0": "1",
"ControllerCoreRGRB1": "1",
"ControllerCoreRGRB10": "0",
"ControllerCoreRGRB11": "0",
"ControllerCoreRGRB12": "0",
"ControllerCoreRGRB13": "0",
"ControllerCoreRGRB14": "0",
"ControllerCoreRGRB15": "0",
"ControllerCoreRGRB2": "1",
"ControllerCoreRGRB3": "1",
"ControllerCoreRGRB4": "0",
"ControllerCoreRGRB5": "0",
"ControllerCoreRGRB6": "0",
"ControllerCoreRGRB7": "0",
"ControllerCoreRGRB8": "0",
"ControllerCoreRGRB9": "0",
"ControllerCoreRGRtFAWBInClkCycles": "0",
"ControllerCoreRGRtRASBInClkCycles": "11",
"ControllerCoreRGRtRCBInClkCycles": "16",
"ControllerCoreRGRtRPBInClkCycles": "5",
"ControllerCoreRGRtRRDB_LInClkCycles": "2",
"ControllerCoreRGRtRRDB_SInClkCycles": "2",
"ControllerCoreRefDisable": "0",
"ControllerCoreRefNumARCmdsIntREFI": "8192",
"DatabaseRecording": "1",
"Debug": "0",
"EnableWindowing": "1",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_4b_opt_timings",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

52
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml
View File

@@ -1,52 +0,0 @@
<simconfig>
<SimulationName value="orgr_4b_opt_timings" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<NumberOfMemChannels value="1"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="0"/>
<ControllerCoreRGRB5 value="0"/>
<ControllerCoreRGRB6 value="0"/>
<ControllerCoreRGRB7 value="0"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<UseMalloc value="0" />
</simconfig>

43
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json
View File

@@ -1 +1,42 @@
{"simconfig": {"SimulationName": {"@value": "orgr_4b_std_timings"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": [{"@value": "1"}, {"@value": "1"}], "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "20"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "8"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "27"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "27"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "0"}, "ControllerCoreRGRB5": {"@value": "0"}, "ControllerCoreRGRB6": {"@value": "0"}, "ControllerCoreRGRB7": {"@value": "0"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"ControllerCoreRGR": {
"@value": "1"
},
"ControllerCoreRGRB0": "1",
"ControllerCoreRGRB1": "1",
"ControllerCoreRGRB10": "0",
"ControllerCoreRGRB11": "0",
"ControllerCoreRGRB12": "0",
"ControllerCoreRGRB13": "0",
"ControllerCoreRGRB14": "0",
"ControllerCoreRGRB15": "0",
"ControllerCoreRGRB2": "1",
"ControllerCoreRGRB3": "1",
"ControllerCoreRGRB4": "0",
"ControllerCoreRGRB5": "0",
"ControllerCoreRGRB6": "0",
"ControllerCoreRGRB7": "0",
"ControllerCoreRGRB8": "0",
"ControllerCoreRGRB9": "0",
"ControllerCoreRGRtFAWBInClkCycles": "27",
"ControllerCoreRGRtRASBInClkCycles": "20",
"ControllerCoreRGRtRCBInClkCycles": "27",
"ControllerCoreRGRtRPBInClkCycles": "8",
"ControllerCoreRGRtRRDB_LInClkCycles": "6",
"ControllerCoreRGRtRRDB_SInClkCycles": "6",
"ControllerCoreRefDisable": "0",
"ControllerCoreRefNumARCmdsIntREFI": "8192",
"DatabaseRecording": "1",
"Debug": "0",
"EnableWindowing": "1",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_4b_std_timings",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

52
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml
View File

@@ -1,52 +0,0 @@
<simconfig>
<SimulationName value="orgr_4b_std_timings" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<NumberOfMemChannels value="1"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
<!-- New commands using optimal timing values -->
<!--
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
-->
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="0"/>
<ControllerCoreRGRB5 value="0"/>
<ControllerCoreRGRB6 value="0"/>
<ControllerCoreRGRB7 value="0"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<UseMalloc value="0" />
</simconfig>

41
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json
View File

@@ -1 +1,40 @@
{"simconfig": {"SimulationName": {"@value": "orgr_8b_opt_timings"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": {"@value": "1"}, "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "11"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "5"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "16"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "0"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "1"}, "ControllerCoreRGRB5": {"@value": "1"}, "ControllerCoreRGRB6": {"@value": "1"}, "ControllerCoreRGRB7": {"@value": "1"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"ControllerCoreRGR": "1",
"ControllerCoreRGRB0": "1",
"ControllerCoreRGRB1": "1",
"ControllerCoreRGRB10": "0",
"ControllerCoreRGRB11": "0",
"ControllerCoreRGRB12": "0",
"ControllerCoreRGRB13": "0",
"ControllerCoreRGRB14": "0",
"ControllerCoreRGRB15": "0",
"ControllerCoreRGRB2": "1",
"ControllerCoreRGRB3": "1",
"ControllerCoreRGRB4": "1",
"ControllerCoreRGRB5": "1",
"ControllerCoreRGRB6": "1",
"ControllerCoreRGRB7": "1",
"ControllerCoreRGRB8": "0",
"ControllerCoreRGRB9": "0",
"ControllerCoreRGRtFAWBInClkCycles": "0",
"ControllerCoreRGRtRASBInClkCycles": "11",
"ControllerCoreRGRtRCBInClkCycles": "16",
"ControllerCoreRGRtRPBInClkCycles": "5",
"ControllerCoreRGRtRRDB_LInClkCycles": "2",
"ControllerCoreRGRtRRDB_SInClkCycles": "2",
"ControllerCoreRefDisable": "0",
"ControllerCoreRefNumARCmdsIntREFI": "8192",
"DatabaseRecording": "1",
"Debug": "0",
"EnableWindowing": "1",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_8b_opt_timings",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

52
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml
View File

@@ -1,52 +0,0 @@
<simconfig>
<SimulationName value="orgr_8b_opt_timings" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<NumberOfMemChannels value="1"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<!--
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
-->
<!-- New commands using optimal timing values -->
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<UseMalloc value="0" />
</simconfig>

43
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json
View File

@@ -1 +1,42 @@
{"simconfig": {"SimulationName": {"@value": "orgr_8b_std_timings_ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": [{"@value": "1"}, {"@value": "1"}], "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "20"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "8"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "27"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "27"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "1"}, "ControllerCoreRGRB5": {"@value": "1"}, "ControllerCoreRGRB6": {"@value": "1"}, "ControllerCoreRGRB7": {"@value": "1"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"ControllerCoreRGR": {
"@value": "1"
},
"ControllerCoreRGRB0": "1",
"ControllerCoreRGRB1": "1",
"ControllerCoreRGRB10": "0",
"ControllerCoreRGRB11": "0",
"ControllerCoreRGRB12": "0",
"ControllerCoreRGRB13": "0",
"ControllerCoreRGRB14": "0",
"ControllerCoreRGRB15": "0",
"ControllerCoreRGRB2": "1",
"ControllerCoreRGRB3": "1",
"ControllerCoreRGRB4": "1",
"ControllerCoreRGRB5": "1",
"ControllerCoreRGRB6": "1",
"ControllerCoreRGRB7": "1",
"ControllerCoreRGRB8": "0",
"ControllerCoreRGRB9": "0",
"ControllerCoreRGRtFAWBInClkCycles": "27",
"ControllerCoreRGRtRASBInClkCycles": "20",
"ControllerCoreRGRtRCBInClkCycles": "27",
"ControllerCoreRGRtRPBInClkCycles": "8",
"ControllerCoreRGRtRRDB_LInClkCycles": "6",
"ControllerCoreRGRtRRDB_SInClkCycles": "6",
"ControllerCoreRefDisable": "0",
"ControllerCoreRefNumARCmdsIntREFI": "8192",
"DatabaseRecording": "1",
"Debug": "0",
"EnableWindowing": "1",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_8b_std_timings_ddr3",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

52
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml
View File

@@ -1,52 +0,0 @@
<simconfig>
<SimulationName value="orgr_8b_std_timings_ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<NumberOfMemChannels value="1"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<ControllerCoreRefDisable value="0"/>
<ControllerCoreRGR value="1"/>
<ControllerCoreRefNumARCmdsIntREFI value="8192"/>
<!-- New commands using starndard timing values -->
<ControllerCoreRGR value="1"/>
<ControllerCoreRGRtRASBInClkCycles value="20"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="6"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="6"/>
<ControllerCoreRGRtRPBInClkCycles value="8"/>
<ControllerCoreRGRtRCBInClkCycles value="27"/>
<ControllerCoreRGRtFAWBInClkCycles value="27"/>
<!-- New commands using optimal timing values -->
<!--
<ControllerCoreRGRtRASBInClkCycles value="11"/>
<ControllerCoreRGRtRRDB_LInClkCycles value="2"/>
<ControllerCoreRGRtRRDB_SInClkCycles value="2"/>
<ControllerCoreRGRtRPBInClkCycles value="5"/>
<ControllerCoreRGRtRCBInClkCycles value="16"/>
<ControllerCoreRGRtFAWBInClkCycles value="0"/>
-->
<!-- Select the banks you want to refresh. 1: Yes, 0: No (max. 16 banks) -->
<ControllerCoreRGRB0 value="1"/>
<ControllerCoreRGRB1 value="1"/>
<ControllerCoreRGRB2 value="1"/>
<ControllerCoreRGRB3 value="1"/>
<ControllerCoreRGRB4 value="1"/>
<ControllerCoreRGRB5 value="1"/>
<ControllerCoreRGRB6 value="1"/>
<ControllerCoreRGRB7 value="1"/>
<ControllerCoreRGRB8 value="0"/>
<ControllerCoreRGRB9 value="0"/>
<ControllerCoreRGRB10 value="0"/>
<ControllerCoreRGRB11 value="0"/>
<ControllerCoreRGRB12 value="0"/>
<ControllerCoreRGRB13 value="0"/>
<ControllerCoreRGRB14 value="0"/>
<ControllerCoreRGRB15 value="0"/>
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/orgr_ddr4.json
View File

@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "orgr_ddr4"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "orgr_ddr4",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

19
DRAMSys/library/resources/configs/simulator/orgr_ddr4.xml
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@@ -1,19 +0,0 @@
<simconfig>
<SimulationName value="orgr_ddr4" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<StoreMode value="NoStorage" />
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "rgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "0"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "2147483648"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "UseMalloc": {"@value": "1"}}}
{
"simconfig": {
"AddressOffset": "2147483648",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "0",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "rgr",
"SimulationProgressBar": "1",
"StoreMode": "Store",
"ThermalSimulation": "0",
"UseMalloc": "1",
"WindowSize": "1000"
}
}

19
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.xml
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@@ -1,19 +0,0 @@
<simconfig>
<SimulationName value="rgr" />
<Debug value="0" />
<DatabaseRecording value="0" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "2147483648" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<StoreMode value="Store" />
<UseMalloc value="1" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "rgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "rgr",
"SimulationProgressBar": "1",
"StoreMode": "Store",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

19
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml
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@@ -1,19 +0,0 @@
<simconfig>
<SimulationName value="rgr" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<StoreMode value="Store" />
<UseMalloc value="0" />
</simconfig>

22
DRAMSys/library/resources/configs/simulator/rgrsimcfg.json
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@@ -1 +1,21 @@
{"simconfig": {"SimulationName": {"@value": "rgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"AddressOffset": "0",
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "4",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "rgr",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

19
DRAMSys/library/resources/configs/simulator/rgrsimcfg.xml
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@@ -1,19 +0,0 @@
<simconfig>
<SimulationName value="rgr" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value="4"/>
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<StoreMode value="NoStorage" />
<UseMalloc value="0" />
</simconfig>

17
DRAMSys/library/resources/configs/simulator/sms.json
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@@ -1 +1,16 @@
{"simconfig": {"SimulationName": {"@value": "sms"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "4"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"EnableWindowing": "1",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "4",
"PowerAnalysis": "1",
"SimulationName": "sms",
"SimulationProgressBar": "1",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

15
DRAMSys/library/resources/configs/simulator/sms.xml
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@@ -1,15 +0,0 @@
<simconfig>
<SimulationName value="sms" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="4"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<UseMalloc value="0" />
</simconfig>

21
DRAMSys/library/resources/configs/simulator/wideio.json
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@@ -1 +1,20 @@
{"simconfig": {"SimulationName": {"@value": "wideio"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "4"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": "../../DRAMSys/library/resources/error/wideio.csv"}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "4",
"PowerAnalysis": "1",
"SimulationName": "wideio",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

24
DRAMSys/library/resources/configs/simulator/wideio.xml
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@@ -1,24 +0,0 @@
<simconfig>
<SimulationName value="wideio" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="4"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/resources/error/wideio.csv" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<UseMalloc value="0" />
</simconfig>

21
DRAMSys/library/resources/configs/simulator/wideio_ecc.json
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@@ -1 +1,20 @@
{"simconfig": {"SimulationName": {"@value": "wideio_ecc"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Hamming"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": "../../DRAMSys/library/resources/error/wideio.csv"}, "StoreMode": {"@value": "ErrorModel"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Hamming",
"EnableWindowing": "1",
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "wideio_ecc",
"SimulationProgressBar": "1",
"StoreMode": "ErrorModel",
"ThermalSimulation": "0",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

24
DRAMSys/library/resources/configs/simulator/wideio_ecc.xml
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@@ -1,24 +0,0 @@
<simconfig>
<SimulationName value="wideio_ecc" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<ECCControllerMode value = "Hamming" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/resources/error/wideio.csv" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="ErrorModel" />
<UseMalloc value="0" />
</simconfig>

21
DRAMSys/library/resources/configs/simulator/wideio_thermal.json
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@@ -1 +1,20 @@
{"simconfig": {"SimulationName": {"@value": "wideio"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": "../../DRAMSys/library/resources/error/wideio.csv"}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}}
{
"simconfig": {
"CheckTLM2Protocol": "0",
"DatabaseRecording": "1",
"Debug": "0",
"ECCControllerMode": "Disabled",
"EnableWindowing": "1",
"ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
"ErrorChipSeed": "42",
"NumberOfDevicesOnDIMM": "1",
"NumberOfMemChannels": "1",
"PowerAnalysis": "1",
"SimulationName": "wideio",
"SimulationProgressBar": "1",
"StoreMode": "NoStorage",
"ThermalSimulation": "1",
"UseMalloc": "0",
"WindowSize": "1000"
}
}

24
DRAMSys/library/resources/configs/simulator/wideio_thermal.xml
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@@ -1,24 +0,0 @@
<simconfig>
<SimulationName value="wideio" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="1"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/resources/error/wideio.csv" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<UseMalloc value="0" />
</simconfig>