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amconfigs files to CONGEN/json format

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This commit is contained in:
scorrea
2020-05-13 20:07:53 +02:00
parent 720ba4e331
commit 587ecbd2a7
76 changed files with 1556 additions and 575 deletions
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42
DRAMSys/library/resources/configs/amconfigs/am_ddr3.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

6
DRAMSys/library/resources/configs/amconfigs/am_ddr3.xml
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@@ -1,6 +0,0 @@
<addressmapping>
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

37
DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json Normal file
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@@ -0,0 +1,37 @@
{
"CONGEN": {
"BANK_BIT": [
24,
25,
26
],
"COLUMN_BIT": [
0,
1,
2,
3,
4,
5,
6,
7,
8,
9
],
"ROW_BIT": [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

21
DRAMSys/library/resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml
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@@ -1,21 +0,0 @@
<!--
DDR3-SDRAM 1Gbit x8 (single device, e.g. Micron MT41J128M8) with Page Size: 1KB
Addressing:
Row addressing: 16K (A[13:0]) -> 14 bits
Bank addressing: 8 (BA[2:0]) -> 3 bits
Column addressing: 1K (A[9:0] -> 10 bits
2 2 2 | 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
6 5 4 | 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | 9 8 7 6 5 4 3 2 1 0 |
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C |
-->
<addressmapping>
<bank from="24" to="26" />
<row from="10" to="23" />
<column from="0" to="9" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

34
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml
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@@ -1,34 +0,0 @@
<!--
DDR3L Unbuffered SODIMM Information:
Part Number: M471B5674QH0-YH9/K0
Density: 2GB
Organization: 256Mx64
Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
Number of Rank: 1
Device mounted: K4B4G1646Q-HYK0
Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.
2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB
DIMM Characteristics:
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
Rows (R): 32K [13:27] (A0 - A14) -> 15 bit
Bank (B): 8 [28:30] (BA0 - BA2) -> 3 bit
3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="28" to="30" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

34
DRAMSys/library/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml
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@@ -1,34 +0,0 @@
<!--
DDR3L Unbuffered SODIMM Information:
Part Number: M471B5674QH0-YH9/K0
Density: 2GB
Organization: 256Mx64
Component Composition: 256Mx16(K4B4G1646Q-HY##)*4
Number of Rank: 1
Device mounted: K4B4G1646Q-HYK0
Original fck is 800 MHz (DDR3-1600). Adapted to fck 533 MHz (DDR-1066).
Deepak provided most of the timing and current values. For the ones not provided datasheet values were used.
2GB x64 DIMM with: 4 * 4Gb x16 devices (K4B4G1646Q-HYK0) with Page Size: 2KB
DIMM Characteristics:
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
Bank (B): 8 [13:15] (BA0 - BA2) -> 3 bit
Rows (R): 32K [16:30] (A0 - A14) -> 15 bit
3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<row from="16" to="30" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
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@@ -1,24 +0,0 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml
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@@ -1,24 +0,0 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<row from="16" to="29" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml
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@@ -1,24 +0,0 @@
<!--
DDR3 Example:
2GB x64 DIMM with: 8 * 2 Gb x8 Devices (e.g. Micron MT41J256M8) with Page Size: 1KB
Device Characteristics:
Rows: 32 K [14:0] -> 15 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
3 2 2 | 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
0 9 8 | 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="28" to="30" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

24
DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml
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@@ -1,24 +0,0 @@
<!--
DDR3 Example:
2GB x64 DIMM with: 8 * 2 Gb x8 Devices (e.g. Micron MT41J256M8) with Page Size: 1KB
Device Characteristics:
Rows: 32 K [14:0] -> 15 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
3 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 | 1 1 1
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 | 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
R R R R R R R R R R R R R R R | B B B | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<row from="16" to="30" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.json Normal file
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@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
26,
27,
28
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_brc.xml
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@@ -1,7 +0,0 @@
<addressmapping>
<bank from="26" to="28" />
<row from="13" to="25" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.json Normal file
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@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_ddr3_x16_rbc.xml
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@@ -1,7 +0,0 @@
<addressmapping>
<row from="16" to="28" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

37
DRAMSys/library/resources/configs/amconfigs/am_ddr4.json Normal file
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@@ -0,0 +1,37 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

16
DRAMSys/library/resources/configs/amconfigs/am_ddr4.xml
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@@ -1,16 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- highest bank parallelism - high hits -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<column from="9" to="18" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

42
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.xml
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@@ -1,7 +0,0 @@
<addressmapping>
<bankgroup from="30" to="31" />
<bank from="28" to="29" />
<row from="13" to="27" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

39
DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json Normal file
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@@ -0,0 +1,39 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9
],
"ROW_BIT": [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

9
DRAMSys/library/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.xml
View File

@@ -1,9 +0,0 @@
<addressmapping>
<!--channel from="30" to="32" /-->
<rank from="29" to="29" /> <!-- 2 pseudo channels -->
<bankgroup from="27" to="28" />
<bank from="25" to="26" />
<row from="10" to="24" />
<column from="3" to="9" />
<bytes from="0" to="2" />
</addressmapping>

37
DRAMSys/library/resources/configs/amconfigs/am_highHits.json Normal file
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@@ -0,0 +1,37 @@
{
"CONGEN": {
"BANK_BIT": [
15,
16,
17,
18
],
"COLUMN_BIT": [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

9
DRAMSys/library/resources/configs/amconfigs/am_highHits.xml
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@@ -1,9 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have highest hit rate, since a (row, bank) bank pair changes infrequently -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<bank from="15" to="18" />
<column from="5" to="14" />
</addressmap>
</dramconfig>

37
DRAMSys/library/resources/configs/amconfigs/am_highPara.json Normal file
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@@ -0,0 +1,37 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

10
DRAMSys/library/resources/configs/amconfigs/am_highPara.xml
View File

@@ -1,10 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have high bank parallelism with good row hit rate, since bank bits have the
highest entropy and row bits the lowest -->
<dramconfig>
<addressmap length="32">
<row from="19" to="31" />
<column from="9" to="18" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

37
DRAMSys/library/resources/configs/amconfigs/am_lowHits.json Normal file
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@@ -0,0 +1,37 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
24,
25,
26,
27,
28,
29,
30,
31
],
"ROW_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

10
DRAMSys/library/resources/configs/amconfigs/am_lowHits.xml
View File

@@ -1,10 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have high bank parallelism with a low hit rate -->
<dramconfig>
<addressmap length="32">
<column from="24" to="31" />
<row from="9" to="23" />
<bank from="5" to="8" />
</addressmap>
</dramconfig>

37
DRAMSys/library/resources/configs/amconfigs/am_lowPara.json Normal file
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@@ -0,0 +1,37 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31
],
"COLUMN_BIT": [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

12
DRAMSys/library/resources/configs/amconfigs/am_lowPara.xml
View File

@@ -1,12 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!-- should have low bank parallelism and a high hit rate -->
<dramconfig>
<addressmap length="32">
<bank from="30" to="31" />
<row from="15" to="29" />
<column from="5" to="14" />
</addressmap>
</dramconfig>

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

6
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.xml
View File

@@ -1,6 +0,0 @@
<addressmapping>
<bank from="27" to="29" />
<row from="11" to="26" />
<column from="1" to="10" />
<bytes from="0" to="0" />
</addressmapping>

6
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_8Gbx16_rbc.xml
View File

@@ -1,6 +0,0 @@
<addressmapping>
<row from="14" to="29" />
<bank from="11" to="13" />
<column from="1" to="10" />
<bytes from="0" to="0" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_ranktest.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

25
DRAMSys/library/resources/configs/amconfigs/am_ranktest.xml
View File

@@ -1,25 +0,0 @@
<!--
DDR3 Example:
1GB x64 DIMM with: 8 * 1 Gb x8 Devices (e.g. Micron MT41J128M8) with Page Size: 1KB
Device Characteristics:
Rows: 16 K [13:0] -> 14 bit
Bank: 8 [2:0] -> 3 bit
Cols: 1 K [9:0] -> 10 bit
Due to the DIMM we have a Byte Offset Y
2 2 2 | 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
9 8 7 | 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<rank from="30" to="31" />
<bank from="27" to="29" />
<row from="13" to="26" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_wideio.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

22
DRAMSys/library/resources/configs/amconfigs/am_wideio.xml
View File

@@ -1,22 +0,0 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<bank from="11" to="13" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
<!-- Bank Row Column -->
<!--
<addressmapping>
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
-->

44
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26,
27
],
"BYTE_BIT": [
0,
1,
2
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.xml
View File

@@ -1,11 +0,0 @@
<!-- Bank Row Column -->
<addressmapping>
<channel from="28" to="29" />
<bank from="25" to="27" />
<row from="12" to="24" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

44
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
12,
13,
14
],
"BYTE_BIT": [
0,
1,
2
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

11
DRAMSys/library/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.xml
View File

@@ -1,11 +0,0 @@
<!-- Row Bank Column -->
<addressmapping>
<channel from="28" to="29" />
<row from="15" to="27" />
<bank from="12" to="14" />
<column from="3" to="11" />
<bytes from="0" to="2" />
</addressmapping>
<!-- Bank Row Column -->

43
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

27
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.xml
View File

@@ -1,27 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<!--
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<colum from="4" to="10" />
<bytes from="0" to="3" />
</addressmap>
</dramconfig>
-->
<dramconfig>
<addressmap length="29">
<channel from="27" to="28" />
<row from="13" to="26" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
<!-- <channel from="27" to="28" />
<row from="14" to="26" />
<bytes from="10" to="13" />
<colum from="3" to="9" />
<bank from="0" to="2" /> -->
</addressmap>
</dramconfig>

43
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="27" to="28" />
<bank from="25" to="26" />
<row from="11" to="24" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

43
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="27" to="28" />
<row from="13" to="26" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
23,
24
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="25" to="26" />
<bank from="23" to="24" />
<row from="11" to="22" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

41
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="25" to="26" />
<row from="13" to="24" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

44
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
26,
27
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="28" to="29" />
<bank from="26" to="27" />
<row from="11" to="25" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

44
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="28" to="29" />
<row from="13" to="27" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

45
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
29,
30
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="29" to="30" />
<bank from="27" to="28" />
<row from="12" to="26" />
<column from="4" to="11" />
<bytes from="0" to="3" />
</addressmapping>

45
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
12,
13
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
29,
30
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="29" to="30" />
<row from="14" to="28" />
<bank from="12" to="13" />
<column from="4" to="11" />
<bytes from="0" to="3" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
24,
25
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
26,
27
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_brc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="26" to="27" />
<bank from="24" to="25" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

42
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
26,
27
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<channel from="26" to="27" />
<row from="13" to="25" />
<bank from="11" to="12" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>

98
DRAMSys/library/resources/configs/amconfigs/congen_extended.json
View File

@@ -1,49 +1,49 @@
{
"CONGEN": {
"XOR":[
{
"FIRST":13,
"SECOND":16
}
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANK_BIT": [
13,
14,
15
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
],
"ID": 0
}
}
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
],
"XOR": [
{
"FIRST": 13,
"SECOND": 16
}
]
}
}

36
DRAMSys/library/resources/configs/amconfigs/congen_extended.xml
View File

@@ -1,36 +0,0 @@
<?xml version="1.0" ?>
<CONGEN>
<SOLUTION ID="0">
<XOR FIRST="13" SECOND="16"/>
<BYTE_BIT>0</BYTE_BIT>
<BYTE_BIT>1</BYTE_BIT>
<BYTE_BIT>2</BYTE_BIT>
<COLUMN_BIT>3</COLUMN_BIT>
<COLUMN_BIT>4</COLUMN_BIT>
<COLUMN_BIT>5</COLUMN_BIT>
<COLUMN_BIT>6</COLUMN_BIT>
<COLUMN_BIT>7</COLUMN_BIT>
<COLUMN_BIT>8</COLUMN_BIT>
<COLUMN_BIT>9</COLUMN_BIT>
<COLUMN_BIT>10</COLUMN_BIT>
<COLUMN_BIT>11</COLUMN_BIT>
<COLUMN_BIT>12</COLUMN_BIT>
<BANK_BIT>13</BANK_BIT>
<BANK_BIT>14</BANK_BIT>
<BANK_BIT>15</BANK_BIT>
<ROW_BIT>16</ROW_BIT>
<ROW_BIT>17</ROW_BIT>
<ROW_BIT>18</ROW_BIT>
<ROW_BIT>19</ROW_BIT>
<ROW_BIT>20</ROW_BIT>
<ROW_BIT>21</ROW_BIT>
<ROW_BIT>22</ROW_BIT>
<ROW_BIT>23</ROW_BIT>
<ROW_BIT>24</ROW_BIT>
<ROW_BIT>25</ROW_BIT>
<ROW_BIT>26</ROW_BIT>
<ROW_BIT>27</ROW_BIT>
<ROW_BIT>28</ROW_BIT>
<ROW_BIT>29</ROW_BIT>
</SOLUTION>
</CONGEN>

45
DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31,
32
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

19
DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.xml
View File

@@ -1,19 +0,0 @@
<!--
DIMM Characteristics:
Bank (B): 8 [30:32] (BA0 - BA2) -> 3 bit
Rows (R): 128K [13:29] (A0 - A16) -> 17 bit
Cols (C): 1K [3:12] (A0 - A9) -> 10 bit
Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
-->
<addressmapping>
<bank from="30" to="32" />
<row from="13" to="29" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

45
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<row from="16" to="32" />
<bank from="13" to="15" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

45
DRAMSys/library/resources/configs/amconfigs/rgram.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31,
32
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

7
DRAMSys/library/resources/configs/amconfigs/rgram.xml
View File

@@ -1,7 +0,0 @@
<addressmapping>
<bank from="30" to="32" />
<row from="13" to="29" />
<column from="3" to="12" />
<bytes from="0" to="2" />
</addressmapping>

2
DRAMSys/library/resources/simulations/ddr3-example.xml
View File

@@ -1,6 +1,6 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example"></simulationid>
<simulationid id="ddr3-example-solution"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->