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Fixes phase conversions if more extended phases are declared outside of DRAMSys.

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This commit is contained in:
Lukas Steiner
2020-05-04 11:25:08 +02:00
parent 01d7beee10
commit 83f93f3620
2 changed files with 20 additions and 20 deletions
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32
DRAMSys/library/src/controller/Command.cpp
View File

@@ -43,7 +43,7 @@ using namespace DRAMPower;
std::string commandToString(Command command)
{
assert(command >= 0 && command <= 15);
assert(command >= Command::NOP && command <= Command::SREFEX);
static std::array<std::string, 16> stringOfCommand =
{"NOP",
"RD",
@@ -71,7 +71,7 @@ unsigned numberOfCommands()
tlm_phase commandToPhase(Command command)
{
assert(command >= 0 && command <= 15);
assert(command >= Command::NOP && command <= Command::SREFEX);
static std::array<tlm_phase, 16> phaseOfCommand =
{UNINITIALIZED_PHASE,
BEGIN_RD,
@@ -94,7 +94,7 @@ tlm_phase commandToPhase(Command command)
Command phaseToCommand(tlm_phase phase)
{
assert(phase >= 5 && phase <= 19);
assert(phase >= BEGIN_RD && phase <= END_SREF);
static std::array<Command, 16> commandOfPhase =
{Command::RD,
Command::WR,
@@ -111,12 +111,12 @@ Command phaseToCommand(tlm_phase phase)
Command::PDXP,
Command::SREFEN,
Command::SREFEX};
return commandOfPhase[phase - 5];
return commandOfPhase[phase - BEGIN_RD];
}
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
{
assert(phase >= 5 && phase <= 19);
assert(phase >= BEGIN_RD && phase <= END_SREF);
static std::array<MemCommand::cmds, 16> phaseOfCommand =
{MemCommand::RD,
MemCommand::WR,
@@ -133,40 +133,40 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
MemCommand::PUP_PRE,
MemCommand::SREN,
MemCommand::SREX};
return phaseOfCommand[phase - 5];
return phaseOfCommand[phase - BEGIN_RD];
}
bool phaseNeedsEnd(tlm_phase phase)
{
return (phase >= 5 && phase <= 13);
return (phase >= BEGIN_RD && phase <= BEGIN_REFA);
}
tlm_phase getEndPhase(tlm_phase phase)
{
assert(phase >= 5 && phase <= 13);
assert(phase >= BEGIN_RD && phase <= BEGIN_REFA);
return (phase + 15);
}
bool isBankCommand(Command command)
{
assert(command >= 0 && command <= 15);
return (command <= 7);
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command <= Command::REFB);
}
bool isRankCommand(Command command)
{
assert(command >= 0 && command <= 15);
return (command >= 8);
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command >= Command::PREA);
}
bool isCasCommand(Command command)
{
assert(command >= 0 && command <= 15);
return (command <= 4);
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command <= Command::WRA);
}
bool isRasCommand(Command command)
{
assert(command >= 0 && command <= 15);
return (command >= 5);
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command >= Command::PRE);
}

8
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -44,11 +44,11 @@ tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
return Controller::nb_transport_fw(trans, phase, delay);
}
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
tlm_sync_enum ControllerRecordable::nb_transport_bw(tlm_generic_payload &,
tlm_phase &, sc_time &)
{
recordPhase(trans, phase, delay);
return Controller::nb_transport_bw(trans, phase, delay);
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called");
return TLM_ACCEPTED;
}
void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase)