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Merge branch 'database_fixes_2' into 'develop'

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Database fixes and improvements

See merge request ems/astdm/dram.sys!288
This commit is contained in:
Lukas Steiner
2021-06-01 13:08:39 +00:00
parent d023ebf128 486b37a3ec
commit 8275fb26f3
23 changed files with 311 additions and 286 deletions
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207
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -42,15 +42,18 @@
#include "TlmRecorder.h"
#include "dramExtensions.h"
#include "../configuration/Configuration.h"
#include "../controller/Command.h"
using namespace tlm;
TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) :
name(name), totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME)
name(name), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME)
{
recordedData.reserve(transactionCommitRate);
setUpTransactionTerminatingPhases();
currentDataBuffer = &recordingDataBuffer[0];
storageDataBuffer = &recordingDataBuffer[1];
currentDataBuffer->reserve(transactionCommitRate);
storageDataBuffer->reserve(transactionCommitRate);
openDB(dbName);
char *sErrMsg;
sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg);
@@ -111,27 +114,31 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth)
void TlmRecorder::recordPhase(tlm_generic_payload &trans,
tlm_phase phase, const sc_time &time)
{
if (currentTransactionsInSystem.count(&trans) == 0)
if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end())
introduceTransactionSystem(trans);
std::string phaseName = getPhaseName(phase);
std::string phaseBeginPrefix = "BEGIN_";
std::string phaseEndPrefix = "END_";
if (phaseName.find(phaseBeginPrefix) != std::string::npos) {
phaseName.erase(0, phaseBeginPrefix.length());
assert(currentTransactionsInSystem.count(&trans) != 0);
currentTransactionsInSystem[&trans].insertPhase(phaseName, time);
} else {
phaseName.erase(0, phaseEndPrefix.length());
assert(currentTransactionsInSystem.count(&trans) != 0);
currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time);
if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA)
{
assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem[&trans].recordedPhases.back().name);
currentTransactionsInSystem[&trans].recordedPhases.back().interval.end = time;
}
else
{
std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"
currentTransactionsInSystem[&trans].recordedPhases.emplace_back(phaseName, time);
}
bool phaseTerminatesTransaction = std::count(transactionTerminatingPhases.begin(),
transactionTerminatingPhases.end(), phase) == 1;
if (phaseTerminatesTransaction)
removeTransactionFromSystem(trans);
if (currentTransactionsInSystem[&trans].cmd == 'X')
{
if (phase == END_REFA || phase == END_REFB || phase == END_REFSB
|| phase == END_PDNA || phase == END_PDNP || phase == END_SREF)
removeTransactionFromSystem(trans);
}
else
{
if (phase == END_RESP)
removeTransactionFromSystem(trans);
}
simulationTimeCoveredByRecording = time;
}
@@ -156,24 +163,22 @@ void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time &
void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans)
{
uint64_t id = totalNumTransactions++;
currentTransactionsInSystem[&trans].id = id;
currentTransactionsInSystem[&trans].cmd = trans.get_command() ==
tlm::TLM_READ_COMMAND ? "R" : "W";
totalNumTransactions++;
currentTransactionsInSystem[&trans].id = totalNumTransactions;
tlm_command command = trans.get_command();
if (command == TLM_READ_COMMAND)
currentTransactionsInSystem[&trans].cmd = 'R';
else if (command == TLM_WRITE_COMMAND)
currentTransactionsInSystem[&trans].cmd = 'W';
else
currentTransactionsInSystem[&trans].cmd = 'X';
currentTransactionsInSystem[&trans].address = trans.get_address();
currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans);
currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans);
currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getTimeOfGeneration(trans);
PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(id) + " generation time " +
PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " +
currentTransactionsInSystem[&trans].timeOfGeneration.to_string());
if (id % transactionCommitRate == 0)
{
PRINTDEBUGMESSAGE(name, "Committing transactions " +
std::to_string(id - transactionCommitRate + 1) + " - " + std::to_string(id));
commitRecordedDataToDB();
}
}
void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans)
@@ -184,14 +189,48 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans)
std::to_string(currentTransactionsInSystem[&trans].id));
Transaction &recordingData = currentTransactionsInSystem[&trans];
recordedData.push_back(recordingData);
currentDataBuffer->push_back(recordingData);
currentTransactionsInSystem.erase(&trans);
if (currentDataBuffer->size() == transactionCommitRate)
{
if (storageThread.joinable())
storageThread.join();
std::swap(currentDataBuffer, storageDataBuffer);
storageThread = std::thread(&TlmRecorder::commitRecordedDataToDB, this);
currentDataBuffer->clear();
}
}
void TlmRecorder::terminateRemainingTransactions()
{
while (!currentTransactionsInSystem.empty())
{
auto transaction = currentTransactionsInSystem.begin();
if (transaction->second.cmd == 'X')
{
std::string beginPhase = transaction->second.recordedPhases.front().name;
if (beginPhase == "PDNA")
recordPhase(*(transaction->first), END_PDNA, sc_time_stamp());
else if (beginPhase == "PDNP")
recordPhase(*(transaction->first), END_PDNP, sc_time_stamp());
else if (beginPhase == "SREF")
recordPhase(*(transaction->first), END_SREF, sc_time_stamp());
else
removeTransactionFromSystem(*transaction->first);
}
else
recordPhase(*(transaction->first), END_RESP, sc_time_stamp());
}
}
void TlmRecorder::commitRecordedDataToDB()
{
sqlite3_exec(db, "BEGIN;", nullptr, nullptr, nullptr);
for (Transaction &recordingData : recordedData)
for (Transaction &recordingData : *storageDataBuffer)
{
assert(!recordingData.recordedPhases.empty());
insertTransactionInDB(recordingData);
@@ -211,31 +250,6 @@ void TlmRecorder::commitRecordedDataToDB()
}
sqlite3_exec(db, "COMMIT;", nullptr, nullptr, nullptr);
recordedData.clear();
}
void TlmRecorder::Transaction::insertPhase(const std::string &phaseName, const sc_time &begin)
{
recordedPhases.emplace_back(phaseName, begin);
}
void TlmRecorder::Transaction::setPhaseEnd(const std::string &phaseName, const sc_time &end)
{
// Find the latest recorder phase for that transaction with a matching phaseName and update it
// Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD)
// only update the latest one that has been recorded
for (size_t i = recordedPhases.size(); i > 0; i--)
{
Phase &data = recordedPhases[i - 1];
if (data.name == phaseName)
{
data.interval.end = end;
return;
}
}
SC_REPORT_FATAL("Recording Error",
"While trying to set phase end: phaseBegin has not been recorded");
}
void TlmRecorder::openDB(const std::string &dbName)
@@ -245,7 +259,7 @@ void TlmRecorder::openDB(const std::string &dbName)
{
if (remove(dbName.c_str()) != 0)
{
SC_REPORT_FATAL("TlmRecorder", "Error deleting file" );
SC_REPORT_FATAL("TlmRecorder", "Error deleting file");
}
}
@@ -256,55 +270,36 @@ void TlmRecorder::openDB(const std::string &dbName)
}
}
void TlmRecorder::setUpTransactionTerminatingPhases()
{
transactionTerminatingPhases.push_back(END_RESP);
// Refresh All
transactionTerminatingPhases.push_back(END_REFA);
// Refresh Bank
transactionTerminatingPhases.push_back(END_REFB);
// Refresh Same Bank
transactionTerminatingPhases.push_back(END_REFSB);
// Phases for Power Down
transactionTerminatingPhases.push_back(END_PDNA);
transactionTerminatingPhases.push_back(END_PDNP);
transactionTerminatingPhases.push_back(END_SREF);
}
void TlmRecorder::prepareSqlStatements()
{
insertTransactionString =
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank,"
":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)";
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank,"
":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)";
insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)";
updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id";
updateDataStrobeString =
"UPDATE Transactions SET DataStrobeBegin = :begin, DataStrobeEnd = :end WHERE ID = :id";
"UPDATE Transactions SET DataStrobeBegin = :begin, DataStrobeEnd = :end WHERE ID = :id";
insertPhaseString =
"INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Transact) VALUES (:name,:begin,:end,:transaction)";
"INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Transact) VALUES (:name,:begin,:end,:transaction)";
updatePhaseString =
"UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name";
"UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name";
insertGeneralInfoString =
"INSERT INTO GeneralInfo VALUES"
"(:numberOfTransactions,:end,:numberOfRanks,:numberOfBankgroups,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,"
":traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread, :maxBufferDepth)";
"INSERT INTO GeneralInfo VALUES"
"(:numberOfTransactions,:end,:numberOfRanks,:numberOfBankgroups,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec,"
":traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread, :maxBufferDepth)";
insertCommandLengthsString =
"INSERT INTO CommandLengths VALUES"
"(:NOP, :RD, :WR, :RDA, :WRA, :ACT, :PRE, :REFB, :PRESB, :REFSB, :PREA, :REFA, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)";
"INSERT INTO CommandLengths VALUES"
"(:NOP, :RD, :WR, :RDA, :WRA, :ACT, :PRE, :REFB, :PRESB, :REFSB, :PREA, :REFA, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)";
insertDebugMessageString =
"INSERT INTO DebugMessages (Time,Message) Values (:time,:message)";
"INSERT INTO DebugMessages (Time,Message) Values (:time,:message)";
insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)";
insertBufferDepthString = "INSERT INTO BufferDepth VALUES (:time,:bufferNumber,:averageBufferDepth)";
@@ -333,7 +328,7 @@ void TlmRecorder::insertDebugMessageInDB(const std::string &message, const sc_ti
void TlmRecorder::insertGeneralInfo()
{
sqlite3_bind_int64(insertGeneralInfoStatement, 1, static_cast<int64_t>(totalNumTransactions - 1));
sqlite3_bind_int64(insertGeneralInfoStatement, 1, static_cast<int64_t>(totalNumTransactions));
sqlite3_bind_int64(insertGeneralInfoStatement, 2, static_cast<int64_t>(simulationTimeCoveredByRecording.value()));
sqlite3_bind_int(insertGeneralInfoStatement, 3, static_cast<int>(Configuration::getInstance().memSpec->numberOfRanks));
sqlite3_bind_int(insertGeneralInfoStatement, 4, static_cast<int>(Configuration::getInstance().memSpec->numberOfBankGroups));
@@ -347,18 +342,18 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 11, 0);
else
sqlite3_bind_int64(insertGeneralInfoStatement, 11,
static_cast<int64_t>((Configuration::getInstance().memSpec->tCK *
Configuration::getInstance().windowSize).value()));
static_cast<int64_t>((Configuration::getInstance().memSpec->tCK *
Configuration::getInstance().windowSize).value()));
if ((Configuration::getInstance().refreshMaxPostponed > 0)
|| (Configuration::getInstance().refreshMaxPulledin > 0))
|| (Configuration::getInstance().refreshMaxPulledin > 0))
{
sqlite3_bind_int(insertGeneralInfoStatement, 12, 1);
sqlite3_bind_int(insertGeneralInfoStatement, 13,
static_cast<int>(std::max(Configuration::getInstance().refreshMaxPostponed,
Configuration::getInstance().refreshMaxPulledin)));
}
else
static_cast<int>(std::max(Configuration::getInstance().refreshMaxPostponed,
Configuration::getInstance().refreshMaxPulledin)));
}
else
{
sqlite3_bind_int(insertGeneralInfoStatement, 12, 0);
sqlite3_bind_int(insertGeneralInfoStatement, 13, 0);
@@ -421,7 +416,7 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData)
sqlite3_bind_int64(insertTransactionStatement, 14,
static_cast<int64_t>(recordingData.timeOfGeneration.value()));
sqlite3_bind_text(insertTransactionStatement, 15,
recordingData.cmd.c_str(), static_cast<int>(recordingData.cmd.length()), nullptr);
&recordingData.cmd, 1, nullptr);
executeSqlStatement(insertTransactionStatement);
}
@@ -453,7 +448,7 @@ void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement)
int errorCode = sqlite3_step(statement);
if (errorCode != SQLITE_DONE)
SC_REPORT_FATAL("Error in TraceRecorder",
(std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)).c_str());
(std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)).c_str());
sqlite3_reset(statement);
}
@@ -474,11 +469,15 @@ void TlmRecorder::executeInitialSqlCommand()
void TlmRecorder::closeConnection()
{
terminateRemainingTransactions();
if (storageThread.joinable())
storageThread.join();
std::swap(currentDataBuffer, storageDataBuffer);
commitRecordedDataToDB();
insertGeneralInfo();
insertCommandLengths();
PRINTDEBUGMESSAGE(name, "Number of transactions written to DB: "
+ std::to_string(totalNumTransactions - 1));
+ std::to_string(totalNumTransactions));
PRINTDEBUGMESSAGE(name, "tlmPhaseRecorder:\tEnd Recording");
sqlite3_close(db);
db = nullptr;

38
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -42,10 +42,11 @@
#include <iostream>
#include <ostream>
#include <string>
#include <map>
#include <unordered_map>
#include <algorithm>
#include <fstream>
#include <cerrno>
#include <thread>
#include <tlm.h>
#include <systemc.h>
#include "sqlite3.h"
@@ -55,8 +56,6 @@
class TlmRecorder
{
public:
std::string sqlScriptURI;
TlmRecorder(const std::string &name, const std::string &dbName);
~TlmRecorder();
@@ -92,7 +91,7 @@ private:
uint64_t id;
uint64_t address;
unsigned int burstLength;
std::string cmd;
char cmd;
DramExtension dramExtension;
sc_time timeOfGeneration;
TimeInterval timeOnDataStrobe;
@@ -104,9 +103,6 @@ private:
TimeInterval interval;
};
std::vector<Phase> recordedPhases;
void insertPhase(const std::string &phaseName, const sc_time &begin);
void setPhaseEnd(const std::string &phaseName, const sc_time &end);
};
std::string name;
@@ -118,11 +114,11 @@ private:
static void executeSqlStatement(sqlite3_stmt *statement);
void openDB(const std::string &dbName);
void setUpTransactionTerminatingPhases();
void introduceTransactionSystem(tlm::tlm_generic_payload &trans);
void removeTransactionFromSystem(tlm::tlm_generic_payload &trans);
void terminateRemainingTransactions();
void commitRecordedDataToDB();
void insertGeneralInfo();
void insertCommandLengths();
@@ -132,24 +128,27 @@ private:
uint64_t transactionID);
void insertDebugMessageInDB(const std::string &message, const sc_time &time);
static const int transactionCommitRate = 1000;
std::vector<Transaction> recordedData;
std::map<tlm::tlm_generic_payload *, Transaction> currentTransactionsInSystem;
static constexpr unsigned transactionCommitRate = 8192;
std::array<std::vector<Transaction>, 2> recordingDataBuffer;
std::vector<Transaction> *currentDataBuffer;
std::vector<Transaction> *storageDataBuffer;
std::thread storageThread;
std::unordered_map<tlm::tlm_generic_payload *, Transaction> currentTransactionsInSystem;
uint64_t totalNumTransactions;
sc_time simulationTimeCoveredByRecording;
std::vector<tlm::tlm_phase> transactionTerminatingPhases;
sqlite3 *db = nullptr;
sqlite3_stmt *insertTransactionStatement, *insertRangeStatement,
*updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement,
*insertGeneralInfoStatement, *insertCommandLengthsStatement,
*insertDebugMessageStatement, *updateDataStrobeStatement,
*insertPowerStatement, *insertBufferDepthStatement, *insertBandwidthStatement;
*updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement,
*insertGeneralInfoStatement, *insertCommandLengthsStatement,
*insertDebugMessageStatement, *updateDataStrobeStatement,
*insertPowerStatement, *insertBufferDepthStatement, *insertBandwidthStatement;
std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString,
updatePhaseString, insertGeneralInfoString, insertCommandLengthsString,
insertDebugMessageString, updateDataStrobeString, insertPowerString,
insertBufferDepthString, insertBandwidthString;
updatePhaseString, insertGeneralInfoString, insertCommandLengthsString,
insertDebugMessageString, updateDataStrobeString, insertPowerString,
insertBufferDepthString, insertBandwidthString;
std::string initialCommand =
"DROP TABLE IF EXISTS Phases; \n"
@@ -266,4 +265,3 @@ private:
};
#endif // TLMRECORDER_H

2
DRAMSys/library/src/common/utils.cpp
View File

@@ -142,7 +142,7 @@ std::string parseString(json &obj, const std::string &name)
void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank)
{
payload.set_address(bank.getStartAddress());
payload.set_command(TLM_READ_COMMAND);
payload.set_command(TLM_IGNORE_COMMAND);
payload.set_data_length(0);
payload.set_response_status(TLM_OK_RESPONSE);
payload.set_dmi_allowed(false);

2
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -70,7 +70,7 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType,
memoryType(memoryType),
burstDuration(tCK * (burstLength / dataRate))
{
commandLengthInCycles = std::vector<unsigned>(numberOfCommands(), 1);
commandLengthInCycles = std::vector<unsigned>(Command::numberOfCommands(), 1);
}
sc_time MemSpec::getCommandLength(Command command) const

108
DRAMSys/library/src/controller/Command.cpp
View File

@@ -41,9 +41,35 @@
using namespace tlm;
using namespace DRAMPower;
std::string commandToString(Command command)
{
assert(command >= Command::NOP && command <= Command::SREFEX);
Command::Command(Command::Type type) : type(type) {}
Command::Command(tlm_phase phase)
{
assert(phase >= BEGIN_RD && phase <= END_SREF);
static constexpr std::array<Command::Type, 18> commandOfPhase =
{Command::RD,
Command::WR,
Command::RDA,
Command::WRA,
Command::ACT,
Command::PRE,
Command::REFB,
Command::PRESB,
Command::REFSB,
Command::PREA,
Command::REFA,
Command::PDEA,
Command::PDEP,
Command::SREFEN,
Command::PDXA,
Command::PDXP,
Command::SREFEX};
type = commandOfPhase[phase - BEGIN_RD];
}
std::string Command::toString() const
{
assert(type >= Command::NOP && type <= Command::SREFEX);
static std::array<std::string, 18> stringOfCommand =
{"NOP",
"RD",
@@ -58,22 +84,22 @@ std::string commandToString(Command command)
"PREA",
"REFA",
"PDEA",
"PDXA",
"PDEP",
"PDXP",
"SREFEN",
"PDXA",
"PDXP",
"SREFEX"};
return stringOfCommand[command];
return stringOfCommand[type];
}
unsigned numberOfCommands()
unsigned Command::numberOfCommands()
{
return 18;
}
tlm_phase commandToPhase(Command command)
tlm_phase Command::toPhase() const
{
assert(command >= Command::NOP && command <= Command::SREFEX);
assert(type >= Command::NOP && type <= Command::SREFEX);
static std::array<tlm_phase, 18> phaseOfCommand =
{UNINITIALIZED_PHASE,
BEGIN_RD,
@@ -88,36 +114,12 @@ tlm_phase commandToPhase(Command command)
BEGIN_PREA,
BEGIN_REFA,
BEGIN_PDNA,
END_PDNA,
BEGIN_PDNP,
END_PDNP,
BEGIN_SREF,
END_PDNA,
END_PDNP,
END_SREF};
return phaseOfCommand[command];
}
Command phaseToCommand(tlm_phase phase)
{
assert(phase >= BEGIN_RD && phase <= END_SREF);
static std::array<Command, 18> commandOfPhase =
{Command::RD,
Command::WR,
Command::RDA,
Command::WRA,
Command::ACT,
Command::PRE,
Command::REFB,
Command::PRESB,
Command::REFSB,
Command::PREA,
Command::REFA,
Command::PDEA,
Command::PDXA,
Command::PDEP,
Command::PDXP,
Command::SREFEN,
Command::SREFEX};
return commandOfPhase[phase - BEGIN_RD];
return phaseOfCommand[type];
}
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
@@ -137,10 +139,10 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
MemCommand::PREA,
MemCommand::REF,
MemCommand::PDN_S_ACT,
MemCommand::PUP_ACT,
MemCommand::PDN_S_PRE,
MemCommand::PUP_PRE,
MemCommand::SREN,
MemCommand::PUP_ACT,
MemCommand::PUP_PRE,
MemCommand::SREX};
return phaseOfCommand[phase - BEGIN_RD];
}
@@ -156,32 +158,32 @@ tlm_phase getEndPhase(tlm_phase phase)
return (phase + 17);
}
bool isBankCommand(Command command)
bool Command::isBankCommand() const
{
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command <= Command::REFB);
assert(type >= Command::NOP && type <= Command::SREFEX);
return (type <= Command::REFB);
}
bool isGroupCommand(Command command)
bool Command::isGroupCommand() const
{
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command >= Command::PRESB && command <= Command::REFSB);
assert(type >= Command::NOP && type <= Command::SREFEX);
return (type >= Command::PRESB && type <= Command::REFSB);
}
bool isRankCommand(Command command)
bool Command::isRankCommand() const
{
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command >= Command::PREA);
assert(type >= Command::NOP && type <= Command::SREFEX);
return (type >= Command::PREA);
}
bool isCasCommand(Command command)
bool Command::isCasCommand() const
{
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command <= Command::WRA);
assert(type >= Command::NOP && type <= Command::SREFEX);
return (type <= Command::WRA);
}
bool isRasCommand(Command command)
bool Command::isRasCommand() const
{
assert(command >= Command::NOP && command <= Command::SREFEX);
return (command >= Command::ACT);
assert(type >= Command::NOP && type <= Command::SREFEX);
return (type >= Command::ACT);
}

94
DRAMSys/library/src/controller/Command.h
View File

@@ -46,6 +46,12 @@
#include "../common/third_party/DRAMPower/src/MemCommand.h"
// DO NOT CHANGE THE ORDER!
// BEGIN_REQ // 1
// END_REQ // 2
// BEGIN_RESP // 3
// END_RESP // 4
DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5
DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6
DECLARE_EXTENDED_PHASE(BEGIN_RDA); // 7
@@ -58,10 +64,11 @@ DECLARE_EXTENDED_PHASE(BEGIN_REFSB); // 13
DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 14
DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 15
DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 16
DECLARE_EXTENDED_PHASE(END_PDNA); // 17
DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 18
DECLARE_EXTENDED_PHASE(END_PDNP); // 19
DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 20
DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 17
DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18
DECLARE_EXTENDED_PHASE(END_PDNA); // 19
DECLARE_EXTENDED_PHASE(END_PDNP); // 20
DECLARE_EXTENDED_PHASE(END_SREF); // 21
DECLARE_EXTENDED_PHASE(END_RD); // 22
@@ -76,45 +83,62 @@ DECLARE_EXTENDED_PHASE(END_REFSB); // 30
DECLARE_EXTENDED_PHASE(END_PREA); // 31
DECLARE_EXTENDED_PHASE(END_REFA); // 32
enum Command
class Command
{
NOP,
RD,
WR,
RDA,
WRA,
ACT,
PRE,
REFB,
PRESB,
REFSB,
PREA,
REFA,
PDEA,
PDXA,
PDEP,
PDXP,
SREFEN,
SREFEX
public:
enum Type : uint8_t
{
NOP, // 0
RD, // 1
WR, // 2
RDA, // 3
WRA, // 4
ACT, // 5
PRE, // 6
REFB, // 7
PRESB, // 8
REFSB, // 9
PREA, // 10
REFA, // 11
PDEA, // 12
PDEP, // 13
SREFEN, // 14
PDXA, // 15
PDXP, // 16
SREFEX // 17
};
private:
Type type;
public:
Command() = default;
Command(Type type);
Command(tlm::tlm_phase phase);
std::string toString() const;
tlm::tlm_phase toPhase() const;
static unsigned numberOfCommands();
bool isBankCommand() const;
bool isGroupCommand() const;
bool isRankCommand() const;
bool isCasCommand() const;
bool isRasCommand() const;
constexpr operator uint8_t() const
{
return type;
}
};
std::string commandToString(Command);
tlm::tlm_phase commandToPhase(Command);
Command phaseToCommand(tlm::tlm_phase);
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
bool phaseNeedsEnd(tlm::tlm_phase);
tlm::tlm_phase getEndPhase(tlm::tlm_phase);
unsigned numberOfCommands();
bool isBankCommand(Command);
bool isGroupCommand(Command);
bool isRankCommand(Command);
bool isCasCommand(Command);
bool isRasCommand(Command);
struct CommandTuple
{
struct CommandTuple
{
using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_time>;
enum Accessor
enum Accessor
{
Command = 0,
Payload = 1,

8
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -293,12 +293,12 @@ void Controller::controllerMethod()
Bank bank = DramExtension::getBank(payload);
unsigned burstLength = DramExtension::getBurstLength(payload);
if (isRankCommand(command))
if (command.isRankCommand())
{
for (auto it : bankMachinesOnRank[rank.ID()])
it->updateState(command);
}
else if (isGroupCommand(command))
else if (command.isGroupCommand())
{
for (unsigned bankID = (bank.ID() % memSpec->banksPerGroup);
bankID < memSpec->banksPerRank; bankID += memSpec->banksPerGroup)
@@ -311,7 +311,7 @@ void Controller::controllerMethod()
powerDownManagers[rank.ID()]->updateState(command);
checker->insert(command, payload);
if (isCasCommand(command))
if (command.isCasCommand())
{
scheduler->removeRequest(payload);
manageRequests(thinkDelayFw);
@@ -499,6 +499,6 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase, s
void Controller::sendToDram(Command command, tlm_generic_payload *payload, sc_time delay)
{
tlm_phase phase = commandToPhase(command);
tlm_phase phase = command.toPhase();
iSocket->nb_transport_fw(*payload, phase, delay);
}

4
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -73,13 +73,13 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phas
void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload, sc_time delay)
{
if (isCasCommand(command))
if (command.isCasCommand())
{
TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, *payload);
tlmRecorder->updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start,
sc_time_stamp() + delay + dataStrobe.end, *payload);
}
tlm_phase phase = commandToPhase(command);
tlm_phase phase = command.toPhase();
iSocket->nb_transport_fw(*payload, phase, delay);
}

8
DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
View File

@@ -44,10 +44,10 @@ CheckerDDR3::CheckerDDR3()
SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -423,7 +423,7 @@ void CheckerDDR3::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();

10
DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
View File

@@ -44,12 +44,12 @@ CheckerDDR4::CheckerDDR4()
SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -456,7 +456,7 @@ void CheckerDDR4::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();

18
DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
View File

@@ -44,18 +44,18 @@ CheckerDDR5::CheckerDDR5()
SC_REPORT_FATAL("CheckerDDR5", "Wrong MemSpec chosen");
lastScheduledByCommandAndDimmRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfDIMMRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfDIMMRanks, sc_max_time()));
lastScheduledByCommandAndPhysicalRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfPhysicalRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfPhysicalRanks, sc_max_time()));
lastScheduledByCommandAndLogicalRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfLogicalRanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfLogicalRanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
// Required for Same Bank Refresh
lastScheduledByCommandAndBankInGroup = std::vector<std::vector<sc_time>>(numberOfCommands(),
lastScheduledByCommandAndBankInGroup = std::vector<std::vector<sc_time>>(Command::numberOfCommands(),
std::vector<sc_time>(memSpec->numberOfRanks * memSpec->banksPerGroup, sc_max_time()));
lastCommandOnBus = sc_max_time();
dummyCommandOnBus.start = sc_max_time();
@@ -827,7 +827,7 @@ void CheckerDDR5::insert(Command command, tlm_generic_payload *payload)
unsigned burstLength = DramExtension::getBurstLength(payload);
PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndDimmRank[command][dimmRank.ID()] = sc_time_stamp();
lastScheduledByCommandAndPhysicalRank[command][physicalRank.ID()] = sc_time_stamp();
@@ -837,7 +837,7 @@ void CheckerDDR5::insert(Command command, tlm_generic_payload *payload)
lastScheduledByCommand[command] = sc_time_stamp();
lastScheduledByCommandAndBankInGroup[command][bankInGroup.ID()] = sc_time_stamp();
if (isCasCommand(command))
if (command.isCasCommand())
{
lastBurstLengthByCommandAndDimmRank[command][dimmRank.ID()] = burstLength;
lastBurstLengthByCommandAndPhysicalRank[command][physicalRank.ID()] = burstLength;

10
DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
View File

@@ -44,12 +44,12 @@ CheckerGDDR5::CheckerGDDR5()
SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last32Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -538,7 +538,7 @@ void CheckerGDDR5::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();

10
DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
View File

@@ -44,12 +44,12 @@ CheckerGDDR5X::CheckerGDDR5X()
SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
last32Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -538,7 +538,7 @@ void CheckerGDDR5X::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();

10
DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
View File

@@ -44,12 +44,12 @@ CheckerGDDR6::CheckerGDDR6()
SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -559,7 +559,7 @@ void CheckerGDDR6::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();

14
DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
View File

@@ -44,12 +44,12 @@ CheckerHBM2::CheckerHBM2()
SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnRasBus = sc_max_time();
lastCommandOnCasBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -492,7 +492,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_paylo
else
SC_REPORT_FATAL("CheckerHBM2", "Unknown command!");
if (isRasCommand(command))
if (command.isRasCommand())
{
if (lastCommandOnRasBus != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
@@ -513,14 +513,14 @@ void CheckerHBM2::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommand[command] = sc_time_stamp();
if (isCasCommand(command))
if (command.isCasCommand())
lastCommandOnCasBus = sc_time_stamp();
else if (command == Command::ACT)
lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK;

8
DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
View File

@@ -44,10 +44,10 @@ CheckerLPDDR4::CheckerLPDDR4()
SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -507,7 +507,7 @@ void CheckerLPDDR4::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();

8
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp
View File

@@ -44,10 +44,10 @@ CheckerSTTMRAM::CheckerSTTMRAM()
SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -379,7 +379,7 @@ void CheckerSTTMRAM::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();

8
DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
View File

@@ -44,10 +44,10 @@ CheckerWideIO::CheckerWideIO()
SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last2Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -396,7 +396,7 @@ void CheckerWideIO::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();

8
DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
View File

@@ -44,10 +44,10 @@ CheckerWideIO2::CheckerWideIO2()
SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands(), sc_max_time());
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
@@ -474,7 +474,7 @@ void CheckerWideIO2::insert(Command command, tlm_generic_payload *payload)
Bank bank = DramExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + commandToString(command));
+ " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();

2
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -89,7 +89,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC
for (auto it : readyCommands)
{
if (isRasCommand(std::get<CommandTuple::Command>(it)))
if (std::get<CommandTuple::Command>(it).isRasCommand())
readyRasCommands.emplace_back(it);
else
readyCasCommands.emplace_back(it);

10
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -56,7 +56,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
if (newTimestamp < lastTimestamp)
{
if (isRasCommand(std::get<CommandTuple::Command>(*it)) || newPayloadID == nextPayloadID)
if (std::get<CommandTuple::Command>(*it).isRasCommand() || newPayloadID == nextPayloadID)
{
lastTimestamp = newTimestamp;
lastPayloadID = newPayloadID;
@@ -65,7 +65,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
}
else if ((newTimestamp == lastTimestamp) && (newPayloadID < lastPayloadID))
{
if (isRasCommand(std::get<CommandTuple::Command>(*it)) || newPayloadID == nextPayloadID)
if (std::get<CommandTuple::Command>(*it).isRasCommand() || newPayloadID == nextPayloadID)
{
lastPayloadID = newPayloadID;
result = it;
@@ -76,7 +76,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
if (result != readyCommands.cend() &&
std::get<CommandTuple::Timestamp>(*result) == sc_time_stamp())
{
if (isCasCommand(std::get<CommandTuple::Command>(*result)))
if (std::get<CommandTuple::Command>(*result).isCasCommand())
nextPayloadID++;
return *result;
}
@@ -99,7 +99,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
for (auto it : readyCommands)
{
if (isRasCommand(std::get<CommandTuple::Command>(it)))
if (std::get<CommandTuple::Command>(it).isRasCommand())
readyRasCommands.emplace_back(it);
else
readyCasCommands.emplace_back(it);
@@ -175,7 +175,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
if (result != readyCommands.cend() &&
std::get<CommandTuple::Timestamp>(*result) == sc_time_stamp())
{
if (isCasCommand(std::get<CommandTuple::Command>(*result)))
if (std::get<CommandTuple::Command>(*result).isCasCommand())
nextPayloadID++;
return *result;
}

4
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -88,7 +88,7 @@ void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase
// These are terminating phases recorded by the DRAM. The execution
// time of the related command must be taken into consideration.
if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF)
recTime += this->memSpec->getCommandLength(phaseToCommand(phase));
recTime += this->memSpec->getCommandLength(Command(phase));
NDEBUG_UNUSED(unsigned thr) = DramExtension::getExtension(trans).getThread().ID();
NDEBUG_UNUSED(unsigned ch) = DramExtension::getExtension(trans).getChannel().ID();
@@ -106,7 +106,7 @@ void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase
if (phaseNeedsEnd(phase))
{
recTime += this->memSpec->getExecutionTime(phaseToCommand(phase), trans);
recTime += this->memSpec->getExecutionTime(Command(phase), trans);
tlmRecorder->recordPhase(trans, getEndPhase(phase), recTime);
}

6
DRAMSys/simulator/StlPlayer.cpp
View File

@@ -50,9 +50,11 @@ StlPlayer::StlPlayer(const sc_module_name &name,
TraceSetup *setup,
bool relative) :
TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests),
file(pathToTrace), currentBuffer(&lineContents[0]), parseBuffer(&lineContents[1]),
relative(relative), playerClk(playerClk)
file(pathToTrace), relative(relative), playerClk(playerClk)
{
currentBuffer = &lineContents[0];
parseBuffer = &lineContents[1];
if (!file.is_open())
SC_REPORT_FATAL("StlPlayer", (std::string("Could not open trace ") + pathToTrace).c_str());
else