From 834e10efde493b7a84068e4aa33ce756e59a42bf Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Fri, 28 May 2021 16:01:22 +0200 Subject: [PATCH 1/6] Code refactoring. --- DRAMSys/library/src/common/TlmRecorder.cpp | 28 ++++++++++++---------- DRAMSys/library/src/common/TlmRecorder.h | 4 ++-- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 8a42044d..319fe53d 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -47,7 +47,7 @@ using namespace tlm; TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) : - name(name), totalNumTransactions(1), simulationTimeCoveredByRecording(SC_ZERO_TIME) + name(name), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME) { recordedData.reserve(transactionCommitRate); setUpTransactionTerminatingPhases(); @@ -118,11 +118,14 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, std::string phaseBeginPrefix = "BEGIN_"; std::string phaseEndPrefix = "END_"; - if (phaseName.find(phaseBeginPrefix) != std::string::npos) { + if (phaseName.find(phaseBeginPrefix) != std::string::npos) + { phaseName.erase(0, phaseBeginPrefix.length()); assert(currentTransactionsInSystem.count(&trans) != 0); currentTransactionsInSystem[&trans].insertPhase(phaseName, time); - } else { + } + else + { phaseName.erase(0, phaseEndPrefix.length()); assert(currentTransactionsInSystem.count(&trans) != 0); currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time); @@ -156,22 +159,23 @@ void TlmRecorder::recordDebugMessage(const std::string &message, const sc_time & void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) { - uint64_t id = totalNumTransactions++; - currentTransactionsInSystem[&trans].id = id; + totalNumTransactions++; + currentTransactionsInSystem[&trans].id = totalNumTransactions; currentTransactionsInSystem[&trans].cmd = trans.get_command() == - tlm::TLM_READ_COMMAND ? "R" : "W"; + tlm::TLM_READ_COMMAND ? 'R' : 'W'; currentTransactionsInSystem[&trans].address = trans.get_address(); currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans); currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans); currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getTimeOfGeneration(trans); - PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(id) + " generation time " + + PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " + currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); - if (id % transactionCommitRate == 0) + if (totalNumTransactions % transactionCommitRate == 0) { PRINTDEBUGMESSAGE(name, "Committing transactions " + - std::to_string(id - transactionCommitRate + 1) + " - " + std::to_string(id)); + std::to_string(totalNumTransactions - transactionCommitRate + 1) + + " - " + std::to_string(totalNumTransactions)); commitRecordedDataToDB(); } } @@ -333,7 +337,7 @@ void TlmRecorder::insertDebugMessageInDB(const std::string &message, const sc_ti void TlmRecorder::insertGeneralInfo() { - sqlite3_bind_int64(insertGeneralInfoStatement, 1, static_cast(totalNumTransactions - 1)); + sqlite3_bind_int64(insertGeneralInfoStatement, 1, static_cast(totalNumTransactions)); sqlite3_bind_int64(insertGeneralInfoStatement, 2, static_cast(simulationTimeCoveredByRecording.value())); sqlite3_bind_int(insertGeneralInfoStatement, 3, static_cast(Configuration::getInstance().memSpec->numberOfRanks)); sqlite3_bind_int(insertGeneralInfoStatement, 4, static_cast(Configuration::getInstance().memSpec->numberOfBankGroups)); @@ -421,7 +425,7 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData) sqlite3_bind_int64(insertTransactionStatement, 14, static_cast(recordingData.timeOfGeneration.value())); sqlite3_bind_text(insertTransactionStatement, 15, - recordingData.cmd.c_str(), static_cast(recordingData.cmd.length()), nullptr); + &recordingData.cmd, 1, nullptr); executeSqlStatement(insertTransactionStatement); } @@ -478,7 +482,7 @@ void TlmRecorder::closeConnection() insertGeneralInfo(); insertCommandLengths(); PRINTDEBUGMESSAGE(name, "Number of transactions written to DB: " - + std::to_string(totalNumTransactions - 1)); + + std::to_string(totalNumTransactions)); PRINTDEBUGMESSAGE(name, "tlmPhaseRecorder:\tEnd Recording"); sqlite3_close(db); db = nullptr; diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index 37bf787b..aeeb8ce1 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -92,7 +92,7 @@ private: uint64_t id; uint64_t address; unsigned int burstLength; - std::string cmd; + char cmd; DramExtension dramExtension; sc_time timeOfGeneration; TimeInterval timeOnDataStrobe; @@ -132,7 +132,7 @@ private: uint64_t transactionID); void insertDebugMessageInDB(const std::string &message, const sc_time &time); - static const int transactionCommitRate = 1000; + static constexpr unsigned transactionCommitRate = 1024; std::vector recordedData; std::map currentTransactionsInSystem; From 57c62ccc879b7b332e1548228deea834cf5c3743 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 31 May 2021 14:15:07 +0200 Subject: [PATCH 2/6] Terminate and record last transaction of simulation. --- DRAMSys/library/src/common/TlmRecorder.cpp | 48 ++++++++++++++++++---- DRAMSys/library/src/common/TlmRecorder.h | 7 ++-- DRAMSys/library/src/common/utils.cpp | 2 +- 3 files changed, 45 insertions(+), 12 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 319fe53d..7e952fa8 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -131,10 +131,16 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time); } - bool phaseTerminatesTransaction = std::count(transactionTerminatingPhases.begin(), - transactionTerminatingPhases.end(), phase) == 1; - if (phaseTerminatesTransaction) - removeTransactionFromSystem(trans); + if (currentTransactionsInSystem[&trans].cmd == 'X') + { + if (std::count(transactionTerminatingPhases.begin(), transactionTerminatingPhases.end(), phase) == 1) + removeTransactionFromSystem(trans); + } + else + { + if (phase == END_RESP) + removeTransactionFromSystem(trans); + } simulationTimeCoveredByRecording = time; } @@ -161,8 +167,13 @@ void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) { totalNumTransactions++; currentTransactionsInSystem[&trans].id = totalNumTransactions; - currentTransactionsInSystem[&trans].cmd = trans.get_command() == - tlm::TLM_READ_COMMAND ? 'R' : 'W'; + tlm_command command = trans.get_command(); + if (command == TLM_READ_COMMAND) + currentTransactionsInSystem[&trans].cmd = 'R'; + else if (command == TLM_WRITE_COMMAND) + currentTransactionsInSystem[&trans].cmd = 'W'; + else + currentTransactionsInSystem[&trans].cmd = 'X'; currentTransactionsInSystem[&trans].address = trans.get_address(); currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans); currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans); @@ -192,6 +203,28 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) currentTransactionsInSystem.erase(&trans); } +void TlmRecorder::terminateRemainingTransactions() +{ + while (!currentTransactionsInSystem.empty()) + { + auto transaction = currentTransactionsInSystem.begin(); + if (transaction->second.cmd == 'X') + { + std::string beginPhase = transaction->second.recordedPhases.front().name; + if (beginPhase == "PDNA") + recordPhase(*(transaction->first), END_PDNA, sc_time_stamp()); + else if (beginPhase == "PDNP") + recordPhase(*(transaction->first), END_PDNP, sc_time_stamp()); + else if (beginPhase == "SREF") + recordPhase(*(transaction->first), END_SREF, sc_time_stamp()); + else + removeTransactionFromSystem(*transaction->first); + } + else + recordPhase(*(transaction->first), END_RESP, sc_time_stamp()); + } +} + void TlmRecorder::commitRecordedDataToDB() { sqlite3_exec(db, "BEGIN;", nullptr, nullptr, nullptr); @@ -262,7 +295,7 @@ void TlmRecorder::openDB(const std::string &dbName) void TlmRecorder::setUpTransactionTerminatingPhases() { - transactionTerminatingPhases.push_back(END_RESP); + transactionTerminatingPhases.emplace_back(END_RESP); // Refresh All transactionTerminatingPhases.push_back(END_REFA); @@ -478,6 +511,7 @@ void TlmRecorder::executeInitialSqlCommand() void TlmRecorder::closeConnection() { + terminateRemainingTransactions(); commitRecordedDataToDB(); insertGeneralInfo(); insertCommandLengths(); diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index aeeb8ce1..deefd36f 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -42,7 +42,7 @@ #include #include #include -#include +#include #include #include #include @@ -55,8 +55,6 @@ class TlmRecorder { public: - std::string sqlScriptURI; - TlmRecorder(const std::string &name, const std::string &dbName); ~TlmRecorder(); @@ -123,6 +121,7 @@ private: void introduceTransactionSystem(tlm::tlm_generic_payload &trans); void removeTransactionFromSystem(tlm::tlm_generic_payload &trans); + void terminateRemainingTransactions(); void commitRecordedDataToDB(); void insertGeneralInfo(); void insertCommandLengths(); @@ -134,7 +133,7 @@ private: static constexpr unsigned transactionCommitRate = 1024; std::vector recordedData; - std::map currentTransactionsInSystem; + std::unordered_map currentTransactionsInSystem; uint64_t totalNumTransactions; sc_time simulationTimeCoveredByRecording; diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index f9b6b520..3a1e86c3 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -142,7 +142,7 @@ std::string parseString(json &obj, const std::string &name) void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank) { payload.set_address(bank.getStartAddress()); - payload.set_command(TLM_READ_COMMAND); + payload.set_command(TLM_IGNORE_COMMAND); payload.set_data_length(0); payload.set_response_status(TLM_OK_RESPONSE); payload.set_dmi_allowed(false); From d6b8e7382723817795391424470aa8d48e1e2291 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Mon, 31 May 2021 15:19:48 +0200 Subject: [PATCH 3/6] Change type of command from enum to class. --- .../src/configuration/memspec/MemSpec.cpp | 2 +- DRAMSys/library/src/controller/Command.cpp | 108 +++++++++--------- DRAMSys/library/src/controller/Command.h | 94 +++++++++------ DRAMSys/library/src/controller/Controller.cpp | 8 +- .../src/controller/ControllerRecordable.cpp | 4 +- .../src/controller/checker/CheckerDDR3.cpp | 8 +- .../src/controller/checker/CheckerDDR4.cpp | 10 +- .../src/controller/checker/CheckerDDR5.cpp | 18 +-- .../src/controller/checker/CheckerGDDR5.cpp | 10 +- .../src/controller/checker/CheckerGDDR5X.cpp | 10 +- .../src/controller/checker/CheckerGDDR6.cpp | 10 +- .../src/controller/checker/CheckerHBM2.cpp | 14 +-- .../src/controller/checker/CheckerLPDDR4.cpp | 8 +- .../src/controller/checker/CheckerSTTMRAM.cpp | 8 +- .../src/controller/checker/CheckerWideIO.cpp | 8 +- .../src/controller/checker/CheckerWideIO2.cpp | 8 +- .../src/controller/cmdmux/CmdMuxOldest.cpp | 2 +- .../src/controller/cmdmux/CmdMuxStrict.cpp | 10 +- .../src/simulation/dram/DramRecordable.cpp | 4 +- 19 files changed, 185 insertions(+), 159 deletions(-) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 0ab6486c..8c049067 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -70,7 +70,7 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType, memoryType(memoryType), burstDuration(tCK * (burstLength / dataRate)) { - commandLengthInCycles = std::vector(numberOfCommands(), 1); + commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); } sc_time MemSpec::getCommandLength(Command command) const diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index a5f50101..39b17f74 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -41,9 +41,35 @@ using namespace tlm; using namespace DRAMPower; -std::string commandToString(Command command) -{ - assert(command >= Command::NOP && command <= Command::SREFEX); +Command::Command(Command::Type type) : type(type) {} + +Command::Command(tlm_phase phase) +{ + assert(phase >= BEGIN_RD && phase <= END_SREF); + static constexpr std::array commandOfPhase = + {Command::RD, + Command::WR, + Command::RDA, + Command::WRA, + Command::ACT, + Command::PRE, + Command::REFB, + Command::PRESB, + Command::REFSB, + Command::PREA, + Command::REFA, + Command::PDEA, + Command::PDEP, + Command::SREFEN, + Command::PDXA, + Command::PDXP, + Command::SREFEX}; + type = commandOfPhase[phase - BEGIN_RD]; +} + +std::string Command::toString() const +{ + assert(type >= Command::NOP && type <= Command::SREFEX); static std::array stringOfCommand = {"NOP", "RD", @@ -58,22 +84,22 @@ std::string commandToString(Command command) "PREA", "REFA", "PDEA", - "PDXA", "PDEP", - "PDXP", "SREFEN", + "PDXA", + "PDXP", "SREFEX"}; - return stringOfCommand[command]; + return stringOfCommand[type]; } -unsigned numberOfCommands() +unsigned Command::numberOfCommands() { return 18; } -tlm_phase commandToPhase(Command command) +tlm_phase Command::toPhase() const { - assert(command >= Command::NOP && command <= Command::SREFEX); + assert(type >= Command::NOP && type <= Command::SREFEX); static std::array phaseOfCommand = {UNINITIALIZED_PHASE, BEGIN_RD, @@ -88,36 +114,12 @@ tlm_phase commandToPhase(Command command) BEGIN_PREA, BEGIN_REFA, BEGIN_PDNA, - END_PDNA, BEGIN_PDNP, - END_PDNP, BEGIN_SREF, + END_PDNA, + END_PDNP, END_SREF}; - return phaseOfCommand[command]; -} - -Command phaseToCommand(tlm_phase phase) -{ - assert(phase >= BEGIN_RD && phase <= END_SREF); - static std::array commandOfPhase = - {Command::RD, - Command::WR, - Command::RDA, - Command::WRA, - Command::ACT, - Command::PRE, - Command::REFB, - Command::PRESB, - Command::REFSB, - Command::PREA, - Command::REFA, - Command::PDEA, - Command::PDXA, - Command::PDEP, - Command::PDXP, - Command::SREFEN, - Command::SREFEX}; - return commandOfPhase[phase - BEGIN_RD]; + return phaseOfCommand[type]; } MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) @@ -137,10 +139,10 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase) MemCommand::PREA, MemCommand::REF, MemCommand::PDN_S_ACT, - MemCommand::PUP_ACT, MemCommand::PDN_S_PRE, - MemCommand::PUP_PRE, MemCommand::SREN, + MemCommand::PUP_ACT, + MemCommand::PUP_PRE, MemCommand::SREX}; return phaseOfCommand[phase - BEGIN_RD]; } @@ -156,32 +158,32 @@ tlm_phase getEndPhase(tlm_phase phase) return (phase + 17); } -bool isBankCommand(Command command) +bool Command::isBankCommand() const { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command <= Command::REFB); + assert(type >= Command::NOP && type <= Command::SREFEX); + return (type <= Command::REFB); } -bool isGroupCommand(Command command) +bool Command::isGroupCommand() const { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command >= Command::PRESB && command <= Command::REFSB); + assert(type >= Command::NOP && type <= Command::SREFEX); + return (type >= Command::PRESB && type <= Command::REFSB); } -bool isRankCommand(Command command) +bool Command::isRankCommand() const { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command >= Command::PREA); + assert(type >= Command::NOP && type <= Command::SREFEX); + return (type >= Command::PREA); } -bool isCasCommand(Command command) +bool Command::isCasCommand() const { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command <= Command::WRA); + assert(type >= Command::NOP && type <= Command::SREFEX); + return (type <= Command::WRA); } -bool isRasCommand(Command command) +bool Command::isRasCommand() const { - assert(command >= Command::NOP && command <= Command::SREFEX); - return (command >= Command::ACT); + assert(type >= Command::NOP && type <= Command::SREFEX); + return (type >= Command::ACT); } diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 5e9c92f8..c2676400 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -46,6 +46,12 @@ #include "../common/third_party/DRAMPower/src/MemCommand.h" // DO NOT CHANGE THE ORDER! + +// BEGIN_REQ // 1 +// END_REQ // 2 +// BEGIN_RESP // 3 +// END_RESP // 4 + DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5 DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6 DECLARE_EXTENDED_PHASE(BEGIN_RDA); // 7 @@ -58,10 +64,11 @@ DECLARE_EXTENDED_PHASE(BEGIN_REFSB); // 13 DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 14 DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 15 DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 16 -DECLARE_EXTENDED_PHASE(END_PDNA); // 17 -DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 18 -DECLARE_EXTENDED_PHASE(END_PDNP); // 19 -DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 20 +DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 17 +DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18 + +DECLARE_EXTENDED_PHASE(END_PDNA); // 19 +DECLARE_EXTENDED_PHASE(END_PDNP); // 20 DECLARE_EXTENDED_PHASE(END_SREF); // 21 DECLARE_EXTENDED_PHASE(END_RD); // 22 @@ -76,45 +83,62 @@ DECLARE_EXTENDED_PHASE(END_REFSB); // 30 DECLARE_EXTENDED_PHASE(END_PREA); // 31 DECLARE_EXTENDED_PHASE(END_REFA); // 32 -enum Command +class Command { - NOP, - RD, - WR, - RDA, - WRA, - ACT, - PRE, - REFB, - PRESB, - REFSB, - PREA, - REFA, - PDEA, - PDXA, - PDEP, - PDXP, - SREFEN, - SREFEX +public: + enum Type : uint8_t + { + NOP, + RD, + WR, + RDA, + WRA, + ACT, + PRE, + REFB, + PRESB, + REFSB, + PREA, + REFA, + PDEA, + PDEP, + SREFEN, + PDXA, + PDXP, + SREFEX + }; + +private: + Type type; + +public: + Command() = default; + Command(Type type); + Command(tlm::tlm_phase phase); + + std::string toString() const; + tlm::tlm_phase toPhase() const; + static unsigned numberOfCommands(); + bool isBankCommand() const; + bool isGroupCommand() const; + bool isRankCommand() const; + bool isCasCommand() const; + bool isRasCommand() const; + + constexpr operator uint8_t() const + { + return type; + } }; -std::string commandToString(Command); -tlm::tlm_phase commandToPhase(Command); -Command phaseToCommand(tlm::tlm_phase); DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase); bool phaseNeedsEnd(tlm::tlm_phase); tlm::tlm_phase getEndPhase(tlm::tlm_phase); -unsigned numberOfCommands(); -bool isBankCommand(Command); -bool isGroupCommand(Command); -bool isRankCommand(Command); -bool isCasCommand(Command); -bool isRasCommand(Command); -struct CommandTuple -{ +struct CommandTuple +{ using Type = std::tuple<::Command, tlm::tlm_generic_payload *, sc_time>; - enum Accessor + enum Accessor { Command = 0, Payload = 1, diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 2d727780..1c10b588 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -293,12 +293,12 @@ void Controller::controllerMethod() Bank bank = DramExtension::getBank(payload); unsigned burstLength = DramExtension::getBurstLength(payload); - if (isRankCommand(command)) + if (command.isRankCommand()) { for (auto it : bankMachinesOnRank[rank.ID()]) it->updateState(command); } - else if (isGroupCommand(command)) + else if (command.isGroupCommand()) { for (unsigned bankID = (bank.ID() % memSpec->banksPerGroup); bankID < memSpec->banksPerRank; bankID += memSpec->banksPerGroup) @@ -311,7 +311,7 @@ void Controller::controllerMethod() powerDownManagers[rank.ID()]->updateState(command); checker->insert(command, payload); - if (isCasCommand(command)) + if (command.isCasCommand()) { scheduler->removeRequest(payload); manageRequests(thinkDelayFw); @@ -499,6 +499,6 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase, s void Controller::sendToDram(Command command, tlm_generic_payload *payload, sc_time delay) { - tlm_phase phase = commandToPhase(command); + tlm_phase phase = command.toPhase(); iSocket->nb_transport_fw(*payload, phase, delay); } diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 1a320d96..9c9adb6f 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -73,13 +73,13 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phas void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload, sc_time delay) { - if (isCasCommand(command)) + if (command.isCasCommand()) { TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, *payload); tlmRecorder->updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start, sc_time_stamp() + delay + dataStrobe.end, *payload); } - tlm_phase phase = commandToPhase(command); + tlm_phase phase = command.toPhase(); iSocket->nb_transport_fw(*payload, phase, delay); } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 784c9a77..809f157e 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -44,10 +44,10 @@ CheckerDDR3::CheckerDDR3() SC_REPORT_FATAL("CheckerDDR3", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -423,7 +423,7 @@ void CheckerDDR3::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index b38d48b0..19c929c5 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -44,12 +44,12 @@ CheckerDDR4::CheckerDDR4() SC_REPORT_FATAL("CheckerDDR4", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -456,7 +456,7 @@ void CheckerDDR4::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index cc0555ed..f9220256 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -44,18 +44,18 @@ CheckerDDR5::CheckerDDR5() SC_REPORT_FATAL("CheckerDDR5", "Wrong MemSpec chosen"); lastScheduledByCommandAndDimmRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfDIMMRanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfDIMMRanks, sc_max_time())); lastScheduledByCommandAndPhysicalRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfPhysicalRanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfPhysicalRanks, sc_max_time())); lastScheduledByCommandAndLogicalRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfLogicalRanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfLogicalRanks, sc_max_time())); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); // Required for Same Bank Refresh - lastScheduledByCommandAndBankInGroup = std::vector>(numberOfCommands(), + lastScheduledByCommandAndBankInGroup = std::vector>(Command::numberOfCommands(), std::vector(memSpec->numberOfRanks * memSpec->banksPerGroup, sc_max_time())); lastCommandOnBus = sc_max_time(); dummyCommandOnBus.start = sc_max_time(); @@ -827,7 +827,7 @@ void CheckerDDR5::insert(Command command, tlm_generic_payload *payload) unsigned burstLength = DramExtension::getBurstLength(payload); PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndDimmRank[command][dimmRank.ID()] = sc_time_stamp(); lastScheduledByCommandAndPhysicalRank[command][physicalRank.ID()] = sc_time_stamp(); @@ -837,7 +837,7 @@ void CheckerDDR5::insert(Command command, tlm_generic_payload *payload) lastScheduledByCommand[command] = sc_time_stamp(); lastScheduledByCommandAndBankInGroup[command][bankInGroup.ID()] = sc_time_stamp(); - if (isCasCommand(command)) + if (command.isCasCommand()) { lastBurstLengthByCommandAndDimmRank[command][dimmRank.ID()] = burstLength; lastBurstLengthByCommandAndPhysicalRank[command][physicalRank.ID()] = burstLength; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index 48ec6cb6..6401f779 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -44,12 +44,12 @@ CheckerGDDR5::CheckerGDDR5() SC_REPORT_FATAL("CheckerGDDR5", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); last32Activates = std::vector>(memSpec->numberOfRanks); @@ -538,7 +538,7 @@ void CheckerGDDR5::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index 7ccd85a0..0c169f2d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -44,12 +44,12 @@ CheckerGDDR5X::CheckerGDDR5X() SC_REPORT_FATAL("CheckerGDDR5X", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); last32Activates = std::vector>(memSpec->numberOfRanks); @@ -538,7 +538,7 @@ void CheckerGDDR5X::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index 4d8efdf2..1be693bb 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -44,12 +44,12 @@ CheckerGDDR6::CheckerGDDR6() SC_REPORT_FATAL("CheckerGDDR6", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -559,7 +559,7 @@ void CheckerGDDR6::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index e2167770..f229c732 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -44,12 +44,12 @@ CheckerHBM2::CheckerHBM2() SC_REPORT_FATAL("CheckerHBM2", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndBankGroup = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBankGroups, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnRasBus = sc_max_time(); lastCommandOnCasBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -492,7 +492,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, tlm_generic_paylo else SC_REPORT_FATAL("CheckerHBM2", "Unknown command!"); - if (isRasCommand(command)) + if (command.isRasCommand()) { if (lastCommandOnRasBus != sc_max_time()) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK); @@ -513,14 +513,14 @@ void CheckerHBM2::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommand[command] = sc_time_stamp(); - if (isCasCommand(command)) + if (command.isCasCommand()) lastCommandOnCasBus = sc_time_stamp(); else if (command == Command::ACT) lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK; diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 6acee003..1ba29f76 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -44,10 +44,10 @@ CheckerLPDDR4::CheckerLPDDR4() SC_REPORT_FATAL("CheckerLPDDR4", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -507,7 +507,7 @@ void CheckerLPDDR4::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp index 7c8438e6..52cbdf18 100644 --- a/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerSTTMRAM.cpp @@ -44,10 +44,10 @@ CheckerSTTMRAM::CheckerSTTMRAM() SC_REPORT_FATAL("CheckerSTTMRAM", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -379,7 +379,7 @@ void CheckerSTTMRAM::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerSTTMRAM", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index bde72d2b..1e29b6ba 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -44,10 +44,10 @@ CheckerWideIO::CheckerWideIO() SC_REPORT_FATAL("CheckerWideIO", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last2Activates = std::vector>(memSpec->numberOfRanks); @@ -396,7 +396,7 @@ void CheckerWideIO::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index bcf0518e..cd82c2bd 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -44,10 +44,10 @@ CheckerWideIO2::CheckerWideIO2() SC_REPORT_FATAL("CheckerWideIO2", "Wrong MemSpec chosen"); lastScheduledByCommandAndBank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); + (Command::numberOfCommands(), std::vector(memSpec->numberOfBanks, sc_max_time())); lastScheduledByCommandAndRank = std::vector> - (numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); - lastScheduledByCommand = std::vector(numberOfCommands(), sc_max_time()); + (Command::numberOfCommands(), std::vector(memSpec->numberOfRanks, sc_max_time())); + lastScheduledByCommand = std::vector(Command::numberOfCommands(), sc_max_time()); lastCommandOnBus = sc_max_time(); last4Activates = std::vector>(memSpec->numberOfRanks); @@ -474,7 +474,7 @@ void CheckerWideIO2::insert(Command command, tlm_generic_payload *payload) Bank bank = DramExtension::getBank(payload); PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) - + " command is " + commandToString(command)); + + " command is " + command.toString()); lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp(); lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp index 46e82a44..f5e150ee 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp @@ -89,7 +89,7 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC for (auto it : readyCommands) { - if (isRasCommand(std::get(it))) + if (std::get(it).isRasCommand()) readyRasCommands.emplace_back(it); else readyCasCommands.emplace_back(it); diff --git a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp index c2517fe2..3749ce4e 100644 --- a/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp +++ b/DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp @@ -56,7 +56,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand if (newTimestamp < lastTimestamp) { - if (isRasCommand(std::get(*it)) || newPayloadID == nextPayloadID) + if (std::get(*it).isRasCommand() || newPayloadID == nextPayloadID) { lastTimestamp = newTimestamp; lastPayloadID = newPayloadID; @@ -65,7 +65,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand } else if ((newTimestamp == lastTimestamp) && (newPayloadID < lastPayloadID)) { - if (isRasCommand(std::get(*it)) || newPayloadID == nextPayloadID) + if (std::get(*it).isRasCommand() || newPayloadID == nextPayloadID) { lastPayloadID = newPayloadID; result = it; @@ -76,7 +76,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) { - if (isCasCommand(std::get(*result))) + if (std::get(*result).isCasCommand()) nextPayloadID++; return *result; } @@ -99,7 +99,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC for (auto it : readyCommands) { - if (isRasCommand(std::get(it))) + if (std::get(it).isRasCommand()) readyRasCommands.emplace_back(it); else readyCasCommands.emplace_back(it); @@ -175,7 +175,7 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC if (result != readyCommands.cend() && std::get(*result) == sc_time_stamp()) { - if (isCasCommand(std::get(*result))) + if (std::get(*result).isCasCommand()) nextPayloadID++; return *result; } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 5167bccf..98749037 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -88,7 +88,7 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF) - recTime += this->memSpec->getCommandLength(phaseToCommand(phase)); + recTime += this->memSpec->getCommandLength(Command(phase)); NDEBUG_UNUSED(unsigned thr) = DramExtension::getExtension(trans).getThread().ID(); NDEBUG_UNUSED(unsigned ch) = DramExtension::getExtension(trans).getChannel().ID(); @@ -106,7 +106,7 @@ void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase if (phaseNeedsEnd(phase)) { - recTime += this->memSpec->getExecutionTime(phaseToCommand(phase), trans); + recTime += this->memSpec->getExecutionTime(Command(phase), trans); tlmRecorder->recordPhase(trans, getEndPhase(phase), recTime); } From 9949c36f83484a8d6152a399cfed6c8c982ca5ef Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 1 Jun 2021 11:11:40 +0200 Subject: [PATCH 4/6] Use separate thread for database creation. --- DRAMSys/library/src/common/TlmRecorder.cpp | 117 ++++++++++----------- DRAMSys/library/src/common/TlmRecorder.h | 26 ++--- DRAMSys/library/src/controller/Command.h | 36 +++---- DRAMSys/simulator/StlPlayer.cpp | 6 +- 4 files changed, 89 insertions(+), 96 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 7e952fa8..61f86e22 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -42,15 +42,18 @@ #include "TlmRecorder.h" #include "dramExtensions.h" #include "../configuration/Configuration.h" -#include "../controller/Command.h" using namespace tlm; TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) : - name(name), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME) + name(name), totalNumTransactions(0), simulationTimeCoveredByRecording(SC_ZERO_TIME) { - recordedData.reserve(transactionCommitRate); - setUpTransactionTerminatingPhases(); + currentDataBuffer = &recordingDataBuffer[0]; + storageDataBuffer = &recordingDataBuffer[1]; + + currentDataBuffer->reserve(transactionCommitRate); + storageDataBuffer->reserve(transactionCommitRate); + openDB(dbName); char *sErrMsg; sqlite3_exec(db, "PRAGMA main.page_size = 4096", nullptr, nullptr, &sErrMsg); @@ -111,29 +114,28 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth) void TlmRecorder::recordPhase(tlm_generic_payload &trans, tlm_phase phase, const sc_time &time) { - if (currentTransactionsInSystem.count(&trans) == 0) + if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) introduceTransactionSystem(trans); std::string phaseName = getPhaseName(phase); std::string phaseBeginPrefix = "BEGIN_"; std::string phaseEndPrefix = "END_"; - if (phaseName.find(phaseBeginPrefix) != std::string::npos) + if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) { - phaseName.erase(0, phaseBeginPrefix.length()); - assert(currentTransactionsInSystem.count(&trans) != 0); - currentTransactionsInSystem[&trans].insertPhase(phaseName, time); + phaseName.erase(0, phaseEndPrefix.length()); + currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time); } else { - phaseName.erase(0, phaseEndPrefix.length()); - assert(currentTransactionsInSystem.count(&trans) != 0); - currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time); + phaseName.erase(0, phaseBeginPrefix.length()); + currentTransactionsInSystem[&trans].insertPhase(phaseName, time); } if (currentTransactionsInSystem[&trans].cmd == 'X') { - if (std::count(transactionTerminatingPhases.begin(), transactionTerminatingPhases.end(), phase) == 1) + if (phase == END_REFA || phase == END_REFB || phase == END_REFSB + || phase == END_PDNA || phase == END_PDNP || phase == END_SREF) removeTransactionFromSystem(trans); } else @@ -181,14 +183,6 @@ void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) PRINTDEBUGMESSAGE(name, "New transaction #" + std::to_string(totalNumTransactions) + " generation time " + currentTransactionsInSystem[&trans].timeOfGeneration.to_string()); - - if (totalNumTransactions % transactionCommitRate == 0) - { - PRINTDEBUGMESSAGE(name, "Committing transactions " + - std::to_string(totalNumTransactions - transactionCommitRate + 1) - + " - " + std::to_string(totalNumTransactions)); - commitRecordedDataToDB(); - } } void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) @@ -199,8 +193,20 @@ void TlmRecorder::removeTransactionFromSystem(tlm_generic_payload &trans) std::to_string(currentTransactionsInSystem[&trans].id)); Transaction &recordingData = currentTransactionsInSystem[&trans]; - recordedData.push_back(recordingData); + currentDataBuffer->push_back(recordingData); currentTransactionsInSystem.erase(&trans); + + if (currentDataBuffer->size() == transactionCommitRate) + { + if (storageThread.joinable()) + storageThread.join(); + + std::swap(currentDataBuffer, storageDataBuffer); + + storageThread = std::thread(&TlmRecorder::commitRecordedDataToDB, this); + currentDataBuffer->clear(); + } + } void TlmRecorder::terminateRemainingTransactions() @@ -228,7 +234,7 @@ void TlmRecorder::terminateRemainingTransactions() void TlmRecorder::commitRecordedDataToDB() { sqlite3_exec(db, "BEGIN;", nullptr, nullptr, nullptr); - for (Transaction &recordingData : recordedData) + for (Transaction &recordingData : *storageDataBuffer) { assert(!recordingData.recordedPhases.empty()); insertTransactionInDB(recordingData); @@ -248,7 +254,6 @@ void TlmRecorder::commitRecordedDataToDB() } sqlite3_exec(db, "COMMIT;", nullptr, nullptr, nullptr); - recordedData.clear(); } @@ -293,55 +298,36 @@ void TlmRecorder::openDB(const std::string &dbName) } } -void TlmRecorder::setUpTransactionTerminatingPhases() -{ - transactionTerminatingPhases.emplace_back(END_RESP); - - // Refresh All - transactionTerminatingPhases.push_back(END_REFA); - - // Refresh Bank - transactionTerminatingPhases.push_back(END_REFB); - - // Refresh Same Bank - transactionTerminatingPhases.push_back(END_REFSB); - - // Phases for Power Down - transactionTerminatingPhases.push_back(END_PDNA); - transactionTerminatingPhases.push_back(END_PDNP); - transactionTerminatingPhases.push_back(END_SREF); -} - void TlmRecorder::prepareSqlStatements() { insertTransactionString = - "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank," - ":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; - + "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:rank," + ":bankgroup,:bank,:row,:column,:dataStrobeBegin,:dataStrobeEnd, :timeOfGeneration,:command)"; + insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)"; updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id"; updateDataStrobeString = - "UPDATE Transactions SET DataStrobeBegin = :begin, DataStrobeEnd = :end WHERE ID = :id"; + "UPDATE Transactions SET DataStrobeBegin = :begin, DataStrobeEnd = :end WHERE ID = :id"; insertPhaseString = - "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Transact) VALUES (:name,:begin,:end,:transaction)"; + "INSERT INTO Phases (PhaseName,PhaseBegin,PhaseEnd,Transact) VALUES (:name,:begin,:end,:transaction)"; updatePhaseString = - "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; + "UPDATE Phases SET PhaseEnd = :end WHERE Transact = :trans AND PhaseName = :name"; insertGeneralInfoString = - "INSERT INTO GeneralInfo VALUES" - "(:numberOfTransactions,:end,:numberOfRanks,:numberOfBankgroups,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec," - ":traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread, :maxBufferDepth)"; + "INSERT INTO GeneralInfo VALUES" + "(:numberOfTransactions,:end,:numberOfRanks,:numberOfBankgroups,:numberOfBanks,:clk,:unitOfTime,:mcconfig,:memspec," + ":traces,:windowSize, :flexibleRefresh, :maxRefBurst, :controllerThread, :maxBufferDepth)"; insertCommandLengthsString = - "INSERT INTO CommandLengths VALUES" - "(:NOP, :RD, :WR, :RDA, :WRA, :ACT, :PRE, :REFB, :PRESB, :REFSB, :PREA, :REFA, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)"; + "INSERT INTO CommandLengths VALUES" + "(:NOP, :RD, :WR, :RDA, :WRA, :ACT, :PRE, :REFB, :PRESB, :REFSB, :PREA, :REFA, :PDEA, :PDXA, :PDEP, :PDXP, :SREFEN, :SREFEX)"; insertDebugMessageString = - "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; + "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; insertPowerString = "INSERT INTO Power VALUES (:time,:averagePower)"; insertBufferDepthString = "INSERT INTO BufferDepth VALUES (:time,:bufferNumber,:averageBufferDepth)"; @@ -384,18 +370,18 @@ void TlmRecorder::insertGeneralInfo() sqlite3_bind_int64(insertGeneralInfoStatement, 11, 0); else sqlite3_bind_int64(insertGeneralInfoStatement, 11, - static_cast((Configuration::getInstance().memSpec->tCK * - Configuration::getInstance().windowSize).value())); - + static_cast((Configuration::getInstance().memSpec->tCK * + Configuration::getInstance().windowSize).value())); + if ((Configuration::getInstance().refreshMaxPostponed > 0) - || (Configuration::getInstance().refreshMaxPulledin > 0)) + || (Configuration::getInstance().refreshMaxPulledin > 0)) { sqlite3_bind_int(insertGeneralInfoStatement, 12, 1); sqlite3_bind_int(insertGeneralInfoStatement, 13, - static_cast(std::max(Configuration::getInstance().refreshMaxPostponed, - Configuration::getInstance().refreshMaxPulledin))); - } - else + static_cast(std::max(Configuration::getInstance().refreshMaxPostponed, + Configuration::getInstance().refreshMaxPulledin))); + } + else { sqlite3_bind_int(insertGeneralInfoStatement, 12, 0); sqlite3_bind_int(insertGeneralInfoStatement, 13, 0); @@ -490,7 +476,7 @@ void TlmRecorder::executeSqlStatement(sqlite3_stmt *statement) int errorCode = sqlite3_step(statement); if (errorCode != SQLITE_DONE) SC_REPORT_FATAL("Error in TraceRecorder", - (std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)).c_str()); + (std::string("Could not execute statement. Error code: ") + std::to_string(errorCode)).c_str()); sqlite3_reset(statement); } @@ -512,6 +498,9 @@ void TlmRecorder::executeInitialSqlCommand() void TlmRecorder::closeConnection() { terminateRemainingTransactions(); + if (storageThread.joinable()) + storageThread.join(); + std::swap(currentDataBuffer, storageDataBuffer); commitRecordedDataToDB(); insertGeneralInfo(); insertCommandLengths(); diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index deefd36f..d4ee9046 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include "sqlite3.h" @@ -116,7 +117,6 @@ private: static void executeSqlStatement(sqlite3_stmt *statement); void openDB(const std::string &dbName); - void setUpTransactionTerminatingPhases(); void introduceTransactionSystem(tlm::tlm_generic_payload &trans); void removeTransactionFromSystem(tlm::tlm_generic_payload &trans); @@ -131,24 +131,27 @@ private: uint64_t transactionID); void insertDebugMessageInDB(const std::string &message, const sc_time &time); - static constexpr unsigned transactionCommitRate = 1024; - std::vector recordedData; + static constexpr unsigned transactionCommitRate = 8192; + std::array, 2> recordingDataBuffer; + std::vector *currentDataBuffer; + std::vector *storageDataBuffer; + std::thread storageThread; + std::unordered_map currentTransactionsInSystem; uint64_t totalNumTransactions; sc_time simulationTimeCoveredByRecording; - std::vector transactionTerminatingPhases; sqlite3 *db = nullptr; sqlite3_stmt *insertTransactionStatement, *insertRangeStatement, - *updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement, - *insertGeneralInfoStatement, *insertCommandLengthsStatement, - *insertDebugMessageStatement, *updateDataStrobeStatement, - *insertPowerStatement, *insertBufferDepthStatement, *insertBandwidthStatement; + *updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement, + *insertGeneralInfoStatement, *insertCommandLengthsStatement, + *insertDebugMessageStatement, *updateDataStrobeStatement, + *insertPowerStatement, *insertBufferDepthStatement, *insertBandwidthStatement; std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString, - updatePhaseString, insertGeneralInfoString, insertCommandLengthsString, - insertDebugMessageString, updateDataStrobeString, insertPowerString, - insertBufferDepthString, insertBandwidthString; + updatePhaseString, insertGeneralInfoString, insertCommandLengthsString, + insertDebugMessageString, updateDataStrobeString, insertPowerString, + insertBufferDepthString, insertBandwidthString; std::string initialCommand = "DROP TABLE IF EXISTS Phases; \n" @@ -265,4 +268,3 @@ private: }; #endif // TLMRECORDER_H - diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index c2676400..db48cd85 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -88,24 +88,24 @@ class Command public: enum Type : uint8_t { - NOP, - RD, - WR, - RDA, - WRA, - ACT, - PRE, - REFB, - PRESB, - REFSB, - PREA, - REFA, - PDEA, - PDEP, - SREFEN, - PDXA, - PDXP, - SREFEX + NOP, // 0 + RD, // 1 + WR, // 2 + RDA, // 3 + WRA, // 4 + ACT, // 5 + PRE, // 6 + REFB, // 7 + PRESB, // 8 + REFSB, // 9 + PREA, // 10 + REFA, // 11 + PDEA, // 12 + PDEP, // 13 + SREFEN, // 14 + PDXA, // 15 + PDXP, // 16 + SREFEX // 17 }; private: diff --git a/DRAMSys/simulator/StlPlayer.cpp b/DRAMSys/simulator/StlPlayer.cpp index 109309bd..1b6e3e33 100644 --- a/DRAMSys/simulator/StlPlayer.cpp +++ b/DRAMSys/simulator/StlPlayer.cpp @@ -50,9 +50,11 @@ StlPlayer::StlPlayer(const sc_module_name &name, TraceSetup *setup, bool relative) : TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests), - file(pathToTrace), currentBuffer(&lineContents[0]), parseBuffer(&lineContents[1]), - relative(relative), playerClk(playerClk) + file(pathToTrace), relative(relative), playerClk(playerClk) { + currentBuffer = &lineContents[0]; + parseBuffer = &lineContents[1]; + if (!file.is_open()) SC_REPORT_FATAL("StlPlayer", (std::string("Could not open trace ") + pathToTrace).c_str()); else From eefbbb52352bd927b54b6f79859d9734d68b5dc6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 1 Jun 2021 11:58:53 +0200 Subject: [PATCH 5/6] Simplify trace recording. --- DRAMSys/library/src/common/TlmRecorder.cpp | 39 +++------------------- DRAMSys/library/src/common/TlmRecorder.h | 3 -- 2 files changed, 4 insertions(+), 38 deletions(-) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 61f86e22..427f4614 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -117,19 +117,12 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) introduceTransactionSystem(trans); - std::string phaseName = getPhaseName(phase); - std::string phaseBeginPrefix = "BEGIN_"; - std::string phaseEndPrefix = "END_"; - if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) - { - phaseName.erase(0, phaseEndPrefix.length()); - currentTransactionsInSystem[&trans].setPhaseEnd(phaseName, time); - } + currentTransactionsInSystem[&trans].recordedPhases.back().interval.end = time; else { - phaseName.erase(0, phaseBeginPrefix.length()); - currentTransactionsInSystem[&trans].insertPhase(phaseName, time); + std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_" + currentTransactionsInSystem[&trans].recordedPhases.emplace_back(phaseName, time); } if (currentTransactionsInSystem[&trans].cmd == 'X') @@ -256,30 +249,6 @@ void TlmRecorder::commitRecordedDataToDB() sqlite3_exec(db, "COMMIT;", nullptr, nullptr, nullptr); } - -void TlmRecorder::Transaction::insertPhase(const std::string &phaseName, const sc_time &begin) -{ - recordedPhases.emplace_back(phaseName, begin); -} - -void TlmRecorder::Transaction::setPhaseEnd(const std::string &phaseName, const sc_time &end) -{ - // Find the latest recorder phase for that transaction with a matching phaseName and update it - // Note: Transactions might have the same phase multiple times (e.g. PRE->ACT->REF->ACT->RD) - // only update the latest one that has been recorded - for (size_t i = recordedPhases.size(); i > 0; i--) - { - Phase &data = recordedPhases[i - 1]; - if (data.name == phaseName) - { - data.interval.end = end; - return; - } - } - SC_REPORT_FATAL("Recording Error", - "While trying to set phase end: phaseBegin has not been recorded"); -} - void TlmRecorder::openDB(const std::string &dbName) { std::ifstream f(dbName.c_str()); @@ -287,7 +256,7 @@ void TlmRecorder::openDB(const std::string &dbName) { if (remove(dbName.c_str()) != 0) { - SC_REPORT_FATAL("TlmRecorder", "Error deleting file" ); + SC_REPORT_FATAL("TlmRecorder", "Error deleting file"); } } diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index d4ee9046..d71af38f 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -103,9 +103,6 @@ private: TimeInterval interval; }; std::vector recordedPhases; - - void insertPhase(const std::string &phaseName, const sc_time &begin); - void setPhaseEnd(const std::string &phaseName, const sc_time &end); }; std::string name; From 486b37a3ec19a0cdf9629d5c4f11ca56f59df9d0 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 1 Jun 2021 14:05:43 +0200 Subject: [PATCH 6/6] Add assert statement for END phases. --- DRAMSys/library/src/common/TlmRecorder.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 427f4614..b991cf61 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -118,7 +118,10 @@ void TlmRecorder::recordPhase(tlm_generic_payload &trans, introduceTransactionSystem(trans); if (phase == END_REQ || phase == END_RESP || phase >= END_PDNA) + { + assert(getPhaseName(phase).substr(4) == currentTransactionsInSystem[&trans].recordedPhases.back().name); currentTransactionsInSystem[&trans].recordedPhases.back().interval.end = time; + } else { std::string phaseName = getPhaseName(phase).substr(6); // remove "BEGIN_"