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FIXME: workaround for bankwise parameters.

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This commit is contained in:
Matthias Jung
2020-02-26 00:01:27 +01:00
parent d96e8c316a
commit 757ec296cf
5 changed files with 24 additions and 23 deletions
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3
DRAMSys/library/src/simulation/dram/Dram.cpp
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@@ -55,9 +55,10 @@
#include "../../common/protocol.h"
#include "../../common/utils.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../common/third_party/DRAMPower/src/MemCommand.h"
using namespace tlm;
using namespace Data;
using namespace DRAMPower;
Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
{

2
DRAMSys/library/src/simulation/dram/Dram.h
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@@ -50,7 +50,7 @@
using namespace std;
using namespace tlm;
using namespace Data;
using namespace DRAMPower;
class Dram : public sc_module
{

14
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
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@@ -67,13 +67,13 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = memSpec->tFAW / clk;
memTimingSpec.RASB = memSpec->tRAS / clk;
memTimingSpec.RCB = memSpec->tRC / clk;
memTimingSpec.RPB = memSpec->tRP / clk;
memTimingSpec.RRDB = memSpec->tRRD / clk;
memTimingSpec.RRDB_L = memSpec->tRRD / clk;
memTimingSpec.RRDB_S = memSpec->tRRD / clk;
//FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / clk;
//FIXME: memTimingSpec.RCB = memSpec->tRC / clk;
//FIXME: memTimingSpec.RPB = memSpec->tRP / clk;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD / clk;
memTimingSpec.CCD_L = memSpec->tCCD / clk;

14
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
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@@ -67,13 +67,13 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = memSpec->tFAW / clk;
memTimingSpec.RASB = memSpec->tRAS / clk;
memTimingSpec.RCB = memSpec->tRC / clk;
memTimingSpec.RPB = memSpec->tRP / clk;
memTimingSpec.RRDB = memSpec->tRRD_S / clk;
memTimingSpec.RRDB_L = memSpec->tRRD_L / clk;
memTimingSpec.RRDB_S = memSpec->tRRD_S / clk;
//FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / clk;
//FIXME: memTimingSpec.RCB = memSpec->tRC / clk;
//FIXME: memTimingSpec.RPB = memSpec->tRP / clk;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / clk;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / clk;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD_S / clk;
memTimingSpec.CCD_L = memSpec->tCCD_L / clk;

14
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
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@@ -69,13 +69,13 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
memArchSpec.dll = false;
MemTimingSpec memTimingSpec;
memTimingSpec.FAWB = memSpec->tTAW / clk;
memTimingSpec.RASB = memSpec->tRAS / clk;
memTimingSpec.RCB = memSpec->tRC / clk;
memTimingSpec.RPB = memSpec->tRP / clk;
memTimingSpec.RRDB = memSpec->tRRD / clk;
memTimingSpec.RRDB_L = memSpec->tRRD / clk;
memTimingSpec.RRDB_S = memSpec->tRRD / clk;
//FIXME: memTimingSpec.FAWB = memSpec->tTAW / clk;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / clk;
//FIXME: memTimingSpec.RCB = memSpec->tRC / clk;
//FIXME: memTimingSpec.RPB = memSpec->tRP / clk;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk;
memTimingSpec.AL = 0;
memTimingSpec.CCD = memSpec->BurstLength;
memTimingSpec.CCD_L = memSpec->BurstLength;