From 757ec296cf916c7fc8d4dd17eecc1d47f07bd130 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 26 Feb 2020 00:01:27 +0100 Subject: [PATCH] FIXME: workaround for bankwise parameters. --- DRAMSys/library/src/simulation/dram/Dram.cpp | 3 ++- DRAMSys/library/src/simulation/dram/Dram.h | 2 +- DRAMSys/library/src/simulation/dram/DramDDR3.cpp | 14 +++++++------- DRAMSys/library/src/simulation/dram/DramDDR4.cpp | 14 +++++++------- DRAMSys/library/src/simulation/dram/DramWideIO.cpp | 14 +++++++------- 5 files changed, 24 insertions(+), 23 deletions(-) diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 9f5cb4ef..93877ee1 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -55,9 +55,10 @@ #include "../../common/protocol.h" #include "../../common/utils.h" #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../../common/third_party/DRAMPower/src/MemCommand.h" using namespace tlm; -using namespace Data; +using namespace DRAMPower; Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") { diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 119be3a8..e317768c 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -50,7 +50,7 @@ using namespace std; using namespace tlm; -using namespace Data; +using namespace DRAMPower; class Dram : public sc_module { diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index 55311aa5..bcdb03eb 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -67,13 +67,13 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) memArchSpec.dll = true; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = memSpec->tFAW / clk; - memTimingSpec.RASB = memSpec->tRAS / clk; - memTimingSpec.RCB = memSpec->tRC / clk; - memTimingSpec.RPB = memSpec->tRP / clk; - memTimingSpec.RRDB = memSpec->tRRD / clk; - memTimingSpec.RRDB_L = memSpec->tRRD / clk; - memTimingSpec.RRDB_S = memSpec->tRRD / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; + //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; + //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD / clk; memTimingSpec.CCD_L = memSpec->tCCD / clk; diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 08bc4b14..7fb03743 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -67,13 +67,13 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) memArchSpec.dll = true; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = memSpec->tFAW / clk; - memTimingSpec.RASB = memSpec->tRAS / clk; - memTimingSpec.RCB = memSpec->tRC / clk; - memTimingSpec.RPB = memSpec->tRP / clk; - memTimingSpec.RRDB = memSpec->tRRD_S / clk; - memTimingSpec.RRDB_L = memSpec->tRRD_L / clk; - memTimingSpec.RRDB_S = memSpec->tRRD_S / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; + //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; + //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / clk; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / clk; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / clk; memTimingSpec.AL = memSpec->tAL / clk; memTimingSpec.CCD = memSpec->tCCD_S / clk; memTimingSpec.CCD_L = memSpec->tCCD_L / clk; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index 232e3224..1ee85597 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -69,13 +69,13 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) memArchSpec.dll = false; MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = memSpec->tTAW / clk; - memTimingSpec.RASB = memSpec->tRAS / clk; - memTimingSpec.RCB = memSpec->tRC / clk; - memTimingSpec.RPB = memSpec->tRP / clk; - memTimingSpec.RRDB = memSpec->tRRD / clk; - memTimingSpec.RRDB_L = memSpec->tRRD / clk; - memTimingSpec.RRDB_S = memSpec->tRRD / clk; + //FIXME: memTimingSpec.FAWB = memSpec->tTAW / clk; + //FIXME: memTimingSpec.RASB = memSpec->tRAS / clk; + //FIXME: memTimingSpec.RCB = memSpec->tRC / clk; + //FIXME: memTimingSpec.RPB = memSpec->tRP / clk; + //FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk; + //FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk; memTimingSpec.AL = 0; memTimingSpec.CCD = memSpec->BurstLength; memTimingSpec.CCD_L = memSpec->BurstLength;