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Resolve "Prepare CI Testing"

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This commit is contained in:
Matthias Jung
2018-11-09 21:36:45 +01:00
parent 7da3358006
commit 716ffbc062
4 changed files with 64 additions and 1 deletions
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2
DRAMSys/library/resources/configs/simulator/ddr3.xml
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@@ -9,7 +9,7 @@
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<CheckTLM2Protocol value = "1" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />

9
DRAMSys/tests/DDR3/ci.yml
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@@ -6,7 +6,16 @@ example_ddr3:
- ls
- sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb
- perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
- cd ../traceAnalyzer
- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-example_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
artifacts:
paths:
- build/simulator/ddr3-example_ddr3_ch0.tdb
expire_in: 2 days
protocol_checker:
stage: DDR3
script:
- cd build/simulator
- ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml ../../DRAMSys/tests/DDR3/
- echo "TODO"

29
DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml Normal file
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@@ -0,0 +1,29 @@
<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "1" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
<UseMalloc value="0" />
</simconfig>

25
DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml Normal file
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@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-protocol_checker"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3-protocol_checker.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>