diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.xml b/DRAMSys/library/resources/configs/simulator/ddr3.xml
index 1613737f..3efbabe7 100644
--- a/DRAMSys/library/resources/configs/simulator/ddr3.xml
+++ b/DRAMSys/library/resources/configs/simulator/ddr3.xml
@@ -9,7 +9,7 @@
     <SimulationProgressBar value="1"/>
     <NumberOfMemChannels value="1"/>
     <NumberOfDevicesOnDIMM value = "8" />
-    <CheckTLM2Protocol value = "0" />
+    <CheckTLM2Protocol value = "1" />
     <AddressOffset value = "0" />
     <ECCControllerMode value = "Disabled" />
     <ErrorChipSeed value="42" />
diff --git a/DRAMSys/tests/DDR3/ci.yml b/DRAMSys/tests/DDR3/ci.yml
index 07145b0b..3e782ac6 100644
--- a/DRAMSys/tests/DDR3/ci.yml
+++ b/DRAMSys/tests/DDR3/ci.yml
@@ -6,7 +6,16 @@ example_ddr3:
         - ls
         - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb
         - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
+        - cd ../traceAnalyzer
+        - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-example_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
     artifacts:
         paths:
           - build/simulator/ddr3-example_ddr3_ch0.tdb
         expire_in: 2 days
+
+protocol_checker:
+    stage: DDR3
+    script:
+        - cd build/simulator
+        - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml ../../DRAMSys/tests/DDR3/
+        - echo "TODO"
diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml
new file mode 100644
index 00000000..3efbabe7
--- /dev/null
+++ b/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml
@@ -0,0 +1,29 @@
+<simconfig>
+    <SimulationName value="ddr3" />
+    <Debug value="0" />
+    <DatabaseRecording value="1" />
+    <PowerAnalysis value="1" />
+    <EnableWindowing value = "1" />
+    <WindowSize value="1000" />
+    <ThermalSimulation value="0"/>
+    <SimulationProgressBar value="1"/>
+    <NumberOfMemChannels value="1"/>
+    <NumberOfDevicesOnDIMM value = "8" />
+    <CheckTLM2Protocol value = "1" />
+    <AddressOffset value = "0" />
+    <ECCControllerMode value = "Disabled" />
+    <ErrorChipSeed value="42" />
+    <ErrorCSVFile value="" />
+    <!-- Modes:
+	- NoStorage,
+	- Store (store data without errormodel),
+	- ErrorModel (store data with errormodel)
+    -->
+    <StoreMode value="NoStorage" />
+    <!-- Gem5 Related Configuration:
+    In the memory controller file the storage mode should be set to Store
+    E.g. the DRAM is located at 0x80000000 for gem5
+    <AddressOffset value = "2147483648" />
+    -->
+    <UseMalloc value="0" />
+</simconfig>
diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml
new file mode 100644
index 00000000..ececf822
--- /dev/null
+++ b/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml
@@ -0,0 +1,25 @@
+<simulation>
+    <!-- Simulation file identifier -->
+    <simulationid id="ddr3-protocol_checker"></simulationid>
+    <!-- Configuration for the DRAMSys Simulator -->
+    <simconfig src="ddr3-protocol_checker.xml" />
+    <!-- Temperature Simulator Configuration -->
+    <thermalconfig src="config.xml" />
+    <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
+    <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
+    <!-- Addressmapping Configuration of the Memory Controller -->
+    <addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
+    <!-- Memory Controller Configuration: -->
+    <mcconfig src="fifoStrict.xml"/>
+    <!--
+    The following trace setup is only used in standalone mode.
+    In library mode e.g. in Platform Architect the trace setup is ignored.
+    -->
+    <tracesetup>
+        <!--
+        This device mimics an image processing application
+        running on an FPGA with 200 Mhz.
+        -->
+        <device clkMhz="200">ddr3_example.stl</device>
+    </tracesetup>
+</simulation>