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Fix HBM2 pseudo channel BW calculation.

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This commit is contained in:
Lukas Steiner
2022-03-04 10:39:28 +01:00
parent 986311a4d0
commit 6d4ad11204
29 changed files with 80 additions and 57 deletions
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30
DRAMSys/library/src/common/configuration/AddressMapping.cpp
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@@ -46,11 +46,11 @@ void to_json(json &j, const AddressMapping &m)
congen = json{{"BYTE_BIT", m.byteBits},
{"COLUMN_BIT", m.columnBits},
{"ROW_BIT", m.rowBits},
{"BANK_BIT", m.bankBits},
{"BANKGROUP_BIT", m.bankGroupBits},
{"ROW_BIT", m.rowBits},
{"CHANNEL_BIT", m.channelBits},
{"RANK_BIT", m.rankBits},
{"CHANNEL_BIT", m.channelBits},
{"XOR", m.xorBits}};
remove_null_values(congen);
@@ -68,27 +68,31 @@ void from_json(const json &j, AddressMapping &m)
else
congen = j_addressmapping["CONGEN"];
if (congen.contains("BYTE_BIT"))
congen.at("BYTE_BIT").get_to(m.byteBits);
if (congen.contains("COLUMN_BIT"))
congen.at("COLUMN_BIT").get_to(m.columnBits);
if (congen.contains("BANK_BIT"))
congen.at("BANK_BIT").get_to(m.bankBits);
if (congen.contains("ROW_BIT"))
congen.at("ROW_BIT").get_to(m.rowBits);
if (congen.contains("RANK_BIT"))
congen.at("RANK_BIT").get_to(m.rankBits);
if (congen.contains("CHANNEL_BIT"))
congen.at("CHANNEL_BIT").get_to(m.channelBits);
if (congen.contains("BYTE_BIT"))
congen.at("BYTE_BIT").get_to(m.byteBits);
if (congen.contains("BANK_BIT"))
congen.at("BANK_BIT").get_to(m.bankBits);
if (congen.contains("BANKGROUP_BIT"))
congen.at("BANKGROUP_BIT").get_to(m.bankGroupBits);
if (congen.contains("RANK_BIT"))
congen.at("RANK_BIT").get_to(m.rankBits);
// HBM pseudo channels are internally modelled as ranks
if (congen.contains("PSEUDOCHANNEL_BIT"))
congen.at("PSEUDOCHANNEL_BIT").get_to(m.rankBits);
if (congen.contains("CHANNEL_BIT"))
congen.at("CHANNEL_BIT").get_to(m.channelBits);
if (congen.contains("XOR"))
congen.at("XOR").get_to(m.xorBits);
}

6
DRAMSys/library/src/common/configuration/AddressMapping.h
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@@ -60,11 +60,11 @@ struct AddressMapping
{
std::optional<std::vector<unsigned int>> byteBits;
std::optional<std::vector<unsigned int>> columnBits;
std::optional<std::vector<unsigned int>> rowBits;
std::optional<std::vector<unsigned int>> bankBits;
std::optional<std::vector<unsigned int>> bankGroupBits;
std::optional<std::vector<unsigned int>> rowBits;
std::optional<std::vector<unsigned int>> channelBits;
std::optional<std::vector<unsigned int>> rankBits;
std::optional<std::vector<unsigned int>> channelBits;
std::optional<std::vector<XorPair>> xorBits;
};
@@ -76,4 +76,4 @@ std::string dump(const AddressMapping &c, unsigned int indentation = -1);
} // namespace Configuration
#endif // ADDRESSMAPPING_H
#endif // DRAMSYSCONFIGURATION_ADDRESSMAPPING_H

2
DRAMSys/library/src/common/configuration/McConfig.h
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@@ -180,4 +180,4 @@ std::string dump(const McConfig &c, unsigned int indentation = -1);
} // namespace Configuration
#endif // MCCONFIG_H
#endif // DRAMSYSCONFIGURATION_MCCONFIG_H

2
DRAMSys/library/src/common/configuration/SimConfig.h
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@@ -86,4 +86,4 @@ std::string dump(const SimConfig &c, unsigned int indentation = -1);
} // namespace Configuration
#endif
#endif // DRAMSYSCONFIGURATION_SIMCONFIG_H

2
DRAMSys/library/src/common/configuration/ThermalConfig.h
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@@ -117,4 +117,4 @@ std::string dump(const ThermalConfig &c, unsigned int indentation = -1);
} // namespace Configuration
#endif // THERMALCONFIG_H
#endif // DRAMSYSCONFIGURATION_THERMALCONFIG_H

2
DRAMSys/library/src/common/configuration/TraceSetup.h
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@@ -141,4 +141,4 @@ std::string dump(const TraceSetup &c, unsigned int indentation = -1);
} // namespace Configuration
#endif
#endif // DRAMSYSCONFIGURATION_TRACESETUP_H

2
DRAMSys/library/src/common/configuration/memspec/MemArchitectureSpec.h
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@@ -53,4 +53,4 @@ void from_json(const json &j, MemArchitectureSpec &c);
} // namespace Configuration
#endif
#endif // DRAMSYSCONFIGURATION_MEMARCHITECTURESPEC_H

2
DRAMSys/library/src/common/configuration/memspec/MemPowerSpec.h
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@@ -53,4 +53,4 @@ void from_json(const json &j, MemPowerSpec &c);
} // namespace Configuration
#endif
#endif // DRAMSYSCONFIGURATION_MEMPOWERSPEC_H

2
DRAMSys/library/src/common/configuration/memspec/MemTimingSpec.h
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@@ -53,4 +53,4 @@ void from_json(const json &j, MemTimingSpec &c);
} // namespace Configuration
#endif
#endif // DRAMSYSCONFIGURATION_MEMTIMINGSPEC_H

2
DRAMSys/library/src/common/configuration/util.h
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@@ -141,4 +141,4 @@ void from_json(const nlohmann::json &j, std::optional<T> &v)
} // namespace nlohmann
#endif
#endif // DRAMSYSCONFIGURATION_UTIL_H

4
DRAMSys/library/src/common/utils.cpp
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@@ -80,7 +80,7 @@ void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank ra
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_streaming_width(0);
payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank, bankGroup, bank, Row(0), Column(0),
0, 0, channelPayloadID));
payload.set_extension(new DramExtension(Thread(UINT_MAX), Channel(0), rank,
bankGroup, bank, Row(0), Column(0), 0, 0, channelPayloadID));
payload.set_extension(new GenerationExtension(SC_ZERO_TIME));
}

3
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
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@@ -41,12 +41,13 @@ using namespace tlm;
MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
MemoryType memoryType,
unsigned numberOfChannels,
unsigned numberOfChannels, unsigned pseudoChannelsPerChannel,
unsigned ranksPerChannel, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned banksPerChannel, unsigned bankGroupsPerChannel,
unsigned devicesPerRank)
: numberOfChannels(numberOfChannels),
pseudoChannelsPerChannel(pseudoChannelsPerChannel),
ranksPerChannel(ranksPerChannel),
banksPerRank(banksPerRank),
groupsPerRank(groupsPerRank),

3
DRAMSys/library/src/configuration/memspec/MemSpec.h
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@@ -51,6 +51,7 @@ class MemSpec
{
public:
const unsigned numberOfChannels;
const unsigned pseudoChannelsPerChannel;
const unsigned ranksPerChannel;
const unsigned banksPerRank;
const unsigned groupsPerRank;
@@ -100,7 +101,7 @@ public:
protected:
MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
MemoryType memoryType,
unsigned numberOfChannels,
unsigned numberOfChannels, unsigned pseudoChannelsPerChannel,
unsigned ranksPerChannel, unsigned banksPerRank,
unsigned groupsPerRank, unsigned banksPerGroup,
unsigned banksPerChannel, unsigned bankGroupsPerChannel,

3
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecDDR3::MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR3,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
1,
@@ -105,7 +106,7 @@ MemSpecDDR3::MemSpecDDR3(const DRAMSysConfiguration::MemSpec &memSpec)
std::cout << " Memory type: " << "DDR3" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;

3
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecDDR4::MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR4,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
@@ -123,7 +124,7 @@ MemSpecDDR4::MemSpecDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
std::cout << " Memory type: " << "DDR4" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;

1
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecDDR5::MemSpecDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::DDR5,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),

1
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
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@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecGDDR5::MemSpecGDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::GDDR5,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),

1
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -44,6 +44,7 @@ using namespace tlm;
MemSpecGDDR5X::MemSpecGDDR5X(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::GDDR5X,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),

1
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
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@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecGDDR6::MemSpecGDDR6(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::GDDR6,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at( "nbrOfBankGroups"),

30
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -45,15 +45,16 @@ using namespace tlm;
MemSpecHBM2::MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::HBM2,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
@@ -93,18 +94,17 @@ MemSpecHBM2::MemSpecHBM2(const DRAMSysConfiguration::MemSpec &memSpec)
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "HBM2" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per rank: " << groupsPerRank << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << " Devices per rank: " << devicesPerRank << std::endl;
std::cout << " Memory type: " << "HBM2" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl;
std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl;
std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl;
std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
}

1
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
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@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecLPDDR4::MemSpecLPDDR4(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::LPDDR4,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
1,

1
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
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@@ -44,6 +44,7 @@ using namespace tlm;
MemSpecLPDDR5::MemSpecLPDDR5(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::LPDDR5,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),

1
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
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@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecSTTMRAM::MemSpecSTTMRAM(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::STTMRAM,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
1,

1
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
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@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecWideIO::MemSpecWideIO(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::WideIO,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
1,

1
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
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@@ -45,6 +45,7 @@ using namespace tlm;
MemSpecWideIO2::MemSpecWideIO2(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::WideIO2,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
1,
memSpec.memArchitectureSpec.entries.at("nbrOfRanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
1,

11
DRAMSys/library/src/controller/ControllerIF.h
View File

@@ -57,9 +57,10 @@ public:
// Destructor
~ControllerIF() override
{
sc_core::sc_time activeTime = numberOfBeatsServed
sc_core::sc_time activeTime = static_cast<double>(numberOfBeatsServed)
/ Configuration::getInstance().memSpec->dataRate
* Configuration::getInstance().memSpec->tCK;
* Configuration::getInstance().memSpec->tCK
/ Configuration::getInstance().memSpec->pseudoChannelsPerChannel;
double bandwidth = activeTime / sc_core::sc_time_stamp();
double bandwidthWoIdle = activeTime / (sc_core::sc_time_stamp() - idleTimeCollector.getIdleTime());
@@ -71,8 +72,10 @@ public:
* Configuration::getInstance().memSpec->dataRate
// BusWidth e.g. 8 or 64
* Configuration::getInstance().memSpec->bitWidth
// Number of devices on a DIMM e.g. 8
* Configuration::getInstance().memSpec->devicesPerRank );
// Number of devices that form a rank, e.g., 8 on a DDR3 DIMM
* Configuration::getInstance().memSpec->devicesPerRank
// HBM specific, one or two pseudo channels per channel
* Configuration::getInstance().memSpec->pseudoChannelsPerChannel);
std::cout << name() << std::string(" Total Time: ")
<< sc_core::sc_time_stamp().to_string()

10
DRAMSys/library/src/simulation/AddressDecoder.cpp
View File

@@ -98,14 +98,16 @@ AddressDecoder::AddressDecoder(const DRAMSysConfiguration::AddressMapping &addre
unsigned columns = std::lround(std::pow(2.0, vColumnBits.size()));
unsigned bytes = std::lround(std::pow(2.0, vByteBits.size()));
maximumAddress = static_cast<uint64_t>(bytes) * columns * rows * banks * bankGroups * ranks * channels - 1;
banksPerGroup = banks;
banks = banksPerGroup * bankGroups * ranks;
maximumAddress = static_cast<uint64_t>(bytes) * columns * rows * banks
* bankGroups * ranks * channels - 1;
bankgroupsPerRank = bankGroups;
bankGroups = bankgroupsPerRank * ranks;
banksPerGroup = banks;
banks = banksPerGroup * bankGroups;
Configuration &config = Configuration::getInstance();
const MemSpec *memSpec = config.memSpec;

5
DRAMSys/library/src/simulation/AddressDecoder.h
View File

@@ -48,8 +48,9 @@ struct DecodedAddress
DecodedAddress(unsigned channel, unsigned rank,
unsigned bankgroup, unsigned bank,
unsigned row, unsigned column, unsigned bytes)
: channel(channel), rank(rank), bankgroup(bankgroup),
bank(bank), row(row), column(column), byte(bytes) {}
: channel(channel), rank(rank),
bankgroup(bankgroup), bank(bank),
row(row), column(column), byte(bytes) {}
DecodedAddress()
: channel(0), rank(0), bankgroup(0),

4
DRAMSys/library/src/simulation/Arbiter.cpp
View File

@@ -143,8 +143,8 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload,
payload.set_address(adjustedAddress);
DecodedAddress decodedAddress = addressDecoder->decodeAddress(adjustedAddress);
DramExtension::setExtension(payload, Thread(static_cast<unsigned int>(id)),
Channel(decodedAddress.channel), Rank(decodedAddress.rank),
DramExtension::setExtension(payload, Thread(static_cast<unsigned int>(id)), Channel(decodedAddress.channel),
Rank(decodedAddress.rank),
BankGroup(decodedAddress.bankgroup), Bank(decodedAddress.bank),
Row(decodedAddress.row), Column(decodedAddress.column),
payload.get_data_length() / bytesPerBeat, 0, 0);