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Merge remote-tracking branch 'origin/develop' into feat/internal_length_conv2

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# Conflicts:
#	DRAMSys/library/src/common/TlmRecorder.cpp
#	DRAMSys/library/src/controller/Command.cpp
#	DRAMSys/library/src/controller/Command.h
#	DRAMSys/library/src/controller/Controller.cpp
#	DRAMSys/library/src/simulation/dram/DramRecordable.cpp
#	DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
#	DRAMSys/traceAnalyzer/data/tracedb.cpp
This commit is contained in:
Lukas Steiner
2022-08-05 13:50:42 +02:00
parent e739dd2413 4b4359ffb6
commit 6ad4a053c9
94 changed files with 2339 additions and 659 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
DRAMSys/gem5/CMakeLists.txt
View File

@@ -37,7 +37,7 @@ set(GEM5_VARIANT opt) # opt, fast
set(GEM5_ISA ARM) # ARM, X86
# Configuration:
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version")
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
find_library(GEM5_LIBRARY gem5_${GEM5_VARIANT} PATHS $ENV{GEM5}/build/${GEM5_ISA}/)

175
DRAMSys/library/CMakeLists.txt
View File

@@ -39,11 +39,15 @@ cmake_minimum_required(VERSION 3.10)
project(DRAMSysLibrary)
# Configuration:
set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version")
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
option(DRAMSYS_WITH_DRAMPOWER "Build with DRAMPower support enabled." ON)
# Add DRAMPower:
if (DRAMSYS_WITH_DRAMPOWER)
add_subdirectory(src/common/third_party/DRAMPower)
endif()
# Add Configuration
add_subdirectory(src/common/configuration)
@@ -77,6 +81,33 @@ if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/common/third_party/sqlite-amalgamation)
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerDDR5.cpp)
message("== DDR5 included")
set(DDR5_SOURCES
src/configuration/memspec/MemSpecDDR5.cpp
src/controller/checker/CheckerDDR5.cpp
src/simulation/dram/DramDDR5.cpp
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerLPDDR5.cpp)
message("== LPDDR5 included")
set(LPDDR5_SOURCES
src/configuration/memspec/MemSpecLPDDR5.cpp
src/controller/checker/CheckerLPDDR5.cpp
src/simulation/dram/DramLPDDR5.cpp
)
endif()
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/controller/checker/CheckerHBM3.cpp)
message("== HBM3 included")
set(HBM3_SOURCES
src/configuration/memspec/MemSpecHBM3.cpp
src/controller/checker/CheckerHBM3.cpp
src/simulation/dram/DramHBM3.cpp
)
endif()
add_library(DRAMSysLibrary
src/common/DebugManager.cpp
src/common/dramExtensions.cpp
@@ -89,9 +120,7 @@ add_library(DRAMSysLibrary
src/configuration/memspec/MemSpec.cpp
src/configuration/memspec/MemSpecDDR3.cpp
src/configuration/memspec/MemSpecDDR4.cpp
src/configuration/memspec/MemSpecDDR5.cpp
src/configuration/memspec/MemSpecLPDDR4.cpp
src/configuration/memspec/MemSpecLPDDR5.cpp
src/configuration/memspec/MemSpecWideIO.cpp
src/configuration/memspec/MemSpecWideIO2.cpp
src/configuration/memspec/MemSpecGDDR5.cpp
@@ -108,9 +137,7 @@ add_library(DRAMSysLibrary
src/controller/checker/CheckerIF.h
src/controller/checker/CheckerDDR3.cpp
src/controller/checker/CheckerDDR4.cpp
src/controller/checker/CheckerDDR5.cpp
src/controller/checker/CheckerLPDDR4.cpp
src/controller/checker/CheckerLPDDR5.cpp
src/controller/checker/CheckerWideIO.cpp
src/controller/checker/CheckerWideIO2.cpp
src/controller/checker/CheckerGDDR5.cpp
@@ -166,10 +193,8 @@ add_library(DRAMSysLibrary
src/simulation/dram/Dram.cpp
src/simulation/dram/DramDDR3.cpp
src/simulation/dram/DramDDR4.cpp
src/simulation/dram/DramDDR5.cpp
src/simulation/dram/DramDDR4.cpp
src/simulation/dram/DramLPDDR4.cpp
src/simulation/dram/DramLPDDR5.cpp
src/simulation/dram/DramWideIO.cpp
src/simulation/dram/DramWideIO2.cpp
src/simulation/dram/DramGDDR5.cpp
@@ -179,116 +204,23 @@ add_library(DRAMSysLibrary
src/simulation/dram/DramSTTMRAM.cpp
${RECORDING_SOURCES}
# Simulation Config Files
resources/simulations/ddr3-example.json
resources/simulations/ddr3-example2.json
resources/simulations/ddr3-gem5-se.json
resources/simulations/ddr4-example.json
resources/simulations/hbm2-example.json
resources/simulations/lpddr4-example.json
resources/simulations/ranktest.json
resources/simulations/wideio-example.json
resources/simulations/wideio-thermal.json
# Address Mapping Config Files
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json
resources/configs/amconfigs/am_ddr3_x16_brc.json
resources/configs/amconfigs/am_ddr3_x16_rbc.json
resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
resources/configs/amconfigs/am_ranktest.json
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x1Gb_brc.json
resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x256Mb_brc.json
resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json
resources/configs/amconfigs/am_wideio_4x2Gb_brc.json
resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x4Gb_brc.json
resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x512Mb_brc.json
resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json
# Memory Controller Config Files
resources/configs/mcconfigs/fifo.json
resources/configs/mcconfigs/fifoStrict.json
resources/configs/mcconfigs/fr_fcfs_grp.json
resources/configs/mcconfigs/fr_fcfs.json
# Memspec Config Files
resources/configs/memspecs/HBM2.json
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
resources/configs/memspecs/memspec_ranktest.json
resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
# Simulator Config Files
resources/configs/simulator/ddr3_ecc.json
resources/configs/simulator/ddr3.json
resources/configs/simulator/ddr3_gem5_se.json
resources/configs/simulator/ddr4.json
resources/configs/simulator/hbm2.json
resources/configs/simulator/lpddr4.json
resources/configs/simulator/wideio.json
resources/configs/simulator/wideio_thermal.json
# Thermal Simulation Config Files
resources/configs/thermalsim/config.json
resources/configs/thermalsim/powerInfo.json
${DDR5_SOURCES}
${LPDDR5_SOURCES}
${HBM3_SOURCES}
)
if(DEFINED DDR5_SOURCES)
target_compile_definitions(DRAMSysLibrary PRIVATE DDR5_SIM)
endif()
if(DEFINED LPDDR5_SOURCES)
target_compile_definitions(DRAMSysLibrary PRIVATE LPDDR5_SIM)
endif()
if(DEFINED HBM3_SOURCES)
target_compile_definitions(DRAMSysLibrary PRIVATE HBM3_SIM)
endif()
if(DEFINED ENV{LIBTHREED_ICE_HOME})
message("== Thermal simulation available")
target_compile_definitions(DRAMSysLibrary PRIVATE THERMALSIM)
@@ -312,7 +244,7 @@ endif()
# Build:
target_include_directories(DRAMSysLibrary
PUBLIC src/common/third_party/DRAMPower/src/
PRIVATE src/common/third_party/DRAMPower/src/
PUBLIC $ENV{SYSTEMC_HOME}/include/
)
@@ -324,6 +256,13 @@ endif()
target_link_libraries(DRAMSysLibrary
PUBLIC ${SYSTEMC_LIBRARY}
PRIVATE DRAMPower
PUBLIC DRAMSysConfiguration
)
if (DRAMSYS_WITH_DRAMPOWER)
target_compile_definitions(DRAMSysLibrary PRIVATE DRAMPOWER)
target_link_libraries(DRAMSysLibrary
PRIVATE DRAMPower
)
endif()

45
DRAMSys/library/resources/configs/amconfigs/am_hbm3_8Gb_pc_brc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"PSEUDOCHANNEL_BIT":[
28
],
"BANKGROUP_BIT":[
26,
27
],
"BANK_BIT": [
24,
25
],
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8
],
"ROW_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

56
DRAMSys/library/resources/configs/memspecs/HBM3.json Normal file
View File

@@ -0,0 +1,56 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 4,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 128,
"nbrOfPseudoChannels": 2,
"nbrOfRows": 32768,
"width": 32,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
},
"memoryId": "",
"memoryType": "HBM3",
"memtimingspec": {
"CCDL": 4,
"CCDS": 2,
"CKE": 8,
"DQSCK": 1,
"FAW": 16,
"PL": 0,
"PPD": 2,
"RAS": 28,
"RC": 42,
"RCDRD": 12,
"RCDWR": 6,
"REFI": 3900,
"REFIPB": 122,
"RFC": 260,
"RFCPB": 96,
"RL": 17,
"RP": 14,
"RRDL": 6,
"RRDS": 4,
"RREFD": 8,
"RTP": 5,
"RTW": 18,
"WL": 12,
"WR": 23,
"WTRL": 9,
"WTRS": 4,
"XP": 8,
"XS": 260,
"clkMhz": 1600
},
"memtimingspec_comments": {
"Annahme": "8-high, 8Gb/die",
"RFCPB": "TBD?"
}
}
}

19
DRAMSys/library/resources/configs/simulator/hbm3.json Normal file
View File

@@ -0,0 +1,19 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "hbm3",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

16
DRAMSys/library/resources/simulations/hbm3-example.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_hbm3_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM3.json",
"simconfig": "hbm3.json",
"simulationid": "hbm3-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "ddr3_example.stl"
}
]
}
}

42
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -39,12 +39,13 @@
* Derek Christ
*/
#include <fstream>
#include "TlmRecorder.h"
#include "DebugManager.h"
#include "../controller/Command.h"
#include "../configuration/Configuration.h"
#include "../controller/Command.h"
#include "DebugManager.h"
#include <fstream>
#include <sqlite3.h>
using namespace sc_core;
using namespace tlm;
@@ -270,7 +271,20 @@ void TlmRecorder::terminateRemainingTransactions()
removeTransactionFromSystem(*transaction->first);
}
else
recordPhase(*(transaction->first), END_RESP, SC_ZERO_TIME);
{
std::string beginPhase = transaction->second.recordedPhases.back().name;
if (beginPhase == "RESP")
recordPhase(*(transaction->first), END_RESP, SC_ZERO_TIME);
else
{
// Do not terminate transaction as it is not ready to be completed.
currentTransactionsInSystem.erase(transaction);
// Decrement totalNumTransactions as this transaction will not be recorded in the database.
totalNumTransactions--;
}
}
}
}
@@ -396,21 +410,14 @@ void TlmRecorder::insertGeneralInfo()
const MemSpec& memSpec = *config.memSpec;
const auto memoryType = memSpec.memoryType;
bool rowColumnCommandBus = [memoryType]() -> bool {
if (memoryType == MemSpec::MemoryType::HBM2)
return true;
else
return false;
}();
bool rowColumnCommandBus = (memoryType == MemSpec::MemoryType::HBM2) || (memoryType == MemSpec::MemoryType::HBM3);
bool pseudoChannelMode = [&memSpec, memoryType]() -> bool {
if (memoryType != MemSpec::MemoryType::HBM2)
if (memoryType != MemSpec::MemoryType::HBM2 && memoryType != MemSpec::MemoryType::HBM3)
return false;
if (memSpec.pseudoChannelsPerChannel != 1)
return true;
else
return false;
return memSpec.pseudoChannelsPerChannel != 1;
}();
sqlite3_bind_int(insertGeneralInfoStatement, 17, static_cast<int>(rowColumnCommandBus));
@@ -426,8 +433,7 @@ void TlmRecorder::insertCommandLengths()
auto commandName = command.toString();
sqlite3_bind_text(insertCommandLengthsStatement, 1, commandName.c_str(), commandName.length(), nullptr);
sqlite3_bind_int(insertCommandLengthsStatement, 2,
static_cast<int>(lround(memSpec.getCommandLength(command) / memSpec.tCK)));
sqlite3_bind_double(insertCommandLengthsStatement, 2, memSpec.getCommandLengthInCylcles(command));
executeSqlStatement(insertCommandLengthsStatement);
};

14
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -42,17 +42,19 @@
#define TLMRECORDER_H
#include <string>
#include <systemc>
#include <thread>
#include <tlm>
#include <unordered_map>
#include <utility>
#include <vector>
#include <thread>
#include <systemc>
#include <tlm>
#include "sqlite3.h"
#include "../configuration/Configuration.h"
#include "dramExtensions.h"
#include "utils.h"
#include "../configuration/Configuration.h"
class sqlite3;
class sqlite3_stmt;
class TlmRecorder
{
@@ -222,7 +224,7 @@ private:
" \n"
"CREATE TABLE CommandLengths( \n"
" Command TEXT, \n"
" Length INTEGER \n"
" Length DOUBLE \n"
"); \n"
" \n"
"CREATE TABLE Power( \n"

10
DRAMSys/library/src/common/configuration/CMakeLists.txt
View File

@@ -33,16 +33,16 @@
set(JSON_BuildTests OFF CACHE INTERNAL "")
set(JSON_ImplicitConversions OFF CACHE INTERNAL "")
add_subdirectory(${CMAKE_SOURCE_DIR}/library/src/common/third_party/nlohmann ${CMAKE_CURRENT_BINARY_DIR}/nlohmann)
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../third_party/nlohmann ${CMAKE_CURRENT_BINARY_DIR}/nlohmann)
option(DRAMSYS_CONFIGURATION_TESTS "Build the unit tests for configuration." OFF)
if (DRAMSYS_CONFIGURATION_TESTS)
add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/tests)
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/tests)
endif()
add_library(DRAMSysConfiguration STATIC
Configuration.cpp
DRAMSysConfiguration.cpp
AddressMapping.cpp
McConfig.cpp
SimConfig.cpp
@@ -55,8 +55,8 @@ add_library(DRAMSysConfiguration STATIC
util.cpp
)
target_compile_definitions(DRAMSysConfiguration PUBLIC DRAMSysResourceDirectory="${CMAKE_SOURCE_DIR}/library/resources")
target_compile_definitions(DRAMSysConfiguration PUBLIC DRAMSysResourceDirectory="${CMAKE_CURRENT_LIST_DIR}/../../../resources")
target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
target_include_directories(DRAMSysConfiguration PUBLIC ${CMAKE_CURRENT_LIST_DIR})
target_link_libraries(DRAMSysConfiguration PUBLIC nlohmann_json::nlohmann_json)

2
DRAMSys/library/src/common/configuration/Configuration.cpp → DRAMSys/library/src/common/configuration/DRAMSysConfiguration.cpp
View File

@@ -33,7 +33,7 @@
* Derek Christ
*/
#include "Configuration.h"
#include "DRAMSysConfiguration.h"
#include <exception>
#include <fstream>

6
DRAMSys/library/src/common/configuration/Configuration.h → DRAMSys/library/src/common/configuration/DRAMSysConfiguration.h
View File

@@ -33,8 +33,8 @@
* Derek Christ
*/
#ifndef DRAMSYSCONFIGURATION_CONFIGURATION_H
#define DRAMSYSCONFIGURATION_CONFIGURATION_H
#ifndef DRAMSYSCONFIGURATION_DRAMSYSCONFIGURATION_H
#define DRAMSYSCONFIGURATION_DRAMSYSCONFIGURATION_H
#include "AddressMapping.h"
#include "McConfig.h"
@@ -85,4 +85,4 @@ Configuration from_path(const std::string &path, const std::string &resourceDire
} // namespace DRAMSysConfiguration
#endif // DRAMSYSCONFIGURATION_CONFIGURATION_H
#endif // DRAMSYSCONFIGURATION_DRAMSYSCONFIGURATION_H

8
DRAMSys/library/src/common/configuration/McConfig.cpp
View File

@@ -34,7 +34,7 @@
*/
#include "McConfig.h"
#include <iostream>
namespace DRAMSysConfiguration
{
@@ -54,7 +54,7 @@ void to_json(json &j, const McConfig &c)
{"PowerDownPolicy", c.powerDownPolicy},
{"Arbiter", c.arbiter},
{"MaxActiveTransactions", c.maxActiveTransactions},
{"RefreshManagment", c.refreshManagement},
{"RefreshManagement", c.refreshManagement},
{"ArbitrationDelayFw", c.arbitrationDelayFw},
{"ArbitrationDelayBw", c.arbitrationDelayBw},
{"ThinkDelayFw", c.thinkDelayFw},
@@ -111,8 +111,8 @@ void from_json(const json &j, McConfig &c)
if (j_mcconfig.contains("MaxActiveTransactions"))
j_mcconfig.at("MaxActiveTransactions").get_to(c.maxActiveTransactions);
if (j_mcconfig.contains("RefreshManagment"))
j_mcconfig.at("RefreshManagment").get_to(c.refreshManagement);
if (j_mcconfig.contains("RefreshManagement"))
j_mcconfig.at("RefreshManagement").get_to(c.refreshManagement);
if (j_mcconfig.contains("ArbitrationDelayFw"))
j_mcconfig.at("ArbitrationDelayFw").get_to(c.arbitrationDelayFw);

2
DRAMSys/library/src/common/configuration/tests/converter.cpp
View File

@@ -36,7 +36,7 @@
#include <nlohmann/json.hpp>
#include <fstream>
#include <iostream>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
int main(int argc, char **argv)
{

2
DRAMSys/library/src/common/configuration/tests/simpletest.cpp
View File

@@ -33,7 +33,7 @@
* Derek Christ
*/
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <fstream>
#include <iostream>

2
DRAMSys/library/src/common/configuration/util.cpp
View File

@@ -34,7 +34,7 @@
*/
#include "util.h"
#include "Configuration.h"
#include "DRAMSysConfiguration.h"
#include <fstream>
#include <iostream>

28
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -42,10 +42,8 @@
#include "Configuration.h"
#include "memspec/MemSpecDDR3.h"
#include "memspec/MemSpecDDR4.h"
#include "memspec/MemSpecDDR5.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecLPDDR5.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
@@ -53,6 +51,16 @@
#include "memspec/MemSpecGDDR6.h"
#include "memspec/MemSpecSTTMRAM.h"
#ifdef DDR5_SIM
#include "memspec/MemSpecDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "memspec/MemSpecLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "memspec/MemSpecHBM3.h"
#endif
using namespace sc_core;
enum sc_time_unit string2TimeUnit(const std::string &s)
@@ -325,12 +333,8 @@ void Configuration::loadMemSpec(const DRAMSysConfiguration::MemSpec &memSpecConf
memSpec = std::make_unique<const MemSpecDDR3>(memSpecConfig);
else if (memoryType == "DDR4")
memSpec = std::make_unique<const MemSpecDDR4>(memSpecConfig);
else if (memoryType == "DDR5")
memSpec = std::make_unique<const MemSpecDDR5>(memSpecConfig);
else if (memoryType == "LPDDR4")
memSpec = std::make_unique<const MemSpecLPDDR4>(memSpecConfig);
else if (memoryType == "LPDDR5")
memSpec = std::make_unique<const MemSpecLPDDR5>(memSpecConfig);
else if (memoryType == "WIDEIO_SDR")
memSpec = std::make_unique<const MemSpecWideIO>(memSpecConfig);
else if (memoryType == "WIDEIO2")
@@ -345,6 +349,18 @@ void Configuration::loadMemSpec(const DRAMSysConfiguration::MemSpec &memSpecConf
memSpec = std::make_unique<const MemSpecGDDR6>(memSpecConfig);
else if (memoryType == "STT-MRAM")
memSpec = std::make_unique<const MemSpecSTTMRAM>(memSpecConfig);
#ifdef DDR5_SIM
else if (memoryType == "DDR5")
memSpec = std::make_unique<const MemSpecDDR5>(memSpecConfig);
#endif
#ifdef LPDDR5_SIM
else if (memoryType == "LPDDR5")
memSpec = std::make_unique<const MemSpecLPDDR5>(memSpecConfig);
#endif
#ifdef HBM3_SIM
else if (memoryType == "HBM3")
memSpec = std::make_unique<const MemSpecHBM3>(memSpecConfig);
#endif
else
SC_REPORT_FATAL("Configuration", "Unsupported DRAM type");
}

2
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -43,7 +43,7 @@
#define CONFIGURATION_H
#include <string>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <systemc>
#include "memspec/MemSpec.h"
#include "TemperatureSimConfig.h"

2
DRAMSys/library/src/configuration/TemperatureSimConfig.h
View File

@@ -41,7 +41,7 @@
#include <string>
#include <vector>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <systemc>
#include <utility>
#include "../common/DebugManager.h"

7
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -75,7 +75,7 @@ MemSpec::MemSpec(const DRAMSysConfiguration::MemSpec &memSpec,
burstDuration(tCK * (static_cast<double>(defaultBurstLength) / dataRate)),
memorySizeBytes(0)
{
commandLengthInCycles = std::vector<unsigned>(Command::numberOfCommands(), 1);
commandLengthInCycles = std::vector<double>(Command::numberOfCommands(), 1);
}
sc_time MemSpec::getCommandLength(Command command) const
@@ -83,6 +83,11 @@ sc_time MemSpec::getCommandLength(Command command) const
return tCK * commandLengthInCycles[command];
}
double MemSpec::getCommandLengthInCylcles(Command command) const
{
return commandLengthInCycles[command];
}
uint64_t MemSpec::getSimMemSizeInBytes() const
{
return memorySizeBytes;

7
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -41,7 +41,7 @@
#include <vector>
#include <string>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <systemc>
#include <tlm>
#include "../../common/utils.h"
@@ -76,7 +76,7 @@ public:
const std::string memoryId;
const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, LPDDR5, WideIO,
WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, STTMRAM} memoryType;
WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, HBM3, STTMRAM} memoryType;
virtual ~MemSpec() = default;
@@ -97,6 +97,7 @@ public:
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0;
sc_core::sc_time getCommandLength(Command) const;
double getCommandLengthInCylcles(Command) const;
uint64_t getSimMemSizeInBytes() const;
protected:
@@ -109,7 +110,7 @@ protected:
unsigned devicesPerRank);
// Command lengths in cycles on bus, usually one clock cycle
std::vector<unsigned> commandLengthInCycles;
std::vector<double> commandLengthInCycles;
sc_core::sc_time burstDuration;
uint64_t memorySizeBytes;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -40,7 +40,7 @@
#include "MemSpec.h"
#include <systemc>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
class MemSpecDDR3 final : public MemSpec
{

195
DRAMSys/library/src/configuration/memspec/MemSpecHBM3.cpp Normal file
View File

@@ -0,0 +1,195 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
* Derek Christ
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecHBM3.h"
using namespace sc_core;
using namespace tlm;
MemSpecHBM3::MemSpecHBM3(const DRAMSysConfiguration::MemSpec &memSpec)
: MemSpec(memSpec, MemoryType::HBM3,
memSpec.memArchitectureSpec.entries.at("nbrOfChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
/ memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups"),
memSpec.memArchitectureSpec.entries.at("nbrOfBanks")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
* memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")),
RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")),
tDQSCK (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
tRC (tCK * memSpec.memTimingSpec.entries.at("RC")),
tRAS (tCK * memSpec.memTimingSpec.entries.at("RAS")),
tRCDRD (tCK * memSpec.memTimingSpec.entries.at("RCDRD")),
tRCDWR (tCK * memSpec.memTimingSpec.entries.at("RCDWR")),
tRRDL (tCK * memSpec.memTimingSpec.entries.at("RRDL")),
tRRDS (tCK * memSpec.memTimingSpec.entries.at("RRDS")),
tFAW (tCK * memSpec.memTimingSpec.entries.at("FAW")),
tRTP (tCK * memSpec.memTimingSpec.entries.at("RTP")),
tRP (tCK * memSpec.memTimingSpec.entries.at("RP")),
tRL (tCK * memSpec.memTimingSpec.entries.at("RL")),
tWL (tCK * memSpec.memTimingSpec.entries.at("WL")),
tPL (tCK * memSpec.memTimingSpec.entries.at("PL")),
tWR (tCK * memSpec.memTimingSpec.entries.at("WR")),
tCCDL (tCK * memSpec.memTimingSpec.entries.at("CCDL")),
tCCDS (tCK * memSpec.memTimingSpec.entries.at("CCDS")),
tWTRL (tCK * memSpec.memTimingSpec.entries.at("WTRL")),
tWTRS (tCK * memSpec.memTimingSpec.entries.at("WTRS")),
tRTW (tCK * memSpec.memTimingSpec.entries.at("RTW")),
tXP (tCK * memSpec.memTimingSpec.entries.at("XP")),
tCKE (tCK * memSpec.memTimingSpec.entries.at("CKE")),
tPD (tCKE),
tCKESR (tCKE + tCK),
tXS (tCK * memSpec.memTimingSpec.entries.at("XS")),
tRFC (tCK * memSpec.memTimingSpec.entries.at("RFC")),
tRFCPB (tCK * memSpec.memTimingSpec.entries.at("RFCPB")),
tRREFD (tCK * memSpec.memTimingSpec.entries.at("RREFD")),
tREFI (tCK * memSpec.memTimingSpec.entries.at("REFI")),
tREFIPB (tCK * memSpec.memTimingSpec.entries.at("REFIPB")),
tPPD (tCK * memSpec.memTimingSpec.entries.at("PPD"))
{
commandLengthInCycles[Command::ACT] = 1.5;
commandLengthInCycles[Command::PREPB] = 0.5;
commandLengthInCycles[Command::PREAB] = 0.5;
commandLengthInCycles[Command::REFPB] = 0.5;
commandLengthInCycles[Command::REFAB] = 0.5;
commandLengthInCycles[Command::RFMPB] = 0.5;
commandLengthInCycles[Command::RFMAB] = 0.5;
commandLengthInCycles[Command::PDXA] = 0.5;
commandLengthInCycles[Command::SREFEX] = 0.5;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * rowsPerBank * columnsPerRow * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * ranksPerChannel * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "HBM3" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Pseudo channels per channel: " << ranksPerChannel << std::endl;
std::cout << " Bank groups per pseudo channel: " << groupsPerRank << std::endl;
std::cout << " Banks per pseudo channel: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << rowsPerBank << std::endl;
std::cout << " Columns per row: " << columnsPerRow << std::endl;
std::cout << " Pseudo channel width in bits: " << bitWidth << std::endl;
std::cout << " Pseudo channel size in bits: " << deviceSizeBits << std::endl;
std::cout << " Pseudo channel size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
}
sc_time MemSpecHBM3::getRefreshIntervalAB() const
{
return tREFI;
}
sc_time MemSpecHBM3::getRefreshIntervalPB() const
{
return tREFIPB;
}
bool MemSpecHBM3::hasRasAndCasBus() const
{
return true;
}
sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload &payload) const
{
if (command == Command::PREPB || command == Command::PREAB)
return tRP;
else if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD + tCK;
else
return tRCDWR + tCK;
}
else if (command == Command::RD)
return tRL + tDQSCK + burstDuration;
else if (command == Command::RDA)
return tRTP + tRP;
else if (command == Command::WR)
return tWL + burstDuration;
else if (command == Command::WRA)
return tWL + burstDuration + tWR + tRP;
else if (command == Command::REFAB || command == Command::RFMAB)
return tRFC;
else if (command == Command::REFPB || command == Command::RFMPB)
return tRFCPB;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
}
TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecHBM3", "Method was called with invalid argument");
return {};
}
}
unsigned MemSpecHBM3::getRAACDR() const
{
return RAACDR;
}
unsigned MemSpecHBM3::getRAAIMT() const
{
return RAAIMT;
}
unsigned MemSpecHBM3::getRAAMMT() const
{
return RAAMMT;
}

102
DRAMSys/library/src/configuration/memspec/MemSpecHBM3.h Normal file
View File

@@ -0,0 +1,102 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
* Derek Christ
*/
#ifndef MemSpecHBM3_H
#define MemSpecHBM3_H
#include <systemc>
#include "MemSpec.h"
class MemSpecHBM3 final : public MemSpec
{
public:
explicit MemSpecHBM3(const DRAMSysConfiguration::MemSpec &memSpec);
const unsigned RAAIMT;
const unsigned RAAMMT;
const unsigned RAACDR;
// Memspec Variables:
const sc_core::sc_time tDQSCK;
// sc_time tDQSQ; // TODO: check actual value of this parameter
const sc_core::sc_time tRC;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRCDRD;
const sc_core::sc_time tRCDWR;
const sc_core::sc_time tRRDL;
const sc_core::sc_time tRRDS;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRTP;
const sc_core::sc_time tRP;
const sc_core::sc_time tRL;
const sc_core::sc_time tWL;
const sc_core::sc_time tPL;
const sc_core::sc_time tWR;
const sc_core::sc_time tCCDL;
const sc_core::sc_time tCCDS;
// sc_time tCCDR; // TODO: consecutive reads to different stack IDs
const sc_core::sc_time tWTRL;
const sc_core::sc_time tWTRS;
const sc_core::sc_time tRTW;
const sc_core::sc_time tXP;
const sc_core::sc_time tCKE;
const sc_core::sc_time tPD; // = tCKE;
const sc_core::sc_time tCKESR; // = tCKE + tCK;
const sc_core::sc_time tXS;
const sc_core::sc_time tRFC;
const sc_core::sc_time tRFCPB;
const sc_core::sc_time tRREFD;
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIPB;
const sc_core::sc_time tPPD;
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
unsigned getRAACDR() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
bool hasRasAndCasBus() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MemSpecHBM3_H

72
DRAMSys/library/src/controller/Command.cpp
View File

@@ -40,40 +40,11 @@
#include "Command.h"
using namespace tlm;
using namespace DRAMPower;
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
{
// TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
assert(phase >= BEGIN_NOP && phase <= END_SREF);
static std::array<MemCommand::cmds, Command::Type::END_ENUM> phaseOfCommand =
{
MemCommand::NOP, // 0
MemCommand::RD, // 1
MemCommand::WR, // 2
MemCommand::RDA, // 3
MemCommand::WRA, // 4
MemCommand::ACT, // 5
MemCommand::PRE, // 6, PREPB
MemCommand::REFB, // 7, REFPB
MemCommand::NOP, // 8, RFMPB
MemCommand::NOP, // 9, REFP2B
MemCommand::NOP, // 10, RFMP2B
MemCommand::NOP, // 11, PRESB
MemCommand::NOP, // 12, REFSB
MemCommand::NOP, // 13, RFMSB
MemCommand::PREA, // 14, PREAB
MemCommand::REF, // 15, REFAB
MemCommand::NOP, // 16, RFMAB
MemCommand::PDN_S_ACT, // 17
MemCommand::PDN_S_PRE, // 18
MemCommand::SREN, // 19
MemCommand::PUP_ACT, // 20
MemCommand::PUP_PRE, // 21
MemCommand::SREX // 22
};
return phaseOfCommand[phase - BEGIN_NOP];
}
#ifdef DRAMPOWER
using namespace DRAMPower;
#endif
bool phaseHasDataStrobe(tlm::tlm_phase phase)
{
@@ -204,6 +175,41 @@ tlm_phase Command::toPhase() const
return phaseOfCommand[type];
}
#ifdef DRAMPOWER
MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
{
// TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
assert(phase >= BEGIN_NOP && phase <= END_SREF);
static std::array<MemCommand::cmds, Command::Type::END_ENUM> phaseOfCommand =
{
MemCommand::NOP, // 0
MemCommand::RD, // 1
MemCommand::WR, // 2
MemCommand::RDA, // 3
MemCommand::WRA, // 4
MemCommand::ACT, // 5
MemCommand::PRE, // 6, PREPB
MemCommand::REFB, // 7, REFPB
MemCommand::NOP, // 8, RFMPB
MemCommand::NOP, // 9, REFP2B
MemCommand::NOP, // 10, RFMP2B
MemCommand::NOP, // 11, PRESB
MemCommand::NOP, // 12, REFSB
MemCommand::NOP, // 13, RFMSB
MemCommand::PREA, // 14, PREAB
MemCommand::REF, // 15, REFAB
MemCommand::NOP, // 16, RFMAB
MemCommand::PDN_S_ACT, // 17
MemCommand::PDN_S_PRE, // 18
MemCommand::SREN, // 19
MemCommand::PUP_ACT, // 20
MemCommand::PUP_PRE, // 21
MemCommand::SREX // 22
};
return phaseOfCommand[phase - BEGIN_NOP];
}
#endif
bool Command::isBankCommand() const
{
assert(type >= Command::NOP && type <= Command::SREFEX);

7
DRAMSys/library/src/controller/Command.h
View File

@@ -43,7 +43,10 @@
#include <systemc>
#include <tlm>
#ifdef DRAMPOWER
#include "../common/third_party/DRAMPower/src/MemCommand.h"
#endif
// DO NOT CHANGE THE ORDER!
@@ -78,7 +81,9 @@ DECLARE_EXTENDED_PHASE(END_PDNA); // 25
DECLARE_EXTENDED_PHASE(END_PDNP); // 26
DECLARE_EXTENDED_PHASE(END_SREF); // 27
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase phase);
#ifdef DRAMPOWER
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
#endif
bool phaseHasDataStrobe(tlm::tlm_phase phase);
bool isPowerDownEntryPhase(tlm::tlm_phase phase);
bool isPowerDownExitPhase(tlm::tlm_phase phase);

48
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -39,10 +39,8 @@
#include "checker/CheckerDDR3.h"
#include "checker/CheckerDDR4.h"
#include "checker/CheckerDDR5.h"
#include "checker/CheckerWideIO.h"
#include "checker/CheckerLPDDR4.h"
#include "checker/CheckerLPDDR5.h"
#include "checker/CheckerWideIO2.h"
#include "checker/CheckerHBM2.h"
#include "checker/CheckerGDDR5.h"
@@ -66,6 +64,16 @@
#include "powerdown/PowerDownManagerStaggered.h"
#include "powerdown/PowerDownManagerDummy.h"
#ifdef DDR5_SIM
#include "checker/CheckerDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "checker/CheckerLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "checker/CheckerHBM3.h"
#endif
using namespace sc_core;
using namespace tlm;
@@ -89,14 +97,10 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
checker = std::make_unique<CheckerDDR3>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::DDR4)
checker = std::make_unique<CheckerDDR4>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::DDR5)
checker = std::make_unique<CheckerDDR5>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::WideIO)
checker = std::make_unique<CheckerWideIO>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR4)
checker = std::make_unique<CheckerLPDDR4>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR5)
checker = std::make_unique<CheckerLPDDR5>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::WideIO2)
checker = std::make_unique<CheckerWideIO2>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::HBM2)
@@ -109,6 +113,19 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
checker = std::make_unique<CheckerGDDR6>(config);
else if (memSpec.memoryType == MemSpec::MemoryType::STTMRAM)
checker = std::make_unique<CheckerSTTMRAM>(config);
#ifdef DDR5_SIM
else if (memSpec.memoryType == MemSpec::MemoryType::DDR5)
checker = std::make_unique<CheckerDDR5>(config);
#endif
#ifdef LPDDR5_SIM
else if (memSpec.memoryType == MemSpec::MemoryType::LPDDR5)
checker = std::make_unique<CheckerLPDDR5>(config);
#endif
#ifdef HBM3_SIM
else if (memSpec.memoryType == MemSpec::MemoryType::HBM3)
checker = std::make_unique<CheckerHBM3>(config);
#endif
// instantiate scheduler and command mux
if (config.scheduler == Configuration::Scheduler::Fifo)
@@ -237,11 +254,14 @@ Controller::Controller(const sc_module_name& name, const Configuration& config,
void Controller::controllerMethod()
{
// (1) Finish last response (END_RESP) and start new response (BEGIN_RESP)
manageResponses();
if (isFullCycle(sc_time_stamp()))
{
// (1) Finish last response (END_RESP) and start new response (BEGIN_RESP)
manageResponses();
// (2) Insert new request into scheduler and send END_REQ or use backpressure
manageRequests(SC_ZERO_TIME);
// (2) Insert new request into scheduler and send END_REQ or use backpressure
manageRequests(SC_ZERO_TIME);
}
// (3) Start refresh and power-down managers to issue requests for the current time
for (auto& it : refreshManagers)
@@ -621,4 +641,10 @@ void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)
}
nextChannelPayloadIDToAppend++;
ParentExtension::setExtension(parentTrans, std::move(childTranses));
}
}
bool Controller::isFullCycle(const sc_core::sc_time& time) const
{
sc_time alignedAtHalfCycle = std::floor((time * 2 / memSpec.tCK + 0.5)) / 2 * memSpec.tCK;
return sc_time::from_value(alignedAtHalfCycle.value() % memSpec.tCK.value()) == SC_ZERO_TIME;
}

2
DRAMSys/library/src/controller/Controller.h
View File

@@ -100,6 +100,8 @@ private:
void manageResponses();
void manageRequests(const sc_core::sc_time &delay);
bool isFullCycle(const sc_core::sc_time& time) const;
sc_core::sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
const unsigned minBytesPerBurst;

806
DRAMSys/library/src/controller/checker/CheckerHBM3.cpp Normal file
View File

@@ -0,0 +1,806 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerHBM3.h"
using namespace sc_core;
using namespace tlm;
CheckerHBM3::CheckerHBM3(const Configuration &config)
{
memSpec = dynamic_cast<const MemSpecHBM3 *>(config.memSpec.get());
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerHBM3", "Wrong MemSpec chosen");
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>(
Command::numberOfCommands(), std::vector<sc_time>(memSpec->banksPerChannel, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>(
Command::numberOfCommands(), std::vector<sc_time>(memSpec->bankGroupsPerChannel, sc_max_time()));
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>(
Command::numberOfCommands(), std::vector<sc_time>(memSpec->ranksPerChannel, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnRasBus = sc_max_time();
lastCommandOnCasBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->ranksPerChannel);
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->ranksPerChannel);
tRDPDE = memSpec->tRL + memSpec->tPL + 2 * memSpec->tCK;
tRDSRE = memSpec->tRL + memSpec->tPL + 3 * memSpec->tCK;
tWRPRE = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWR;
tWRPDE = memSpec->tWL + memSpec->tPL + 3 * memSpec->tCK + memSpec->tWR;
tWRAPDE = memSpec->tWL + memSpec->tPL + 3 * memSpec->tCK + memSpec->tWR;
tWRRDS = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWTRS;
tWRRDL = memSpec->tWL + 2 * memSpec->tCK + memSpec->tWTRL;
}
sc_time CheckerHBM3::timeToSatisfyConstraints(Command command, const tlm_generic_payload &payload) const
{
Rank rank = ControllerExtension::getRank(payload);
BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
Bank bank = ControllerExtension::getBank(payload);
sc_time lastCommandStart;
sc_time earliestTimeToStart = sc_time_stamp();
if (command == Command::PREPB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK / 2);
}
else if (command == Command::RD)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::WR)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::RDA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + 2 * memSpec->tCK +
std::max(memSpec->tWR - memSpec->tRTP, memSpec->tWTRL));
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::WRA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTW);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::ACT)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart =
std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart =
std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS - memSpec->tCK);
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart =
std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::REFAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PREAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK / 2);
}
else if (command == Command::REFAB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (bankwiseRefreshCounter[rank.ID()] == 0)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
}
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart =
std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::SREFEN)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart =
std::max(earliestTimeToStart, lastCommandStart + std::max(memSpec->tRTP + memSpec->tRP, tRDSRE));
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXP);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::RFMAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::RFMAB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::REFPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
lastCommandStart = lastScheduledByCommandAndBank[Command::RFMPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCPB);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RFMPB][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
lastCommandStart = lastScheduledByCommandAndRank[Command::RFMPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDEA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDEP)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAPDE);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKE);
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEX][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tXS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDXP)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::PDEP][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PDXA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::PDEA][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPD);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::SREFEX)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::SREFEN][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCKESR);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else
{
SC_REPORT_FATAL("CheckerHBM3", "Unknown command!");
}
// Don't issue commands at half cycles.
if (command != Command::PREAB && command != Command::PREPB && !isFullCycle(earliestTimeToStart))
earliestTimeToStart += memSpec->tCK / 2;
return earliestTimeToStart;
}
void CheckerHBM3::insert(Command command, const tlm_generic_payload &payload)
{
Rank rank = ControllerExtension::getRank(payload);
BankGroup bankGroup = ControllerExtension::getBankGroup(payload);
Bank bank = ControllerExtension::getBank(payload);
PRINTDEBUGMESSAGE("CheckerHBM3",
"Changing state on bank " + std::to_string(bank.ID()) + " command is " + command.toString());
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommand[command] = sc_time_stamp();
if (command.isCasCommand())
lastCommandOnCasBus = sc_time_stamp();
else if (command == Command::ACT)
lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK;
else
lastCommandOnRasBus = sc_time_stamp();
if (command == Command::ACT || command == Command::REFPB)
{
if (last4Activates[rank.ID()].size() == 4)
last4Activates[rank.ID()].pop();
last4Activates[rank.ID()].push(lastCommandOnRasBus);
}
if (command == Command::REFPB)
bankwiseRefreshCounter[rank.ID()] = (bankwiseRefreshCounter[rank.ID()] + 1) % memSpec->banksPerRank;
}
bool CheckerHBM3::isFullCycle(const sc_core::sc_time& time) const
{
sc_time aligedAtHalfCycle = std::floor((time * 2 / memSpec->tCK + 0.5)) / 2 * memSpec->tCK;
return sc_time::from_value(aligedAtHalfCycle.value() % memSpec->tCK.value()) == SC_ZERO_TIME;
}

78
DRAMSys/library/src/controller/checker/CheckerHBM3.h Normal file
View File

@@ -0,0 +1,78 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#ifndef CHECKERHBM3_H
#define CHECKERHBM3_H
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecHBM3.h"
#include "../../configuration/Configuration.h"
class CheckerHBM3 final : public CheckerIF
{
public:
explicit CheckerHBM3(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:
bool isFullCycle(const sc_core::sc_time& time) const;
const MemSpecHBM3 *memSpec;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnRasBus;
sc_core::sc_time lastCommandOnCasBus;
// Four activate window
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<unsigned> bankwiseRefreshCounter;
sc_core::sc_time tRDPDE;
sc_core::sc_time tRDSRE;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRPDE;
sc_core::sc_time tWRAPDE;
sc_core::sc_time tWRRDS;
sc_core::sc_time tWRRDL;
};
#endif // CHECKERHBM3_H

8
DRAMSys/library/src/error/errormodel.cpp
View File

@@ -39,6 +39,10 @@
#include "../simulation/AddressDecoder.h"
#include "../common/dramExtensions.h"
#ifdef DRAMPOWER
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#endif
#include <random>
#include <chrono>
#include <bitset>
@@ -504,6 +508,7 @@ double errorModel::getTemperature()
if (this->myChannel != -1)
{
#ifdef DRAMPOWER
if (thermalSim && powerAnalysis)
{
// TODO
@@ -515,6 +520,9 @@ double errorModel::getTemperature()
} else {
temperature = temperatureController.getTemperature(this->myChannel, 0);
}
#else
temperature = temperatureController.getTemperature(this->myChannel, 0);
#endif
}
return temperature;

3
DRAMSys/library/src/error/errormodel.h
View File

@@ -41,9 +41,10 @@
#include <systemc>
#include "../configuration/Configuration.h"
#include "../simulation/AddressDecoder.h"
#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../simulation/TemperatureController.h"
class libDRAMPower;
class errorModel : public sc_core::sc_module
{
public:

2
DRAMSys/library/src/simulation/AddressDecoder.h
View File

@@ -41,7 +41,7 @@
#include <vector>
#include <utility>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include "../configuration/Configuration.h"
struct DecodedAddress

4
DRAMSys/library/src/simulation/Arbiter.cpp
View File

@@ -41,7 +41,7 @@
#include "AddressDecoder.h"
#include "../configuration/Configuration.h"
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
using namespace sc_core;
using namespace tlm;
@@ -128,7 +128,7 @@ void ArbiterReorder::end_of_elaboration()
tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload,
tlm_phase &phase, sc_time &fwDelay)
{
sc_time clockOffset = (sc_time_stamp() + fwDelay) % tCK;
sc_time clockOffset = sc_time::from_value((sc_time_stamp() + fwDelay).value() % tCK.value());
sc_time notDelay = (clockOffset == SC_ZERO_TIME) ? fwDelay : (fwDelay + tCK - clockOffset);
if (phase == BEGIN_REQ)

33
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -51,10 +51,8 @@
#include "../error/ecchamming.h"
#include "dram/DramDDR3.h"
#include "dram/DramDDR4.h"
#include "dram/DramDDR5.h"
#include "dram/DramWideIO.h"
#include "dram/DramLPDDR4.h"
#include "dram/DramLPDDR5.h"
#include "dram/DramWideIO2.h"
#include "dram/DramHBM2.h"
#include "dram/DramGDDR5.h"
@@ -63,6 +61,16 @@
#include "dram/DramSTTMRAM.h"
#include "../controller/Controller.h"
#ifdef DDR5_SIM
#include "dram/DramDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "dram/DramLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "dram/DramHBM3.h"
#endif
DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
const DRAMSysConfiguration::Configuration &configLib)
: DRAMSys(name, configLib, true)
@@ -177,18 +185,12 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping& add
else if (memoryType == MemSpec::MemoryType::DDR4)
drams.emplace_back(std::make_unique<DramDDR4>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(std::make_unique<DramDDR5>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
else if (memoryType == MemSpec::MemoryType::WideIO)
drams.emplace_back(std::make_unique<DramWideIO>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
drams.emplace_back(std::make_unique<DramLPDDR4>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(std::make_unique<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
else if (memoryType == MemSpec::MemoryType::WideIO2)
drams.emplace_back(std::make_unique<DramWideIO2>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
@@ -207,6 +209,21 @@ void DRAMSys::instantiateModules(const DRAMSysConfiguration::AddressMapping& add
else if (memoryType == MemSpec::MemoryType::STTMRAM)
drams.emplace_back(std::make_unique<DramSTTMRAM>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
#ifdef DDR5_SIM
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(std::make_unique<DramDDR5>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
#endif
#ifdef LPDDR5_SIM
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(std::make_unique<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
#endif
#ifdef HBM3_SIM
else if (memoryType == MemSpec::MemoryType::HBM3)
drams.emplace_back(std::make_unique<DramHBM3>(("dram" + std::to_string(i)).c_str(), config,
*temperatureController));
#endif
if (config.checkTLM2Protocol)
controllersTlmCheckers.push_back(std::make_unique<tlm_utils::tlm2_base_protocol_checker<>>

2
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -50,7 +50,7 @@
#include "TemperatureController.h"
#include "AddressDecoder.h"
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <string>
#include <systemc>
#include <list>

33
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
View File

@@ -41,10 +41,8 @@
#include "dram/DramRecordable.h"
#include "dram/DramDDR3.h"
#include "dram/DramDDR4.h"
#include "dram/DramDDR5.h"
#include "dram/DramWideIO.h"
#include "dram/DramLPDDR4.h"
#include "dram/DramLPDDR5.h"
#include "dram/DramWideIO2.h"
#include "dram/DramHBM2.h"
#include "dram/DramGDDR5.h"
@@ -55,6 +53,16 @@
#include "../simulation/TemperatureController.h"
#include "../error/ecchamming.h"
#ifdef DDR5_SIM
#include "dram/DramDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "dram/DramLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "dram/DramHBM3.h"
#endif
using namespace sc_core;
DRAMSysRecordable::DRAMSysRecordable(const sc_module_name& name, const DRAMSysConfiguration::Configuration& configLib)
@@ -142,18 +150,12 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
else if (memoryType == MemSpec::MemoryType::DDR4)
drams.emplace_back(std::make_unique<DramRecordable<DramDDR4>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramDDR5>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO)
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR4>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR5>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO2)
drams.emplace_back(std::make_unique<DramRecordable<DramWideIO2>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
@@ -172,6 +174,21 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
else if (memoryType == MemSpec::MemoryType::STTMRAM)
drams.emplace_back(std::make_unique<DramRecordable<DramSTTMRAM>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
#ifdef DDR5_SIM
else if (memoryType == MemSpec::MemoryType::DDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramDDR5>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
#endif
#ifdef LPDDR5_SIM
else if (memoryType == MemSpec::MemoryType::LPDDR5)
drams.emplace_back(std::make_unique<DramRecordable<DramLPDDR5>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
#endif
#ifdef HBM3_SIM
else if (memoryType == MemSpec::MemoryType::HBM3)
drams.emplace_back(std::make_unique<DramRecordable<DramHBM3>>(("dram" + std::to_string(i)).c_str(),
config, *temperatureController, tlmRecorders[i]));
#endif
if (config.checkTLM2Protocol)
controllersTlmCheckers.emplace_back(std::make_unique<tlm_utils::tlm2_base_protocol_checker<>>

2
DRAMSys/library/src/simulation/DRAMSysRecordable.h
View File

@@ -40,7 +40,7 @@
#include "DRAMSys.h"
#include "../common/TlmRecorder.h"
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
class DRAMSysRecordable : public DRAMSys
{

14
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -55,12 +55,19 @@
#include "../../common/DebugManager.h"
#include "../../common/dramExtensions.h"
#include "../../common/utils.h"
#include "../../common/third_party/DRAMPower/src/MemCommand.h"
#include "../../controller/Command.h"
#ifdef DRAMPOWER
#include "../../common/third_party/DRAMPower/src/MemCommand.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#endif
using namespace sc_core;
using namespace tlm;
#ifdef DRAMPOWER
using namespace DRAMPower;
#endif
Dram::Dram(const sc_module_name& name, const Configuration& config)
: sc_module(name), memSpec(*config.memSpec), tSocket("socket"), storeMode(config.storeMode),
@@ -99,6 +106,7 @@ Dram::~Dram()
void Dram::reportPower()
{
#ifdef DRAMPOWER
DRAMPower->calcEnergy();
// Print the final total energy and the average power for
@@ -115,6 +123,7 @@ void Dram::reportPower()
<< DRAMPower->getPower().average_power
* memSpec.devicesPerRank
<< std::string(" mW") << std::endl;
#endif
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
@@ -126,7 +135,10 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
{
int bank = static_cast<int>(ControllerExtension::getBank(payload).ID());
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
#ifdef DRAMPOWER
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
#endif
}
if (storeMode == Configuration::StoreMode::Store)

5
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -47,7 +47,8 @@
#include <tlm_utils/simple_target_socket.h>
#include "../../configuration/Configuration.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
class libDRAMPower;
class Dram : public sc_core::sc_module
{
@@ -63,7 +64,9 @@ protected:
unsigned char *memory;
const bool useMalloc;
#ifdef DRAMPOWER
std::unique_ptr<libDRAMPower> DRAMPower;
#endif
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_core::sc_time &delay);

9
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
View File

@@ -37,11 +37,14 @@
#include <memory>
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecDDR3.h"
using namespace sc_core;
#ifdef DRAMPOWER
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
using namespace DRAMPower;
#endif
using namespace sc_core;
DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config,
TemperatureController& temperatureController)
@@ -56,6 +59,7 @@ DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config,
if (memSpecDDR3 == nullptr)
SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen");
#ifdef DRAMPOWER
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpecDDR3->defaultBurstLength;
memArchSpec.dataRate = memSpecDDR3->dataRate;
@@ -143,5 +147,6 @@ DramDDR3::DramDDR3(const sc_module_name& name, const Configuration& config,
powerSpec.memArchSpec = memArchSpec;
DRAMPower = std::make_unique<libDRAMPower>(powerSpec, false);
#endif
}
}

9
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
View File

@@ -37,11 +37,14 @@
#include <memory>
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecDDR4.h"
using namespace sc_core;
#ifdef DRAMPOWER
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
using namespace DRAMPower;
#endif
using namespace sc_core;
DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config,
TemperatureController& temperatureController)
@@ -56,6 +59,7 @@ DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config,
if (memSpecDDR4 == nullptr)
SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen");
#ifdef DRAMPOWER
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpecDDR4->defaultBurstLength;
memArchSpec.dataRate = memSpecDDR4->dataRate;
@@ -143,5 +147,6 @@ DramDDR4::DramDDR4(const sc_module_name& name, const Configuration& config,
powerSpec.memArchSpec = memArchSpec;
DRAMPower = std::make_unique<libDRAMPower>(powerSpec, false);
#endif
}
}

2
DRAMSys/library/src/simulation/dram/DramDDR5.cpp
View File

@@ -35,11 +35,9 @@
#include "DramDDR5.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecDDR5.h"
using namespace sc_core;
using namespace DRAMPower;
DramDDR5::DramDDR5(const sc_module_name& name, const Configuration& config,
TemperatureController& temperatureController)

1
DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
View File

@@ -35,7 +35,6 @@
#include "DramGDDR5.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR5.h"
using namespace sc_core;

1
DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
View File

@@ -35,7 +35,6 @@
#include "DramGDDR5X.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR5X.h"
using namespace sc_core;

1
DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
View File

@@ -35,7 +35,6 @@
#include "DramGDDR6.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR6.h"
using namespace sc_core;

1
DRAMSys/library/src/simulation/dram/DramHBM2.cpp
View File

@@ -35,7 +35,6 @@
#include "DramHBM2.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecHBM2.h"
using namespace sc_core;

51
DRAMSys/library/src/simulation/dram/DramHBM3.cpp Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramHBM3.h"
#include "../../configuration/Configuration.h"
#include "../../configuration/memspec/MemSpecHBM3.h"
using namespace sc_core;
DramHBM3::DramHBM3(const sc_module_name& name, const Configuration& config,
TemperatureController& temperatureController)
: Dram(name, config)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramHBM3", "Error Model not supported for HBM3");
if (powerAnalysis)
SC_REPORT_FATAL("DramHBM3", "DRAMPower does not support HBM3");
}

52
DRAMSys/library/src/simulation/dram/DramHBM3.h Normal file
View File

@@ -0,0 +1,52 @@
/*
* Copyright (c) 2019, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef DRAMHBM3_H
#define DRAMHBM3_H
#include <systemc>
#include "Dram.h"
#include "../TemperatureController.h"
class DramHBM3 : public Dram
{
public:
DramHBM3(const sc_core::sc_module_name &name, const Configuration& config,
TemperatureController& temperatureController);
SC_HAS_PROCESS(DramHBM3);
};
#endif // DRAMHBM3_H

1
DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
View File

@@ -35,7 +35,6 @@
#include "DramLPDDR4.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecLPDDR4.h"
using namespace sc_core;

1
DRAMSys/library/src/simulation/dram/DramLPDDR5.cpp
View File

@@ -37,7 +37,6 @@
#include "Dram.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecLPDDR5.h"
using namespace sc_core;

29
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -40,10 +40,8 @@
#include "../../common/utils.h"
#include "DramDDR3.h"
#include "DramDDR4.h"
#include "DramDDR5.h"
#include "DramWideIO.h"
#include "DramLPDDR4.h"
#include "DramLPDDR5.h"
#include "DramWideIO2.h"
#include "DramHBM2.h"
#include "DramGDDR5.h"
@@ -51,6 +49,16 @@
#include "DramGDDR6.h"
#include "DramSTTMRAM.h"
#ifdef DDR5_SIM
#include "DramDDR5.h"
#endif
#ifdef LPDDR5_SIM
#include "DramLPDDR5.h"
#endif
#ifdef HBM3_SIM
#include "DramHBM3.h"
#endif
using namespace sc_core;
using namespace tlm;
@@ -60,19 +68,23 @@ DramRecordable<BaseDram>::DramRecordable(const sc_module_name& name, const Confi
: BaseDram(name, config, temperatureController), tlmRecorder(tlmRecorder),
powerWindowSize(config.memSpec->tCK * config.windowSize)
{
#ifdef DRAMPOWER
// Create a thread that is triggered every $powerWindowSize
// to generate a Power over Time plot in the Trace analyzer:
if (config.powerAnalysis && config.enableWindowing)
SC_THREAD(powerWindow);
#endif
}
template<class BaseDram>
void DramRecordable<BaseDram>::reportPower()
{
BaseDram::reportPower();
#ifdef DRAMPOWER
tlmRecorder.recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* this->memSpec.devicesPerRank);
#endif
}
template<class BaseDram>
@@ -83,6 +95,7 @@ tlm_sync_enum DramRecordable<BaseDram>::nb_transport_fw(tlm_generic_payload &pay
return BaseDram::nb_transport_fw(payload, phase, delay);
}
#ifdef DRAMPOWER
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for visualization purposes.
template<class BaseDram>
@@ -117,12 +130,11 @@ void DramRecordable<BaseDram>::powerWindow()
}
}
#endif
template class DramRecordable<DramDDR3>;
template class DramRecordable<DramDDR4>;
template class DramRecordable<DramDDR5>;
template class DramRecordable<DramLPDDR4>;
template class DramRecordable<DramLPDDR5>;
template class DramRecordable<DramWideIO>;
template class DramRecordable<DramWideIO2>;
template class DramRecordable<DramGDDR5>;
@@ -130,3 +142,12 @@ template class DramRecordable<DramGDDR5X>;
template class DramRecordable<DramGDDR6>;
template class DramRecordable<DramHBM2>;
template class DramRecordable<DramSTTMRAM>;
#ifdef DDR5_SIM
template class DramRecordable<DramDDR5>;
#endif
#ifdef LPDDR5_SIM
template class DramRecordable<DramLPDDR5>;
#endif
#ifdef HBM3_SIM
template class DramRecordable<DramHBM3>;
#endif

7
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -40,9 +40,12 @@
#include <tlm>
#include "../../common/TlmRecorder.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../TemperatureController.h"
#ifdef DRAMPOWER
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#endif
template<class BaseDram>
class DramRecordable final : public BaseDram
{
@@ -69,9 +72,11 @@ private:
return std::fabs(a - b) < epsilon;
}
#ifdef DRAMPOWER
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for visualization purposes.
void powerWindow();
#endif
};
#endif // DRAMRECORDABLE_H

2
DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp
View File

@@ -35,11 +35,9 @@
#include "DramSTTMRAM.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecSTTMRAM.h"
using namespace sc_core;
using namespace DRAMPower;
DramSTTMRAM::DramSTTMRAM(const sc_module_name& name, const Configuration& config,
TemperatureController& temperatureController)

13
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -39,12 +39,16 @@
#include "DramWideIO.h"
#include "../../configuration/Configuration.h"
#include "../../error/errormodel.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecWideIO.h"
#ifdef DRAMPOWER
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
using namespace DRAMPower;
#endif
using namespace sc_core;
using namespace tlm;
using namespace DRAMPower;
DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config,
TemperatureController& temperatureController)
@@ -52,6 +56,7 @@ DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config,
{
if (powerAnalysis)
{
#ifdef DRAMPOWER
const auto* memSpecWideIO = dynamic_cast<const MemSpecWideIO *>(config.memSpec.get());
if (memSpecWideIO == nullptr)
SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen");
@@ -144,6 +149,7 @@ DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config,
DRAMPower = std::make_unique<libDRAMPower>(powerSpec, false);
// For each bank in a channel a error Model is created:
if (storeMode == Configuration::StoreMode::ErrorModel)
{
@@ -154,6 +160,7 @@ DramWideIO::DramWideIO(const sc_module_name& name, const Configuration& config,
temperatureController, DRAMPower.get()));
}
}
#endif
}
else
{
@@ -174,12 +181,14 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
assert(phase >= 5 && phase <= 19);
#ifdef DRAMPOWER
if (powerAnalysis)
{
int bank = static_cast<int>(ControllerExtension::getBank(payload).ID());
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}
#endif
if (storeMode == Configuration::StoreMode::Store)
{

1
DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
View File

@@ -35,7 +35,6 @@
#include "DramWideIO2.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecWideIO2.h"
using namespace sc_core;

2
DRAMSys/simulator/TraceSetup.h
View File

@@ -37,7 +37,7 @@
#ifndef TRACESETUP_H
#define TRACESETUP_H
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <vector>
#include <string>
#include <memory>

3
DRAMSys/simulator/main.cpp
View File

@@ -44,7 +44,7 @@
#include <vector>
#include <list>
#include <chrono>
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <memory>
#include <systemc>
@@ -98,7 +98,6 @@ int sc_main(int argc, char **argv)
}
std::vector<std::unique_ptr<TrafficInitiator>> players;
std::vector<std::unique_ptr<LengthConverter>> lengthConverters;
DRAMSysConfiguration::Configuration configLib = DRAMSysConfiguration::from_path(simulationJson, resources);

62
DRAMSys/traceAnalyzer/businessObjects/commandlengths.h
View File

@@ -38,38 +38,38 @@
struct CommandLengths
{
unsigned NOP = 1;
unsigned RD = 1;
unsigned WR = 1;
unsigned RDA = 1;
unsigned WRA = 1;
unsigned ACT = 1;
unsigned PREPB = 1;
unsigned REFPB = 1;
unsigned RFMPB = 1;
unsigned REFP2B = 1;
unsigned RFMP2B = 1;
unsigned PRESB = 1;
unsigned REFSB = 1;
unsigned RFMSB = 1;
unsigned PREAB = 1;
unsigned REFAB = 1;
unsigned RFMAB = 1;
unsigned PDEA = 1;
unsigned PDXA = 1;
unsigned PDEP = 1;
unsigned PDXP = 1;
unsigned SREFEN = 1;
unsigned SREFEX = 1;
double NOP = 1;
double RD = 1;
double WR = 1;
double RDA = 1;
double WRA = 1;
double ACT = 1;
double PREPB = 1;
double REFPB = 1;
double RFMPB = 1;
double REFP2B = 1;
double RFMP2B = 1;
double PRESB = 1;
double REFSB = 1;
double RFMSB = 1;
double PREAB = 1;
double REFAB = 1;
double RFMAB = 1;
double PDEA = 1;
double PDXA = 1;
double PDEP = 1;
double PDXP = 1;
double SREFEN = 1;
double SREFEX = 1;
CommandLengths(unsigned NOP, unsigned RD, unsigned WR,
unsigned RDA, unsigned WRA, unsigned ACT,
unsigned PREPB, unsigned REFPB, unsigned RFMPB,
unsigned REFP2B, unsigned RFMP2B,
unsigned PRESB, unsigned REFSB, unsigned RFMSB,
unsigned PREAB, unsigned REFAB, unsigned RFMAB,
unsigned PDEA, unsigned PDXA, unsigned PDEP, unsigned PDXP,
unsigned SREFEN, unsigned SREFEX) :
CommandLengths(double NOP, double RD, double WR,
double RDA, double WRA, double ACT,
double PREPB, double REFPB, double RFMPB,
double REFP2B, double RFMP2B,
double PRESB, double REFSB, double RFMSB,
double PREAB, double REFAB, double RFMAB,
double PDEA, double PDXA, double PDEP, double PDXP,
double SREFEN, double SREFEX) :
NOP(NOP), RD(RD), WR(WR),
RDA(RDA), WRA(WRA), ACT(ACT),
PREPB(PREPB), REFPB(REFPB), RFMPB(RFMPB),

8
DRAMSys/traceAnalyzer/businessObjects/configmodels.cpp
View File

@@ -69,6 +69,10 @@ void McConfigModel::parseJson(const QString &jsonString)
{
entries.push_back({key, currentValue.toString()});
}
else if (currentValue.isBool())
{
entries.push_back({key, currentValue.toBool() ? "True" : "False"});
}
}
}
@@ -183,6 +187,10 @@ void MemSpecModel::parseJson(const QString &jsonString)
{
value = currentValue.toString();
}
else if (currentValue.isBool())
{
value = currentValue.toBool() ? "True" : "False";
}
std::unique_ptr<Node> node = std::unique_ptr<Node>(new Node({key, value}, parentNode.get()));
addNodes(obj[key].toObject(), node);

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h
View File

@@ -64,4 +64,4 @@ struct DBDependencyEntry {
QString timeDependency;
size_t dependencyPhaseID;
QString dependencyPhaseName;
};
};

18
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h
View File

@@ -36,20 +36,34 @@
#pragma once
#include <QString>
#include <memory>
#include "StringMapper.h"
class DBPhaseEntryBase;
#define PASSFUNCTIONDECL (const std::shared_ptr<DBPhaseEntryBase> thisPhase, const std::shared_ptr<DBPhaseEntryBase> otherPhase)
struct PassFunction {
using Fn = std::function<bool PASSFUNCTIONDECL>;
PassFunction(Fn passFunction) : mPassFn{std::move(passFunction)} {}
bool execute PASSFUNCTIONDECL { return mPassFn(thisPhase, otherPhase); }
Fn mPassFn;
};
class TimeDependency {
public:
TimeDependency() = default;
TimeDependency(size_t timeValue, QString phaseDep, DependencyType depType,
QString timeDepName, bool considerIntraRank = false)
QString timeDepName, std::shared_ptr<PassFunction> pass=nullptr)
: timeValue{timeValue}, phaseDep{phaseDep}, depType{depType},
timeDepName{timeDepName} {}
timeDepName{timeDepName}, passFunction{pass} {}
size_t timeValue;
StringMapper phaseDep;
DependencyType depType;
QString timeDepName;
std::shared_ptr<PassFunction> passFunction;
bool isPool() { return phaseDep.isPool(); }
};

29
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h
View File

@@ -41,23 +41,26 @@
#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
class ConfigurationBase {
public:
ConfigurationBase() {};
virtual ~ConfigurationBase() = default;
public:
ConfigurationBase() {};
virtual ~ConfigurationBase() = default;
virtual std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const { return nullptr; }
virtual QString getQueryStr(const std::vector<QString>& commands) const = 0;
virtual std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const = 0;
// Delegated methods
const uint getClk() const;
DependencyMap getDependencies(std::vector<QString>& commands) const;
PoolControllerMap getPools() const;
// Delegated methods
const uint getClk() const;
DependencyMap getDependencies(std::vector<QString>& commands) const;
PoolControllerMap getPools() const;
static const QString getDeviceName(const TraceDB& tdb);
static const QString getDeviceName(const TraceDB& tdb);
protected:
std::shared_ptr<DRAMTimeDependenciesBase> mDeviceDeps = nullptr;
protected:
std::shared_ptr<DRAMTimeDependenciesBase> mDeviceDeps = nullptr;
static const uint mGetClk(const TraceDB& tdb);
static const QJsonObject mGetMemspec(const TraceDB& tdb);
static const uint mGetClk(const TraceDB& tdb);
static const QJsonObject mGetMemspec(const TraceDB& tdb);
QSqlQuery mExecuteQuery(const QString& queryStr);
};

15
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
View File

@@ -41,6 +41,21 @@ DDR3Configuration::DDR3Configuration(const TraceDB& tdb) {
}
QString DDR3Configuration::getQueryStr(const std::vector<QString>& commands) const
{
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Rank "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
return queryStr;
}
std::shared_ptr<DBPhaseEntryBase> DDR3Configuration::makePhaseEntry(const QSqlQuery& query) const {
return std::make_shared<DDR3DBPhaseEntry>(query);
}

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h
View File

@@ -44,6 +44,7 @@ class DDR3Configuration : public ConfigurationBase {
public:
DDR3Configuration(const TraceDB& tdb);
QString getQueryStr(const std::vector<QString>& commands) const override;
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

17
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp
View File

@@ -35,9 +35,24 @@
#include "DDR4Configuration.h"
DDR4Configuration::DDR4Configuration(const TraceDB& tdb) {
DDR4Configuration::DDR4Configuration(const TraceDB& tdb)
{
mDeviceDeps = std::make_shared<TimeDependenciesInfoDDR4>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
}
QString DDR4Configuration::getQueryStr(const std::vector<QString>& commands) const
{
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
return queryStr;
}
std::shared_ptr<DBPhaseEntryBase> DDR4Configuration::makePhaseEntry(const QSqlQuery& query) const {

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h
View File

@@ -43,6 +43,7 @@ class DDR4Configuration : public ConfigurationBase {
public:
DDR4Configuration(const TraceDB& tdb);
QString getQueryStr(const std::vector<QString>& commands) const override;
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

15
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp
View File

@@ -41,6 +41,21 @@ DDR5Configuration::DDR5Configuration(const TraceDB& tdb) {
}
QString DDR5Configuration::getQueryStr(const std::vector<QString>& commands) const
{
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
return queryStr;
}
std::shared_ptr<DBPhaseEntryBase> DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const {
auto phase = std::make_shared<DDR5DBPhaseEntry>(query);

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h
View File

@@ -43,6 +43,7 @@ class DDR5Configuration : public ConfigurationBase {
public:
DDR5Configuration(const TraceDB& tdb);
QString getQueryStr(const std::vector<QString>& commands) const override;
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

15
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp
View File

@@ -40,6 +40,21 @@ HBM2Configuration::HBM2Configuration(const TraceDB& tdb) {
}
QString HBM2Configuration::getQueryStr(const std::vector<QString>& commands) const
{
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
return queryStr;
}
std::shared_ptr<DBPhaseEntryBase> HBM2Configuration::makePhaseEntry(const QSqlQuery& query) const {
return std::make_shared<HBM2DBPhaseEntry>(query);
}

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h
View File

@@ -43,6 +43,7 @@ class HBM2Configuration : public ConfigurationBase {
public:
HBM2Configuration(const TraceDB& tdb);
QString getQueryStr(const std::vector<QString>& commands) const override;
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

15
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp
View File

@@ -41,6 +41,21 @@ LPDDR4Configuration::LPDDR4Configuration(const TraceDB& tdb) {
}
QString LPDDR4Configuration::getQueryStr(const std::vector<QString>& commands) const
{
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Rank "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
return queryStr;
}
std::shared_ptr<DBPhaseEntryBase> LPDDR4Configuration::makePhaseEntry(const QSqlQuery& query) const {
return std::make_shared<LPDDR4DBPhaseEntry>(query);
}

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h
View File

@@ -43,6 +43,7 @@ class LPDDR4Configuration : public ConfigurationBase {
public:
LPDDR4Configuration(const TraceDB& tdb);
QString getQueryStr(const std::vector<QString>& commands) const override;
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

15
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp
View File

@@ -41,6 +41,21 @@ LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) {
}
QString LPDDR5Configuration::getQueryStr(const std::vector<QString>& commands) const
{
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank, Phases.BurstLength "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
return queryStr;
}
std::shared_ptr<DBPhaseEntryBase> LPDDR5Configuration::makePhaseEntry(const QSqlQuery& query) const {
auto phase = std::make_shared<LPDDR5DBPhaseEntry>(query);

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h
View File

@@ -43,6 +43,7 @@ class LPDDR5Configuration : public ConfigurationBase {
public:
LPDDR5Configuration(const TraceDB& tdb);
QString getQueryStr(const std::vector<QString>& commands) const override;
std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
};

4
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h
View File

@@ -40,12 +40,12 @@
#include "businessObjects/phases/phasedependency.h"
#include "businessObjects/dramTimeDependencies/common/common.h"
class DBPhaseEntryBase {
class DBPhaseEntryBase : public std::enable_shared_from_this<DBPhaseEntryBase>{
public:
DBPhaseEntryBase() = default;
virtual ~DBPhaseEntryBase() = default;
virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const { return false; }
virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) { return false; }
size_t id;
StringMapper phaseName;

5
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp
View File

@@ -42,11 +42,10 @@ DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) {
phaseEnd = query.value(3).toLongLong();
transact = query.value(4).toLongLong();
tBank = query.value(5).toLongLong();
// tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
tRank = query.value(6).toLongLong();
}
bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) {
auto other = std::dynamic_pointer_cast<DDR3DBPhaseEntry>(otherPhase);
if (!other) return false;

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h
View File

@@ -41,8 +41,7 @@ class DDR3DBPhaseEntry : public DBPhaseEntryBase {
public:
DDR3DBPhaseEntry(const QSqlQuery&);
// size_t tBankgroup;
size_t tRank;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) override;
};

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp
View File

@@ -46,7 +46,7 @@ DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) {
tRank = query.value(7).toLongLong();
}
bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) {
auto other = std::dynamic_pointer_cast<DDR4DBPhaseEntry>(otherPhase);
if (!other) return false;

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h
View File

@@ -44,5 +44,5 @@ class DDR4DBPhaseEntry : public DBPhaseEntryBase {
size_t tBankgroup;
size_t tRank;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) override;
};

6
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp
View File

@@ -44,12 +44,16 @@ DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) {
tBank = query.value(5).toLongLong();
tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
tBurstLength = query.value(8).toLongLong();
}
bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) {
auto other = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) return false;
bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
bool const skipOnIntraBankAndDifferentBanks = {

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h
View File

@@ -44,10 +44,11 @@ class DDR5DBPhaseEntry : public DBPhaseEntryBase {
size_t tBankgroup;
size_t tBankInGroup;
size_t tRank;
size_t tBurstLength;
size_t tLogicalRank;
size_t tPhysicalRank;
size_t tDIMMRank;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) override;
};

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp
View File

@@ -46,7 +46,7 @@ HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) {
tRank = query.value(7).toLongLong();
}
bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) {
auto other = std::dynamic_pointer_cast<HBM2DBPhaseEntry>(otherPhase);
if (!other) return false;

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h
View File

@@ -44,5 +44,5 @@ class HBM2DBPhaseEntry : public DBPhaseEntryBase {
size_t tBankgroup;
size_t tRank;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) override;
};

5
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp
View File

@@ -42,11 +42,10 @@ LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) {
phaseEnd = query.value(3).toLongLong();
transact = query.value(4).toLongLong();
tBank = query.value(5).toLongLong();
// tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
tRank = query.value(6).toLongLong();
}
bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) {
auto other = std::dynamic_pointer_cast<LPDDR4DBPhaseEntry>(otherPhase);
if (!other) return false;

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h
View File

@@ -42,8 +42,7 @@ class LPDDR4DBPhaseEntry : public DBPhaseEntryBase {
public:
LPDDR4DBPhaseEntry(const QSqlQuery&);
// size_t tBankgroup;
size_t tRank;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) override;
};

6
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp
View File

@@ -44,12 +44,16 @@ LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) {
tBank = query.value(5).toLongLong();
tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
tBurstLength = query.value(8).toLongLong();
}
bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
if (dep.passFunction && !dep.passFunction->execute(shared_from_this(), other)) return false;
bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
bool thisIsREFP2B = phaseName == StringMapper::Identifier::REFP2B;
bool otherIsREFP2B = dep.phaseDep == StringMapper::Identifier::REFP2B;

3
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h
View File

@@ -43,7 +43,8 @@ class LPDDR5DBPhaseEntry : public DBPhaseEntryBase {
size_t tBankgroup;
size_t tRank;
size_t tBurstLength;
size_t bankOffsetREFP2B;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) override;
};

361
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
View File

@@ -86,6 +86,7 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt();
tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt();
tCCD_L_WR2_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt();
tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt();
tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt();
tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt();
@@ -138,8 +139,6 @@ void TimeDependenciesInfoDDR5::mInitializeValues() {
}
cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
if (!(burstLength == 16 && bitWidth == 4))
tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt();
tBURST16 = 8 * tCK;
tBURST32 = 16 * tCK;
@@ -236,6 +235,49 @@ const std::vector<QString> TimeDependenciesInfoDDR5::getPossiblePhases() {
DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
DependencyMap dmap;
auto passBurstLength16 = std::make_shared<PassFunction>(
[] PASSFUNCTIONDECL {
auto other = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
return other->tBurstLength == 16;
}
);
auto passBurstLength32 = std::make_shared<PassFunction>(
[] PASSFUNCTIONDECL {
auto other = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
return other->tBurstLength == 32;
}
);
const auto localBitWidth = bitWidth;
auto passThisBL16AndBW4 = std::make_shared<PassFunction>(
[localBitWidth] PASSFUNCTIONDECL {
auto thisP = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(thisPhase);
if (!thisP) return false;
return thisP->tBurstLength == 16 && localBitWidth == 4;
}
);
auto passOtherBL32ThisBL16BW4 = std::make_shared<PassFunction>(
[passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL {
return passBurstLength32->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase);
}
);
auto passOtherBL32ThisNotBL16BW4 = std::make_shared<PassFunction>(
[passBurstLength32, passThisBL16AndBW4] PASSFUNCTIONDECL {
return passBurstLength32->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase);
}
);
auto passOtherBL16ThisBL16BW4 = std::make_shared<PassFunction>(
[passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL {
return passBurstLength16->execute(thisPhase, otherPhase) && passThisBL16AndBW4->execute(thisPhase, otherPhase);
}
);
auto passOtherBL16ThisNotBL16BW4 = std::make_shared<PassFunction>(
[passBurstLength16, passThisBL16AndBW4] PASSFUNCTIONDECL {
return passBurstLength16->execute(thisPhase, otherPhase) && !passThisBL16AndBW4->execute(thisPhase, otherPhase);
}
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("ACT"),
@@ -246,8 +288,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"},
{tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"},
{tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
{tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
{tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"},
{tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT", passBurstLength16},
{tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16", passBurstLength32},
{tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
{tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"},
{tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"},
@@ -274,40 +316,40 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
{tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
{tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
{tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -319,43 +361,48 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4},
{tCCD_L_WR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4},
{tCCD_L_WR2_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4},
{tCCD_L_WR2_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4},
{tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"},
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
{tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passOtherBL16ThisBL16BW4},
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passOtherBL32ThisBL16BW4},
{tCCD_L_WR2_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr", passOtherBL16ThisNotBL16BW4},
{tCCD_L_WR2_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR2_slr + tBURST16", passOtherBL32ThisNotBL16BW4},
{tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
{tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -368,8 +415,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK", passBurstLength16},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"},
@@ -386,42 +433,42 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
{tBURST32, "RD", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
{tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
{tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
{tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
{tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
{tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
{tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"},
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
{tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA"},
{tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16"},
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"},
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
{tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr", passBurstLength16},
{tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr", passBurstLength16},
{tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16", passBurstLength32},
{tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr", passBurstLength16},
{tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16", passBurstLength32},
{tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA", passBurstLength16},
{tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16", passBurstLength32},
{tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
{tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
{tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
{tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
{tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
{tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
{tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
{tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
{tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
{tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
{tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr", passBurstLength16},
{tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16", passBurstLength32},
{tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr", passBurstLength16},
{tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16", passBurstLength32},
{tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr", passBurstLength16},
{tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16", passBurstLength32},
{tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr", passBurstLength16},
{tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16", passBurstLength32},
{tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr", passBurstLength16},
{tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16", passBurstLength32},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -433,43 +480,43 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"},
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
{tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
{tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
{tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
{tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
{tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
{tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
{tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
{tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
{tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
{tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
{tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr", passBurstLength16},
{tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16", passBurstLength32},
{tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr", passBurstLength16},
{tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16", passBurstLength32},
{tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr", passBurstLength16},
{tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16", passBurstLength32},
{tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr", passBurstLength16},
{tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16", passBurstLength32},
{tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr", passBurstLength16},
{tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16", passBurstLength32},
{tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"},
{tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
{tBURST32, "WR", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
{tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
{tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
{tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
{tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr", passBurstLength16},
{tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16", passBurstLength32},
{tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
{tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"},
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
{tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr", passBurstLength16},
{tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tBURST32", passBurstLength32},
{tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr", passBurstLength16},
{tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16", passBurstLength32},
{tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr", passBurstLength16},
{tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16", passBurstLength32},
{2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
}
)
@@ -482,8 +529,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"},
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16},
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32},
{tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
{tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
@@ -504,8 +551,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"},
{tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK", passBurstLength16},
{tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16", passBurstLength32},
{tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
{tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
@@ -527,8 +574,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"},
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK"},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK", passBurstLength16},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32},
{tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"},
{tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
@@ -556,8 +603,8 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"},
{tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
{tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"},
{tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK", passBurstLength16},
{tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16", passBurstLength32},
{tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"},
{tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"},
{tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
@@ -585,10 +632,10 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"},
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK", passBurstLength16},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
@@ -604,10 +651,10 @@ DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
{tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"},
{tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"},
{tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK"},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"},
{tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16},
{tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32},
{tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK", passBurstLength16},
{tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
{tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
{tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h
View File

@@ -36,6 +36,7 @@
#pragma once
#include "../dramtimedependenciesbase.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h"
class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase {
public:
@@ -79,6 +80,7 @@ class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase {
uint tWR;
uint tCCD_L_slr;
uint tCCD_L_WR_slr;
uint tCCD_L_WR2_slr;
uint tCCD_S_slr;
uint tCCD_S_WR_slr;
uint tCCD_dlr;

231
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp
View File

@@ -142,6 +142,21 @@ const std::vector<QString> TimeDependenciesInfoLPDDR5::getPossiblePhases() {
DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
DependencyMap dmap;
auto passBurstLength16 = std::make_shared<PassFunction>(
[] PASSFUNCTIONDECL {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
return other->tBurstLength == 16;
}
);
auto passBurstLength32 = std::make_shared<PassFunction>(
[] PASSFUNCTIONDECL {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
return other->tBurstLength == 32;
}
);
dmap.emplace(
piecewise_construct,
forward_as_tuple("ACT"),
@@ -149,10 +164,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
{tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
{BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK"},
{BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK"},
{BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK", passBurstLength32},
{tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"},
{tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"},
{tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"},
@@ -172,26 +187,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -203,26 +218,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -234,10 +249,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP"},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP", passBurstLength16},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
@@ -250,26 +265,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -281,26 +296,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -312,10 +327,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
{tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
@@ -330,14 +345,14 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
{BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
{tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32},
{BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16},
{BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
@@ -351,10 +366,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
@@ -372,10 +387,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"},

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h
View File

@@ -36,6 +36,7 @@
#pragma once
#include "../dramtimedependenciesbase.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h"
class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase {
public:

16
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
View File

@@ -153,19 +153,10 @@ void PhaseDependenciesTracker::mInsertIntoTable(TraceDB& tdb, const std::vector<
}
const std::vector<std::shared_ptr<DBPhaseEntryBase>>
PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr<ConfigurationBase> deviceConfig, TraceDB& tdb, const std::vector<QString>& commands) {
PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr<ConfigurationBase> deviceConfig, TraceDB& tdb, const std::vector<QString>& commands)
{
std::vector<std::shared_ptr<DBPhaseEntryBase>> phases;
QString queryStr = "SELECT Phases.ID, Phases.PhaseName, Phases.PhaseBegin, Phases.PhaseEnd, Phases.Transact, Phases.Bank, Phases.Bankgroup, Phases.Rank "
" FROM Phases "
" WHERE PhaseName IN (";
for (const auto& cmd : commands) {
queryStr = queryStr + '\"' + cmd + "\",";
}
queryStr.back() = ')';
queryStr += " ORDER BY PhaseBegin; ";
QString queryStr = deviceConfig->getQueryStr(commands);
auto query = mExecuteQuery(tdb, queryStr);
if (!query.next())
@@ -189,7 +180,6 @@ PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr<Configuration
size_t rowIt = 0;
do {
// TODO factory method
phases[rowIt] = deviceConfig->makePhaseEntry(query);
++rowIt;

71
DRAMSys/traceAnalyzer/data/tracedb.cpp
View File

@@ -359,12 +359,12 @@ CommandLengths TraceDB::getCommandLengthsFromDB()
return {};
};
auto getCommandLength = [=, &table](const std::string &command) -> unsigned
auto getCommandLength = [=, &table](const std::string &command) -> double
{
QVariant length = getLengthFromDb(command);
if (length.isValid())
return length.toUInt();
return length.toDouble();
else
{
qDebug() << "CommandLength for" << command.c_str() << "not present in table" << table.c_str()
@@ -373,54 +373,33 @@ CommandLengths TraceDB::getCommandLengthsFromDB()
}
};
auto getCommandLengthOrElse = [=, &table](const std::string &command, const std::string &elseCommand) -> unsigned
{
QVariant length = getLengthFromDb(command);
double NOP = getCommandLength("NOP");
double RD = getCommandLength("RD");
double WR = getCommandLength("RD");
double RDA = getCommandLength("RDA");
double WRA = getCommandLength("WRA");
double ACT = getCommandLength("ACT");
if (length.isValid())
return length.toUInt();
else
{
length = getLengthFromDb(command);
double PREPB = getCommandLength("PREPB");
double REFPB = getCommandLength("REFPB");
if (length.isValid())
return length.toUInt();
else
{
qDebug() << "CommandLength for" << command.c_str() << "and" << elseCommand.c_str()
<< "not present in table" << table.c_str() << ". Defaulting to 1.";
return 1;
}
}
};
double RFMPB = getCommandLength("RFMPB");
double REFP2B = getCommandLength("REFP2B");
double RFMP2B = getCommandLength("RFMP2B");
double PRESB = getCommandLength("PRESB");
double REFSB = getCommandLength("REFSB");
double RFMSB = getCommandLength("RFMSB");
unsigned NOP = getCommandLength("NOP");
unsigned RD = getCommandLength("RD");
unsigned WR = getCommandLength("RD");
unsigned RDA = getCommandLength("RDA");
unsigned WRA = getCommandLength("WRA");
unsigned ACT = getCommandLength("ACT");
double PREAB = getCommandLength("PREAB");
double REFAB = getCommandLength("REFAB");
unsigned PREPB = getCommandLength("PREPB");
unsigned REFPB = getCommandLength("REFPB");
unsigned RFMPB = getCommandLength("RFMPB");
unsigned REFP2B = getCommandLength("REFP2B");
unsigned RFMP2B = getCommandLength("RFMP2B");
unsigned PRESB = getCommandLength("PRESB");
unsigned REFSB = getCommandLength("REFSB");
unsigned RFMSB = getCommandLength("RFMSB");
unsigned PREAB = getCommandLength("PREAB");
unsigned REFAB = getCommandLength("REFAB");
unsigned RFMAB = getCommandLength("RFMAB");
unsigned PDEA = getCommandLength("PDEA");
unsigned PDXA = getCommandLength("PDXA");
unsigned PDEP = getCommandLength("PDEP");
unsigned PDXP = getCommandLength("PDXP");
unsigned SREFEN = getCommandLength("SREFEN");
unsigned SREFEX = getCommandLength("SREFEX");
double RFMAB = getCommandLength("RFMAB");
double PDEA = getCommandLength("PDEA");
double PDXA = getCommandLength("PDXA");
double PDEP = getCommandLength("PDEP");
double PDXP = getCommandLength("PDXP");
double SREFEN = getCommandLength("SREFEN");
double SREFEX = getCommandLength("SREFEX");
return {NOP, RD, WR, RDA, WRA, ACT, PREPB, REFPB, RFMPB, REFP2B, RFMP2B, PRESB, REFSB, RFMSB,
PREAB, REFAB, RFMAB, PDEA, PDXA, PDEP, PDXP, SREFEN, SREFEX};

2
DRAMSys/traceAnalyzer/simulationdialog.h
View File

@@ -38,7 +38,7 @@
#include "ui_simulationdialog.h"
#include <Configuration.h>
#include <DRAMSysConfiguration.h>
#include <QFileInfo>
#include <QPointer>
#include <QProcess>