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Code refactoring.

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This commit is contained in:
Lukas Steiner
2021-06-15 17:21:08 +02:00
parent bfd16317d2
commit 66f72c88b6
50 changed files with 141 additions and 155 deletions
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3
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
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@@ -68,7 +68,8 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType,
tCK(sc_time(1.0 / fCKMHz, SC_US)),
memoryId(parseString(memspec["memoryId"], "memoryId")),
memoryType(memoryType),
burstDuration(tCK * (burstLength / dataRate))
burstDuration(tCK * (static_cast<double>(burstLength) / dataRate)),
memorySizeBytes(0)
{
commandLengthInCycles = std::vector<unsigned>(Command::numberOfCommands(), 1);
}

2
DRAMSys/library/src/configuration/memspec/MemSpec.h
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@@ -72,7 +72,7 @@ public:
const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO,
WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, STTMRAM} memoryType;
virtual ~MemSpec() {}
virtual ~MemSpec() = default;
virtual sc_time getRefreshIntervalAB() const;
virtual sc_time getRefreshIntervalPB() const;

6
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -142,12 +142,12 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL, tRL + burstDuration);
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

8
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -42,7 +42,7 @@
class MemSpecDDR3 final : public MemSpec
{
public:
MemSpecDDR3(nlohmann::json &memspec);
explicit MemSpecDDR3(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -87,10 +87,10 @@ public:
const double iDD3P0;
const double iDD3P1;
virtual sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECDDR3_H

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -67,9 +67,9 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tREFI ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) :
(tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 4)) :
((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) :
(tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 2)) :
(tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")))),
tRFC ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC4"], "RFC4")) :
@@ -162,12 +162,12 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL, tRL + burstDuration);
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

8
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -42,7 +42,7 @@
class MemSpecDDR4 final : public MemSpec
{
public:
MemSpecDDR4(nlohmann::json &memspec);
explicit MemSpecDDR4(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -95,10 +95,10 @@ public:
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECDDR4_H

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -230,20 +230,20 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
if (command == Command::RD || command == Command::RDA)
{
if (DramExtension::getBurstLength(payload) == 32)
return TimeInterval(tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset);
return {tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset};
else
return TimeInterval(tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset);
return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset};
}
else if (command == Command::WR || command == Command::WRA)
{
if (DramExtension::getBurstLength(payload) == 32)
return TimeInterval(tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset);
return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset};
else
return TimeInterval(tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset);
return {tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset};
}
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
View File

@@ -42,7 +42,7 @@
class MemSpecDDR5 final : public MemSpec
{
public:
MemSpecDDR5(nlohmann::json &memspec);
explicit MemSpecDDR5(nlohmann::json &memspec);
const unsigned numberOfDIMMRanks;
const unsigned physicalRanksPerDIMMRank;
@@ -109,11 +109,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalSB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalSB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECDDR5_H

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
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@@ -150,14 +150,12 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
View File

@@ -42,7 +42,7 @@
class MemSpecGDDR5 final : public MemSpec
{
public:
MemSpecGDDR5(nlohmann::json &memspec);
explicit MemSpecGDDR5(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
@@ -85,11 +85,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECGDDR5_H

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
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@@ -150,14 +150,12 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -42,7 +42,7 @@
class MemSpecGDDR5X final : public MemSpec
{
public:
MemSpecGDDR5X(nlohmann::json &memspec);
explicit MemSpecGDDR5X(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
@@ -85,11 +85,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECGDDR5X_H

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -152,14 +152,12 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
View File

@@ -42,7 +42,7 @@
struct MemSpecGDDR6 final : public MemSpec
{
public:
MemSpecGDDR6(nlohmann::json &memspec);
explicit MemSpecGDDR6(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
@@ -87,11 +87,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECGDDR6_H

6
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -152,12 +152,12 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

12
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -42,7 +42,7 @@
class MemSpecHBM2 final : public MemSpec
{
public:
MemSpecHBM2(nlohmann::json &memspec);
explicit MemSpecHBM2(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tDQSCK;
@@ -80,13 +80,13 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual bool hasRasAndCasBus() const override;
bool hasRasAndCasBus() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECHBM2_H

8
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -153,14 +153,12 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tDQSCK + 3 * tCK,
tRL + tDQSCK + burstDuration + 3 * tCK);
return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tDQSS + tDQS2DQ + 3 * tCK,
tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK);
return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK};
else
{
SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -42,7 +42,7 @@
class MemSpecLPDDR4 final : public MemSpec
{
public:
MemSpecLPDDR4(nlohmann::json &memspec);
explicit MemSpecLPDDR4(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tREFI;
@@ -80,11 +80,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECLPDDR4_H

6
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -120,12 +120,12 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl
TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL, tRL + burstDuration);
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

6
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
View File

@@ -42,7 +42,7 @@
class MemSpecSTTMRAM final : public MemSpec
{
public:
MemSpecSTTMRAM(nlohmann::json &memspec);
explicit MemSpecSTTMRAM(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -73,8 +73,8 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECSTTMRAM_H

6
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -147,12 +147,12 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tAC, tRL + tAC + burstDuration);
return {tRL + tAC, tRL + tAC + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

8
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -42,7 +42,7 @@
class MemSpecWideIO final : public MemSpec
{
public:
MemSpecWideIO(nlohmann::json &memspec);
explicit MemSpecWideIO(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -93,10 +93,10 @@ public:
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECWIDEIO_H

6
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -138,12 +138,12 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tDQSS, tWL + tDQSS + burstDuration);
return {tWL + tDQSS, tWL + tDQSS + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
View File

@@ -42,7 +42,7 @@
class MemSpecWideIO2 final : public MemSpec
{
public:
MemSpecWideIO2(nlohmann::json &memspec);
explicit MemSpecWideIO2(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tDQSCK;
@@ -74,11 +74,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECWIDEIO2_H

9
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -51,7 +51,8 @@
#include <array>
#include <cassert>
#include <cstdint>
#include <stdlib.h>
#include <cstdlib>
#include <cmath>
#include "../../common/DebugManager.h"
#include "../../common/dramExtensions.h"
#include "../../configuration/Configuration.h"
@@ -63,7 +64,7 @@
using namespace tlm;
using namespace DRAMPower;
Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
Dram::Dram(const sc_module_name &name) : sc_module(name), tSocket("socket")
{
Configuration &config = Configuration::getInstance();
// Adjust number of bytes per burst dynamically to the selected ecc controller
@@ -87,7 +88,7 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported");
memory = 0; // FIXME
#else
memory = (unsigned char *)mmap(NULL, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
memory = (unsigned char *)mmap(nullptr, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
#endif
}
}
@@ -140,7 +141,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
if (Configuration::getInstance().powerAnalysis)
{
int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}

4
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -54,7 +54,7 @@ private:
bool powerReported = false;
protected:
Dram(sc_module_name);
explicit Dram(const sc_module_name &name);
SC_HAS_PROCESS(Dram);
const MemSpec *memSpec = Configuration::getInstance().memSpec;
@@ -75,7 +75,7 @@ public:
tlm_utils::simple_target_socket<Dram> tSocket;
virtual void reportPower();
virtual ~Dram();
~Dram() override;
};
#endif // DRAM_H

6
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
View File

@@ -42,14 +42,14 @@
using namespace DRAMPower;
DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3");
if (Configuration::getInstance().powerAnalysis)
{
const MemSpecDDR3 *memSpec = dynamic_cast<const MemSpecDDR3 *>(this->memSpec);
const auto *memSpec = dynamic_cast<const MemSpecDDR3 *>(this->memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen");
@@ -139,6 +139,6 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, 0);
DRAMPower = new libDRAMPower(powerSpec, false);
}
}

3
DRAMSys/library/src/simulation/dram/DramDDR3.h
View File

@@ -42,9 +42,8 @@
class DramDDR3 : public Dram
{
public:
DramDDR3(sc_module_name);
explicit DramDDR3(const sc_module_name&);
SC_HAS_PROCESS(DramDDR3);
virtual ~DramDDR3() {}
};
#endif // DRAMDDR3_H

6
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
View File

@@ -42,14 +42,14 @@
using namespace DRAMPower;
DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4");
if (Configuration::getInstance().powerAnalysis)
{
const MemSpecDDR4 *memSpec = dynamic_cast<const MemSpecDDR4 *>(this->memSpec);
const auto *memSpec = dynamic_cast<const MemSpecDDR4 *>(this->memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen");
@@ -139,6 +139,6 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, 0);
DRAMPower = new libDRAMPower(powerSpec, false);
}
}

3
DRAMSys/library/src/simulation/dram/DramDDR4.h
View File

@@ -42,9 +42,8 @@
class DramDDR4 : public Dram
{
public:
DramDDR4(sc_module_name);
explicit DramDDR4(const sc_module_name &name);
SC_HAS_PROCESS(DramDDR4);
virtual ~DramDDR4() {}
};
#endif // DRAMDDR4_H

2
DRAMSys/library/src/simulation/dram/DramDDR5.cpp
View File

@@ -42,7 +42,7 @@
using namespace DRAMPower;
DramDDR5::DramDDR5(sc_module_name name) : Dram(name)
DramDDR5::DramDDR5(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramDDR5", "Error Model not supported for DDR5");

3
DRAMSys/library/src/simulation/dram/DramDDR5.h
View File

@@ -42,9 +42,8 @@
class DramDDR5 : public Dram
{
public:
DramDDR5(sc_module_name);
explicit DramDDR5(const sc_module_name &name);
SC_HAS_PROCESS(DramDDR5);
virtual ~DramDDR5() {}
};
#endif // DRAMDDR5_H

2
DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR5.h"
DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name)
DramGDDR5::DramGDDR5(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5");

3
DRAMSys/library/src/simulation/dram/DramGDDR5.h
View File

@@ -42,9 +42,8 @@
class DramGDDR5 : public Dram
{
public:
DramGDDR5(sc_module_name);
explicit DramGDDR5(const sc_module_name &name);
SC_HAS_PROCESS(DramGDDR5);
virtual ~DramGDDR5() {}
};
#endif // DRAMGDDR5_H

2
DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR5X.h"
DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name)
DramGDDR5X::DramGDDR5X(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X");

3
DRAMSys/library/src/simulation/dram/DramGDDR5X.h
View File

@@ -42,9 +42,8 @@
class DramGDDR5X : public Dram
{
public:
DramGDDR5X(sc_module_name);
explicit DramGDDR5X(const sc_module_name &name);
SC_HAS_PROCESS(DramGDDR5X);
virtual ~DramGDDR5X() {}
};
#endif // DRAMGDDR5X_H

2
DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR6.h"
DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name)
DramGDDR6::DramGDDR6(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6");

3
DRAMSys/library/src/simulation/dram/DramGDDR6.h
View File

@@ -42,9 +42,8 @@
class DramGDDR6 : public Dram
{
public:
DramGDDR6(sc_module_name);
explicit DramGDDR6(const sc_module_name &name);
SC_HAS_PROCESS(DramGDDR6);
virtual ~DramGDDR6() {}
};

2
DRAMSys/library/src/simulation/dram/DramHBM2.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecHBM2.h"
DramHBM2::DramHBM2(sc_module_name name) : Dram(name)
DramHBM2::DramHBM2(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2");

3
DRAMSys/library/src/simulation/dram/DramHBM2.h
View File

@@ -42,9 +42,8 @@
class DramHBM2 : public Dram
{
public:
DramHBM2(sc_module_name);
explicit DramHBM2(const sc_module_name &name);
SC_HAS_PROCESS(DramHBM2);
virtual ~DramHBM2() {}
};
#endif // DRAMHBM2_H

2
DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecLPDDR4.h"
DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name)
DramLPDDR4::DramLPDDR4(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4");

3
DRAMSys/library/src/simulation/dram/DramLPDDR4.h
View File

@@ -42,9 +42,8 @@
class DramLPDDR4 : public Dram
{
public:
DramLPDDR4(sc_module_name);
explicit DramLPDDR4(const sc_module_name &name);
SC_HAS_PROCESS(DramLPDDR4);
virtual ~DramLPDDR4() {}
};
#endif // DRAMLPDDR4_H

10
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -35,6 +35,7 @@
#include "DramRecordable.h"
#include <cmath>
#include <systemc.h>
#include <tlm.h>
#include "../../common/TlmRecorder.h"
@@ -54,7 +55,7 @@
using namespace tlm;
template<class BaseDram>
DramRecordable<BaseDram>::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder)
DramRecordable<BaseDram>::DramRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder)
: BaseDram(name), tlmRecorder(tlmRecorder)
{
// Create a thread that is triggered every $powerWindowSize
@@ -120,11 +121,12 @@ void DramRecordable<BaseDram>::powerWindow()
{
int64_t clkCycles = 0;
do {
while (true)
{
// At the very beginning (zero clock cycles) the energy is 0, so we wait first
wait(powerWindowSize);
clkCycles = static_cast<int64_t>(sc_time_stamp() / this->memSpec->tCK + 0.5);
clkCycles = std::lround(sc_time_stamp() / this->memSpec->tCK);
this->DRAMPower->calcWindowEnergy(clkCycles);
@@ -144,7 +146,7 @@ void DramRecordable<BaseDram>::powerWindow()
this->DRAMPower->getPower().window_average_power *
Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]"));
} while (true);
}
}
template class DramRecordable<DramDDR3>;

9
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -46,15 +46,14 @@ template<class BaseDram>
class DramRecordable final : public BaseDram
{
public:
DramRecordable(sc_module_name, TlmRecorder *);
DramRecordable(const sc_module_name &name, TlmRecorder *);
SC_HAS_PROCESS(DramRecordable);
virtual ~DramRecordable() {}
virtual void reportPower() override;
void reportPower() override;
private:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);

2
DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp
View File

@@ -42,7 +42,7 @@
using namespace DRAMPower;
DramSTTMRAM::DramSTTMRAM(sc_module_name name) : Dram(name)
DramSTTMRAM::DramSTTMRAM(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramSTTMRAM", "Error Model not supported for STT-MRAM");

3
DRAMSys/library/src/simulation/dram/DramSTTMRAM.h
View File

@@ -42,9 +42,8 @@
class DramSTTMRAM : public Dram
{
public:
DramSTTMRAM(sc_module_name);
explicit DramSTTMRAM(const sc_module_name &name);
SC_HAS_PROCESS(DramSTTMRAM);
virtual ~DramSTTMRAM() {}
};
#endif // DRAMSTTMRAM_H

9
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -35,6 +35,7 @@
#include "DramWideIO.h"
#include <cmath>
#include <systemc.h>
#include <tlm.h>
#include "Dram.h"
@@ -46,11 +47,11 @@
using namespace tlm;
using namespace DRAMPower;
DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
{
if (Configuration::getInstance().powerAnalysis)
{
const MemSpecWideIO *memSpec = dynamic_cast<const MemSpecWideIO *>(this->memSpec);
const auto *memSpec = dynamic_cast<const MemSpecWideIO *>(this->memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen");
@@ -140,7 +141,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, 0);
DRAMPower = new libDRAMPower(powerSpec, false);
// For each bank in a channel a error Model is created:
if (storeMode == Configuration::StoreMode::ErrorModel)
@@ -184,7 +185,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
if (Configuration::getInstance().powerAnalysis)
{
int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}

8
DRAMSys/library/src/simulation/dram/DramWideIO.h
View File

@@ -44,13 +44,13 @@
class DramWideIO : public Dram
{
public:
DramWideIO(sc_module_name);
explicit DramWideIO(const sc_module_name &name);
SC_HAS_PROCESS(DramWideIO);
virtual ~DramWideIO();
~DramWideIO() override;
protected:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
private:
std::vector<errorModel *> ememory;

2
DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecWideIO2.h"
DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name)
DramWideIO2::DramWideIO2(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2");

3
DRAMSys/library/src/simulation/dram/DramWideIO2.h
View File

@@ -42,9 +42,8 @@
class DramWideIO2 : public Dram
{
public:
DramWideIO2(sc_module_name);
explicit DramWideIO2(const sc_module_name &name);
SC_HAS_PROCESS(DramWideIO2);
virtual ~DramWideIO2() {}
};
#endif // DRAMWIDEIO2_H