diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
index 7cd28f80..cba95c58 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
@@ -68,7 +68,8 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType,
       tCK(sc_time(1.0 / fCKMHz, SC_US)),
       memoryId(parseString(memspec["memoryId"], "memoryId")),
       memoryType(memoryType),
-      burstDuration(tCK * (burstLength / dataRate))
+      burstDuration(tCK * (static_cast<double>(burstLength) / dataRate)),
+      memorySizeBytes(0)
 {
     commandLengthInCycles = std::vector<unsigned>(Command::numberOfCommands(), 1);
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h
index 6596c388..d8bdec44 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h
@@ -72,7 +72,7 @@ public:
     const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO,
             WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, STTMRAM} memoryType;
 
-    virtual ~MemSpec() {}
+    virtual ~MemSpec() = default;
 
     virtual sc_time getRefreshIntervalAB() const;
     virtual sc_time getRefreshIntervalPB() const;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
index e56f62f4..5144172e 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
@@ -142,12 +142,12 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
 TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL, tRL + burstDuration);
+        return {tRL, tRL + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL, tWL + burstDuration);
+        return {tWL, tWL + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
index b0910bbd..d238031b 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
@@ -42,7 +42,7 @@
 class MemSpecDDR3 final : public MemSpec
 {
 public:
-    MemSpecDDR3(nlohmann::json &memspec);
+    explicit MemSpecDDR3(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tCKE;
@@ -87,10 +87,10 @@ public:
     const double iDD3P0;
     const double iDD3P1;
 
-    virtual sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalAB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECDDR3_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
index 3f705235..72dfffe7 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
@@ -67,9 +67,9 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
       tXP      (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
       tXS      (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
       tREFI    ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
-                   (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) :
+                   (tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 4)) :
                    ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
-                   (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) :
+                   (tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 2)) :
                    (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")))),
       tRFC     ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
                    (tCK * parseUint(memspec["memtimingspec"]["RFC4"], "RFC4")) :
@@ -162,12 +162,12 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
 TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL, tRL + burstDuration);
+        return {tRL, tRL + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL, tWL + burstDuration);
+        return {tWL, tWL + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
index 5db3b3ea..85571ae7 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
@@ -42,7 +42,7 @@
 class MemSpecDDR4 final : public MemSpec
 {
 public:
-    MemSpecDDR4(nlohmann::json &memspec);
+    explicit MemSpecDDR4(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tCKE;
@@ -95,10 +95,10 @@ public:
     const double iDD62;
     const double vDD2;
 
-    virtual sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalAB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECDDR4_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
index 990ea9d7..a21699f5 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
@@ -230,20 +230,20 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
     if (command == Command::RD || command == Command::RDA)
     {
         if (DramExtension::getBurstLength(payload) == 32)
-            return TimeInterval(tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset);
+            return {tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset};
         else
-            return TimeInterval(tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset);
+            return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset};
     }
     else if (command == Command::WR || command == Command::WRA)
     {
         if (DramExtension::getBurstLength(payload) == 32)
-            return TimeInterval(tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset);
+            return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset};
         else
-            return TimeInterval(tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset);
+            return {tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset};
     }
     else
     {
         SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
index 95142700..62076591 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
@@ -42,7 +42,7 @@
 class MemSpecDDR5 final : public MemSpec
 {
 public:
-    MemSpecDDR5(nlohmann::json &memspec);
+    explicit MemSpecDDR5(nlohmann::json &memspec);
 
     const unsigned numberOfDIMMRanks;
     const unsigned physicalRanksPerDIMMRank;
@@ -109,11 +109,11 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalSB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalSB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECDDR5_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
index de222b57..5de6bba8 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
@@ -150,14 +150,12 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
 TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
-                tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
+        return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
-                tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
+        return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
index 6c607421..2fe5a733 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
@@ -42,7 +42,7 @@
 class MemSpecGDDR5 final : public MemSpec
 {
 public:
-    MemSpecGDDR5(nlohmann::json &memspec);
+    explicit MemSpecGDDR5(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tRP;
@@ -85,11 +85,11 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalPB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalPB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECGDDR5_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
index 6667d00f..a00bcc26 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
@@ -150,14 +150,12 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
 TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
-                tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
+        return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
-                tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
+        return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
index da79ad3b..ab9c0c5c 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
@@ -42,7 +42,7 @@
 class MemSpecGDDR5X final : public MemSpec
 {
 public:
-    MemSpecGDDR5X(nlohmann::json &memspec);
+    explicit MemSpecGDDR5X(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tRP;
@@ -85,11 +85,11 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalPB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalPB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECGDDR5X_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
index 6107d89b..d305cf15 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
@@ -152,14 +152,12 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
 TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
-                tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
+        return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
-                tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
+        return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
index da13f143..e39165e8 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
@@ -42,7 +42,7 @@
 struct MemSpecGDDR6 final : public MemSpec
 {
 public:
-    MemSpecGDDR6(nlohmann::json &memspec);
+    explicit MemSpecGDDR6(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tRP;
@@ -87,11 +87,11 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalPB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalPB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECGDDR6_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
index afc986a2..a49a3c47 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
@@ -152,12 +152,12 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
 TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
+        return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL, tWL + burstDuration);
+        return {tWL, tWL + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
index 9572a7a0..04ff4d81 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
@@ -42,7 +42,7 @@
 class MemSpecHBM2 final : public MemSpec
 {
 public:
-    MemSpecHBM2(nlohmann::json &memspec);
+    explicit MemSpecHBM2(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tDQSCK;
@@ -80,13 +80,13 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalPB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalPB() const override;
 
-    virtual bool hasRasAndCasBus() const override;
+    bool hasRasAndCasBus() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECHBM2_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
index e24fbb67..2fe87bb7 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
@@ -153,14 +153,12 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
 TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL + tDQSCK + 3 * tCK,
-                            tRL + tDQSCK + burstDuration + 3 * tCK);
+        return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL + tDQSS + tDQS2DQ + 3 * tCK,
-                            tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK);
+        return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK};
     else
     {
         SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
index 42e4e076..6e65d09f 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
@@ -42,7 +42,7 @@
 class MemSpecLPDDR4 final : public MemSpec
 {
 public:
-    MemSpecLPDDR4(nlohmann::json &memspec);
+    explicit MemSpecLPDDR4(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tREFI;
@@ -80,11 +80,11 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalPB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalPB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECLPDDR4_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
index 73b97171..626e374a 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
@@ -120,12 +120,12 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl
 TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL, tRL + burstDuration);
+        return {tRL, tRL + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL, tWL + burstDuration);
+        return {tWL, tWL + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
index 323e8adb..e4eddfce 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
@@ -42,7 +42,7 @@
 class MemSpecSTTMRAM final : public MemSpec
 {
 public:
-    MemSpecSTTMRAM(nlohmann::json &memspec);
+    explicit MemSpecSTTMRAM(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tCKE;
@@ -73,8 +73,8 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECSTTMRAM_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
index c88dde77..fbd39ef7 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
@@ -147,12 +147,12 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
 TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL + tAC, tRL + tAC + burstDuration);
+        return {tRL + tAC, tRL + tAC + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL, tWL + burstDuration);
+        return {tWL, tWL + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
index ad50ba1c..bf3b88b7 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
@@ -42,7 +42,7 @@
 class MemSpecWideIO final : public MemSpec
 {
 public:
-    MemSpecWideIO(nlohmann::json &memspec);
+    explicit MemSpecWideIO(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tCKE;
@@ -93,10 +93,10 @@ public:
     const double iDD62;
     const double vDD2;
 
-    virtual sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalAB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECWIDEIO_H
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
index 4746b0ad..1077d0b5 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
@@ -138,12 +138,12 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
 TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
 {
     if (command == Command::RD || command == Command::RDA)
-        return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
+        return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
     else if (command == Command::WR || command == Command::WRA)
-        return TimeInterval(tWL + tDQSS, tWL + tDQSS + burstDuration);
+        return {tWL + tDQSS, tWL + tDQSS + burstDuration};
     else
     {
         SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
-        return TimeInterval();
+        return {};
     }
 }
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
index 494f8665..6069e56a 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
@@ -42,7 +42,7 @@
 class MemSpecWideIO2 final : public MemSpec
 {
 public:
-    MemSpecWideIO2(nlohmann::json &memspec);
+    explicit MemSpecWideIO2(nlohmann::json &memspec);
 
     // Memspec Variables:
     const sc_time tDQSCK;
@@ -74,11 +74,11 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    virtual sc_time getRefreshIntervalAB() const override;
-    virtual sc_time getRefreshIntervalPB() const override;
+    sc_time getRefreshIntervalAB() const override;
+    sc_time getRefreshIntervalPB() const override;
 
-    virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 };
 
 #endif // MEMSPECWIDEIO2_H
diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp
index 8624b4c1..a897f0c1 100644
--- a/DRAMSys/library/src/simulation/dram/Dram.cpp
+++ b/DRAMSys/library/src/simulation/dram/Dram.cpp
@@ -51,7 +51,8 @@
 #include <array>
 #include <cassert>
 #include <cstdint>
-#include <stdlib.h>
+#include <cstdlib>
+#include <cmath>
 #include "../../common/DebugManager.h"
 #include "../../common/dramExtensions.h"
 #include "../../configuration/Configuration.h"
@@ -63,7 +64,7 @@
 using namespace tlm;
 using namespace DRAMPower;
 
-Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
+Dram::Dram(const sc_module_name &name) : sc_module(name), tSocket("socket")
 {
     Configuration &config = Configuration::getInstance();
     // Adjust number of bytes per burst dynamically to the selected ecc controller
@@ -87,7 +88,7 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
                 SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported");
                 memory = 0; // FIXME
             #else
-                memory = (unsigned char *)mmap(NULL, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
+                memory = (unsigned char *)mmap(nullptr, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
             #endif
         }
     }
@@ -140,7 +141,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
     if (Configuration::getInstance().powerAnalysis)
     {
         int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
-        int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
+        int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK);
         DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
     }
 
diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h
index 43d08ddb..18e9162c 100644
--- a/DRAMSys/library/src/simulation/dram/Dram.h
+++ b/DRAMSys/library/src/simulation/dram/Dram.h
@@ -54,7 +54,7 @@ private:
     bool powerReported = false;
 
 protected:
-    Dram(sc_module_name);
+    explicit Dram(const sc_module_name &name);
     SC_HAS_PROCESS(Dram);
 
     const MemSpec *memSpec = Configuration::getInstance().memSpec;
@@ -75,7 +75,7 @@ public:
     tlm_utils::simple_target_socket<Dram> tSocket;
 
     virtual void reportPower();
-    virtual ~Dram();
+    ~Dram() override;
 };
 
 #endif // DRAM_H
diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp
index be8ce944..de363dc9 100644
--- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp
@@ -42,14 +42,14 @@
 
 using namespace DRAMPower;
 
-DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
+DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3");
 
     if (Configuration::getInstance().powerAnalysis)
     {
-        const MemSpecDDR3 *memSpec = dynamic_cast<const MemSpecDDR3 *>(this->memSpec);
+        const auto *memSpec = dynamic_cast<const MemSpecDDR3 *>(this->memSpec);
         if (memSpec == nullptr)
             SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen");
 
@@ -139,6 +139,6 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
         powerSpec.memPowerSpec  = memPowerSpec;
         powerSpec.memArchSpec   = memArchSpec;
 
-        DRAMPower = new libDRAMPower(powerSpec, 0);
+        DRAMPower = new libDRAMPower(powerSpec, false);
     }
 }
diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.h b/DRAMSys/library/src/simulation/dram/DramDDR3.h
index 13545740..2f75c328 100644
--- a/DRAMSys/library/src/simulation/dram/DramDDR3.h
+++ b/DRAMSys/library/src/simulation/dram/DramDDR3.h
@@ -42,9 +42,8 @@
 class DramDDR3 : public Dram
 {
 public:
-    DramDDR3(sc_module_name);
+    explicit DramDDR3(const sc_module_name&);
     SC_HAS_PROCESS(DramDDR3);
-    virtual ~DramDDR3() {}
 };
 
 #endif // DRAMDDR3_H
diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp
index 7ebbff11..30c132f8 100644
--- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp
@@ -42,14 +42,14 @@
 
 using namespace DRAMPower;
 
-DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
+DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4");
 
     if (Configuration::getInstance().powerAnalysis)
     {
-        const MemSpecDDR4 *memSpec = dynamic_cast<const MemSpecDDR4 *>(this->memSpec);
+        const auto *memSpec = dynamic_cast<const MemSpecDDR4 *>(this->memSpec);
         if (memSpec == nullptr)
             SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen");
 
@@ -139,6 +139,6 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
         powerSpec.memPowerSpec  = memPowerSpec;
         powerSpec.memArchSpec   = memArchSpec;
 
-        DRAMPower = new libDRAMPower(powerSpec, 0);
+        DRAMPower = new libDRAMPower(powerSpec, false);
     }
 }
diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.h b/DRAMSys/library/src/simulation/dram/DramDDR4.h
index 3e68eb1b..5c10f57a 100644
--- a/DRAMSys/library/src/simulation/dram/DramDDR4.h
+++ b/DRAMSys/library/src/simulation/dram/DramDDR4.h
@@ -42,9 +42,8 @@
 class DramDDR4 : public Dram
 {
 public:
-    DramDDR4(sc_module_name);
+    explicit DramDDR4(const sc_module_name &name);
     SC_HAS_PROCESS(DramDDR4);
-    virtual ~DramDDR4() {}
 };
 
 #endif // DRAMDDR4_H
diff --git a/DRAMSys/library/src/simulation/dram/DramDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramDDR5.cpp
index 8b10e911..f4d1f2be 100644
--- a/DRAMSys/library/src/simulation/dram/DramDDR5.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramDDR5.cpp
@@ -42,7 +42,7 @@
 
 using namespace DRAMPower;
 
-DramDDR5::DramDDR5(sc_module_name name) : Dram(name)
+DramDDR5::DramDDR5(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramDDR5", "Error Model not supported for DDR5");
diff --git a/DRAMSys/library/src/simulation/dram/DramDDR5.h b/DRAMSys/library/src/simulation/dram/DramDDR5.h
index 14898af1..4d7042ae 100644
--- a/DRAMSys/library/src/simulation/dram/DramDDR5.h
+++ b/DRAMSys/library/src/simulation/dram/DramDDR5.h
@@ -42,9 +42,8 @@
 class DramDDR5 : public Dram
 {
 public:
-    DramDDR5(sc_module_name);
+    explicit DramDDR5(const sc_module_name &name);
     SC_HAS_PROCESS(DramDDR5);
-    virtual ~DramDDR5() {}
 };
 
 #endif // DRAMDDR5_H
diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
index e3fe6014..40f0c309 100644
--- a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
@@ -40,7 +40,7 @@
 #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../../configuration/memspec/MemSpecGDDR5.h"
 
-DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name)
+DramGDDR5::DramGDDR5(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5");
diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.h b/DRAMSys/library/src/simulation/dram/DramGDDR5.h
index ced59f23..979811de 100644
--- a/DRAMSys/library/src/simulation/dram/DramGDDR5.h
+++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.h
@@ -42,9 +42,8 @@
 class DramGDDR5 : public Dram
 {
 public:
-    DramGDDR5(sc_module_name);
+    explicit DramGDDR5(const sc_module_name &name);
     SC_HAS_PROCESS(DramGDDR5);
-    virtual ~DramGDDR5() {}
 };
 
 #endif // DRAMGDDR5_H
diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
index 3c767638..cabd8cfe 100644
--- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
@@ -40,7 +40,7 @@
 #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../../configuration/memspec/MemSpecGDDR5X.h"
 
-DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name)
+DramGDDR5X::DramGDDR5X(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X");
diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h
index 7027c6ae..a8432bf6 100644
--- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h
+++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h
@@ -42,9 +42,8 @@
 class DramGDDR5X : public Dram
 {
 public:
-    DramGDDR5X(sc_module_name);
+    explicit DramGDDR5X(const sc_module_name &name);
     SC_HAS_PROCESS(DramGDDR5X);
-    virtual ~DramGDDR5X() {}
 };
 
 #endif // DRAMGDDR5X_H
diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
index 24fbed6f..068bbf72 100644
--- a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
@@ -40,7 +40,7 @@
 #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../../configuration/memspec/MemSpecGDDR6.h"
 
-DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name)
+DramGDDR6::DramGDDR6(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6");
diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.h b/DRAMSys/library/src/simulation/dram/DramGDDR6.h
index 02904fd4..088b7acd 100644
--- a/DRAMSys/library/src/simulation/dram/DramGDDR6.h
+++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.h
@@ -42,9 +42,8 @@
 class DramGDDR6 : public Dram
 {
 public:
-    DramGDDR6(sc_module_name);
+    explicit DramGDDR6(const sc_module_name &name);
     SC_HAS_PROCESS(DramGDDR6);
-    virtual ~DramGDDR6() {}
 };
 
 
diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp
index 1dec6977..ef01f51d 100644
--- a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp
@@ -40,7 +40,7 @@
 #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../../configuration/memspec/MemSpecHBM2.h"
 
-DramHBM2::DramHBM2(sc_module_name name) : Dram(name)
+DramHBM2::DramHBM2(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2");
diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.h b/DRAMSys/library/src/simulation/dram/DramHBM2.h
index eaa86278..05315d9a 100644
--- a/DRAMSys/library/src/simulation/dram/DramHBM2.h
+++ b/DRAMSys/library/src/simulation/dram/DramHBM2.h
@@ -42,9 +42,8 @@
 class DramHBM2 : public Dram
 {
 public:
-    DramHBM2(sc_module_name);
+    explicit DramHBM2(const sc_module_name &name);
     SC_HAS_PROCESS(DramHBM2);
-    virtual ~DramHBM2() {}
 };
 
 #endif // DRAMHBM2_H
diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
index 503d2774..716242f3 100644
--- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
@@ -40,7 +40,7 @@
 #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../../configuration/memspec/MemSpecLPDDR4.h"
 
-DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name)
+DramLPDDR4::DramLPDDR4(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4");
diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h
index 0116e722..611ea1aa 100644
--- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h
+++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h
@@ -42,9 +42,8 @@
 class DramLPDDR4 : public Dram
 {
 public:
-    DramLPDDR4(sc_module_name);
+    explicit DramLPDDR4(const sc_module_name &name);
     SC_HAS_PROCESS(DramLPDDR4);
-    virtual ~DramLPDDR4() {}
 };
 
 #endif // DRAMLPDDR4_H
diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp
index 98749037..aaa2491d 100644
--- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp
@@ -35,6 +35,7 @@
 
 #include "DramRecordable.h"
 
+#include <cmath>
 #include <systemc.h>
 #include <tlm.h>
 #include "../../common/TlmRecorder.h"
@@ -54,7 +55,7 @@
 using namespace tlm;
 
 template<class BaseDram>
-DramRecordable<BaseDram>::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder)
+DramRecordable<BaseDram>::DramRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder)
     : BaseDram(name), tlmRecorder(tlmRecorder)
 {
     // Create a thread that is triggered every $powerWindowSize
@@ -120,11 +121,12 @@ void DramRecordable<BaseDram>::powerWindow()
 {
     int64_t clkCycles = 0;
 
-    do {
+    while (true)
+    {
         // At the very beginning (zero clock cycles) the energy is 0, so we wait first
         wait(powerWindowSize);
 
-        clkCycles = static_cast<int64_t>(sc_time_stamp() / this->memSpec->tCK + 0.5);
+        clkCycles = std::lround(sc_time_stamp() / this->memSpec->tCK);
 
         this->DRAMPower->calcWindowEnergy(clkCycles);
 
@@ -144,7 +146,7 @@ void DramRecordable<BaseDram>::powerWindow()
                               this->DRAMPower->getPower().window_average_power *
                               Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]"));
 
-    } while (true);
+    }
 }
 
 template class DramRecordable<DramDDR3>;
diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h
index e750ecfc..cf6122d9 100644
--- a/DRAMSys/library/src/simulation/dram/DramRecordable.h
+++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h
@@ -46,15 +46,14 @@ template<class BaseDram>
 class DramRecordable final : public BaseDram
 {
 public:
-    DramRecordable(sc_module_name, TlmRecorder *);
+    DramRecordable(const sc_module_name &name, TlmRecorder *);
     SC_HAS_PROCESS(DramRecordable);
-    virtual ~DramRecordable() {}
 
-    virtual void reportPower() override;
+    void reportPower() override;
 
 private:
-    virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
-                                          tlm::tlm_phase &phase, sc_time &delay) override;
+    tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
+                                       tlm::tlm_phase &phase, sc_time &delay) override;
 
     void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
 
diff --git a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp
index 3680ce05..5ecffd8e 100644
--- a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp
@@ -42,7 +42,7 @@
 
 using namespace DRAMPower;
 
-DramSTTMRAM::DramSTTMRAM(sc_module_name name) : Dram(name)
+DramSTTMRAM::DramSTTMRAM(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramSTTMRAM", "Error Model not supported for STT-MRAM");
diff --git a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h
index 3d481be1..3df7ac11 100644
--- a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h
+++ b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h
@@ -42,9 +42,8 @@
 class DramSTTMRAM : public Dram
 {
 public:
-    DramSTTMRAM(sc_module_name);
+    explicit DramSTTMRAM(const sc_module_name &name);
     SC_HAS_PROCESS(DramSTTMRAM);
-    virtual ~DramSTTMRAM() {}
 };
 
 #endif // DRAMSTTMRAM_H
diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp
index c0fe072c..7b978695 100644
--- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp
@@ -35,6 +35,7 @@
 
 #include "DramWideIO.h"
 
+#include <cmath>
 #include <systemc.h>
 #include <tlm.h>
 #include "Dram.h"
@@ -46,11 +47,11 @@
 using namespace tlm;
 using namespace DRAMPower;
 
-DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
+DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
 {
     if (Configuration::getInstance().powerAnalysis)
     {
-        const MemSpecWideIO *memSpec = dynamic_cast<const MemSpecWideIO *>(this->memSpec);
+        const auto *memSpec = dynamic_cast<const MemSpecWideIO *>(this->memSpec);
         if (memSpec == nullptr)
             SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen");
 
@@ -140,7 +141,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
         powerSpec.memPowerSpec  = memPowerSpec;
         powerSpec.memArchSpec   = memArchSpec;
 
-        DRAMPower = new libDRAMPower(powerSpec, 0);
+        DRAMPower = new libDRAMPower(powerSpec, false);
 
         // For each bank in a channel a error Model is created:
         if (storeMode == Configuration::StoreMode::ErrorModel)
@@ -184,7 +185,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
     if (Configuration::getInstance().powerAnalysis)
     {
         int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
-        int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
+        int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK);
         DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
     }
 
diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.h b/DRAMSys/library/src/simulation/dram/DramWideIO.h
index b54c8c15..d46b0867 100644
--- a/DRAMSys/library/src/simulation/dram/DramWideIO.h
+++ b/DRAMSys/library/src/simulation/dram/DramWideIO.h
@@ -44,13 +44,13 @@
 class DramWideIO : public Dram
 {
 public:
-    DramWideIO(sc_module_name);
+    explicit DramWideIO(const sc_module_name &name);
     SC_HAS_PROCESS(DramWideIO);
-    virtual ~DramWideIO();
+    ~DramWideIO() override;
 
 protected:
-    virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
-                                          tlm::tlm_phase &phase, sc_time &delay) override;
+    tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
+                                       tlm::tlm_phase &phase, sc_time &delay) override;
 
 private:
     std::vector<errorModel *> ememory;
diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
index 2dbce0cc..a5b33758 100644
--- a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
+++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
@@ -40,7 +40,7 @@
 #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../../configuration/memspec/MemSpecWideIO2.h"
 
-DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name)
+DramWideIO2::DramWideIO2(const sc_module_name &name) : Dram(name)
 {
     if (storeMode == Configuration::StoreMode::ErrorModel)
         SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2");
diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.h b/DRAMSys/library/src/simulation/dram/DramWideIO2.h
index 8e00c077..aa26a175 100644
--- a/DRAMSys/library/src/simulation/dram/DramWideIO2.h
+++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.h
@@ -42,9 +42,8 @@
 class DramWideIO2 : public Dram
 {
 public:
-    DramWideIO2(sc_module_name);
+    explicit DramWideIO2(const sc_module_name &name);
     SC_HAS_PROCESS(DramWideIO2);
-    virtual ~DramWideIO2() {}
 };
 
 #endif // DRAMWIDEIO2_H