changed build structure

This commit is contained in:
gernhard
2014-03-15 18:31:16 +01:00
parent 8ecd91c040
commit 4dffbf9383
49 changed files with 214 additions and 447 deletions

View File

@@ -1,20 +1,22 @@
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@@ -131,9 +161,13 @@
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2
DRAM/.gitignore vendored
View File

@@ -1 +1,3 @@
/Debug
/platformArchitect
/standalone

View File

@@ -1,20 +1,23 @@
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View File

@@ -15,13 +15,15 @@ namespace controller{
struct Configuration
{
Configuration():Timings(numberOfBanks){}
unsigned int numberOfBanks = 8;
Configuration(): numberOfBanks(8),Timings(numberOfBanks), RefreshBankwise(false),
nActivate(4)
{}
unsigned int numberOfBanks;
TimingConfiguration Timings;
bool RefreshBankwise = false;
bool RefreshBankwise;
unsigned int nActivate = 4;
unsigned int nActivate;
};
} /* namespace controller */

View File

@@ -19,10 +19,10 @@ Controller::Controller() :
*this), refreshManager(config.Timings.refreshTimings[0], bus), bus(config, state,
allCommandChecker)
{
addCommandChecker(Command::Activate, new ActivateChecker(config, bus));
addCommandChecker(Command::Precharge, new PrechargeChecker(config, bus));
addCommandChecker(Command::Read, new ReadChecker(config, bus));
addCommandChecker(Command::Write, new WriteChecker(config, bus));
addCommandChecker(Activate, new ActivateChecker(config, bus));
addCommandChecker(Precharge, new PrechargeChecker(config, bus));
addCommandChecker(Read, new ReadChecker(config, bus));
addCommandChecker(Write, new WriteChecker(config, bus));
}
void Controller::addCommandChecker(Command command, ICommandChecker* checker)

View File

@@ -17,7 +17,7 @@ public:
ControllerState(unsigned int numberOfBanks);
virtual ~ControllerState();
common::BankStates bankStates;
BankStates bankStates;
};
} /* namespace controller */

View File

@@ -30,27 +30,26 @@ struct TimingConfiguration
sc_time tREFI = sc_time(15.6, SC_US); //TODO align
refreshTimings.push_back(RefreshTiming(tRFC, tREFI));
}
clk = sc_time(6.0, SC_NS); // 166MHz
tRP = 3*clk; //precharge-time (pre -> act same bank)
tRAS = 6*clk; //active-time (act -> pre same bank)
tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks)
tRCD = 5*clk; //act -> read/write
tTAW = clkAlign(sc_time(50, SC_NS), clk);
}
sc_time clk = sc_time(6.0, SC_NS); // 166MHz
sc_time tRP = 3*clk; //precharge-time (pre -> act same bank)
sc_time tRAS = 6*clk; //active-time (act -> pre same bank)
sc_time tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks)
sc_time tRCD = 5*clk; //act -> read/write
sc_time tTAW = clkAlign(sc_time(50, SC_NS), clk, Alignment::UP);
//Refresh
//sc_time tRFC = 18*clk;
//sc_time tREF = sc_time(64, SC_MS);
//sc_time tREFA = tRP + tRFC;
//sc_time tREFB = tRP + tRC;
//sc_time tREFI = tREFA;
sc_time clk;
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRRD;
sc_time tRCD;
sc_time tTAW;
std::vector<RefreshTiming> refreshTimings;

View File

@@ -7,7 +7,6 @@
#include <core/refresh/BankwiseRefreshManager.h>
using namespace common;
using namespace std;
namespace controller {

View File

@@ -9,7 +9,7 @@
#define BANKWISEREFRESHMANAGER_H_
#include "IRefreshManager.h"
#include "common/dramextension.h"
#include "common/dramExtension.h"
#include "RefreshManager.h"
namespace controller {

View File

@@ -8,7 +8,7 @@
#include <core/refresh/RefreshManager.h>
#include "core/utils/Utils.h"
using namespace common;
namespace controller {
@@ -17,7 +17,7 @@ RefreshManager::RefreshManager(const RefreshTiming& refreshTiming,
refreshTiming(refreshTiming), internalScheduler(internalScheduler)
{
setupTransaction(refreshTransaction, Bank(0));
nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Command::Refresh, SC_ZERO_TIME,
nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Refresh, SC_ZERO_TIME,
refreshTiming.tRFC);
planNextRefresh(*nextPlannedRefresh);
}
@@ -27,7 +27,7 @@ RefreshManager::RefreshManager(const RefreshTiming& refreshTiming,
refreshTiming(refreshTiming), internalScheduler(internalScheduler)
{
setupTransaction(refreshTransaction, bank);
nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Command::Refresh, SC_ZERO_TIME,
nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Refresh, SC_ZERO_TIME,
refreshTiming.tRFC);
planNextRefresh(*nextPlannedRefresh);
}
@@ -70,7 +70,7 @@ void RefreshManager::scheduleRefresh(ScheduledCommand& refresh)
void RefreshManager::planNextRefresh(ScheduledCommand& refresh) //TODO nicer to return the reference ?
{
refresh.delayStart(refreshTiming.tREFI);
internalScheduler.scheduleTrigger(Trigger::RefreshTrigger, refresh.getStart());
internalScheduler.scheduleTrigger(RefreshTrigger, refresh.getStart());
}
void RefreshManager::setupTransaction(tlm::tlm_generic_payload& transaction, Bank bank)

View File

@@ -9,7 +9,7 @@
#define REFRESHMANAGER_H_
#include "IRefreshManager.h"
#include "common/dramextension.h"
#include "common/dramExtension.h"
namespace controller {
@@ -17,7 +17,7 @@ class RefreshManager : public IRefreshManager
{
public:
RefreshManager(const RefreshTiming& refreshTiming, IInternalScheduler& internalScheduler);
RefreshManager(const RefreshTiming& refreshTiming, IInternalScheduler& internalScheduler, common::Bank bank);
RefreshManager(const RefreshTiming& refreshTiming, IInternalScheduler& internalScheduler, Bank bank);
virtual ~RefreshManager();
virtual bool hasCollision(const CommandSchedule& schedule);
@@ -33,7 +33,7 @@ private:
void scheduleRefresh(ScheduledCommand& refresh);
void planNextRefresh(ScheduledCommand& refresh);
static void setupTransaction(tlm::tlm_generic_payload& transaction, common::Bank bank);
static void setupTransaction(tlm::tlm_generic_payload& transaction, Bank bank);
};
} /* namespace controller */

View File

@@ -10,7 +10,7 @@
namespace controller {
enum class Command {NOP, Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, Refresh};
enum Command {NOP, Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, Refresh};
typedef std::vector<Command> CommandSequence;

View File

@@ -37,17 +37,17 @@ void CommandBus::scheduleTrigger(const Trigger command, sc_time time)
//notify tlm wrapper
}
ScheduledCommand& CommandBus::getLastCommand(Command command, common::Bank bank)
ScheduledCommand& CommandBus::getLastCommand(Command command, Bank bank)
{
return lastCommandsOnBus[command][bank];
}
ScheduledCommand& CommandBus::getLastCommand(Command command)
{
ScheduledCommand* max = &getLastCommand(command, common::Bank(0));
ScheduledCommand* max = &getLastCommand(command, Bank(0));
for (unsigned int i = 0; i < config.numberOfBanks; ++i)
{
ScheduledCommand* current = &getLastCommand(command, common::Bank(i));
ScheduledCommand* current = &getLastCommand(command, Bank(i));
if (current->getStart() > max->getStart())
max = current;
}
@@ -59,7 +59,7 @@ bool CommandBus::notYetScheduled(Command command) const
return (lastCommandsOnBus.count(command) == 0);
}
bool CommandBus::notYetScheduled(Command command, common::Bank bank) const
bool CommandBus::notYetScheduled(Command command, Bank bank) const
{
return (notYetScheduled(command) || lastCommandsOnBus.find(command)->second.count(bank) == 0);
}
@@ -88,13 +88,13 @@ void CommandBus::changeControllerState(const ScheduledCommand& command)
{
switch (command.getCommand())
{
case Command::Refresh:
case Refresh:
refresh(command);
break;
case Command::Activate:
case Activate:
activate(command);
break;
case Command::Precharge:
case Precharge:
precharge(command);
default:
break;
@@ -116,11 +116,11 @@ void CommandBus::refresh(const ScheduledCommand& command)
void CommandBus::precharge(const ScheduledCommand& command)
{
if(command.getCommand() == Command::Precharge)
if(command.getCommand() == Precharge)
{
state.bankStates.closeRowBuffer(command.getBank());
}
else if(command.getCommand() == Command::PrechargeAll)
else if(command.getCommand() == PrechargeAll)
{
state.bankStates.closeAllRowBuffers();
}
@@ -128,7 +128,7 @@ void CommandBus::precharge(const ScheduledCommand& command)
void CommandBus::activate(const ScheduledCommand& command)
{
if(command.getCommand() == Command::Activate)
if(command.getCommand() == Activate)
{
state.bankStates.openRowInRowBuffer(command.getBank(), command.getRow());
}

View File

@@ -29,10 +29,10 @@ public:
void cleanUpBus(sc_time currentTime);
ScheduledCommand& getLastCommand(Command command, common::Bank bank);//TODO simple way to make it const?
ScheduledCommand& getLastCommand(Command command, Bank bank);//TODO simple way to make it const?
ScheduledCommand& getLastCommand(Command command);
bool notYetScheduled(Command command) const;
bool notYetScheduled(Command command, common::Bank bank) const;
bool notYetScheduled(Command command, Bank bank) const;
sc_time getEarliestStartTime(const ScheduledCommand& command) const;
const std::set<sc_time>& getPendingBusCommands() const {return pendingBusCommands;}
@@ -42,7 +42,7 @@ private:
controller::ControllerState& state;
std::vector<ICommandChecker*>& checker;
std::map<Command,std::map<common::Bank, ScheduledCommand>> lastCommandsOnBus;
std::map<Command,std::map<Bank, ScheduledCommand> > lastCommandsOnBus;
std::set<sc_time> pendingBusCommands;
void changeControllerState(const ScheduledCommand& command);

View File

@@ -9,7 +9,7 @@
#define COMMANDSCHEDULE_H_
#include <vector>
#include "common/dramextension.h"
#include "common/dramExtension.h"
#include "ScheduledCommand.h"
namespace controller {
@@ -18,7 +18,7 @@ class CommandSchedule
{
public:
CommandSchedule(tlm::tlm_generic_payload& transaction) :
transaction(&transaction), extension(common::DramExtension::getExtension(&transaction))
transaction(&transaction), extension(DramExtension::getExtension(&transaction))
{
}
@@ -53,7 +53,7 @@ public:
return scheduledCommands.back().getEnd() - scheduledCommands.front().getStart();
}
common::Bank getBank() const
Bank getBank() const
{
return extension.getBank();
}
@@ -62,7 +62,7 @@ private:
std::vector<ScheduledCommand> scheduledCommands;
tlm::tlm_generic_payload* transaction;
common::DramExtension extension;
DramExtension extension;
};
} /* namespace controller */

View File

@@ -6,9 +6,8 @@
*/
#include "CommandSequenceGenerator.h"
#include "common/dramextension.h"
#include "common/dramExtension.h"
using namespace common;
using namespace std;
namespace controller {
@@ -44,7 +43,7 @@ CommandSequence CommandSequenceGenerator::generateCommandSequence(
CommandSequence CommandSequenceGenerator::getBankMissCommandSequence(tlm::tlm_generic_payload& transaction)
{
vector<Command> result;
result.push_back(Command::Activate);
result.push_back(Activate);
result.push_back(getReadWriteCommand(transaction));
return result;
}
@@ -52,8 +51,8 @@ CommandSequence CommandSequenceGenerator::getBankMissCommandSequence(tlm::tlm_ge
CommandSequence CommandSequenceGenerator::getRowMissCommandSequence(tlm::tlm_generic_payload& transaction)
{
vector<Command> result;
result.push_back(Command::Precharge);
result.push_back(Command::Activate);
result.push_back(Precharge);
result.push_back(Activate);
result.push_back(getReadWriteCommand(transaction));
return result;
}
@@ -67,14 +66,14 @@ CommandSequence CommandSequenceGenerator::getRowHitCommandSequence(tlm::tlm_gene
Command CommandSequenceGenerator::getReadWriteCommand(tlm::tlm_generic_payload& transaction)
{
if (transaction.get_command() == tlm::tlm_command::TLM_READ_COMMAND)
if (transaction.get_command() == tlm::TLM_READ_COMMAND)
{
//TODO READA
return Command::Read;
return Read;
}
else
{
return Command::Write;
return Write;
}
}

View File

@@ -11,7 +11,7 @@
#include <systemc.h>
#include <tlm.h>
#include "Command.h"
#include "common/dramextension.h"
#include "common/dramExtension.h"
namespace controller {
@@ -22,18 +22,18 @@ public:
ScheduledCommand(tlm::tlm_generic_payload& transaction, Command command, sc_time time,
sc_time executionTime) :
transaction(&transaction), command(command), start(time), executionTime(executionTime), extension(common::DramExtension::getExtension(&transaction))
transaction(&transaction), command(command), start(time), executionTime(executionTime), extension(DramExtension::getExtension(&transaction))
{
}
ScheduledCommand() :
transaction(NULL), command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), extension()
transaction(NULL), command(NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), extension()
{
}
bool isNoCommand() const
{
return (*this == ScheduledCommand::NoCommand);
return (*this == NoCommand);
}
const sc_time getStart() const
@@ -67,12 +67,12 @@ public:
return *transaction;
}
common::Bank getBank() const
Bank getBank() const
{
return extension.getBank();
}
common::Row getRow() const
Row getRow() const
{
return extension.getRow();
}
@@ -94,7 +94,7 @@ private:
sc_time start;
sc_time executionTime;
common::DramExtension extension;
DramExtension extension;
};
} /* namespace controller */

View File

@@ -10,7 +10,7 @@
namespace controller {
enum class Trigger {RefreshTrigger};
enum Trigger {RefreshTrigger};
} /* namespace controller */

View File

@@ -5,18 +5,17 @@
* Author: jonny
*/
#include <core/scheduling/checker/ActivateChecker.h>
#include <map>
#include "core/utils/Utils.h"
#include <algorithm>
#include "core/utils/Utils.h"
#include "core/scheduling/checker/ActivateChecker.h"
using namespace common;
namespace controller {
void ActivateChecker::check(ScheduledCommand& command) const
{
if (command.getCommand() != Command::Activate)
if (command.getCommand() != Activate)
return;
check_activateToActivate(command);
check_nActivateWindow(command);
@@ -26,17 +25,17 @@ void ActivateChecker::check(ScheduledCommand& command) const
sc_time ActivateChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction,
Command command) const
{
assert(command == Command::Activate);
assert(command == Activate);
return config.Timings.tRCD;
}
void ActivateChecker::check_activateToActivate(ScheduledCommand& command) const
{
if (bus.notYetScheduled(Command::Activate))
if (bus.notYetScheduled(Activate))
return;
sc_time lastActivate = bus.getLastCommand(Command::Activate).getStart();
sc_time lastActivateOnBank = bus.getLastCommand(Command::Activate, command.getBank()).getStart();
sc_time lastActivate = bus.getLastCommand(Activate).getStart();
sc_time lastActivateOnBank = bus.getLastCommand(Activate, command.getBank()).getStart();
command.delayStart(delayByConstraint(lastActivate, command.getStart(), config.Timings.tRRD));
command.delayStart(
@@ -46,8 +45,8 @@ void ActivateChecker::check_activateToActivate(ScheduledCommand& command) const
void ActivateChecker::check_prechargeToActivate(ScheduledCommand& command) const
{
sc_time lastPrechargeOnBank = std::max(
bus.getLastCommand(Command::Precharge, command.getBank()).getStart(),
bus.getLastCommand(Command::PrechargeAll, command.getBank()).getStart());
bus.getLastCommand(Precharge, command.getBank()).getStart(),
bus.getLastCommand(PrechargeAll, command.getBank()).getStart());
command.delayStart(
delayByConstraint(lastPrechargeOnBank, command.getStart(), config.Timings.tRC));
}
@@ -68,7 +67,7 @@ void ActivateChecker::check_bus(ScheduledCommand& command) const
void ActivateChecker::cb_IInternalScheduler(const ScheduledCommand& command)
{
if (command.getCommand() == Command::Activate)
if (command.getCommand() == Activate)
{
nActivateWindow.put(command.getStart());
}

View File

@@ -16,7 +16,7 @@ void PrechargeChecker::check(ScheduledCommand& command) const
sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction,
Command command) const
{
assert(command == Command::Precharge || command == Command::PrechargeAll);
assert(command == Precharge || command == PrechargeAll);
return config.Timings.tRP;
}
void PrechargeChecker::cb_IInternalScheduler(const ScheduledCommand& command)

View File

@@ -16,7 +16,7 @@ void ReadChecker::check(ScheduledCommand& command) const
sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction,
Command command) const
{
assert(command == Command::Read || command == Command::ReadA);
assert(command == Read || command == ReadA);
return config.Timings.clk*8;
}

View File

@@ -16,7 +16,7 @@ void WriteChecker::check(ScheduledCommand& command) const
sc_time WriteChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction,
Command command) const
{
assert(command == Command::Write || command == Command::WriteA);
assert(command == Write || command == WriteA);
return config.Timings.clk*8;
}

View File

@@ -7,8 +7,6 @@
#include "Utils.h"
using namespace common;
unsigned int getStartAddress(Bank bank)
{
return 0;
@@ -24,7 +22,7 @@ sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint)
const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment)
{
if (alignment == Alignment::UP)
if (alignment == UP)
return ceil(time / clk) * clk;
else
return floor(time / clk) * clk;

View File

@@ -8,16 +8,16 @@
#ifndef UTILS_H_
#define UTILS_H_
#include "common/dramextension.h"
#include "common/dramExtension.h"
#include <systemc.h>
unsigned int getStartAddress(common::Bank bank);
unsigned int getStartAddress(Bank bank);
sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint);
enum class Alignment {UP, DOWN};
enum Alignment {UP, DOWN};
const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = Alignment::UP);
const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = UP);
bool isClkAligned(sc_time time, sc_time clk);
#endif /* UTILS_H_ */

View File

@@ -1,57 +0,0 @@
/*
* BankStates.cpp
*
* Created on: Feb 24, 2014
* Author: robert
*/
#include "BankStates.h"
namespace common {
using namespace std;
BankStates::BankStates(unsigned int numberOfBanks) :
rowsInRowBuffers(numberOfBanks)
{
for (unsigned int i = 0; i < numberOfBanks; ++i)
{
banks.push_back(Bank(i));
}
closeAllRowBuffers();
}
BankStates::~BankStates()
{
}
bool BankStates::rowBufferIsOpen(const Bank &bank) const
{
return rowsInRowBuffers.at(bank.ID()) != Row::NO_ROW;
}
Row BankStates::getRowInRowBuffer(const Bank &bank) const
{
return rowsInRowBuffers.at(bank.ID());
}
void BankStates::openRowInRowBuffer(const Bank &bank, const Row &row)
{
rowsInRowBuffers.at(bank.ID()) = row;
}
void BankStates::closeRowBuffer(const Bank &bank)
{
rowsInRowBuffers.at(bank.ID()) = Row::NO_ROW;
}
void BankStates::closeAllRowBuffers()
{
for(vector<Bank>::iterator it = banks.begin(); it != banks.end(); ++it)
{
closeRowBuffer(*it);
}
}
} /* namespace scheduler */

View File

@@ -1,37 +0,0 @@
/*
* BankStates.h
*
* Created on: Feb 24, 2014
* Author: robert
*/
#ifndef BANKSTATES_H_
#define BANKSTATES_H_
#include <vector>
#include "dramextension.h"
namespace common {
class BankStates {
public:
BankStates(unsigned int numberOfBanks);
virtual ~BankStates();
unsigned int getNumberOfBanks() const {return rowsInRowBuffers.size();}
const std::vector<Bank>& getBanks() const {return banks;}
bool rowBufferIsOpen(const Bank &bank) const;
Row getRowInRowBuffer(const Bank &bank) const;
void openRowInRowBuffer(const Bank &bank, const Row &row);
void closeRowBuffer(const Bank &bank);
void closeAllRowBuffers();
private:
std::vector<Bank> banks;
std::vector<Row> rowsInRowBuffers;
};
} /* namespace scheduler */
#endif /* BANKSTATES_H_ */

View File

@@ -1,83 +0,0 @@
#include "dramextension.h"
#include <assert.h>
using namespace tlm;
namespace common {
tlm_extension_base* DramExtension::clone() const
{
return new DramExtension(thread, bank, row, column);
}
void DramExtension::copy_from(const tlm_extension_base &ext)
{
const DramExtension &cpyFrom = static_cast<const DramExtension&>(ext);
thread = cpyFrom.thread;
bank = cpyFrom.bank;
row = cpyFrom.row;
column = cpyFrom.column;
}
/* Static methods
*
*/
const DramExtension& DramExtension::getExtension(const tlm_generic_payload *payload)
{
DramExtension *result = NULL;
payload->get_extension(result);
assert(result != NULL);
return *result;
}
bool operator ==(const Thread& lhs, const Thread& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Thread& lhs, const Thread& rhs)
{
return !(lhs == rhs);
}
bool operator ==(const Bank& lhs, const Bank& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Bank& lhs, const Bank& rhs)
{
return !(lhs == rhs);
}
bool operator <(const Bank& lhs, const Bank& rhs)
{
return lhs.ID() < rhs.ID();
}
const Row Row::NO_ROW;
bool operator ==(const Row& lhs, const Row& rhs)
{
if(lhs.isNoRow != rhs.isNoRow)
return false;
return lhs.ID() == rhs.ID();
}
bool operator !=(const Row& lhs, const Row& rhs)
{
return !(lhs == rhs);
}
bool operator ==(const Column& lhs, const Column& rhs)
{
return lhs.ID() == rhs.ID();
}
bool operator !=(const Column& lhs, const Column& rhs)
{
return !(lhs == rhs);
}
}

View File

@@ -1,92 +0,0 @@
#ifndef SCHEDULEREXTENSION_H
#define SCHEDULEREXTENSION_H
#include <tlm.h>
#include <iostream>
namespace common{
class Thread
{
public :
explicit Thread(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
class Bank
{
public :
explicit Bank(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
class Row
{
public :
static const Row NO_ROW;
Row() : id(0), isNoRow(true) {}
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
bool isNoRow;
friend bool operator==(const Row &lhs, const Row &rhs);
};
class Column
{
public :
explicit Column(unsigned int id) : id(id) {}
unsigned int ID() const { return id;}
private:
unsigned int id;
};
bool operator==(const Thread &lhs, const Thread &rhs);
bool operator!=(const Thread &lhs, const Thread &rhs);
bool operator==(const Bank &lhs, const Bank &rhs);
bool operator!=(const Bank &lhs, const Bank &rhs);
bool operator<(const Bank &lhs, const Bank &rhs);
bool operator==(const Row &lhs, const Row &rhs);
bool operator!=(const Row &lhs, const Row &rhs);
bool operator==(const Column &lhs, const Column &rhs);
bool operator!=(const Column &lhs, const Column &rhs);
class DramExtension : public tlm::tlm_extension<DramExtension>
{
private:
Thread thread;
Bank bank;
Row row;
Column column;
public:
DramExtension():thread(0),bank(0),row(0),column(0){}
DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column) :
thread(thread),bank(bank),row(row),column(column){}
~DramExtension(){}
virtual tlm::tlm_extension_base* clone() const;
virtual void copy_from(const tlm_extension_base &ext);
const Thread& getThread() const{return thread;}
const Bank& getBank() const{return bank;}
const Row& getRow() const{return row;}
const Column& getColumn() const{return column;}
static const DramExtension& getExtension(const tlm::tlm_generic_payload *payload);
};
}
#endif // SCHEDULEREXTENSION_H

View File

@@ -9,10 +9,10 @@
#include <gmock/gmock.h>
#include <core/refresh/BankwiseRefreshManager.h>
#include "testUtils.h"
#include "common/dramextension.h"
#include "common/dramExtension.h"
using namespace testing;
using namespace common;
namespace controller {
@@ -39,7 +39,7 @@ public:
sc_time tREFI = config.Timings.refreshTimings.at(i).tREFI;
sc_time clk = config.Timings.clk;
colliding.add(Command::Read, tREFI - 1 * clk, 2 * clk);
colliding.add(Read, tREFI - 1 * clk, 2 * clk);
return colliding;
};
@@ -50,7 +50,7 @@ public:
sc_time tREFI = config.Timings.refreshTimings.at(i).tREFI;
sc_time clk = config.Timings.clk;
non_colliding.add(Command::Read, tREFI - 3 * clk, 2 * clk);
non_colliding.add(Read, tREFI - 3 * clk, 2 * clk);
return non_colliding;
};
};

View File

@@ -36,10 +36,10 @@ public:
TEST_F(CommandBusTest, cleanUpBusWorks)
{
shared_ptr<tlm::tlm_generic_payload> dummy = createDummyPayload();
ScheduledCommand cmd1(*dummy.get(), Command::Read, 2*clk, clk);
ScheduledCommand cmd2(*dummy.get(), Command::Read, 3*clk, clk);
ScheduledCommand cmd3(*dummy.get(), Command::Read, 5*clk, clk);
ScheduledCommand cmd4(*dummy.get(), Command::Read, 7*clk, clk);
ScheduledCommand cmd1(*dummy.get(), Read, 2*clk, clk);
ScheduledCommand cmd2(*dummy.get(), Read, 3*clk, clk);
ScheduledCommand cmd3(*dummy.get(), Read, 5*clk, clk);
ScheduledCommand cmd4(*dummy.get(), Read, 7*clk, clk);
bus.scheduleCommand(cmd1);
bus.scheduleCommand(cmd2);
@@ -57,13 +57,13 @@ TEST_F(CommandBusTest, cleanUpBusWorks)
TEST_F(CommandBusTest, getEarliestStartTimeWorks)
{
shared_ptr<tlm::tlm_generic_payload> dummy = createDummyPayload();
ScheduledCommand cmd1(*dummy.get(), Command::Read, 2*clk, clk);
ScheduledCommand cmd2(*dummy.get(), Command::Read, 3*clk, clk);
ScheduledCommand cmd3(*dummy.get(), Command::Read, 5*clk, clk);
ScheduledCommand cmd4(*dummy.get(), Command::Read, 7*clk, clk);
ScheduledCommand cmd1(*dummy.get(), Read, 2*clk, clk);
ScheduledCommand cmd2(*dummy.get(), Read, 3*clk, clk);
ScheduledCommand cmd3(*dummy.get(), Read, 5*clk, clk);
ScheduledCommand cmd4(*dummy.get(), Read, 7*clk, clk);
ScheduledCommand collision(*dummy.get(), Command::Read, 3*clk, clk);
ScheduledCommand noCollision(*dummy.get(), Command::Read, 6*clk, clk);
ScheduledCommand collision(*dummy.get(), Read, 3*clk, clk);
ScheduledCommand noCollision(*dummy.get(), Read, 6*clk, clk);
bus.scheduleCommand(cmd1);
bus.scheduleCommand(cmd2);
@@ -78,34 +78,34 @@ TEST_F(CommandBusTest, getEarliestStartTimeWorks)
TEST_F(CommandBusTest, getESTDiesWithNotClkAligned)
{
shared_ptr<tlm::tlm_generic_payload> dummy = createDummyPayload();
ScheduledCommand notAligned(*dummy.get(), Command::Read, 2.5*clk, clk);
ScheduledCommand notAligned(*dummy.get(), Read, 2.5*clk, clk);
EXPECT_DEATH(bus.getEarliestStartTime(notAligned), ".*");
}
TEST_F(CommandBusTest, getLastCommandWorks)
{
shared_ptr<tlm::tlm_generic_payload> dummy0 = createDummyPayload(common::Thread(0), common::Bank(0));
shared_ptr<tlm::tlm_generic_payload> dummy2 = createDummyPayload(common::Thread(0), common::Bank(2));
shared_ptr<tlm::tlm_generic_payload> dummy0 = createDummyPayload(Thread(0), Bank(0));
shared_ptr<tlm::tlm_generic_payload> dummy2 = createDummyPayload(Thread(0), Bank(2));
ScheduledCommand read0(*dummy0.get(), Command::Read, 2*clk, clk);
ScheduledCommand read2(*dummy2.get(), Command::Read, 3*clk, clk);
ScheduledCommand read0(*dummy0.get(), Read, 2*clk, clk);
ScheduledCommand read2(*dummy2.get(), Read, 3*clk, clk);
bus.scheduleCommand(read0);
bus.scheduleCommand(read2);
EXPECT_EQ(read0, bus.getLastCommand(Command::Read, read0.getBank()));
EXPECT_EQ(read2, bus.getLastCommand(Command::Read, read2.getBank()));
EXPECT_EQ(read2.getStart(), bus.getLastCommand(Command::Read).getStart());
EXPECT_EQ(read0, bus.getLastCommand(Read, read0.getBank()));
EXPECT_EQ(read2, bus.getLastCommand(Read, read2.getBank()));
EXPECT_EQ(read2.getStart(), bus.getLastCommand(Read).getStart());
}
TEST_F(CommandBusTest, notYetScheduledWorks)
{
shared_ptr<tlm::tlm_generic_payload> dummy = createDummyPayload(common::Thread(0), common::Bank(0));
ScheduledCommand read(*dummy.get(), Command::Read, 2*clk, clk);
shared_ptr<tlm::tlm_generic_payload> dummy = createDummyPayload(Thread(0), Bank(0));
ScheduledCommand read(*dummy.get(), Read, 2*clk, clk);
EXPECT_TRUE(bus.notYetScheduled(Command::Read));
EXPECT_TRUE(bus.notYetScheduled(Read));
bus.scheduleCommand(read);
EXPECT_FALSE(bus.notYetScheduled(Command::Read));
EXPECT_FALSE(bus.notYetScheduled(Read));
}

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@@ -1,16 +1,17 @@
#include <gtest/gtest.h>
#include <vector>
#include <tlm.h>
#include "core/scheduling/CommandSequenceGenerator.h"
#include "testUtils.h"
#include <vector>
using namespace controller;
using namespace common;
using namespace std;
constexpr unsigned int numberOfBanks = 8;
constexpr tlm::tlm_command READ = tlm::tlm_command::TLM_READ_COMMAND;
constexpr tlm::tlm_command WRITE = tlm::tlm_command::TLM_WRITE_COMMAND;
constexpr tlm::tlm_command READ = tlm::TLM_READ_COMMAND;
constexpr tlm::tlm_command WRITE = tlm::TLM_WRITE_COMMAND;
TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit)
{
@@ -23,8 +24,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit)
auto hit_write = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), WRITE);
vector<Command> expected_read ({Command::Read});
vector<Command> expected_write ({Command::Write});
vector<Command> expected_read ({Read});
vector<Command> expected_write ({Write});
EXPECT_EQ(expected_read, generator.generateCommandSequence(hit_read.get()));
EXPECT_EQ(expected_write, generator.generateCommandSequence(hit_write.get()));
@@ -41,8 +42,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithRowMiss)
auto miss_write = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), WRITE);
vector<Command> expected_read ({Command::Precharge, Command::Activate, Command::Read});
vector<Command> expected_write ({Command::Precharge, Command::Activate, Command::Write});
vector<Command> expected_read ({Precharge, Activate, Read});
vector<Command> expected_write ({Precharge, Activate, Write});
EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));
@@ -59,8 +60,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithBankMiss)
auto miss_write = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), WRITE);
vector<Command> expected_read ({Command::Activate, Command::Read});
vector<Command> expected_write ({Command::Activate, Command::Write});
vector<Command> expected_read ({Activate, Read});
vector<Command> expected_write ({Activate, Write});
EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));

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@@ -41,7 +41,7 @@ public:
sc_time tREFI = config.Timings.refreshTimings.at(0).tREFI;
sc_time clk = config.Timings.clk;
colliding.add(Command::Read, tREFI - 1 * clk, 2 * clk);
colliding.add(Read, tREFI - 1 * clk, 2 * clk);
return colliding;
};
@@ -52,7 +52,7 @@ public:
sc_time tREFI = config.Timings.refreshTimings.at(0).tREFI;
sc_time clk = config.Timings.clk;
non_colliding.add(Command::Read, tREFI - 3 * clk, 2 * clk);
non_colliding.add(Read, tREFI - 3 * clk, 2 * clk);
return non_colliding;
};
};

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@@ -3,7 +3,7 @@
using namespace std;
using namespace tlm;
using namespace common;
/* Scheduler related stuff
*

View File

@@ -3,24 +3,24 @@
#include <tlm.h>
#include <memory>
#include "common/dramextension.h"
#include "common/dramExtension.h"
#include "core/scheduling/ScheduledCommand.h"
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload();
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(common::DramExtension* extension);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(DramExtension* extension);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const common::Thread& thread,
const common::Bank& bank, const common::Row& row, const common::Column& column);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const Thread& thread,
const Bank& bank, const Row& row, const Column& column);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const common::Thread& thread,
const common::Bank& bank, const common::Row& row);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const Thread& thread,
const Bank& bank, const Row& row);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const common::Thread& thread,
const common::Bank& bank);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const Thread& thread,
const Bank& bank);
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const common::Thread& thread,
const common::Bank& bank, const common::Row& row, const common::Column& column,
std::shared_ptr<tlm::tlm_generic_payload> createDummyPayload(const Thread& thread,
const Bank& bank, const Row& row, const Column& column,
const tlm::tlm_command& command);
//std::shared_ptr<controller::ScheduledCommand> createDummyScheduledCommand(const sc_time);