From 4dffbf938385da96f8d2bd1054a7b06a69ecb011 Mon Sep 17 00:00:00 2001 From: gernhard Date: Sat, 15 Mar 2014 18:31:16 +0100 Subject: [PATCH] changed build structure --- DRAM/.cproject | 100 ++++++++++++------ DRAM/.gitignore | 2 + DRAM/.settings/language.settings.xml | 11 +- DRAM/{src => dram}/core/Configuration.h | 10 +- DRAM/{src => dram}/core/Controller.cpp | 8 +- DRAM/{src => dram}/core/Controller.h | 0 DRAM/{src => dram}/core/ControllerState.cpp | 0 DRAM/{src => dram}/core/ControllerState.h | 2 +- DRAM/{src => dram}/core/TimingConfiguration.h | 37 ++++--- .../core/powerdown/PowerDownManager.cpp | 0 .../core/powerdown/PowerDownManager.h | 0 .../core/refresh/BankwiseRefreshManager.cpp | 1 - .../core/refresh/BankwiseRefreshManager.h | 2 +- .../core/refresh/IRefreshManager.h | 0 .../core/refresh/RefreshManager.cpp | 8 +- .../core/refresh/RefreshManager.h | 6 +- DRAM/{src => dram}/core/scheduling/Command.h | 2 +- .../core/scheduling/CommandBus.cpp | 20 ++-- .../core/scheduling/CommandBus.h | 6 +- .../core/scheduling/CommandSchedule.h | 8 +- .../scheduling/CommandSequenceGenerator.cpp | 15 ++- .../scheduling/CommandSequenceGenerator.h | 0 .../scheduling/CommandSequenceScheduler.cpp | 0 .../scheduling/CommandSequenceScheduler.h | 0 .../core/scheduling/IInternalScheduler.h | 0 .../core/scheduling/ScheduledCommand.h | 14 +-- DRAM/{src => dram}/core/scheduling/Trigger.h | 2 +- .../scheduling/checker/ActivateChecker.cpp | 21 ++-- .../core/scheduling/checker/ActivateChecker.h | 0 .../core/scheduling/checker/ICommandChecker.h | 0 .../scheduling/checker/PrechargeChecker.cpp | 2 +- .../scheduling/checker/PrechargeChecker.h | 0 .../core/scheduling/checker/ReadChecker.cpp | 2 +- .../core/scheduling/checker/ReadChecker.h | 0 .../core/scheduling/checker/WriteChecker.cpp | 2 +- .../core/scheduling/checker/WriteChecker.h | 0 DRAM/{src => dram}/core/utils/RingBuffer.h | 0 DRAM/{src => dram}/core/utils/Utils.cpp | 4 +- DRAM/{src => dram}/core/utils/Utils.h | 8 +- DRAM/src/common/BankStates.cpp | 57 ---------- DRAM/src/common/BankStates.h | 37 ------- DRAM/src/common/dramextension.cpp | 83 --------------- DRAM/src/common/dramextension.h | 92 ---------------- DRAM/testing/BankwiseRefreshManager_test.cpp | 8 +- DRAM/testing/CommandBus_test.cpp | 44 ++++---- DRAM/testing/CommandGenerator_test.cpp | 21 ++-- DRAM/testing/RefreshManager_test.cpp | 4 +- DRAM/testing/testUtils.cpp | 2 +- DRAM/testing/testUtils.h | 20 ++-- 49 files changed, 214 insertions(+), 447 deletions(-) rename DRAM/{src => dram}/core/Configuration.h (64%) rename DRAM/{src => dram}/core/Controller.cpp (87%) rename DRAM/{src => dram}/core/Controller.h (100%) rename DRAM/{src => dram}/core/ControllerState.cpp (100%) rename DRAM/{src => dram}/core/ControllerState.h (91%) rename DRAM/{src => dram}/core/TimingConfiguration.h (54%) rename DRAM/{src => dram}/core/powerdown/PowerDownManager.cpp (100%) rename DRAM/{src => dram}/core/powerdown/PowerDownManager.h (100%) rename DRAM/{src => dram}/core/refresh/BankwiseRefreshManager.cpp (98%) rename DRAM/{src => dram}/core/refresh/BankwiseRefreshManager.h (95%) rename DRAM/{src => dram}/core/refresh/IRefreshManager.h (100%) rename DRAM/{src => dram}/core/refresh/RefreshManager.cpp (88%) rename DRAM/{src => dram}/core/refresh/RefreshManager.h (89%) rename DRAM/{src => dram}/core/scheduling/Command.h (70%) rename DRAM/{src => dram}/core/scheduling/CommandBus.cpp (83%) rename DRAM/{src => dram}/core/scheduling/CommandBus.h (86%) rename DRAM/{src => dram}/core/scheduling/CommandSchedule.h (86%) rename DRAM/{src => dram}/core/scheduling/CommandSequenceGenerator.cpp (85%) rename DRAM/{src => dram}/core/scheduling/CommandSequenceGenerator.h (100%) rename DRAM/{src => dram}/core/scheduling/CommandSequenceScheduler.cpp (100%) rename DRAM/{src => dram}/core/scheduling/CommandSequenceScheduler.h (100%) rename DRAM/{src => dram}/core/scheduling/IInternalScheduler.h (100%) rename DRAM/{src => dram}/core/scheduling/ScheduledCommand.h (79%) rename DRAM/{src => dram}/core/scheduling/Trigger.h (83%) rename DRAM/{src => dram}/core/scheduling/checker/ActivateChecker.cpp (73%) rename DRAM/{src => dram}/core/scheduling/checker/ActivateChecker.h (100%) rename DRAM/{src => dram}/core/scheduling/checker/ICommandChecker.h (100%) rename DRAM/{src => dram}/core/scheduling/checker/PrechargeChecker.cpp (86%) rename DRAM/{src => dram}/core/scheduling/checker/PrechargeChecker.h (100%) rename DRAM/{src => dram}/core/scheduling/checker/ReadChecker.cpp (87%) rename DRAM/{src => dram}/core/scheduling/checker/ReadChecker.h (100%) rename DRAM/{src => dram}/core/scheduling/checker/WriteChecker.cpp (87%) rename DRAM/{src => dram}/core/scheduling/checker/WriteChecker.h (100%) rename DRAM/{src => dram}/core/utils/RingBuffer.h (100%) rename DRAM/{src => dram}/core/utils/Utils.cpp (90%) rename DRAM/{src => dram}/core/utils/Utils.h (71%) delete mode 100644 DRAM/src/common/BankStates.cpp delete mode 100644 DRAM/src/common/BankStates.h delete mode 100644 DRAM/src/common/dramextension.cpp delete mode 100644 DRAM/src/common/dramextension.h diff --git a/DRAM/.cproject b/DRAM/.cproject index 856f3c3b..9bfc63fc 100644 --- a/DRAM/.cproject +++ b/DRAM/.cproject @@ -1,20 +1,22 @@ - + + + - + + - - + @@ -25,9 +27,10 @@ - - - + + + + + + + + + + - - - - - - - - - - @@ -131,9 +161,13 @@ + + + + diff --git a/DRAM/.gitignore b/DRAM/.gitignore index 98bbc316..9de9ebd0 100644 --- a/DRAM/.gitignore +++ b/DRAM/.gitignore @@ -1 +1,3 @@ /Debug +/platformArchitect +/standalone diff --git a/DRAM/.settings/language.settings.xml b/DRAM/.settings/language.settings.xml index e5d25993..57de1927 100644 --- a/DRAM/.settings/language.settings.xml +++ b/DRAM/.settings/language.settings.xml @@ -1,20 +1,23 @@ - + - + - + - + + + + diff --git a/DRAM/src/core/Configuration.h b/DRAM/dram/core/Configuration.h similarity index 64% rename from DRAM/src/core/Configuration.h rename to DRAM/dram/core/Configuration.h index 2dfe1511..37631c23 100644 --- a/DRAM/src/core/Configuration.h +++ b/DRAM/dram/core/Configuration.h @@ -15,13 +15,15 @@ namespace controller{ struct Configuration { - Configuration():Timings(numberOfBanks){} - unsigned int numberOfBanks = 8; + Configuration(): numberOfBanks(8),Timings(numberOfBanks), RefreshBankwise(false), + nActivate(4) + {} + unsigned int numberOfBanks; TimingConfiguration Timings; - bool RefreshBankwise = false; + bool RefreshBankwise; - unsigned int nActivate = 4; + unsigned int nActivate; }; } /* namespace controller */ diff --git a/DRAM/src/core/Controller.cpp b/DRAM/dram/core/Controller.cpp similarity index 87% rename from DRAM/src/core/Controller.cpp rename to DRAM/dram/core/Controller.cpp index 9fd7fae4..2b1a2fa9 100644 --- a/DRAM/src/core/Controller.cpp +++ b/DRAM/dram/core/Controller.cpp @@ -19,10 +19,10 @@ Controller::Controller() : *this), refreshManager(config.Timings.refreshTimings[0], bus), bus(config, state, allCommandChecker) { - addCommandChecker(Command::Activate, new ActivateChecker(config, bus)); - addCommandChecker(Command::Precharge, new PrechargeChecker(config, bus)); - addCommandChecker(Command::Read, new ReadChecker(config, bus)); - addCommandChecker(Command::Write, new WriteChecker(config, bus)); + addCommandChecker(Activate, new ActivateChecker(config, bus)); + addCommandChecker(Precharge, new PrechargeChecker(config, bus)); + addCommandChecker(Read, new ReadChecker(config, bus)); + addCommandChecker(Write, new WriteChecker(config, bus)); } void Controller::addCommandChecker(Command command, ICommandChecker* checker) diff --git a/DRAM/src/core/Controller.h b/DRAM/dram/core/Controller.h similarity index 100% rename from DRAM/src/core/Controller.h rename to DRAM/dram/core/Controller.h diff --git a/DRAM/src/core/ControllerState.cpp b/DRAM/dram/core/ControllerState.cpp similarity index 100% rename from DRAM/src/core/ControllerState.cpp rename to DRAM/dram/core/ControllerState.cpp diff --git a/DRAM/src/core/ControllerState.h b/DRAM/dram/core/ControllerState.h similarity index 91% rename from DRAM/src/core/ControllerState.h rename to DRAM/dram/core/ControllerState.h index 85b46c91..ce728d12 100644 --- a/DRAM/src/core/ControllerState.h +++ b/DRAM/dram/core/ControllerState.h @@ -17,7 +17,7 @@ public: ControllerState(unsigned int numberOfBanks); virtual ~ControllerState(); - common::BankStates bankStates; + BankStates bankStates; }; } /* namespace controller */ diff --git a/DRAM/src/core/TimingConfiguration.h b/DRAM/dram/core/TimingConfiguration.h similarity index 54% rename from DRAM/src/core/TimingConfiguration.h rename to DRAM/dram/core/TimingConfiguration.h index f175a5cc..9273526b 100644 --- a/DRAM/src/core/TimingConfiguration.h +++ b/DRAM/dram/core/TimingConfiguration.h @@ -30,27 +30,26 @@ struct TimingConfiguration sc_time tREFI = sc_time(15.6, SC_US); //TODO align refreshTimings.push_back(RefreshTiming(tRFC, tREFI)); } + + clk = sc_time(6.0, SC_NS); // 166MHz + + tRP = 3*clk; //precharge-time (pre -> act same bank) + tRAS = 6*clk; //active-time (act -> pre same bank) + + tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank) + tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks) + tRCD = 5*clk; //act -> read/write + + tTAW = clkAlign(sc_time(50, SC_NS), clk); } - sc_time clk = sc_time(6.0, SC_NS); // 166MHz - - - sc_time tRP = 3*clk; //precharge-time (pre -> act same bank) - sc_time tRAS = 6*clk; //active-time (act -> pre same bank) - - sc_time tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank) - sc_time tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks) - sc_time tRCD = 5*clk; //act -> read/write - - sc_time tTAW = clkAlign(sc_time(50, SC_NS), clk, Alignment::UP); - - //Refresh - //sc_time tRFC = 18*clk; - //sc_time tREF = sc_time(64, SC_MS); - //sc_time tREFA = tRP + tRFC; - //sc_time tREFB = tRP + tRC; - - //sc_time tREFI = tREFA; + sc_time clk; + sc_time tRP; + sc_time tRAS; + sc_time tRC; + sc_time tRRD; + sc_time tRCD; + sc_time tTAW; std::vector refreshTimings; diff --git a/DRAM/src/core/powerdown/PowerDownManager.cpp b/DRAM/dram/core/powerdown/PowerDownManager.cpp similarity index 100% rename from DRAM/src/core/powerdown/PowerDownManager.cpp rename to DRAM/dram/core/powerdown/PowerDownManager.cpp diff --git a/DRAM/src/core/powerdown/PowerDownManager.h b/DRAM/dram/core/powerdown/PowerDownManager.h similarity index 100% rename from DRAM/src/core/powerdown/PowerDownManager.h rename to DRAM/dram/core/powerdown/PowerDownManager.h diff --git a/DRAM/src/core/refresh/BankwiseRefreshManager.cpp b/DRAM/dram/core/refresh/BankwiseRefreshManager.cpp similarity index 98% rename from DRAM/src/core/refresh/BankwiseRefreshManager.cpp rename to DRAM/dram/core/refresh/BankwiseRefreshManager.cpp index 02e51465..bff3c405 100644 --- a/DRAM/src/core/refresh/BankwiseRefreshManager.cpp +++ b/DRAM/dram/core/refresh/BankwiseRefreshManager.cpp @@ -7,7 +7,6 @@ #include -using namespace common; using namespace std; namespace controller { diff --git a/DRAM/src/core/refresh/BankwiseRefreshManager.h b/DRAM/dram/core/refresh/BankwiseRefreshManager.h similarity index 95% rename from DRAM/src/core/refresh/BankwiseRefreshManager.h rename to DRAM/dram/core/refresh/BankwiseRefreshManager.h index caf7f3a2..59b7e084 100644 --- a/DRAM/src/core/refresh/BankwiseRefreshManager.h +++ b/DRAM/dram/core/refresh/BankwiseRefreshManager.h @@ -9,7 +9,7 @@ #define BANKWISEREFRESHMANAGER_H_ #include "IRefreshManager.h" -#include "common/dramextension.h" +#include "common/dramExtension.h" #include "RefreshManager.h" namespace controller { diff --git a/DRAM/src/core/refresh/IRefreshManager.h b/DRAM/dram/core/refresh/IRefreshManager.h similarity index 100% rename from DRAM/src/core/refresh/IRefreshManager.h rename to DRAM/dram/core/refresh/IRefreshManager.h diff --git a/DRAM/src/core/refresh/RefreshManager.cpp b/DRAM/dram/core/refresh/RefreshManager.cpp similarity index 88% rename from DRAM/src/core/refresh/RefreshManager.cpp rename to DRAM/dram/core/refresh/RefreshManager.cpp index f524e505..37fc4cc1 100644 --- a/DRAM/src/core/refresh/RefreshManager.cpp +++ b/DRAM/dram/core/refresh/RefreshManager.cpp @@ -8,7 +8,7 @@ #include #include "core/utils/Utils.h" -using namespace common; + namespace controller { @@ -17,7 +17,7 @@ RefreshManager::RefreshManager(const RefreshTiming& refreshTiming, refreshTiming(refreshTiming), internalScheduler(internalScheduler) { setupTransaction(refreshTransaction, Bank(0)); - nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Command::Refresh, SC_ZERO_TIME, + nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Refresh, SC_ZERO_TIME, refreshTiming.tRFC); planNextRefresh(*nextPlannedRefresh); } @@ -27,7 +27,7 @@ RefreshManager::RefreshManager(const RefreshTiming& refreshTiming, refreshTiming(refreshTiming), internalScheduler(internalScheduler) { setupTransaction(refreshTransaction, bank); - nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Command::Refresh, SC_ZERO_TIME, + nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Refresh, SC_ZERO_TIME, refreshTiming.tRFC); planNextRefresh(*nextPlannedRefresh); } @@ -70,7 +70,7 @@ void RefreshManager::scheduleRefresh(ScheduledCommand& refresh) void RefreshManager::planNextRefresh(ScheduledCommand& refresh) //TODO nicer to return the reference ? { refresh.delayStart(refreshTiming.tREFI); - internalScheduler.scheduleTrigger(Trigger::RefreshTrigger, refresh.getStart()); + internalScheduler.scheduleTrigger(RefreshTrigger, refresh.getStart()); } void RefreshManager::setupTransaction(tlm::tlm_generic_payload& transaction, Bank bank) diff --git a/DRAM/src/core/refresh/RefreshManager.h b/DRAM/dram/core/refresh/RefreshManager.h similarity index 89% rename from DRAM/src/core/refresh/RefreshManager.h rename to DRAM/dram/core/refresh/RefreshManager.h index 54a19d06..054e1995 100644 --- a/DRAM/src/core/refresh/RefreshManager.h +++ b/DRAM/dram/core/refresh/RefreshManager.h @@ -9,7 +9,7 @@ #define REFRESHMANAGER_H_ #include "IRefreshManager.h" -#include "common/dramextension.h" +#include "common/dramExtension.h" namespace controller { @@ -17,7 +17,7 @@ class RefreshManager : public IRefreshManager { public: RefreshManager(const RefreshTiming& refreshTiming, IInternalScheduler& internalScheduler); - RefreshManager(const RefreshTiming& refreshTiming, IInternalScheduler& internalScheduler, common::Bank bank); + RefreshManager(const RefreshTiming& refreshTiming, IInternalScheduler& internalScheduler, Bank bank); virtual ~RefreshManager(); virtual bool hasCollision(const CommandSchedule& schedule); @@ -33,7 +33,7 @@ private: void scheduleRefresh(ScheduledCommand& refresh); void planNextRefresh(ScheduledCommand& refresh); - static void setupTransaction(tlm::tlm_generic_payload& transaction, common::Bank bank); + static void setupTransaction(tlm::tlm_generic_payload& transaction, Bank bank); }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/Command.h b/DRAM/dram/core/scheduling/Command.h similarity index 70% rename from DRAM/src/core/scheduling/Command.h rename to DRAM/dram/core/scheduling/Command.h index d791a2a0..d2b9436a 100644 --- a/DRAM/src/core/scheduling/Command.h +++ b/DRAM/dram/core/scheduling/Command.h @@ -10,7 +10,7 @@ namespace controller { -enum class Command {NOP, Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, Refresh}; +enum Command {NOP, Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, Refresh}; typedef std::vector CommandSequence; diff --git a/DRAM/src/core/scheduling/CommandBus.cpp b/DRAM/dram/core/scheduling/CommandBus.cpp similarity index 83% rename from DRAM/src/core/scheduling/CommandBus.cpp rename to DRAM/dram/core/scheduling/CommandBus.cpp index f69435a4..f4ad233d 100644 --- a/DRAM/src/core/scheduling/CommandBus.cpp +++ b/DRAM/dram/core/scheduling/CommandBus.cpp @@ -37,17 +37,17 @@ void CommandBus::scheduleTrigger(const Trigger command, sc_time time) //notify tlm wrapper } -ScheduledCommand& CommandBus::getLastCommand(Command command, common::Bank bank) +ScheduledCommand& CommandBus::getLastCommand(Command command, Bank bank) { return lastCommandsOnBus[command][bank]; } ScheduledCommand& CommandBus::getLastCommand(Command command) { - ScheduledCommand* max = &getLastCommand(command, common::Bank(0)); + ScheduledCommand* max = &getLastCommand(command, Bank(0)); for (unsigned int i = 0; i < config.numberOfBanks; ++i) { - ScheduledCommand* current = &getLastCommand(command, common::Bank(i)); + ScheduledCommand* current = &getLastCommand(command, Bank(i)); if (current->getStart() > max->getStart()) max = current; } @@ -59,7 +59,7 @@ bool CommandBus::notYetScheduled(Command command) const return (lastCommandsOnBus.count(command) == 0); } -bool CommandBus::notYetScheduled(Command command, common::Bank bank) const +bool CommandBus::notYetScheduled(Command command, Bank bank) const { return (notYetScheduled(command) || lastCommandsOnBus.find(command)->second.count(bank) == 0); } @@ -88,13 +88,13 @@ void CommandBus::changeControllerState(const ScheduledCommand& command) { switch (command.getCommand()) { - case Command::Refresh: + case Refresh: refresh(command); break; - case Command::Activate: + case Activate: activate(command); break; - case Command::Precharge: + case Precharge: precharge(command); default: break; @@ -116,11 +116,11 @@ void CommandBus::refresh(const ScheduledCommand& command) void CommandBus::precharge(const ScheduledCommand& command) { - if(command.getCommand() == Command::Precharge) + if(command.getCommand() == Precharge) { state.bankStates.closeRowBuffer(command.getBank()); } - else if(command.getCommand() == Command::PrechargeAll) + else if(command.getCommand() == PrechargeAll) { state.bankStates.closeAllRowBuffers(); } @@ -128,7 +128,7 @@ void CommandBus::precharge(const ScheduledCommand& command) void CommandBus::activate(const ScheduledCommand& command) { - if(command.getCommand() == Command::Activate) + if(command.getCommand() == Activate) { state.bankStates.openRowInRowBuffer(command.getBank(), command.getRow()); } diff --git a/DRAM/src/core/scheduling/CommandBus.h b/DRAM/dram/core/scheduling/CommandBus.h similarity index 86% rename from DRAM/src/core/scheduling/CommandBus.h rename to DRAM/dram/core/scheduling/CommandBus.h index 0740b50a..4c55ffbf 100644 --- a/DRAM/src/core/scheduling/CommandBus.h +++ b/DRAM/dram/core/scheduling/CommandBus.h @@ -29,10 +29,10 @@ public: void cleanUpBus(sc_time currentTime); - ScheduledCommand& getLastCommand(Command command, common::Bank bank);//TODO simple way to make it const? + ScheduledCommand& getLastCommand(Command command, Bank bank);//TODO simple way to make it const? ScheduledCommand& getLastCommand(Command command); bool notYetScheduled(Command command) const; - bool notYetScheduled(Command command, common::Bank bank) const; + bool notYetScheduled(Command command, Bank bank) const; sc_time getEarliestStartTime(const ScheduledCommand& command) const; const std::set& getPendingBusCommands() const {return pendingBusCommands;} @@ -42,7 +42,7 @@ private: controller::ControllerState& state; std::vector& checker; - std::map> lastCommandsOnBus; + std::map > lastCommandsOnBus; std::set pendingBusCommands; void changeControllerState(const ScheduledCommand& command); diff --git a/DRAM/src/core/scheduling/CommandSchedule.h b/DRAM/dram/core/scheduling/CommandSchedule.h similarity index 86% rename from DRAM/src/core/scheduling/CommandSchedule.h rename to DRAM/dram/core/scheduling/CommandSchedule.h index 087590e3..a7e79a02 100644 --- a/DRAM/src/core/scheduling/CommandSchedule.h +++ b/DRAM/dram/core/scheduling/CommandSchedule.h @@ -9,7 +9,7 @@ #define COMMANDSCHEDULE_H_ #include -#include "common/dramextension.h" +#include "common/dramExtension.h" #include "ScheduledCommand.h" namespace controller { @@ -18,7 +18,7 @@ class CommandSchedule { public: CommandSchedule(tlm::tlm_generic_payload& transaction) : - transaction(&transaction), extension(common::DramExtension::getExtension(&transaction)) + transaction(&transaction), extension(DramExtension::getExtension(&transaction)) { } @@ -53,7 +53,7 @@ public: return scheduledCommands.back().getEnd() - scheduledCommands.front().getStart(); } - common::Bank getBank() const + Bank getBank() const { return extension.getBank(); } @@ -62,7 +62,7 @@ private: std::vector scheduledCommands; tlm::tlm_generic_payload* transaction; - common::DramExtension extension; + DramExtension extension; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/CommandSequenceGenerator.cpp b/DRAM/dram/core/scheduling/CommandSequenceGenerator.cpp similarity index 85% rename from DRAM/src/core/scheduling/CommandSequenceGenerator.cpp rename to DRAM/dram/core/scheduling/CommandSequenceGenerator.cpp index 1ac53204..54e93b13 100644 --- a/DRAM/src/core/scheduling/CommandSequenceGenerator.cpp +++ b/DRAM/dram/core/scheduling/CommandSequenceGenerator.cpp @@ -6,9 +6,8 @@ */ #include "CommandSequenceGenerator.h" -#include "common/dramextension.h" +#include "common/dramExtension.h" -using namespace common; using namespace std; namespace controller { @@ -44,7 +43,7 @@ CommandSequence CommandSequenceGenerator::generateCommandSequence( CommandSequence CommandSequenceGenerator::getBankMissCommandSequence(tlm::tlm_generic_payload& transaction) { vector result; - result.push_back(Command::Activate); + result.push_back(Activate); result.push_back(getReadWriteCommand(transaction)); return result; } @@ -52,8 +51,8 @@ CommandSequence CommandSequenceGenerator::getBankMissCommandSequence(tlm::tlm_ge CommandSequence CommandSequenceGenerator::getRowMissCommandSequence(tlm::tlm_generic_payload& transaction) { vector result; - result.push_back(Command::Precharge); - result.push_back(Command::Activate); + result.push_back(Precharge); + result.push_back(Activate); result.push_back(getReadWriteCommand(transaction)); return result; } @@ -67,14 +66,14 @@ CommandSequence CommandSequenceGenerator::getRowHitCommandSequence(tlm::tlm_gene Command CommandSequenceGenerator::getReadWriteCommand(tlm::tlm_generic_payload& transaction) { - if (transaction.get_command() == tlm::tlm_command::TLM_READ_COMMAND) + if (transaction.get_command() == tlm::TLM_READ_COMMAND) { //TODO READA - return Command::Read; + return Read; } else { - return Command::Write; + return Write; } } diff --git a/DRAM/src/core/scheduling/CommandSequenceGenerator.h b/DRAM/dram/core/scheduling/CommandSequenceGenerator.h similarity index 100% rename from DRAM/src/core/scheduling/CommandSequenceGenerator.h rename to DRAM/dram/core/scheduling/CommandSequenceGenerator.h diff --git a/DRAM/src/core/scheduling/CommandSequenceScheduler.cpp b/DRAM/dram/core/scheduling/CommandSequenceScheduler.cpp similarity index 100% rename from DRAM/src/core/scheduling/CommandSequenceScheduler.cpp rename to DRAM/dram/core/scheduling/CommandSequenceScheduler.cpp diff --git a/DRAM/src/core/scheduling/CommandSequenceScheduler.h b/DRAM/dram/core/scheduling/CommandSequenceScheduler.h similarity index 100% rename from DRAM/src/core/scheduling/CommandSequenceScheduler.h rename to DRAM/dram/core/scheduling/CommandSequenceScheduler.h diff --git a/DRAM/src/core/scheduling/IInternalScheduler.h b/DRAM/dram/core/scheduling/IInternalScheduler.h similarity index 100% rename from DRAM/src/core/scheduling/IInternalScheduler.h rename to DRAM/dram/core/scheduling/IInternalScheduler.h diff --git a/DRAM/src/core/scheduling/ScheduledCommand.h b/DRAM/dram/core/scheduling/ScheduledCommand.h similarity index 79% rename from DRAM/src/core/scheduling/ScheduledCommand.h rename to DRAM/dram/core/scheduling/ScheduledCommand.h index cd3e4fb1..59719f1d 100644 --- a/DRAM/src/core/scheduling/ScheduledCommand.h +++ b/DRAM/dram/core/scheduling/ScheduledCommand.h @@ -11,7 +11,7 @@ #include #include #include "Command.h" -#include "common/dramextension.h" +#include "common/dramExtension.h" namespace controller { @@ -22,18 +22,18 @@ public: ScheduledCommand(tlm::tlm_generic_payload& transaction, Command command, sc_time time, sc_time executionTime) : - transaction(&transaction), command(command), start(time), executionTime(executionTime), extension(common::DramExtension::getExtension(&transaction)) + transaction(&transaction), command(command), start(time), executionTime(executionTime), extension(DramExtension::getExtension(&transaction)) { } ScheduledCommand() : - transaction(NULL), command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), extension() + transaction(NULL), command(NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), extension() { } bool isNoCommand() const { - return (*this == ScheduledCommand::NoCommand); + return (*this == NoCommand); } const sc_time getStart() const @@ -67,12 +67,12 @@ public: return *transaction; } - common::Bank getBank() const + Bank getBank() const { return extension.getBank(); } - common::Row getRow() const + Row getRow() const { return extension.getRow(); } @@ -94,7 +94,7 @@ private: sc_time start; sc_time executionTime; - common::DramExtension extension; + DramExtension extension; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/Trigger.h b/DRAM/dram/core/scheduling/Trigger.h similarity index 83% rename from DRAM/src/core/scheduling/Trigger.h rename to DRAM/dram/core/scheduling/Trigger.h index bf127fc6..461bc581 100644 --- a/DRAM/src/core/scheduling/Trigger.h +++ b/DRAM/dram/core/scheduling/Trigger.h @@ -10,7 +10,7 @@ namespace controller { -enum class Trigger {RefreshTrigger}; +enum Trigger {RefreshTrigger}; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/checker/ActivateChecker.cpp b/DRAM/dram/core/scheduling/checker/ActivateChecker.cpp similarity index 73% rename from DRAM/src/core/scheduling/checker/ActivateChecker.cpp rename to DRAM/dram/core/scheduling/checker/ActivateChecker.cpp index 3fd6b39e..ce2f2f42 100644 --- a/DRAM/src/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAM/dram/core/scheduling/checker/ActivateChecker.cpp @@ -5,18 +5,17 @@ * Author: jonny */ -#include #include -#include "core/utils/Utils.h" #include +#include "core/utils/Utils.h" +#include "core/scheduling/checker/ActivateChecker.h" -using namespace common; namespace controller { void ActivateChecker::check(ScheduledCommand& command) const { - if (command.getCommand() != Command::Activate) + if (command.getCommand() != Activate) return; check_activateToActivate(command); check_nActivateWindow(command); @@ -26,17 +25,17 @@ void ActivateChecker::check(ScheduledCommand& command) const sc_time ActivateChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const { - assert(command == Command::Activate); + assert(command == Activate); return config.Timings.tRCD; } void ActivateChecker::check_activateToActivate(ScheduledCommand& command) const { - if (bus.notYetScheduled(Command::Activate)) + if (bus.notYetScheduled(Activate)) return; - sc_time lastActivate = bus.getLastCommand(Command::Activate).getStart(); - sc_time lastActivateOnBank = bus.getLastCommand(Command::Activate, command.getBank()).getStart(); + sc_time lastActivate = bus.getLastCommand(Activate).getStart(); + sc_time lastActivateOnBank = bus.getLastCommand(Activate, command.getBank()).getStart(); command.delayStart(delayByConstraint(lastActivate, command.getStart(), config.Timings.tRRD)); command.delayStart( @@ -46,8 +45,8 @@ void ActivateChecker::check_activateToActivate(ScheduledCommand& command) const void ActivateChecker::check_prechargeToActivate(ScheduledCommand& command) const { sc_time lastPrechargeOnBank = std::max( - bus.getLastCommand(Command::Precharge, command.getBank()).getStart(), - bus.getLastCommand(Command::PrechargeAll, command.getBank()).getStart()); + bus.getLastCommand(Precharge, command.getBank()).getStart(), + bus.getLastCommand(PrechargeAll, command.getBank()).getStart()); command.delayStart( delayByConstraint(lastPrechargeOnBank, command.getStart(), config.Timings.tRC)); } @@ -68,7 +67,7 @@ void ActivateChecker::check_bus(ScheduledCommand& command) const void ActivateChecker::cb_IInternalScheduler(const ScheduledCommand& command) { - if (command.getCommand() == Command::Activate) + if (command.getCommand() == Activate) { nActivateWindow.put(command.getStart()); } diff --git a/DRAM/src/core/scheduling/checker/ActivateChecker.h b/DRAM/dram/core/scheduling/checker/ActivateChecker.h similarity index 100% rename from DRAM/src/core/scheduling/checker/ActivateChecker.h rename to DRAM/dram/core/scheduling/checker/ActivateChecker.h diff --git a/DRAM/src/core/scheduling/checker/ICommandChecker.h b/DRAM/dram/core/scheduling/checker/ICommandChecker.h similarity index 100% rename from DRAM/src/core/scheduling/checker/ICommandChecker.h rename to DRAM/dram/core/scheduling/checker/ICommandChecker.h diff --git a/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp b/DRAM/dram/core/scheduling/checker/PrechargeChecker.cpp similarity index 86% rename from DRAM/src/core/scheduling/checker/PrechargeChecker.cpp rename to DRAM/dram/core/scheduling/checker/PrechargeChecker.cpp index 6cc78572..b52ce2ee 100644 --- a/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAM/dram/core/scheduling/checker/PrechargeChecker.cpp @@ -16,7 +16,7 @@ void PrechargeChecker::check(ScheduledCommand& command) const sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const { - assert(command == Command::Precharge || command == Command::PrechargeAll); + assert(command == Precharge || command == PrechargeAll); return config.Timings.tRP; } void PrechargeChecker::cb_IInternalScheduler(const ScheduledCommand& command) diff --git a/DRAM/src/core/scheduling/checker/PrechargeChecker.h b/DRAM/dram/core/scheduling/checker/PrechargeChecker.h similarity index 100% rename from DRAM/src/core/scheduling/checker/PrechargeChecker.h rename to DRAM/dram/core/scheduling/checker/PrechargeChecker.h diff --git a/DRAM/src/core/scheduling/checker/ReadChecker.cpp b/DRAM/dram/core/scheduling/checker/ReadChecker.cpp similarity index 87% rename from DRAM/src/core/scheduling/checker/ReadChecker.cpp rename to DRAM/dram/core/scheduling/checker/ReadChecker.cpp index e8a010ad..532dc04b 100644 --- a/DRAM/src/core/scheduling/checker/ReadChecker.cpp +++ b/DRAM/dram/core/scheduling/checker/ReadChecker.cpp @@ -16,7 +16,7 @@ void ReadChecker::check(ScheduledCommand& command) const sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const { - assert(command == Command::Read || command == Command::ReadA); + assert(command == Read || command == ReadA); return config.Timings.clk*8; } diff --git a/DRAM/src/core/scheduling/checker/ReadChecker.h b/DRAM/dram/core/scheduling/checker/ReadChecker.h similarity index 100% rename from DRAM/src/core/scheduling/checker/ReadChecker.h rename to DRAM/dram/core/scheduling/checker/ReadChecker.h diff --git a/DRAM/src/core/scheduling/checker/WriteChecker.cpp b/DRAM/dram/core/scheduling/checker/WriteChecker.cpp similarity index 87% rename from DRAM/src/core/scheduling/checker/WriteChecker.cpp rename to DRAM/dram/core/scheduling/checker/WriteChecker.cpp index d3b1924d..55032ad9 100644 --- a/DRAM/src/core/scheduling/checker/WriteChecker.cpp +++ b/DRAM/dram/core/scheduling/checker/WriteChecker.cpp @@ -16,7 +16,7 @@ void WriteChecker::check(ScheduledCommand& command) const sc_time WriteChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const { - assert(command == Command::Write || command == Command::WriteA); + assert(command == Write || command == WriteA); return config.Timings.clk*8; } diff --git a/DRAM/src/core/scheduling/checker/WriteChecker.h b/DRAM/dram/core/scheduling/checker/WriteChecker.h similarity index 100% rename from DRAM/src/core/scheduling/checker/WriteChecker.h rename to DRAM/dram/core/scheduling/checker/WriteChecker.h diff --git a/DRAM/src/core/utils/RingBuffer.h b/DRAM/dram/core/utils/RingBuffer.h similarity index 100% rename from DRAM/src/core/utils/RingBuffer.h rename to DRAM/dram/core/utils/RingBuffer.h diff --git a/DRAM/src/core/utils/Utils.cpp b/DRAM/dram/core/utils/Utils.cpp similarity index 90% rename from DRAM/src/core/utils/Utils.cpp rename to DRAM/dram/core/utils/Utils.cpp index 93ecf2d7..4e9c1889 100644 --- a/DRAM/src/core/utils/Utils.cpp +++ b/DRAM/dram/core/utils/Utils.cpp @@ -7,8 +7,6 @@ #include "Utils.h" -using namespace common; - unsigned int getStartAddress(Bank bank) { return 0; @@ -24,7 +22,7 @@ sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint) const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment) { - if (alignment == Alignment::UP) + if (alignment == UP) return ceil(time / clk) * clk; else return floor(time / clk) * clk; diff --git a/DRAM/src/core/utils/Utils.h b/DRAM/dram/core/utils/Utils.h similarity index 71% rename from DRAM/src/core/utils/Utils.h rename to DRAM/dram/core/utils/Utils.h index 247caefb..7de11b41 100644 --- a/DRAM/src/core/utils/Utils.h +++ b/DRAM/dram/core/utils/Utils.h @@ -8,16 +8,16 @@ #ifndef UTILS_H_ #define UTILS_H_ -#include "common/dramextension.h" +#include "common/dramExtension.h" #include -unsigned int getStartAddress(common::Bank bank); +unsigned int getStartAddress(Bank bank); sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint); -enum class Alignment {UP, DOWN}; +enum Alignment {UP, DOWN}; -const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = Alignment::UP); +const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = UP); bool isClkAligned(sc_time time, sc_time clk); #endif /* UTILS_H_ */ diff --git a/DRAM/src/common/BankStates.cpp b/DRAM/src/common/BankStates.cpp deleted file mode 100644 index 1fd01545..00000000 --- a/DRAM/src/common/BankStates.cpp +++ /dev/null @@ -1,57 +0,0 @@ -/* - * BankStates.cpp - * - * Created on: Feb 24, 2014 - * Author: robert - */ - -#include "BankStates.h" - -namespace common { - -using namespace std; - -BankStates::BankStates(unsigned int numberOfBanks) : - rowsInRowBuffers(numberOfBanks) -{ - for (unsigned int i = 0; i < numberOfBanks; ++i) - { - banks.push_back(Bank(i)); - } - - closeAllRowBuffers(); -} - -BankStates::~BankStates() -{ -} - -bool BankStates::rowBufferIsOpen(const Bank &bank) const -{ - return rowsInRowBuffers.at(bank.ID()) != Row::NO_ROW; -} - -Row BankStates::getRowInRowBuffer(const Bank &bank) const -{ - return rowsInRowBuffers.at(bank.ID()); -} - -void BankStates::openRowInRowBuffer(const Bank &bank, const Row &row) -{ - rowsInRowBuffers.at(bank.ID()) = row; -} - -void BankStates::closeRowBuffer(const Bank &bank) -{ - rowsInRowBuffers.at(bank.ID()) = Row::NO_ROW; -} - -void BankStates::closeAllRowBuffers() -{ - for(vector::iterator it = banks.begin(); it != banks.end(); ++it) - { - closeRowBuffer(*it); - } -} - -} /* namespace scheduler */ diff --git a/DRAM/src/common/BankStates.h b/DRAM/src/common/BankStates.h deleted file mode 100644 index fe46c39b..00000000 --- a/DRAM/src/common/BankStates.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * BankStates.h - * - * Created on: Feb 24, 2014 - * Author: robert - */ - -#ifndef BANKSTATES_H_ -#define BANKSTATES_H_ -#include -#include "dramextension.h" - -namespace common { - -class BankStates { -public: - BankStates(unsigned int numberOfBanks); - virtual ~BankStates(); - - unsigned int getNumberOfBanks() const {return rowsInRowBuffers.size();} - const std::vector& getBanks() const {return banks;} - - bool rowBufferIsOpen(const Bank &bank) const; - Row getRowInRowBuffer(const Bank &bank) const; - - void openRowInRowBuffer(const Bank &bank, const Row &row); - void closeRowBuffer(const Bank &bank); - void closeAllRowBuffers(); - -private: - std::vector banks; - std::vector rowsInRowBuffers; -}; - -} /* namespace scheduler */ - -#endif /* BANKSTATES_H_ */ diff --git a/DRAM/src/common/dramextension.cpp b/DRAM/src/common/dramextension.cpp deleted file mode 100644 index 5a057f56..00000000 --- a/DRAM/src/common/dramextension.cpp +++ /dev/null @@ -1,83 +0,0 @@ -#include "dramextension.h" -#include - -using namespace tlm; - -namespace common { - -tlm_extension_base* DramExtension::clone() const -{ - return new DramExtension(thread, bank, row, column); -} - -void DramExtension::copy_from(const tlm_extension_base &ext) -{ - const DramExtension &cpyFrom = static_cast(ext); - thread = cpyFrom.thread; - bank = cpyFrom.bank; - row = cpyFrom.row; - column = cpyFrom.column; -} - -/* Static methods - * - */ -const DramExtension& DramExtension::getExtension(const tlm_generic_payload *payload) -{ - DramExtension *result = NULL; - payload->get_extension(result); - assert(result != NULL); - return *result; -} - - -bool operator ==(const Thread& lhs, const Thread& rhs) -{ - return lhs.ID() == rhs.ID(); -} - -bool operator !=(const Thread& lhs, const Thread& rhs) -{ - return !(lhs == rhs); -} - -bool operator ==(const Bank& lhs, const Bank& rhs) -{ - return lhs.ID() == rhs.ID(); -} - -bool operator !=(const Bank& lhs, const Bank& rhs) -{ - return !(lhs == rhs); -} - -bool operator <(const Bank& lhs, const Bank& rhs) -{ - return lhs.ID() < rhs.ID(); -} - -const Row Row::NO_ROW; - -bool operator ==(const Row& lhs, const Row& rhs) -{ - if(lhs.isNoRow != rhs.isNoRow) - return false; - return lhs.ID() == rhs.ID(); -} - -bool operator !=(const Row& lhs, const Row& rhs) -{ - return !(lhs == rhs); -} - -bool operator ==(const Column& lhs, const Column& rhs) -{ - return lhs.ID() == rhs.ID(); -} - -bool operator !=(const Column& lhs, const Column& rhs) -{ - return !(lhs == rhs); -} - -} diff --git a/DRAM/src/common/dramextension.h b/DRAM/src/common/dramextension.h deleted file mode 100644 index 8d934451..00000000 --- a/DRAM/src/common/dramextension.h +++ /dev/null @@ -1,92 +0,0 @@ -#ifndef SCHEDULEREXTENSION_H -#define SCHEDULEREXTENSION_H -#include -#include - -namespace common{ - -class Thread -{ -public : - explicit Thread(unsigned int id) : id(id) {} - - unsigned int ID() const { return id;} -private: - unsigned int id; -}; - -class Bank -{ -public : - explicit Bank(unsigned int id) : id(id) {} - unsigned int ID() const { return id;} -private: - unsigned int id; -}; - - -class Row -{ -public : - static const Row NO_ROW; - - Row() : id(0), isNoRow(true) {} - explicit Row(unsigned int id) : id(id), isNoRow(false) {} - - unsigned int ID() const { return id;} -private: - unsigned int id; - bool isNoRow; - - friend bool operator==(const Row &lhs, const Row &rhs); -}; - -class Column -{ -public : - explicit Column(unsigned int id) : id(id) {} - - unsigned int ID() const { return id;} -private: - unsigned int id; -}; - -bool operator==(const Thread &lhs, const Thread &rhs); -bool operator!=(const Thread &lhs, const Thread &rhs); -bool operator==(const Bank &lhs, const Bank &rhs); -bool operator!=(const Bank &lhs, const Bank &rhs); -bool operator<(const Bank &lhs, const Bank &rhs); -bool operator==(const Row &lhs, const Row &rhs); -bool operator!=(const Row &lhs, const Row &rhs); -bool operator==(const Column &lhs, const Column &rhs); -bool operator!=(const Column &lhs, const Column &rhs); - -class DramExtension : public tlm::tlm_extension -{ -private: - Thread thread; - Bank bank; - Row row; - Column column; - -public: - - DramExtension():thread(0),bank(0),row(0),column(0){} - DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column) : - thread(thread),bank(bank),row(row),column(column){} - - ~DramExtension(){} - virtual tlm::tlm_extension_base* clone() const; - virtual void copy_from(const tlm_extension_base &ext); - - const Thread& getThread() const{return thread;} - const Bank& getBank() const{return bank;} - const Row& getRow() const{return row;} - const Column& getColumn() const{return column;} - - static const DramExtension& getExtension(const tlm::tlm_generic_payload *payload); -}; - - -} -#endif // SCHEDULEREXTENSION_H diff --git a/DRAM/testing/BankwiseRefreshManager_test.cpp b/DRAM/testing/BankwiseRefreshManager_test.cpp index 627f2810..abbb18e8 100644 --- a/DRAM/testing/BankwiseRefreshManager_test.cpp +++ b/DRAM/testing/BankwiseRefreshManager_test.cpp @@ -9,10 +9,10 @@ #include #include #include "testUtils.h" -#include "common/dramextension.h" +#include "common/dramExtension.h" using namespace testing; -using namespace common; + namespace controller { @@ -39,7 +39,7 @@ public: sc_time tREFI = config.Timings.refreshTimings.at(i).tREFI; sc_time clk = config.Timings.clk; - colliding.add(Command::Read, tREFI - 1 * clk, 2 * clk); + colliding.add(Read, tREFI - 1 * clk, 2 * clk); return colliding; }; @@ -50,7 +50,7 @@ public: sc_time tREFI = config.Timings.refreshTimings.at(i).tREFI; sc_time clk = config.Timings.clk; - non_colliding.add(Command::Read, tREFI - 3 * clk, 2 * clk); + non_colliding.add(Read, tREFI - 3 * clk, 2 * clk); return non_colliding; }; }; diff --git a/DRAM/testing/CommandBus_test.cpp b/DRAM/testing/CommandBus_test.cpp index 32d28cae..ea54e8d6 100644 --- a/DRAM/testing/CommandBus_test.cpp +++ b/DRAM/testing/CommandBus_test.cpp @@ -36,10 +36,10 @@ public: TEST_F(CommandBusTest, cleanUpBusWorks) { shared_ptr dummy = createDummyPayload(); - ScheduledCommand cmd1(*dummy.get(), Command::Read, 2*clk, clk); - ScheduledCommand cmd2(*dummy.get(), Command::Read, 3*clk, clk); - ScheduledCommand cmd3(*dummy.get(), Command::Read, 5*clk, clk); - ScheduledCommand cmd4(*dummy.get(), Command::Read, 7*clk, clk); + ScheduledCommand cmd1(*dummy.get(), Read, 2*clk, clk); + ScheduledCommand cmd2(*dummy.get(), Read, 3*clk, clk); + ScheduledCommand cmd3(*dummy.get(), Read, 5*clk, clk); + ScheduledCommand cmd4(*dummy.get(), Read, 7*clk, clk); bus.scheduleCommand(cmd1); bus.scheduleCommand(cmd2); @@ -57,13 +57,13 @@ TEST_F(CommandBusTest, cleanUpBusWorks) TEST_F(CommandBusTest, getEarliestStartTimeWorks) { shared_ptr dummy = createDummyPayload(); - ScheduledCommand cmd1(*dummy.get(), Command::Read, 2*clk, clk); - ScheduledCommand cmd2(*dummy.get(), Command::Read, 3*clk, clk); - ScheduledCommand cmd3(*dummy.get(), Command::Read, 5*clk, clk); - ScheduledCommand cmd4(*dummy.get(), Command::Read, 7*clk, clk); + ScheduledCommand cmd1(*dummy.get(), Read, 2*clk, clk); + ScheduledCommand cmd2(*dummy.get(), Read, 3*clk, clk); + ScheduledCommand cmd3(*dummy.get(), Read, 5*clk, clk); + ScheduledCommand cmd4(*dummy.get(), Read, 7*clk, clk); - ScheduledCommand collision(*dummy.get(), Command::Read, 3*clk, clk); - ScheduledCommand noCollision(*dummy.get(), Command::Read, 6*clk, clk); + ScheduledCommand collision(*dummy.get(), Read, 3*clk, clk); + ScheduledCommand noCollision(*dummy.get(), Read, 6*clk, clk); bus.scheduleCommand(cmd1); bus.scheduleCommand(cmd2); @@ -78,34 +78,34 @@ TEST_F(CommandBusTest, getEarliestStartTimeWorks) TEST_F(CommandBusTest, getESTDiesWithNotClkAligned) { shared_ptr dummy = createDummyPayload(); - ScheduledCommand notAligned(*dummy.get(), Command::Read, 2.5*clk, clk); + ScheduledCommand notAligned(*dummy.get(), Read, 2.5*clk, clk); EXPECT_DEATH(bus.getEarliestStartTime(notAligned), ".*"); } TEST_F(CommandBusTest, getLastCommandWorks) { - shared_ptr dummy0 = createDummyPayload(common::Thread(0), common::Bank(0)); - shared_ptr dummy2 = createDummyPayload(common::Thread(0), common::Bank(2)); + shared_ptr dummy0 = createDummyPayload(Thread(0), Bank(0)); + shared_ptr dummy2 = createDummyPayload(Thread(0), Bank(2)); - ScheduledCommand read0(*dummy0.get(), Command::Read, 2*clk, clk); - ScheduledCommand read2(*dummy2.get(), Command::Read, 3*clk, clk); + ScheduledCommand read0(*dummy0.get(), Read, 2*clk, clk); + ScheduledCommand read2(*dummy2.get(), Read, 3*clk, clk); bus.scheduleCommand(read0); bus.scheduleCommand(read2); - EXPECT_EQ(read0, bus.getLastCommand(Command::Read, read0.getBank())); - EXPECT_EQ(read2, bus.getLastCommand(Command::Read, read2.getBank())); - EXPECT_EQ(read2.getStart(), bus.getLastCommand(Command::Read).getStart()); + EXPECT_EQ(read0, bus.getLastCommand(Read, read0.getBank())); + EXPECT_EQ(read2, bus.getLastCommand(Read, read2.getBank())); + EXPECT_EQ(read2.getStart(), bus.getLastCommand(Read).getStart()); } TEST_F(CommandBusTest, notYetScheduledWorks) { - shared_ptr dummy = createDummyPayload(common::Thread(0), common::Bank(0)); - ScheduledCommand read(*dummy.get(), Command::Read, 2*clk, clk); + shared_ptr dummy = createDummyPayload(Thread(0), Bank(0)); + ScheduledCommand read(*dummy.get(), Read, 2*clk, clk); - EXPECT_TRUE(bus.notYetScheduled(Command::Read)); + EXPECT_TRUE(bus.notYetScheduled(Read)); bus.scheduleCommand(read); - EXPECT_FALSE(bus.notYetScheduled(Command::Read)); + EXPECT_FALSE(bus.notYetScheduled(Read)); } diff --git a/DRAM/testing/CommandGenerator_test.cpp b/DRAM/testing/CommandGenerator_test.cpp index a1bfd068..0cb04cf6 100644 --- a/DRAM/testing/CommandGenerator_test.cpp +++ b/DRAM/testing/CommandGenerator_test.cpp @@ -1,16 +1,17 @@ #include +#include +#include #include "core/scheduling/CommandSequenceGenerator.h" #include "testUtils.h" -#include using namespace controller; -using namespace common; + using namespace std; constexpr unsigned int numberOfBanks = 8; -constexpr tlm::tlm_command READ = tlm::tlm_command::TLM_READ_COMMAND; -constexpr tlm::tlm_command WRITE = tlm::tlm_command::TLM_WRITE_COMMAND; +constexpr tlm::tlm_command READ = tlm::TLM_READ_COMMAND; +constexpr tlm::tlm_command WRITE = tlm::TLM_WRITE_COMMAND; TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit) { @@ -23,8 +24,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithRowHit) auto hit_write = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), WRITE); - vector expected_read ({Command::Read}); - vector expected_write ({Command::Write}); + vector expected_read ({Read}); + vector expected_write ({Write}); EXPECT_EQ(expected_read, generator.generateCommandSequence(hit_read.get())); EXPECT_EQ(expected_write, generator.generateCommandSequence(hit_write.get())); @@ -41,8 +42,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithRowMiss) auto miss_write = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), WRITE); - vector expected_read ({Command::Precharge, Command::Activate, Command::Read}); - vector expected_write ({Command::Precharge, Command::Activate, Command::Write}); + vector expected_read ({Precharge, Activate, Read}); + vector expected_write ({Precharge, Activate, Write}); EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get())); EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get())); @@ -59,8 +60,8 @@ TEST(CommandSequenceGenerator, ReadAndWriteWithBankMiss) auto miss_write = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), WRITE); - vector expected_read ({Command::Activate, Command::Read}); - vector expected_write ({Command::Activate, Command::Write}); + vector expected_read ({Activate, Read}); + vector expected_write ({Activate, Write}); EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get())); EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get())); diff --git a/DRAM/testing/RefreshManager_test.cpp b/DRAM/testing/RefreshManager_test.cpp index 57243419..d3c35cba 100644 --- a/DRAM/testing/RefreshManager_test.cpp +++ b/DRAM/testing/RefreshManager_test.cpp @@ -41,7 +41,7 @@ public: sc_time tREFI = config.Timings.refreshTimings.at(0).tREFI; sc_time clk = config.Timings.clk; - colliding.add(Command::Read, tREFI - 1 * clk, 2 * clk); + colliding.add(Read, tREFI - 1 * clk, 2 * clk); return colliding; }; @@ -52,7 +52,7 @@ public: sc_time tREFI = config.Timings.refreshTimings.at(0).tREFI; sc_time clk = config.Timings.clk; - non_colliding.add(Command::Read, tREFI - 3 * clk, 2 * clk); + non_colliding.add(Read, tREFI - 3 * clk, 2 * clk); return non_colliding; }; }; diff --git a/DRAM/testing/testUtils.cpp b/DRAM/testing/testUtils.cpp index d245c70f..f31c2fdc 100644 --- a/DRAM/testing/testUtils.cpp +++ b/DRAM/testing/testUtils.cpp @@ -3,7 +3,7 @@ using namespace std; using namespace tlm; -using namespace common; + /* Scheduler related stuff * diff --git a/DRAM/testing/testUtils.h b/DRAM/testing/testUtils.h index fb45c6cf..21c81eda 100644 --- a/DRAM/testing/testUtils.h +++ b/DRAM/testing/testUtils.h @@ -3,24 +3,24 @@ #include #include -#include "common/dramextension.h" +#include "common/dramExtension.h" #include "core/scheduling/ScheduledCommand.h" std::shared_ptr createDummyPayload(); -std::shared_ptr createDummyPayload(common::DramExtension* extension); +std::shared_ptr createDummyPayload(DramExtension* extension); -std::shared_ptr createDummyPayload(const common::Thread& thread, - const common::Bank& bank, const common::Row& row, const common::Column& column); +std::shared_ptr createDummyPayload(const Thread& thread, + const Bank& bank, const Row& row, const Column& column); -std::shared_ptr createDummyPayload(const common::Thread& thread, - const common::Bank& bank, const common::Row& row); +std::shared_ptr createDummyPayload(const Thread& thread, + const Bank& bank, const Row& row); -std::shared_ptr createDummyPayload(const common::Thread& thread, - const common::Bank& bank); +std::shared_ptr createDummyPayload(const Thread& thread, + const Bank& bank); -std::shared_ptr createDummyPayload(const common::Thread& thread, - const common::Bank& bank, const common::Row& row, const common::Column& column, +std::shared_ptr createDummyPayload(const Thread& thread, + const Bank& bank, const Row& row, const Column& column, const tlm::tlm_command& command); //std::shared_ptr createDummyScheduledCommand(const sc_time);