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Merge remote branch 'upstream/master'

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Éder Ferreira Zulian
2015-06-05 17:02:53 +02:00
parent 1ebcd504e9 f47097d914
commit 3e15e0dd66
1 changed files with 47 additions and 38 deletions
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85
dram/src/simulation/Dram.h
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@@ -65,31 +65,33 @@ using namespace Data;
//configuration->ModelStorage
//configuration->ModelErrotInjection
#ifdef POWER
#define IFPOW(x) x
#else
#define IFPOW(x)
#endif
template<unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false,
unsigned int FIXED_BL_VALUE = 0>
struct Dram: sc_module
{
// TLM Related:
tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
IFPOW(libDRAMPower *DRAMPower);
// Power Model related
bool powerAnalysis = Configuration::getInstance().PowerAnalysis;
libDRAMPower * DRAMPower;
// Error Model related:
ErrorStorageMode ErrorStoreMode = Configuration::getInstance().ErrorStoreMode;
flip_memory * fmemory;
// Data Storage:
map< unsigned long int, unsigned char[BUSWIDTH/2] > memory;
SC_CTOR(Dram) : tSocket("socket")
{
tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
IFPOW( MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)) );
IFPOW( DRAMPower = new libDRAMPower( memSpec, 0 ) );
if(powerAnalysis == true)
{
MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri));
DRAMPower = new libDRAMPower( memSpec, 0 );
}
cout << "ErrorStorageMode: " << EnumToString(ErrorStoreMode) << endl;
if(ErrorStoreMode == ErrorStorageMode::ErrorModel)
@@ -100,10 +102,13 @@ struct Dram: sc_module
~Dram()
{
IFPOW( DRAMPower->updateCounters(true));
IFPOW( DRAMPower->calcEnergy() );
IFPOW( cout << endl << endl << "Total Energy" << "\t" << DRAMPower->getEnergy().total_energy << endl);
IFPOW( cout << "Average Power" << "\t" << DRAMPower->getPower().average_power << endl );
if(powerAnalysis == true)
{
DRAMPower->updateCounters(true);
DRAMPower->calcEnergy();
cout << endl << endl << "Total Energy" << "\t" << DRAMPower->getEnergy().total_energy << endl;
cout << "Average Power" << "\t" << DRAMPower->getPower().average_power << endl;
}
if(ErrorStoreMode == ErrorStorageMode::ErrorModel)
{
for(int b = 0; b < 8; b++)
@@ -121,22 +126,26 @@ struct Dram: sc_module
TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay);
// This is only needed for power simulation:
IFPOW(unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().memSpec.clk.value());
unsigned long long cycle = 0;
if(powerAnalysis == true)
{
cycle = sc_time_stamp().value()/Configuration::getInstance().memSpec.clk.value();
}
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
if (phase == BEGIN_PRE)
{
IFPOW(DRAMPower->doCommand(MemCommand::PRE, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PRE, bank, cycle);}
sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
}
else if (phase == BEGIN_PRE_ALL)
{
IFPOW(DRAMPower->doCommand(MemCommand::PREA, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PREA, bank, cycle);}
sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload));
}
else if (phase == BEGIN_ACT)
{
IFPOW(DRAMPower->doCommand(MemCommand::ACT, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::ACT, bank, cycle);}
sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
@@ -147,7 +156,7 @@ struct Dram: sc_module
}
else if (phase == BEGIN_WR)
{
IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WR, bank, cycle);}
//save data:
if (ErrorStoreMode == ErrorStorageMode::NoStorage)
@@ -166,7 +175,7 @@ struct Dram: sc_module
}
else if (phase == BEGIN_RD)
{
IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RD, bank, cycle);}
// Load data:
if (ErrorStoreMode == ErrorStorageMode::Store) //use ErrorStorageMode
@@ -189,7 +198,7 @@ struct Dram: sc_module
}
else if (phase == BEGIN_WRA)
{
IFPOW(DRAMPower->doCommand(MemCommand::WRA, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WRA, bank, cycle);}
//save data:
if (ErrorStoreMode == ErrorStorageMode::NoStorage)
@@ -208,7 +217,7 @@ struct Dram: sc_module
}
else if (phase == BEGIN_RDA)
{
IFPOW(DRAMPower->doCommand(MemCommand::RDA, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RDA, bank, cycle);}
// Load data:
if (ErrorStoreMode == ErrorStorageMode::Store) //use ErrorStorageMode
@@ -231,7 +240,7 @@ struct Dram: sc_module
}
else if (phase == BEGIN_REFA)
{
IFPOW(DRAMPower->doCommand(MemCommand::REF, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::REF, bank, cycle);}
sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
@@ -243,62 +252,62 @@ struct Dram: sc_module
else if (phase == BEGIN_REFB)
{
IFPOW( SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported") );
if(powerAnalysis == true){ SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload));
}
//Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
else if (phase == BEGIN_PDNA)
{
IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);}
}
else if (phase == END_PDNA)
{
IFPOW(DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);}
}
else if (phase == BEGIN_PDNAB)
{
IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
}
else if (phase == END_PDNAB)
{
IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
}
else if (phase == BEGIN_PDNP)
{
IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);}
}
else if (phase == END_PDNP)
{
IFPOW(DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);}
}
else if (phase == BEGIN_PDNPB)
{
IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
}
else if (phase == END_PDNPB)
{
IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
}
else if (phase == BEGIN_SREF)
{
IFPOW(DRAMPower->doCommand(MemCommand::SREN, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::SREN, bank, cycle);}
}
else if (phase == END_SREF)
{
IFPOW(DRAMPower->doCommand(MemCommand::SREX, bank, cycle));
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::SREX, bank, cycle);}
}
else if (phase == BEGIN_SREFB)
{
IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
}
else if (phase == END_SREFB)
{
IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");}
}
else
{
IFPOW(SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"));
if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");}
}
return tlm::TLM_ACCEPTED;
}