From 939e971445e54d751fcde7e629bd4ecf739b1590 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Wed, 13 May 2015 16:52:26 +0200 Subject: [PATCH 1/2] Change readme accoring to submodules --- README.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index bac9ac77..e8b7ed82 100644 --- a/README.md +++ b/README.md @@ -26,10 +26,16 @@ fork is a copy of a repository. In that case, after pushing changes into your copy you should create a **pull request** in order to your supervisor check and possibly bring your changes to the official codebase. +If you youst want to use DRAMSys clone this repository: + +``` +$ git clone --recursive https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system.git +``` + In case of doubts about which repository you should clone ask your supervisor. ``` -$ git clone https://@git.rhrk.uni-kl.de//dram.vp.system.git +$ git clone --recursive https://@git.rhrk.uni-kl.de//dram.vp.system.git ``` Go to the project directory. From f47097d914753e33ca58a2f8b1003df8620ccebc Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Fri, 5 Jun 2015 15:08:34 +0200 Subject: [PATCH 2/2] removed IFPOW macro --- dram/src/simulation/Dram.h | 85 +++++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 38 deletions(-) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index a29d6a5b..0748227f 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -65,31 +65,33 @@ using namespace Data; //configuration->ModelStorage //configuration->ModelErrotInjection -#ifdef POWER - #define IFPOW(x) x -#else - #define IFPOW(x) -#endif - - template struct Dram: sc_module { + // TLM Related: tlm_utils::simple_target_socket tSocket; - IFPOW(libDRAMPower *DRAMPower); + // Power Model related + bool powerAnalysis = Configuration::getInstance().PowerAnalysis; + libDRAMPower * DRAMPower; + + // Error Model related: ErrorStorageMode ErrorStoreMode = Configuration::getInstance().ErrorStoreMode; - flip_memory * fmemory; + + // Data Storage: map< unsigned long int, unsigned char[BUSWIDTH/2] > memory; SC_CTOR(Dram) : tSocket("socket") { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - IFPOW( MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)) ); - IFPOW( DRAMPower = new libDRAMPower( memSpec, 0 ) ); + if(powerAnalysis == true) + { + MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); + DRAMPower = new libDRAMPower( memSpec, 0 ); + } cout << "ErrorStorageMode: " << EnumToString(ErrorStoreMode) << endl; if(ErrorStoreMode == ErrorStorageMode::ErrorModel) @@ -100,10 +102,13 @@ struct Dram: sc_module ~Dram() { - IFPOW( DRAMPower->updateCounters(true)); - IFPOW( DRAMPower->calcEnergy() ); - IFPOW( cout << endl << endl << "Total Energy" << "\t" << DRAMPower->getEnergy().total_energy << endl); - IFPOW( cout << "Average Power" << "\t" << DRAMPower->getPower().average_power << endl ); + if(powerAnalysis == true) + { + DRAMPower->updateCounters(true); + DRAMPower->calcEnergy(); + cout << endl << endl << "Total Energy" << "\t" << DRAMPower->getEnergy().total_energy << endl; + cout << "Average Power" << "\t" << DRAMPower->getPower().average_power << endl; + } if(ErrorStoreMode == ErrorStorageMode::ErrorModel) { for(int b = 0; b < 8; b++) @@ -121,22 +126,26 @@ struct Dram: sc_module TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay); // This is only needed for power simulation: - IFPOW(unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().memSpec.clk.value()); + unsigned long long cycle = 0; + if(powerAnalysis == true) + { + cycle = sc_time_stamp().value()/Configuration::getInstance().memSpec.clk.value(); + } unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); if (phase == BEGIN_PRE) { - IFPOW(DRAMPower->doCommand(MemCommand::PRE, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PRE, bank, cycle);} sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { - IFPOW(DRAMPower->doCommand(MemCommand::PREA, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PREA, bank, cycle);} sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACT) { - IFPOW(DRAMPower->doCommand(MemCommand::ACT, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::ACT, bank, cycle);} sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); @@ -147,7 +156,7 @@ struct Dram: sc_module } else if (phase == BEGIN_WR) { - IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WR, bank, cycle);} //save data: if (ErrorStoreMode == ErrorStorageMode::NoStorage) @@ -166,7 +175,7 @@ struct Dram: sc_module } else if (phase == BEGIN_RD) { - IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RD, bank, cycle);} // Load data: if (ErrorStoreMode == ErrorStorageMode::Store) //use ErrorStorageMode @@ -189,7 +198,7 @@ struct Dram: sc_module } else if (phase == BEGIN_WRA) { - IFPOW(DRAMPower->doCommand(MemCommand::WRA, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WRA, bank, cycle);} //save data: if (ErrorStoreMode == ErrorStorageMode::NoStorage) @@ -208,7 +217,7 @@ struct Dram: sc_module } else if (phase == BEGIN_RDA) { - IFPOW(DRAMPower->doCommand(MemCommand::RDA, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RDA, bank, cycle);} // Load data: if (ErrorStoreMode == ErrorStorageMode::Store) //use ErrorStorageMode @@ -231,7 +240,7 @@ struct Dram: sc_module } else if (phase == BEGIN_REFA) { - IFPOW(DRAMPower->doCommand(MemCommand::REF, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::REF, bank, cycle);} sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload)); unsigned int row = DramExtension::getExtension(payload).getRow().ID(); @@ -243,62 +252,62 @@ struct Dram: sc_module else if (phase == BEGIN_REFB) { - IFPOW( SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported") ); + if(powerAnalysis == true){ SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload)); } //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) { - IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);} } else if (phase == END_PDNA) { - IFPOW(DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);} } else if (phase == BEGIN_PDNAB) { - IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} } else if (phase == END_PDNAB) { - IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} } else if (phase == BEGIN_PDNP) { - IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);} } else if (phase == END_PDNP) { - IFPOW(DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);} } else if (phase == BEGIN_PDNPB) { - IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} } else if (phase == END_PDNPB) { - IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} } else if (phase == BEGIN_SREF) { - IFPOW(DRAMPower->doCommand(MemCommand::SREN, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::SREN, bank, cycle);} } else if (phase == END_SREF) { - IFPOW(DRAMPower->doCommand(MemCommand::SREX, bank, cycle)); + if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::SREX, bank, cycle);} } else if (phase == BEGIN_SREFB) { - IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} } else if (phase == END_SREFB) { - IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported");} } else { - IFPOW(SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase")); + if(powerAnalysis == true){SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");} } return tlm::TLM_ACCEPTED; }