Add comment in Dram.cpp regarding delays

src/libdramsys/DRAMSys/simulation/Dram.cpp

@@ -152,7 +152,8 @@ void Dram::reportPower()
     }
 }
 
-tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay)
+tlm_sync_enum
+Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, [[maybe_unused]] sc_time& delay)
 {
     assert(phase >= BEGIN_RD && phase <= END_SREF);
 
@@ -186,6 +187,11 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
         DRAMPower->doCoreInterfaceCommand(command);
     }
 
+    // Strictly speaking, the DRAM should honor the delay value before executing the read or write
+    // transaction in the memory. However, as the controller issues only a constant delay, this
+    // would not make a difference. When coupling with RTL models however, it could make a
+    // difference.
+
     if (storeMode == Config::StoreModeType::Store)
     {
         if (phase == BEGIN_RD || phase == BEGIN_RDA)