Test script improved
Created classes to get easily memory specifications and memory configurations. Each class handles the peculiarities of the related XML file. Other changes: - git ignore file updated.
This commit is contained in:
Éder F. Zulian
2
.gitignore
vendored
2
.gitignore
vendored
@@ -14,4 +14,6 @@ build*/
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._.DS_Store
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.DS_Store
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*.swp
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*.swo
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cscope*
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DRAMSys/analyzer/scripts/__pycache__/
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@@ -4,34 +4,52 @@ import sqlite3
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import os
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import xml.etree.ElementTree as ET
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def getPathToConfigs():
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return os.path.dirname(os.path.abspath(__file__).replace("/scripts","/configs"))
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def getValueFromConfigXML(root, id):
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return root.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value']
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class MemConfig(object):
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""" Memory Configuration Class
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def getIntValueFromConfigXML(root, id):
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return int(root.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value'])
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The format used in memory specification XML files differs from the
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format used in memory configuration XML files. Each class uses the
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proper format when searching for elements.
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"""
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def getValue(self, id):
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return self.xmlMemSpec.findall(id)[0].attrib['value']
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def getMemconfig(connection):
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cursor = connection.cursor()
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cursor.execute("SELECT Memconfig FROM GeneralInfo")
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result = cursor.fetchone()
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memconfig = result[0]
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return ET.parse(memconfig)
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def getIntValue(self, id):
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return int(self.getValue(id))
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def __init__(self, dbconnection):
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cursor = dbconnection.cursor()
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cursor.execute("SELECT Memconfig FROM GeneralInfo")
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result = cursor.fetchone()
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self.xmlMemSpec = ET.parse(result[0])
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class MemSpec(object):
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""" Memory Specification Class
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The format used in memory specification XML files differs from the
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format used in memory configuration XML files. Each class uses the
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proper format when searching for elements.
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"""
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def getValue(self, id):
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return self.xmlMemSpec.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value']
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def getIntValue(self, id):
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return int(self.getValue(id))
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def __init__(self, dbconnection):
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cursor = dbconnection.cursor()
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cursor.execute("SELECT Memspec FROM GeneralInfo")
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result = cursor.fetchone()
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self.xmlMemSpec = ET.parse(result[0])
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def getMemspec(connection):
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cursor = connection.cursor()
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cursor.execute("SELECT Memspec FROM GeneralInfo")
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result = cursor.fetchone()
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memspec = result[0]
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return ET.parse(memspec)
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def getClock(connection):
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cursor = connection.cursor()
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cursor.execute("SELECT clk, UnitOfTime FROM GeneralInfo")
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result = cursor.fetchone()
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return (result[0],result[1])
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return (result[0], result[1])
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class DramConfig(object):
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memoryType = ""
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@@ -70,71 +88,74 @@ class DramConfig(object):
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def readConfigFromFiles(self, connection):
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print("Parsing dram configuration")
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memspec = getMemspec(connection)
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memconfig = MemConfig(connection)
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memspec = MemSpec(connection)
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clkWithUnit = getClock(connection)
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self.clk = clkWithUnit[0]
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self.unitOfTime = clkWithUnit[1].lower()
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print(getMemconfig(connection))
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self.bankwiseLogic = getMemconfig(connection).findall("BankwiseLogic")[0].attrib['value']
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self.scheduler = getMemconfig(connection).findall("Scheduler")[0].attrib['value']
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self.numberOfBanks = getIntValueFromConfigXML(memspec, "nbrOfBanks")
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self.burstLength = getIntValueFromConfigXML(memspec, "burstLength")
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self.memoryType = getValueFromConfigXML(memspec, "memoryType")
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self.dataRate = getIntValueFromConfigXML(memspec, "dataRate")
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self.bankwiseLogic = memconfig.getValue("BankwiseLogic")
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self.scheduler = memconfig.getValue("Scheduler")
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self.numberOfBanks = memspec.getIntValue("nbrOfBanks")
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print(self.numberOfBanks)
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self.burstLength = memspec.getIntValue("burstLength")
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self.memoryType = memspec.getValue("memoryType")
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self.dataRate = memspec.getIntValue("dataRate")
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if(self.memoryType == "WIDEIO_SDR"):
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self.nActivateWindow = 2;
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self.tRP = self.clk * getIntValueFromConfigXML(memspec, "RP")
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self.tRAS = self.clk * getIntValueFromConfigXML(memspec, "RAS")
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self.tRC = self.clk * getIntValueFromConfigXML(memspec, "RC")
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self.tRRD_S = self.clk * getIntValueFromConfigXML(memspec, "RRD")
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self.tRP = self.clk * memspec.getIntValue("RP")
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self.tRAS = self.clk * memspec.getIntValue("RAS")
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self.tRC = self.clk * memspec.getIntValue("RC")
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self.tRRD_S = self.clk * memspec.getIntValue("RRD")
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self.tRRD_L = self.tRRD_S
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self.tCCD_S = self.clk * getIntValueFromConfigXML(memspec, "CCD")
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self.tCCD_S = self.clk * memspec.getIntValue("CCD")
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self.tCCD_L = self.tCCD_S
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self.tRCD = self.clk * getIntValueFromConfigXML(memspec, "RCD")
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self.tNAW = self.clk * getIntValueFromConfigXML(memspec, "TAW")
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self.tRL = self.clk * getIntValueFromConfigXML(memspec, "RL")
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self.tWL = self.clk * getIntValueFromConfigXML(memspec, "WL")
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self.tWR = self.clk * getIntValueFromConfigXML(memspec, "WR")
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self.tWTR_S = self.clk * getIntValueFromConfigXML(memspec, "WTR")
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self.tRCD = self.clk * memspec.getIntValue("RCD")
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self.tNAW = self.clk * memspec.getIntValue("TAW")
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self.tRL = self.clk * memspec.getIntValue("RL")
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self.tWL = self.clk * memspec.getIntValue("WL")
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self.tWR = self.clk * memspec.getIntValue("WR")
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self.tWTR_S = self.clk * memspec.getIntValue("WTR")
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self.tWTR_L = self.tWTR_S
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self.tRTP = self.clk * getIntValueFromConfigXML(memspec, "RTP");
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self.tCKESR = self.clk * getIntValueFromConfigXML(memspec, "CKESR")
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self.tCKE = self.clk * getIntValueFromConfigXML(memspec, "CKE")
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self.tXP = self.clk * getIntValueFromConfigXML(memspec, "XP")
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self.tRTP = self.clk * memspec.getIntValue("RTP");
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self.tCKESR = self.clk * memspec.getIntValue("CKESR")
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self.tCKE = self.clk * memspec.getIntValue("CKE")
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self.tXP = self.clk * memspec.getIntValue("XP")
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self.tXPDLL = self.tXP
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self.tXSR = self.clk * getIntValueFromConfigXML(memspec, "XS")
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self.tXSR = self.clk * memspec.getIntValue("XS")
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self.tXSRDLL = self.tXSR
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self.tAL = self.clk * getIntValueFromConfigXML(memspec, "AL")
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self.tRFC = self.clk * getIntValueFromConfigXML(memspec, "RFC")
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self.tAL = self.clk * memspec.getIntValue("AL")
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self.tRFC = self.clk * memspec.getIntValue("RFC")
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elif(self. memoryType == "DDR4"):
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self.nActivateWindow = 4;
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self.tRP = self.clk * getIntValueFromConfigXML(memspec, "RP");
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self.tRAS = self.clk * getIntValueFromConfigXML(memspec, "RAS");
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self.tRC = self.clk * getIntValueFromConfigXML(memspec, "RC");
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self.tRTP = self.clk * getIntValueFromConfigXML(memspec, "RTP");
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self.tRRD_S = self.clk * getIntValueFromConfigXML(memspec, "RRD_S");
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self.tRRD_L = self.clk * getIntValueFromConfigXML(memspec, "RRD_L");
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self.tCCD_S = self.clk * getIntValueFromConfigXML(memspec, "CCD_S");
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self.tCCD_L = self.clk * getIntValueFromConfigXML(memspec, "CCD_L");
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self.tRCD = self.clk * getIntValueFromConfigXML(memspec, "RCD");
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self.tNAW = self.clk * getIntValueFromConfigXML(memspec, "FAW");
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self.tRL = self.clk * getIntValueFromConfigXML(memspec, "RL");
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self.tWL = self.clk * getIntValueFromConfigXML(memspec, "WL");
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self.tWR = self.clk * getIntValueFromConfigXML(memspec, "WR");
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self.tWTR_S = self.clk * getIntValueFromConfigXML(memspec, "WTR_S");
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self.tWTR_L = self.clk * getIntValueFromConfigXML(memspec, "WTR_L");
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self.tCKESR = self.clk * getIntValueFromConfigXML(memspec, "CKESR");
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self.tCKE = self.clk * getIntValueFromConfigXML(memspec, "CKE");
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self.tXP = self.clk * getIntValueFromConfigXML(memspec, "XP");
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self.tXPDLL = self.clk * getIntValueFromConfigXML(memspec, "XPDLL");
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self.tXSR = self.clk * getIntValueFromConfigXML(memspec, "XS");
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self.tXSRDLL = self.clk * getIntValueFromConfigXML(memspec, "XSDLL");
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self.tAL = self.clk * getIntValueFromConfigXML(memspec, "AL");
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self.tRFC = self.clk * getIntValueFromConfigXML(memspec, "RFC");
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self.nActivateWindow = 4
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self.tRP = self.clk * memspec.getIntValue("RP")
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self.tRAS = self.clk * memspec.getIntValue("RAS")
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self.tRC = self.clk * memspec.getIntValue("RC")
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self.tRTP = self.clk * memspec.getIntValue("RTP")
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self.tRRD_S = self.clk * memspec.getIntValue("RRD_S")
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self.tRRD_L = self.clk * memspec.getIntValue("RRD_L")
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self.tCCD_S = self.clk * memspec.getIntValue("CCD_S")
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self.tCCD_L = self.clk * memspec.getIntValue("CCD_L")
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self.tRCD = self.clk * memspec.getIntValue("RCD")
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self.tNAW = self.clk * memspec.getIntValue("FAW")
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self.tRL = self.clk * memspec.getIntValue("RL")
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self.tWL = self.clk * memspec.getIntValue("WL")
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self.tWR = self.clk * memspec.getIntValue("WR")
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self.tWTR_S = self.clk * memspec.getIntValue("WTR_S")
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self.tWTR_L = self.clk * memspec.getIntValue("WTR_L")
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self.tCKESR = self.clk * memspec.getIntValue("CKESR")
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self.tCKE = self.clk * memspec.getIntValue("CKE")
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self.tXP = self.clk * memspec.getIntValue("XP")
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self.tXPDLL = self.clk * memspec.getIntValue("XPDLL")
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self.tXSR = self.clk * memspec.getIntValue("XS");
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self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL")
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self.tAL = self.clk * memspec.getIntValue("AL")
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self.tRFC = self.clk * memspec.getIntValue("RFC")
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else:
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raise Exception("MemoryType not supported yet. Insert a coin into the coin machine and try again")
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@@ -152,7 +173,6 @@ class DramConfig(object):
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def getReadAccessTime(self):
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return self.burstLength/self.dataRate * dramconfig.clk
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def __init__(self):
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pass
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@@ -172,6 +192,7 @@ def test(function):
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tests.append(function)
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return function
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class TestResult(object):
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passed = True
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message = ''
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@@ -179,12 +200,15 @@ class TestResult(object):
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self.passed = passed
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self.message = message
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def TestSuceeded():
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return TestResult()
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def TestFailed(message):
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return TestResult(False,message);
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def formatTime(time):
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return ('{0} {1}'.format(time, dramconfig.unitOfTime))
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@@ -205,6 +229,7 @@ def commands_are_clockaligned(connection):
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.format(result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk)))
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return TestSuceeded()
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@test
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def commandbus_slots_are_used_once(connection):
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"""Checks that no two phases on the command bus start at the same time"""
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@@ -342,9 +367,10 @@ def timing_constraint(FirstPhase, SecondPhase):
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return 0
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@test
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def timing_constraits_on_the_same_bank_hold(connection):
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"""Checks that all transitions of two consequtive phases on the same bank meet their timing constraints"""
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"""Checks that all transitions of two consecutive phases on the same bank meet their timing constraints"""
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cursor = connection.cursor()
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validTransitions = {}
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@@ -363,6 +389,7 @@ def timing_constraits_on_the_same_bank_hold(connection):
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lastRow = currentRow
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return TestSuceeded()
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@test
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def row_buffer_is_used_correctly(connection):
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"""Checks that each bank's row buffer is used correctly"""
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@@ -394,8 +421,6 @@ def row_buffer_is_used_correctly(connection):
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rowBufferIsClosed = True
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for currentRow in cursor:
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if(currentRow[0] in accessingPhases and rowBufferIsClosed == True):
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return TestFailed("Phase {0}({1}) acesses a closed rowbuffer".format(currentRow[1], currentRow[0]))
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