From 3085b3949bbd7cfa6bf1f4e92377ac01bc306f8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Thu, 11 Feb 2016 10:35:44 -0200 Subject: [PATCH] Test script improved Created classes to get easily memory specifications and memory configurations. Each class handles the peculiarities of the related XML file. Other changes: - git ignore file updated. --- .gitignore | 2 + DRAMSys/analyzer/scripts/tests.py | 171 +++++++++++++++++------------- 2 files changed, 100 insertions(+), 73 deletions(-) diff --git a/.gitignore b/.gitignore index 06b27a1f..f1ef5004 100644 --- a/.gitignore +++ b/.gitignore @@ -14,4 +14,6 @@ build*/ ._.DS_Store .DS_Store *.swp +*.swo cscope* +DRAMSys/analyzer/scripts/__pycache__/ diff --git a/DRAMSys/analyzer/scripts/tests.py b/DRAMSys/analyzer/scripts/tests.py index 37d9baa1..e824378a 100644 --- a/DRAMSys/analyzer/scripts/tests.py +++ b/DRAMSys/analyzer/scripts/tests.py @@ -4,34 +4,52 @@ import sqlite3 import os import xml.etree.ElementTree as ET -def getPathToConfigs(): - return os.path.dirname(os.path.abspath(__file__).replace("/scripts","/configs")) -def getValueFromConfigXML(root, id): - return root.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value'] +class MemConfig(object): + """ Memory Configuration Class -def getIntValueFromConfigXML(root, id): - return int(root.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value']) + The format used in memory specification XML files differs from the + format used in memory configuration XML files. Each class uses the + proper format when searching for elements. + """ + def getValue(self, id): + return self.xmlMemSpec.findall(id)[0].attrib['value'] -def getMemconfig(connection): - cursor = connection.cursor() - cursor.execute("SELECT Memconfig FROM GeneralInfo") - result = cursor.fetchone() - memconfig = result[0] - return ET.parse(memconfig) + def getIntValue(self, id): + return int(self.getValue(id)) + + def __init__(self, dbconnection): + cursor = dbconnection.cursor() + cursor.execute("SELECT Memconfig FROM GeneralInfo") + result = cursor.fetchone() + self.xmlMemSpec = ET.parse(result[0]) + + +class MemSpec(object): + """ Memory Specification Class + + The format used in memory specification XML files differs from the + format used in memory configuration XML files. Each class uses the + proper format when searching for elements. + """ + def getValue(self, id): + return self.xmlMemSpec.findall(".//parameter[@id='{0}']".format(id))[0].attrib['value'] + + def getIntValue(self, id): + return int(self.getValue(id)) + + def __init__(self, dbconnection): + cursor = dbconnection.cursor() + cursor.execute("SELECT Memspec FROM GeneralInfo") + result = cursor.fetchone() + self.xmlMemSpec = ET.parse(result[0]) -def getMemspec(connection): - cursor = connection.cursor() - cursor.execute("SELECT Memspec FROM GeneralInfo") - result = cursor.fetchone() - memspec = result[0] - return ET.parse(memspec) def getClock(connection): cursor = connection.cursor() cursor.execute("SELECT clk, UnitOfTime FROM GeneralInfo") result = cursor.fetchone() - return (result[0],result[1]) + return (result[0], result[1]) class DramConfig(object): memoryType = "" @@ -70,71 +88,74 @@ class DramConfig(object): def readConfigFromFiles(self, connection): print("Parsing dram configuration") - memspec = getMemspec(connection) + + memconfig = MemConfig(connection) + memspec = MemSpec(connection) clkWithUnit = getClock(connection) self.clk = clkWithUnit[0] self.unitOfTime = clkWithUnit[1].lower() - print(getMemconfig(connection)) - self.bankwiseLogic = getMemconfig(connection).findall("BankwiseLogic")[0].attrib['value'] - self.scheduler = getMemconfig(connection).findall("Scheduler")[0].attrib['value'] - self.numberOfBanks = getIntValueFromConfigXML(memspec, "nbrOfBanks") - self.burstLength = getIntValueFromConfigXML(memspec, "burstLength") - self.memoryType = getValueFromConfigXML(memspec, "memoryType") - self.dataRate = getIntValueFromConfigXML(memspec, "dataRate") + self.bankwiseLogic = memconfig.getValue("BankwiseLogic") + self.scheduler = memconfig.getValue("Scheduler") + + self.numberOfBanks = memspec.getIntValue("nbrOfBanks") + print(self.numberOfBanks) + self.burstLength = memspec.getIntValue("burstLength") + self.memoryType = memspec.getValue("memoryType") + self.dataRate = memspec.getIntValue("dataRate") if(self.memoryType == "WIDEIO_SDR"): self.nActivateWindow = 2; - self.tRP = self.clk * getIntValueFromConfigXML(memspec, "RP") - self.tRAS = self.clk * getIntValueFromConfigXML(memspec, "RAS") - self.tRC = self.clk * getIntValueFromConfigXML(memspec, "RC") - self.tRRD_S = self.clk * getIntValueFromConfigXML(memspec, "RRD") + self.tRP = self.clk * memspec.getIntValue("RP") + self.tRAS = self.clk * memspec.getIntValue("RAS") + self.tRC = self.clk * memspec.getIntValue("RC") + self.tRRD_S = self.clk * memspec.getIntValue("RRD") self.tRRD_L = self.tRRD_S - self.tCCD_S = self.clk * getIntValueFromConfigXML(memspec, "CCD") + self.tCCD_S = self.clk * memspec.getIntValue("CCD") self.tCCD_L = self.tCCD_S - self.tRCD = self.clk * getIntValueFromConfigXML(memspec, "RCD") - self.tNAW = self.clk * getIntValueFromConfigXML(memspec, "TAW") - self.tRL = self.clk * getIntValueFromConfigXML(memspec, "RL") - self.tWL = self.clk * getIntValueFromConfigXML(memspec, "WL") - self.tWR = self.clk * getIntValueFromConfigXML(memspec, "WR") - self.tWTR_S = self.clk * getIntValueFromConfigXML(memspec, "WTR") + self.tRCD = self.clk * memspec.getIntValue("RCD") + self.tNAW = self.clk * memspec.getIntValue("TAW") + self.tRL = self.clk * memspec.getIntValue("RL") + self.tWL = self.clk * memspec.getIntValue("WL") + self.tWR = self.clk * memspec.getIntValue("WR") + self.tWTR_S = self.clk * memspec.getIntValue("WTR") self.tWTR_L = self.tWTR_S - self.tRTP = self.clk * getIntValueFromConfigXML(memspec, "RTP"); - self.tCKESR = self.clk * getIntValueFromConfigXML(memspec, "CKESR") - self.tCKE = self.clk * getIntValueFromConfigXML(memspec, "CKE") - self.tXP = self.clk * getIntValueFromConfigXML(memspec, "XP") + self.tRTP = self.clk * memspec.getIntValue("RTP"); + self.tCKESR = self.clk * memspec.getIntValue("CKESR") + self.tCKE = self.clk * memspec.getIntValue("CKE") + self.tXP = self.clk * memspec.getIntValue("XP") self.tXPDLL = self.tXP - self.tXSR = self.clk * getIntValueFromConfigXML(memspec, "XS") + self.tXSR = self.clk * memspec.getIntValue("XS") self.tXSRDLL = self.tXSR - self.tAL = self.clk * getIntValueFromConfigXML(memspec, "AL") - self.tRFC = self.clk * getIntValueFromConfigXML(memspec, "RFC") + self.tAL = self.clk * memspec.getIntValue("AL") + self.tRFC = self.clk * memspec.getIntValue("RFC") elif(self. memoryType == "DDR4"): - self.nActivateWindow = 4; - self.tRP = self.clk * getIntValueFromConfigXML(memspec, "RP"); - self.tRAS = self.clk * getIntValueFromConfigXML(memspec, "RAS"); - self.tRC = self.clk * getIntValueFromConfigXML(memspec, "RC"); - self.tRTP = self.clk * getIntValueFromConfigXML(memspec, "RTP"); - self.tRRD_S = self.clk * getIntValueFromConfigXML(memspec, "RRD_S"); - self.tRRD_L = self.clk * getIntValueFromConfigXML(memspec, "RRD_L"); - self.tCCD_S = self.clk * getIntValueFromConfigXML(memspec, "CCD_S"); - self.tCCD_L = self.clk * getIntValueFromConfigXML(memspec, "CCD_L"); - self.tRCD = self.clk * getIntValueFromConfigXML(memspec, "RCD"); - self.tNAW = self.clk * getIntValueFromConfigXML(memspec, "FAW"); - self.tRL = self.clk * getIntValueFromConfigXML(memspec, "RL"); - self.tWL = self.clk * getIntValueFromConfigXML(memspec, "WL"); - self.tWR = self.clk * getIntValueFromConfigXML(memspec, "WR"); - self.tWTR_S = self.clk * getIntValueFromConfigXML(memspec, "WTR_S"); - self.tWTR_L = self.clk * getIntValueFromConfigXML(memspec, "WTR_L"); - self.tCKESR = self.clk * getIntValueFromConfigXML(memspec, "CKESR"); - self.tCKE = self.clk * getIntValueFromConfigXML(memspec, "CKE"); - self.tXP = self.clk * getIntValueFromConfigXML(memspec, "XP"); - self.tXPDLL = self.clk * getIntValueFromConfigXML(memspec, "XPDLL"); - self.tXSR = self.clk * getIntValueFromConfigXML(memspec, "XS"); - self.tXSRDLL = self.clk * getIntValueFromConfigXML(memspec, "XSDLL"); - self.tAL = self.clk * getIntValueFromConfigXML(memspec, "AL"); - self.tRFC = self.clk * getIntValueFromConfigXML(memspec, "RFC"); + self.nActivateWindow = 4 + self.tRP = self.clk * memspec.getIntValue("RP") + self.tRAS = self.clk * memspec.getIntValue("RAS") + self.tRC = self.clk * memspec.getIntValue("RC") + self.tRTP = self.clk * memspec.getIntValue("RTP") + self.tRRD_S = self.clk * memspec.getIntValue("RRD_S") + self.tRRD_L = self.clk * memspec.getIntValue("RRD_L") + self.tCCD_S = self.clk * memspec.getIntValue("CCD_S") + self.tCCD_L = self.clk * memspec.getIntValue("CCD_L") + self.tRCD = self.clk * memspec.getIntValue("RCD") + self.tNAW = self.clk * memspec.getIntValue("FAW") + self.tRL = self.clk * memspec.getIntValue("RL") + self.tWL = self.clk * memspec.getIntValue("WL") + self.tWR = self.clk * memspec.getIntValue("WR") + self.tWTR_S = self.clk * memspec.getIntValue("WTR_S") + self.tWTR_L = self.clk * memspec.getIntValue("WTR_L") + self.tCKESR = self.clk * memspec.getIntValue("CKESR") + self.tCKE = self.clk * memspec.getIntValue("CKE") + self.tXP = self.clk * memspec.getIntValue("XP") + self.tXPDLL = self.clk * memspec.getIntValue("XPDLL") + self.tXSR = self.clk * memspec.getIntValue("XS"); + self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL") + self.tAL = self.clk * memspec.getIntValue("AL") + self.tRFC = self.clk * memspec.getIntValue("RFC") else: raise Exception("MemoryType not supported yet. Insert a coin into the coin machine and try again") @@ -152,7 +173,6 @@ class DramConfig(object): def getReadAccessTime(self): return self.burstLength/self.dataRate * dramconfig.clk - def __init__(self): pass @@ -172,6 +192,7 @@ def test(function): tests.append(function) return function + class TestResult(object): passed = True message = '' @@ -179,12 +200,15 @@ class TestResult(object): self.passed = passed self.message = message + def TestSuceeded(): return TestResult() + def TestFailed(message): return TestResult(False,message); + def formatTime(time): return ('{0} {1}'.format(time, dramconfig.unitOfTime)) @@ -205,6 +229,7 @@ def commands_are_clockaligned(connection): .format(result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk))) return TestSuceeded() + @test def commandbus_slots_are_used_once(connection): """Checks that no two phases on the command bus start at the same time""" @@ -342,9 +367,10 @@ def timing_constraint(FirstPhase, SecondPhase): return 0 + @test def timing_constraits_on_the_same_bank_hold(connection): - """Checks that all transitions of two consequtive phases on the same bank meet their timing constraints""" + """Checks that all transitions of two consecutive phases on the same bank meet their timing constraints""" cursor = connection.cursor() validTransitions = {} @@ -363,6 +389,7 @@ def timing_constraits_on_the_same_bank_hold(connection): lastRow = currentRow return TestSuceeded() + @test def row_buffer_is_used_correctly(connection): """Checks that each bank's row buffer is used correctly""" @@ -394,8 +421,6 @@ def row_buffer_is_used_correctly(connection): rowBufferIsClosed = True - - for currentRow in cursor: if(currentRow[0] in accessingPhases and rowBufferIsClosed == True): return TestFailed("Phase {0}({1}) acesses a closed rowbuffer".format(currentRow[1], currentRow[0]))