Correct error in timing configuration.

2022-01-11 07:57:43 +00:00
parent 9bb28525ee
commit 171fc19e7e
1 changed files with 1 additions and 1 deletions
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
@@ -98,7 +98,7 @@ MemSpecLPDDR5::MemSpecLPDDR5(json &memspec)
      tWTR_S   (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
      tWCK2DQO(tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
      tpbR2act(tCK * parseUint(memspec["memtimingspec"], "pbR2act")),
-      tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "tpbR2pbR")),
+      tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "pbR2pbR")),
      tRTRS   (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
    commandLengthInCycles[Command::ACT] = 2;