From 171fc19e7e26ad416ad292e1184d7d0af480e0c5 Mon Sep 17 00:00:00 2001
From: Lukas Steiner <lsteiner@rhrk.uni-kl.de>
Date: Tue, 11 Jan 2022 07:57:43 +0000
Subject: [PATCH] Correct error in timing configuration.

---
 DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
index 64122b69..50532945 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp
@@ -98,7 +98,7 @@ MemSpecLPDDR5::MemSpecLPDDR5(json &memspec)
       tWTR_S   (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
       tWCK2DQO(tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
       tpbR2act(tCK * parseUint(memspec["memtimingspec"], "pbR2act")),
-      tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "tpbR2pbR")),
+      tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "pbR2pbR")),
       tRTRS   (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     commandLengthInCycles[Command::ACT] = 2;