Do not allow masked write in default case.

extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp

@@ -283,7 +283,7 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
     }
 }
 
-bool MemSpecDDR5::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
+bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
     auto burstLength = ControllerExtension::getBurstLength(payload);
 

extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h

@@ -119,17 +119,17 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    sc_core::sc_time getRefreshIntervalAB() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
-    sc_core::sc_time getRefreshIntervalSB() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalSB() const override;
 
-    unsigned getRAADEC() const override;
+    [[nodiscard]] unsigned getRAADEC() const override;
-    unsigned getRAAIMT() const override;
+    [[nodiscard]] unsigned getRAAIMT() const override;
-    unsigned getRAAMMT() const override;
+    [[nodiscard]] unsigned getRAAMMT() const override;
 
-    sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
 
-    bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.cpp

@@ -197,16 +197,4 @@ unsigned MemSpecHBM3::getRAAMMT() const
     return RAAMMT;
 }
 
-bool MemSpecHBM3::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
-{
-    bool maskedWrite = payload.get_byte_enable_ptr() != nullptr;
-
-    if (maskedWrite)
-    {
-        SC_REPORT_FATAL("MemSpecHBM3", "HBM3 does not support masked writes!");
-    }
-
-    return maskedWrite;
-}
-
 } // namespace DRAMSys

extensions/standards/HBM3/DRAMSys/configuration/memspec/MemSpecHBM3.h

@@ -89,19 +89,17 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    sc_core::sc_time getRefreshIntervalAB() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
-    sc_core::sc_time getRefreshIntervalPB() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
 
-    unsigned getRAADEC() const override;
+    [[nodiscard]] unsigned getRAADEC() const override;
-    unsigned getRAAIMT() const override;
+    [[nodiscard]] unsigned getRAAIMT() const override;
-    unsigned getRAAMMT() const override;
+    [[nodiscard]] unsigned getRAAMMT() const override;
 
-    bool hasRasAndCasBus() const override;
+    [[nodiscard]] bool hasRasAndCasBus() const override;
 
-    sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
-
-    bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp

@@ -248,4 +248,9 @@ TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_g
     }
 }
 
+bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h

@@ -111,14 +111,16 @@ public:
     // Currents and Voltages:
     // TODO: to be completed
 
-    sc_core::sc_time getRefreshIntervalAB() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
-    sc_core::sc_time getRefreshIntervalPB() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
-    sc_core::sc_time getRefreshIntervalP2B() const override;
+    [[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override;
 
-    unsigned getPer2BankOffset() const override;
+    [[nodiscard]] unsigned getPer2BankOffset() const override;
 
-    sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
+    [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
-    TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+    [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 
 private:
     unsigned per2BankOffset;

src/libdramsys/DRAMSys/configuration/memspec/MemSpec.cpp

@@ -148,9 +148,13 @@ bool MemSpec::hasRasAndCasBus() const
     return false;
 }
 
-bool MemSpec::requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const
+bool MemSpec::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
 {
-    return payload.get_byte_enable_ptr() != nullptr;
+    if (payload.get_byte_enable_ptr() == nullptr)
+        return false;
+
+    SC_REPORT_FATAL("MemSpec", "Standard does not support masked writes!");
+    throw;
 }
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h

@@ -103,7 +103,7 @@ public:
 
     [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
     [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
-    [[nodiscard]] virtual bool requiresReadModifyWrite(const tlm::tlm_generic_payload& payload) const;
+    [[nodiscard]] virtual bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const;
 
     [[nodiscard]] sc_core::sc_time getCommandLength(Command command) const;
     [[nodiscard]] double getCommandLengthInCycles(Command command) const;

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.cpp

@@ -168,4 +168,9 @@ TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, [[maybe_unuse
     throw;
 }
 
+bool MemSpecDDR3::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h

@@ -97,6 +97,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp

@@ -186,4 +186,9 @@ TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unuse
     throw;
 }
 
+bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h

@@ -104,6 +104,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.cpp

@@ -145,10 +145,10 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
     if (command == Command::RDA)
         return tRTP + tRP;
 
-    if (command == Command::WR || command == Command::MWR)
+    if (command == Command::WR)
         return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
 
-    if (command == Command::WRA || command == Command::MWRA)
+    if (command == Command::WRA)
         return tWL + burstDuration + tWR + tRP;
 
     if (command == Command::REFAB)
@@ -167,7 +167,7 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, [[maybe_unus
     if (command == Command::RD || command == Command::RDA)
         return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
 
-    if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
+    if (command == Command::WR || command == Command::WRA)
         return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
 
     SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.cpp

@@ -145,10 +145,10 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
     if (command == Command::RDA)
         return tRTP + tRP;
 
-    if (command == Command::WR || command == Command::MWR)
+    if (command == Command::WR)
         return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
 
-    if (command == Command::WRA || command == Command::MWRA)
+    if (command == Command::WRA)
         return tWL + burstDuration + tWR + tRP;
 
     if (command == Command::REFAB)
@@ -167,7 +167,7 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, [[maybe_unu
     if (command == Command::RD || command == Command::RDA)
         return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
 
-    if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
+    if (command == Command::WR || command == Command::WRA)
         return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
 
     SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");

src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.cpp

@@ -158,10 +158,10 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
     if (command == Command::RDA)
         return tRTP + tRP;
 
-    if (command == Command::WR || command == Command::MWR)
+    if (command == Command::WR)
         return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
 
-    if (command == Command::WRA || command == Command::MWRA)
+    if (command == Command::WRA)
         return tWL + burstDuration + tWR + tRP;
 
     if (command == Command::REFAB)
@@ -180,7 +180,7 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, [[maybe_unus
     if (command == Command::RD || command == Command::RDA)
         return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
 
-    if (command == Command::WR || command == Command::WRA || command == Command::MWR || command == Command::MWRA)
+    if (command == Command::WR || command == Command::WRA)
         return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
 
     SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");

src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.cpp

@@ -175,4 +175,9 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, [[maybe_unuse
     throw;
 }
 
+bool MemSpecHBM2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h

@@ -92,6 +92,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp

@@ -181,4 +181,9 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, [[maybe_unu
     throw;
 }
 
+bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h

@@ -92,6 +92,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.cpp

@@ -141,4 +141,9 @@ TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, [[maybe_un
     throw;
 }
 
+bool MemSpecSTTMRAM::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h

@@ -80,6 +80,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.cpp

@@ -173,4 +173,9 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, [[maybe_unu
     throw;
 }
 
+bool MemSpecWideIO::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h

@@ -102,6 +102,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.cpp

@@ -163,4 +163,9 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, [[maybe_un
     throw;
 }
 
+bool MemSpecWideIO2::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
+{
+    return payload.get_byte_enable_ptr() != nullptr;
+}
+
 } // namespace DRAMSys

src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h

@@ -84,6 +84,8 @@ public:
 
     [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
     [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
+
+    [[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
 };
 
 } // namespace DRAMSys

src/libdramsys/DRAMSys/controller/BankMachine.cpp

@@ -201,7 +201,7 @@ void BankMachineOpen::evaluate()
                     nextCommand = Command::RD;
                 else
                 {
-                    nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
+                    nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
                 }
             }
             else // row miss
@@ -243,7 +243,7 @@ void BankMachineClosed::evaluate()
                 nextCommand = Command::RDA;
             else
             {
-                nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
             }
         }
     }
@@ -287,7 +287,7 @@ void BankMachineOpenAdaptive::evaluate()
                         nextCommand = Command::RDA;
                     else
                     {
-                        nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                        nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
                     }
                 }
                 else
@@ -297,7 +297,7 @@ void BankMachineOpenAdaptive::evaluate()
                         nextCommand = Command::RD;
                     else
                     {
-                        nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
+                        nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
                     }
                 }
             }
@@ -345,7 +345,7 @@ void BankMachineClosedAdaptive::evaluate()
                         nextCommand = Command::RD;
                     else
                     {
-                        nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWR : Command::WR;
+                        nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWR : Command::WR;
                     }
                 }
                 else
@@ -355,7 +355,7 @@ void BankMachineClosedAdaptive::evaluate()
                         nextCommand = Command::RDA;
                     else
                     {
-                        nextCommand = memSpec.requiresReadModifyWrite(*currentPayload) ? Command::MWRA : Command::WRA;
+                        nextCommand = memSpec.requiresMaskedWrite(*currentPayload) ? Command::MWRA : Command::WRA;
                     }
                 }
             }