Releated work PIMSimulator

references.bib

@@ -1,6 +1,6 @@
 @misc{blas1979,
   title = {{{BLAS}} ({{Basic Linear Algebra Subprograms}})},
-  author = {{BLAS}},
+  author = {{Netlib}},
   year = {1979},
   urldate = {2024-01-08},
   howpublished = {https://www.netlib.org/blas/}
@@ -20,7 +20,7 @@
   urldate = {2024-01-09},
   isbn = {978-1-72817-383-2},
   keywords = {reviewed},
-  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/7M7QNRVN/He et al. - 2020 - Newton A DRAM-maker’s Accelerator-in-Memory (AiM).pdf}
+  file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\7M7QNRVN\He et al. - 2020 - Newton A DRAM-maker’s Accelerator-in-Memory (AiM).pdf}
 }
 
 @inproceedings{kang2022,
@@ -38,7 +38,7 @@
   isbn = {978-1-4503-9149-8},
   langid = {english},
   keywords = {reviewed},
-  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/YPD3XGJ6/Kang et al. - 2022 - An FPGA-based RNN-T Inference Accelerator with PIM.pdf}
+  file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\YPD3XGJ6\Kang et al. - 2022 - An FPGA-based RNN-T Inference Accelerator with PIM.pdf}
 }
 
 @inproceedings{kwon2021,
@@ -55,7 +55,7 @@
   isbn = {978-1-72819-549-0},
   langid = {english},
   keywords = {reviewed},
-  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/UMUTRR6K/Kwon et al. - 2021 - 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on .pdf}
+  file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\UMUTRR6K\Kwon et al. - 2021 - 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on .pdf}
 }
 
 @inproceedings{lee2021,
@@ -74,7 +74,35 @@
   isbn = {978-1-66543-333-4},
   langid = {english},
   keywords = {reviewed},
-  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/YWUR6TWQ/Lee et al. - 2021 - Hardware Architecture and Software Stack for PIM B.pdf}
+  file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\YWUR6TWQ\Lee et al. - 2021 - Hardware Architecture and Software Stack for PIM B.pdf}
+}
+
+@article{rosenfeld2011,
+  title = {{{DRAMSim2}}: {{A Cycle Accurate Memory System Simulator}}},
+  shorttitle = {{{DRAMSim2}}},
+  author = {Rosenfeld, P and {Cooper-Balis}, E and Jacob, B},
+  year = {2011},
+  month = jan,
+  journal = {IEEE Computer Architecture Letters},
+  volume = {10},
+  number = {1},
+  pages = {16--19},
+  issn = {1556-6056},
+  doi = {10.1109/L-CA.2011.4},
+  urldate = {2024-03-11},
+  abstract = {In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results. We outline the combination of DRAMSim2 with a cycle-accurate x86 simulator that can be used to perform full system simulations. Finally, we discuss DRAMVis, a visualization tool that can be used to graph and compare the results of DRAMSim2 simulations.},
+  langid = {english},
+  file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\CC5GSUA5\Rosenfeld et al. - 2011 - DRAMSim2 A Cycle Accurate Memory System Simulator.pdf}
+}
+
+@misc{shin-haengkang2023,
+  title = {{{PIMSimulator}}},
+  author = {{Shin-haeng Kang} and {Sanghoon Cha} and {Seungwoo Seo} and {Jin-seong Kim}},
+  year = {2023},
+  month = nov,
+  urldate = {2024-02-08},
+  abstract = {Processing-In-Memory (PIM) Simulator},
+  howpublished = {https://github.com/SAITPublic/PIMSimulator}
 }
 
 @article{steiner2022a,

samplepaper.tex

@@ -82,9 +82,14 @@ Contributions:
 \end{itemize}
 %
 \section{Related Work}
-Onur Ramulator
-Samsung DRAMSim2
 % TODO Derek/Lukas
+Onur Ramulator
+
+With the \textbf{PIMSimulator} \cite{shin-haengkang2023}, Samsung provides a virtual prototype of \ac{fimdram} based on the DRAMSim2 \cite{rosenfeld2011} cycle-accurate memory simulator.
+PIMSimulator offers two simulation modes: it can either accept pre-recorded memory traces or generate very simplified memory traffic using a minimal host processor model that essentially executes only the \ac{pim}-related program regions.
+However, neither approach accurately models a complete system consisting of a host processor running a real compiled binary and the memory system that integrates \ac{fimdram}.
+As a result, only limited conclusions can be made about the performance impact of \ac{fimdram} and the changes that are required in the application code to support the new architecture.
+
 \section{Background DRAM-PIM}
 \label{sec:dram_pim}
 % TODO Derek