Master thesis simulation setup

pim-os/build.sh

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+#!/bin/bash
+
+CARGO_TARGET_DIR=kernels/X1 cargo build --release --features X1
+CARGO_TARGET_DIR=kernels/X2 cargo build --release --features X2
+CARGO_TARGET_DIR=kernels/X3 cargo build --release --features X3
+CARGO_TARGET_DIR=kernels/X4 cargo build --release --features X4

pim-os/src/bin/classic_gemv.rs

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+#![no_std]
+#![no_main]
+
+extern crate alloc;
+
+use core::{arch::asm, fmt::Write};
+use nalgebra::{SMatrix, SVector};
+use pim_os::{pim::vector::F16x1, uart::Uart0};
+
+#[cfg(feature = "X1")]
+const ROWS: usize = 128;
+
+#[cfg(feature = "X2")]
+const ROWS: usize = 256;
+
+#[cfg(feature = "X3")]
+const ROWS: usize = 512;
+
+#[cfg(feature = "X4")]
+const ROWS: usize = 1024;
+
+const COLUMNS: usize = 128;
+
+#[no_mangle]
+pub extern "C" fn main() {
+    let matrix = SMatrix::<F16x1, ROWS, COLUMNS>::zeros();
+    let input_vector = SVector::<F16x1, COLUMNS>::zeros();
+
+    // Flush cache
+    for element in matrix.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+    for element in input_vector.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+
+    pim_os::m5op::exit(0);
+    for _ in 0..10 {
+        let output_vector = matrix * input_vector;
+        core::hint::black_box(output_vector);
+    }
+    pim_os::m5op::exit(0);
+
+    writeln!(Uart0, "Done").unwrap();
+}

pim-os/src/bin/classic_gemv_layers.rs

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+#![no_std]
+#![no_main]
+
+extern crate alloc;
+
+use core::fmt::Write;
+use half::f16;
+use nalgebra::{SMatrix, SVector};
+use pim_os::{pim::vector::F16x1, uart::Uart0};
+
+#[cfg(feature = "X1")]
+const DIMENSIONS: usize = 128;
+
+#[cfg(feature = "X2")]
+const DIMENSIONS: usize = 256;
+
+#[cfg(feature = "X3")]
+const DIMENSIONS: usize = 512;
+
+#[cfg(feature = "X4")]
+const DIMENSIONS: usize = 1024;
+
+const ROWS: usize = DIMENSIONS;
+const COLUMNS: usize = DIMENSIONS;
+
+#[no_mangle]
+pub extern "C" fn main() {
+    let matrix = SMatrix::<F16x1, ROWS, COLUMNS>::zeros();
+    let mut input_vector = SVector::<F16x1, COLUMNS>::zeros();
+
+    pim_os::m5op::exit(0);
+    for _ in 0..1 {
+        input_vector = matrix * input_vector;
+        input_vector = input_vector.map(|element| {
+            if element.0 < f16::ZERO {
+                F16x1(f16::ZERO)
+            } else {
+                element
+            }
+        });
+        core::hint::black_box(input_vector);
+    }
+    pim_os::m5op::exit(0);
+
+    writeln!(Uart0, "Done").unwrap();
+}

pim-os/src/bin/classic_haxpy.rs

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+#![no_std]
+#![no_main]
+
+extern crate alloc;
+
+use core::{arch::asm, fmt::Write};
+use nalgebra::SVector;
+use num_traits::identities::Zero;
+use pim_os::{pim::vector::F16x1, uart::Uart0};
+
+#[cfg(feature = "X1")]
+const ROWS: usize = 256;
+
+#[cfg(feature = "X2")]
+const ROWS: usize = 512;
+
+#[cfg(feature = "X3")]
+const ROWS: usize = 1024;
+
+#[cfg(feature = "X4")]
+const ROWS: usize = 2048;
+
+#[no_mangle]
+pub extern "C" fn main() {
+    let a = SVector::<F16x1, ROWS>::zeros();
+    let b = SVector::<F16x1, ROWS>::zeros();
+    let s = F16x1::zero();
+
+    // Flush cache
+    for element in a.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+    for element in b.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+
+    pim_os::m5op::exit(0);
+    for _ in 0..10 {
+        let a_s = a * s;
+        let c = a_s.component_mul(&b);
+        core::hint::black_box(c);
+    }
+    pim_os::m5op::exit(0);
+
+    writeln!(Uart0, "Done").unwrap();
+}

pim-os/src/bin/classic_vadd.rs

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+#![no_std]
+#![no_main]
+
+extern crate alloc;
+
+use core::{arch::asm, fmt::Write};
+use nalgebra::SVector;
+use pim_os::{pim::vector::F16x1, uart::Uart0};
+
+#[cfg(feature = "X1")]
+const ROWS: usize = 256;
+
+#[cfg(feature = "X2")]
+const ROWS: usize = 512;
+
+#[cfg(feature = "X3")]
+const ROWS: usize = 1024;
+
+#[cfg(feature = "X4")]
+const ROWS: usize = 2048;
+
+#[no_mangle]
+pub extern "C" fn main() {
+    let a = SVector::<F16x1, ROWS>::zeros();
+    let b = SVector::<F16x1, ROWS>::zeros();
+
+    for element in a.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+    for element in b.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+
+    pim_os::m5op::exit(0);
+    for _ in 0..10 {
+        let c = a + b;
+        core::hint::black_box(c);
+    }
+    pim_os::m5op::exit(0);
+
+    writeln!(Uart0, "Done").unwrap();
+}

pim-os/src/bin/classic_vmul.rs

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+#![no_std]
+#![no_main]
+
+extern crate alloc;
+
+use core::{arch::asm, fmt::Write};
+use nalgebra::SVector;
+use pim_os::{pim::vector::F16x1, uart::Uart0};
+
+#[cfg(feature = "X1")]
+const ROWS: usize = 256;
+
+#[cfg(feature = "X2")]
+const ROWS: usize = 512;
+
+#[cfg(feature = "X3")]
+const ROWS: usize = 1024;
+
+#[cfg(feature = "X4")]
+const ROWS: usize = 2048;
+
+#[no_mangle]
+pub extern "C" fn main() {
+    let a = SVector::<F16x1, ROWS>::zeros();
+    let b = SVector::<F16x1, ROWS>::zeros();
+
+    for element in a.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+    for element in b.iter() {
+        unsafe { asm!("dc civac, {val}", val = in(reg) element) }
+    }
+
+    pim_os::m5op::exit(0);
+    for _ in 0..10 {
+        let c = a.component_mul(&b);
+        core::hint::black_box(c);
+    }
+    pim_os::m5op::exit(0);
+
+    writeln!(Uart0, "Done").unwrap();
+}