Preamble for PIM chapter

src/chapters/pim.tex

@@ -1,9 +1,15 @@
 \section{Processing-in-Memory}
 \label{sec:pim}
 
-% Allgemeiner overview hier...
-% wird seit 70ern diskutiert...
-% durch DNNs neuer Aufwind...
+In the conventional von Neumann architecture, compute is completely separated from memory.
+Memory-intensive workloads operate on a large data set, have poor spatial and temporal locality, and low operational density.
+As a consequence, the data movement between the memory and compute forms the so-called von Neumann bottleneck \cite{zou2021}.
+In the past, this bottleneck was hidden using latency hiding techniques such as out-of-order execution, branch prediction, and multiple layers of cache \cite{radojkovic2021}.
+However, new memory-intensive applications, including \acp{dnn}, have led researchers to reconsider \ac{pim} as a new approach to meet future processing demands.
+First proposals for \ac{pim} date back to the 1970s, were hindered by the limitations of existing memory systems, but are now experiencing a renaissance \cite{radojkovic2021,ghose2019a}.
+
+In the following, the workloads suitable for \ac{pim} will be discussed in more detail, followed by an overview of the different types of \ac{pim} implementations.
+Finally, a number of concrete examples are presented.
 
 \subsection{Applicable Workloads}
 \label{sec:pim_workloads}

src/doc.bib

@@ -394,6 +394,23 @@
   file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/3XHCI9KG/Oliveira et al. - 2023 - DaPPA A Data-Parallel Framework for Processing-in.pdf}
 }
 
+@techreport{radojkovic2021,
+  title = {Processing in {{Memory}}: {{The Tipping Point}}},
+  shorttitle = {Processing in {{Memory}}},
+  author = {Radojkovi{\'c}, Petar and Carpenter, Paul and {Esmaili-Dokht}, Pouya and Cimadomo, R{\'e}my and Charles, Henri-Pierre and Sebastian, Abu and Amato, Paolo},
+  year = {2021},
+  month = jul,
+  institution = {{Zenodo}},
+  doi = {10.5281/ZENODO.4767489},
+  url = {https://zenodo.org/record/4767489},
+  urldate = {2024-02-06},
+  abstract = {Decades after being initially explored in the 1970s, Processing in Memory (PIM) is currently experiencing a renaissance. By moving part of the computation to the memory devices, PIM addresses a fundamental issue in the design of modern computing systems, the mismatch between the von Neumann architecture and the requirements of important data-centric applications. A number of industrial prototypes and products are under development or already available in the marketplace, and these devices show the potential for cost-effective and energy-efficient acceleration of HPC, AI and data analytics workloads. This paper reviews the reasons for the renewed interest in PIM and surveys industrial prototypes and products, discussing their technological readiness. Wide adoption of PIM in production, however, depends on our ability to create an ecosystem to drive and coordinate innovations and co-design across the whole stack. European companies and research centres should be involved in all aspects, from technology, hardware, system software and programming environment, to updating of the algorithm and application. In this paper, we identify the main challenges that must be addressed and we provide guidelines to prioritise the research efforts and funding. We aim to help make PIM a reality in production HPC, AI and data analytics.},
+  copyright = {Creative Commons Attribution 4.0 International, Open Access},
+  langid = {english},
+  keywords = {not read,PIM,Processing in Memory},
+  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/U92WPM5C/Radojković et al. - 2021 - Processing in Memory The Tipping Point.pdf}
+}
+
 @inproceedings{seshadri2013,
   title = {{{RowClone}}: Fast and Energy-Efficient in-{{DRAM}} Bulk Data Copy and Initialization},
   shorttitle = {{{RowClone}}},
@@ -511,3 +528,21 @@
   archiveprefix = {arxiv},
   file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/MGQYNDPQ/Touvron et al. - 2023 - LLaMA Open and Efficient Foundation Language Mode.pdf;/home/derek/Nextcloud/Verschiedenes/Zotero/storage/YDAT8K7L/2302.html}
 }
+
+@article{zou2021,
+  title = {Breaking the von {{Neumann}} Bottleneck: Architecture-Level Processing-in-Memory Technology},
+  shorttitle = {Breaking the von {{Neumann}} Bottleneck},
+  author = {Zou, Xingqi and Xu, Sheng and Chen, Xiaoming and Yan, Liang and Han, Yinhe},
+  year = {2021},
+  month = jun,
+  journal = {Science China Information Sciences},
+  volume = {64},
+  number = {6},
+  pages = {160404},
+  issn = {1674-733X, 1869-1919},
+  doi = {10.1007/s11432-020-3227-1},
+  url = {https://link.springer.com/10.1007/s11432-020-3227-1},
+  urldate = {2024-02-06},
+  langid = {english},
+  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/7BKACKF8/Zou et al. - 2021 - Breaking the von Neumann bottleneck architecture-.pdf}
+}