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master-thesis-presentation/slides/pim.md
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---
layout: figure
figureUrl: dnn.svg
figureCaption: A fully connected DNN layer
figureFootnoteNumber: 1
---
## Processing-in-Memory
### Applicable Workloads
<hr/>
<Footnotes separator>
<Footnote :number=1>
He et al. „Newton: A DRAM-makers Accelerator-in-Memory (AiM) Architecture for Machine Learning“, 2020.
</Footnote>
</Footnotes>
---
## Processing-in-Memory
### Architectures
<hr/>
<br>
<br>
Possible placements of compute logic<sup>1</sup>:
<v-clicks>
- Inside the memory subarray
- In the PSA region near a subarray
- Outside the bank in its peripheral region
- In the I/O region of the memory
</v-clicks>
<br>
<div v-click class="text-xl"> The nearer the computation is to the memory array, the higher the achievable bandwidth! </div>
<Footnotes separator>
<Footnote :number=1>
Sudarshan et al. „A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions“, 2022.
</Footnote>
</Footnotes>