Add new pictures for architectures
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public/pim_positions_0.svg
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@@ -31,7 +31,7 @@ clicks: 1
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### Applicable Workloads
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### Applicable Workloads
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<hr/>
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<hr/>
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- Fully connected layers have a small filter matrix
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- Convolutional layers have a small filter matrix
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- Matrix does fit onto on-chip cache
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- Matrix does fit onto on-chip cache
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- Excessive data reuse in the matrix
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- Excessive data reuse in the matrix
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@@ -54,6 +54,33 @@ clicks: 1
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---
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---
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## Processing-in-Memory
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### Applicable Workloads
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<hr/>
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<br>
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<br>
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<br>
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<br>
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<div class="grid grid-cols-2 gap-4">
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<div>
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### Suitable candidates for PIM:
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- Multilayer perceptrons (MLPs)
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- Layers in recurrent neural networks (RNNs)
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</div>
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<div>
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### Unsuitable candidates for PIM:
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- Convolutional neural networks (CNNs)
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</div>
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</div>
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---
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## Processing-in-Memory
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## Processing-in-Memory
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### Architectures
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### Architectures
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<hr/>
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<br>
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<br>
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<br>
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<br>
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Possible placements of compute logic<sup>1</sup>:
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<div class="grid grid-cols-2 gap-4">
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<div>
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<v-clicks>
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<v-clicks>
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@@ -72,6 +100,21 @@ Possible placements of compute logic<sup>1</sup>:
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</v-clicks>
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</v-clicks>
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</div>
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<div>
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<img v-click="[0,1]" class="absolute right-80px top-150px" src="/pim_positions_0.svg">
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<img v-click="[1,2]" class="absolute right-80px top-150px" src="/pim_positions_1.svg">
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<img v-click="[2,3]" class="absolute right-80px top-150px" src="/pim_positions_2.svg">
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<img v-click="[3,4]" class="absolute right-80px top-150px" src="/pim_positions_3.svg">
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<img v-click="4" class="absolute right-80px top-150px" src="/pim_positions_4.svg">
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</div>
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</div>
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<br>
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<br>
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<br>
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<br>
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<br>
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<div v-click class="text-xl"> The nearer the computation is to the memory cells, the higher the achievable bandwidth! </div>
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<div v-click class="text-xl"> The nearer the computation is to the memory cells, the higher the achievable bandwidth! </div>
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@@ -82,6 +125,22 @@ Possible placements of compute logic<sup>1</sup>:
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</Footnote>
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</Footnote>
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</Footnotes>
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</Footnotes>
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<!--
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- Inside the memory SA
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- Ambit
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- activate multiple rows at the same time
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- bulk logic operations
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- Near SA in PSA output region
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- CMOS-based logic gates in the region
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- Near a bank in its peripheral region
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- computation units with control at bank output
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- I/O region of memory
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- more traditional accelerator approach
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-->
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---
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---
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layout: figure
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layout: figure
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figureUrl: /hbm-pim.svg
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figureUrl: /hbm-pim.svg
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