Add new pictures for architectures
This commit is contained in:
6390
public/pim_positions_0.svg
Normal file
6390
public/pim_positions_0.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 344 KiB |
6443
public/pim_positions_1.svg
Normal file
6443
public/pim_positions_1.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 346 KiB |
6443
public/pim_positions_2.svg
Normal file
6443
public/pim_positions_2.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 346 KiB |
6443
public/pim_positions_3.svg
Normal file
6443
public/pim_positions_3.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 346 KiB |
6443
public/pim_positions_4.svg
Normal file
6443
public/pim_positions_4.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 346 KiB |
@@ -31,7 +31,7 @@ clicks: 1
|
||||
### Applicable Workloads
|
||||
<hr/>
|
||||
|
||||
- Fully connected layers have a small filter matrix
|
||||
- Convolutional layers have a small filter matrix
|
||||
- Matrix does fit onto on-chip cache
|
||||
- Excessive data reuse in the matrix
|
||||
|
||||
@@ -54,6 +54,33 @@ clicks: 1
|
||||
|
||||
---
|
||||
|
||||
## Processing-in-Memory
|
||||
### Applicable Workloads
|
||||
<hr/>
|
||||
|
||||
<br>
|
||||
<br>
|
||||
<br>
|
||||
<br>
|
||||
|
||||
<div class="grid grid-cols-2 gap-4">
|
||||
<div>
|
||||
|
||||
### Suitable candidates for PIM:
|
||||
- Multilayer perceptrons (MLPs)
|
||||
- Layers in recurrent neural networks (RNNs)
|
||||
|
||||
</div>
|
||||
<div>
|
||||
|
||||
### Unsuitable candidates for PIM:
|
||||
- Convolutional neural networks (CNNs)
|
||||
|
||||
</div>
|
||||
</div>
|
||||
|
||||
---
|
||||
|
||||
## Processing-in-Memory
|
||||
### Architectures
|
||||
<hr/>
|
||||
@@ -61,7 +88,8 @@ clicks: 1
|
||||
<br>
|
||||
<br>
|
||||
|
||||
Possible placements of compute logic<sup>1</sup>:
|
||||
<div class="grid grid-cols-2 gap-4">
|
||||
<div>
|
||||
|
||||
<v-clicks>
|
||||
|
||||
@@ -72,6 +100,21 @@ Possible placements of compute logic<sup>1</sup>:
|
||||
|
||||
</v-clicks>
|
||||
|
||||
</div>
|
||||
<div>
|
||||
|
||||
<img v-click="[0,1]" class="absolute right-80px top-150px" src="/pim_positions_0.svg">
|
||||
<img v-click="[1,2]" class="absolute right-80px top-150px" src="/pim_positions_1.svg">
|
||||
<img v-click="[2,3]" class="absolute right-80px top-150px" src="/pim_positions_2.svg">
|
||||
<img v-click="[3,4]" class="absolute right-80px top-150px" src="/pim_positions_3.svg">
|
||||
<img v-click="4" class="absolute right-80px top-150px" src="/pim_positions_4.svg">
|
||||
|
||||
</div>
|
||||
</div>
|
||||
|
||||
<br>
|
||||
<br>
|
||||
<br>
|
||||
<br>
|
||||
|
||||
<div v-click class="text-xl"> The nearer the computation is to the memory cells, the higher the achievable bandwidth! </div>
|
||||
@@ -82,6 +125,22 @@ Possible placements of compute logic<sup>1</sup>:
|
||||
</Footnote>
|
||||
</Footnotes>
|
||||
|
||||
<!--
|
||||
- Inside the memory SA
|
||||
- Ambit
|
||||
- activate multiple rows at the same time
|
||||
- bulk logic operations
|
||||
|
||||
- Near SA in PSA output region
|
||||
- CMOS-based logic gates in the region
|
||||
|
||||
- Near a bank in its peripheral region
|
||||
- computation units with control at bank output
|
||||
|
||||
- I/O region of memory
|
||||
- more traditional accelerator approach
|
||||
-->
|
||||
|
||||
---
|
||||
layout: figure
|
||||
figureUrl: /hbm-pim.svg
|
||||
|
||||
Reference in New Issue
Block a user