Refactor presentation
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@@ -1,9 +1,14 @@
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## Conclusion and Future Work
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<hr/>
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- achievable speedup of 17.6 × and 9.0 × hypothetical infinite compute system
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- lower bound
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- linux driver implementation
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- comparison with real neural network workloads
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- consider replacing library approach with compiler approach
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- power comparison, power models needed
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<br>
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A speedup of 17.6× and 9.0× for the hypothetical infinite compute system has been achieved
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<br>
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Future work:
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- Implementation of Linux driver
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- Comparison with complete neural networks
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- Consider replacing library approach with compiler approach
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- Implement a power model to analyze the power efficiency gains
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@@ -1,13 +1,23 @@
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---
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layout: figure
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figureUrl: /dramsys.svg
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figureCaption: The PIM-HBM model integrated into DRAMSys
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---
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## Virtual Prototype
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### Processing Units
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<hr/>
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<br>
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- Integrate DRAMSys into gem5
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- Implement PIM-HBM virtual prototype in DRAM model
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<br>
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<div class="flex justify-center items-center">
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<img src="/dramsys.svg">
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</div>
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<!--
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- VP interprets the programmed microkernel
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- not yet drop-in replacement
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-->
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---
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layout: figure-side
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figureUrl: /data_structures.svg
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@@ -18,12 +28,15 @@ figureCaption: Data structures for instructions and register files
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### Software Library
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<hr/>
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<br>
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<br>
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<br>
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- Software support library
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- Provides data structures for PIM-HBM
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- Adhering special memory layout requirements
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#### Software support library
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<br>
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- Provides data structures for operand data and microkernels
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- Executes programmed microkernels
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---
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@@ -1,33 +1,41 @@
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---
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layout: figure
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figureUrl: /world_energy.svg
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figureCaption: Total energy of computing
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figureFootnoteNumber: 1
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---
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## Introduction
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### Energy Demand of Applications
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<hr/>
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<br>
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- Total compute energy approaches world's energy production
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--> drastic improvements in energy efficiency needed
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<div class="flex justify-center">
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<img src="/world_energy.svg">
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</div>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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SRC. „Decadal Plan for Semiconductors“, Januar 2021. https://www.src.org/about/decadal-plan/.
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</Footnote>
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</Footnote>
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</Footnotes>
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---
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layout: figure
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figureUrl: /gpt.svg
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figureCaption: Roofline model of GPT revisions
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figureFootnoteNumber: 1
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---
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## Introduction
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### Memory Bound Workloads
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<hr/>
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<br>
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#### Roofline model of GPT revisions<sup>1</sup>
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<br>
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<div class="flex justify-center">
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<img src="/gpt.svg">
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</div>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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Ivo Bolsens. „Scalable AI Architectures for Edge and Cloud“, 2023.
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</Footnote>
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</Footnote>
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</Footnotes>
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@@ -79,6 +79,10 @@ clicks: 1
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</div>
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</div>
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<!--
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To summarize...
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-->
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---
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## Processing-in-Memory
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@@ -94,8 +98,8 @@ clicks: 1
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<v-clicks>
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- Inside the memory subarray
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- In the PSA region near a subarray
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- Outside the bank in its peripheral region
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- Near the subarray in the PSA output region
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- Near the bank in its peripheral region
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- In the I/O region of the memory
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</v-clicks>
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@@ -120,7 +124,7 @@ clicks: 1
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<div v-click class="text-xl"> The nearer the computation is to the memory cells, the higher the achievable bandwidth! </div>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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Sudarshan et al. „A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions“, 2022.
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</Footnote>
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</Footnotes>
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@@ -141,19 +145,27 @@ clicks: 1
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- more traditional accelerator approach
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-->
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---
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layout: figure
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figureUrl: /hbm-pim.svg
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figureCaption: Architecture of PIM-HBM
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figureFootnoteNumber: 1
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---
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## Processing-in-Memory
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### Samsung's HBM-PIM
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### Samsung's PIM-HBM
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<hr/>
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<br>
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- Real-world PIM implementation based on HBM2
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- PIM units embedded at the bank level
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<br>
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<div class="flex justify-center items-center">
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<img src="/hbm-pim.svg">
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</div>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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Lee et al. „Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product“, 2021.
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</Footnote>
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</Footnotes>
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@@ -167,19 +179,23 @@ figureFootnoteNumber: 1
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- All-Bank-PIM (AB-PIM)
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-->
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---
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layout: figure
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figureUrl: /pu.svg
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figureCaption: Architecture of a PIM processing unit
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figureFootnoteNumber: 1
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---
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## Processing-in-Memory
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### Samsung's HBM-PIM
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### Samsung's PIM-HBM
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<hr/>
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<br>
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- Two 16-wide 16-bit FPUs
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- Register files and control unit
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<div class="flex justify-center items-center">
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<img src="/pu.svg">
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</div>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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Lee et al. „Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product“, 2021.
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</Footnote>
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</Footnotes>
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@@ -201,15 +217,14 @@ figureFootnoteNumber: 1
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layout: figure
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figureUrl: /gemv.svg
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figureCaption: Procedure to perform a (128×8)×(128) GEMV operation
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figureFootnoteNumber: 1
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---
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## Processing-in-Memory
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### Samsung's HBM-PIM
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### Samsung's PIM-HBM
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<hr/>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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Lee et al. „Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product“, 2021.
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</Footnote>
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</Footnotes>
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@@ -221,7 +236,7 @@ figureCaption: Mapping of the weight matrix onto the memory banks
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---
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## Processing-in-Memory
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### Samsung's HBM-PIM
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### Samsung's PIM-HBM
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<hr/>
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<!--
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@@ -234,8 +249,14 @@ figureCaption: Mapping of the weight matrix onto the memory banks
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### Research
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<hr/>
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simulation models needed
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<br>
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<br>
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<br>
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<br>
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research should not only focus on hardware but also explore the software side!
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- To analyze the performance gains of PIM, simulation models are needed
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- Research should not only focus on hardware but also explore the software side
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deswegen baue ich einen virutal protoype
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<br>
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- In the following, a virtual prototype of PIM-HBM is implemented
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@@ -2,7 +2,6 @@
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### Microbenchmarks
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<hr/>
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<br>
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<br>
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<div class="grid grid-cols-2 gap-4">
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@@ -15,11 +14,16 @@
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- Vector-Matrix benchmarks (BLAS level 2)
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- GEMV: $z = A \cdot x$
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- DNN Layer: $z = ReLU(A \cdot x)$
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- DNN:
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- $f(x) = z = ReLU(A \cdot x)$
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- $z_{n+1} = f(z_n)$
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- 5 layers in total
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</div>
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<div>
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<br>
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| Level | Vector | GEMV | DNN |
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|-------|--------|---------------|---------------|
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| X1 | (2M) | (1024 x 4096) | (256 x 256) |
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@@ -27,6 +31,8 @@
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| X3 | (8M) | (4096 x 8192) | (1024 x 1024) |
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| X4 | (16M) | (4096 x 8192) | (2048 x 2048) |
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Operand Dimensions
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</div>
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</div>
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@@ -36,11 +42,18 @@
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### System Configuration
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<hr/>
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- Two system configurations:
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- ARM 3GHz
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- ARM Infinite
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<br>
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<br>
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- TODO ... GPU und so
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- Two simulated systems:
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- Generic ARM systems
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- Infinite compute ARM system
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<br>
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- Two real GPUs using HBM2:
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- AMD RX Vega 56
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- NVIDIA V100
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---
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layout: figure
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@@ -49,7 +62,7 @@ figureCaption: Speedups of PIM compared to non-PIM
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---
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## Simulations
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### Speedups / ARM System
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### Speedups / Generic ARM System
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<hr/>
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---
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@@ -74,11 +87,18 @@ figureFootnoteNumber: 1
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<hr/>
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<Footnotes separator>
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<Footnote :number=1>
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<Footnote>
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Lee et al. „Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product“, 2021.
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</Footnote>
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</Footnotes>
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<!--
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- GEMV matches good
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- ADD shows deviation
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-> differences in hardware architecture
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-->
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---
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layout: figure
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figureUrl: /runtimes_vector.svg
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@@ -89,6 +109,11 @@ figureCaption: Runtimes for Vector Benchmarks
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### Runtimes / Vector Benchmarks
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<hr/>
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<!--
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- Real GPUs use multiple memory channels
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- Also architectural differences
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-->
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---
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layout: figure
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figureUrl: /runtimes_matrix.svg
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