75 lines
2.6 KiB
VHDL
75 lines
2.6 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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-- the decoder_shadow decodes instructions which are needed but not part of user-available instruction set (e.g. push).
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-- it is fully combinatoric.
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entity decoder_shadow is
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port(
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-- input signals from decoder finite state machine
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input : in fsm_decshd;
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-- output signals to control path (or decoder mux)
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output : out dec_cp
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);
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end entity decoder_shadow;
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architecture RTL of decoder_shadow is
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begin
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-- decode instruction
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decode : process(input.instruction) is
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begin
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-- set defaults to prevent taking values from previous operations
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output.s1 <= get_default_dec_cp_s1;
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output.s2 <= get_default_dec_cp_s2;
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output.s3 <= get_default_dec_cp_s3;
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output.hardfault <= '0';
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-- set instruction specific signals
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case input.instruction(31 downto 28) is
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when op_shd_push => -- push instruction
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-- write to mem
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output.s1.register_read_number_b <= reg_number(input.instruction(3 downto 0));
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output.s3.dmem_write_en <= '1';
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output.s3.dmem_write_size <= size_word;
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output.s3.dmem_write_data_select <= sel_register_value;
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-- decrement SP
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output.s1.register_read_number_a <= sp_num;
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output.s2.alu_mode <= alu_sub;
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output.s2.alu_input_data_select <= sel_imm;
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output.s2.immediate <= to_signed(4, 8);
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output.s3.register_write_number <= sp_num;
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output.s3.register_write_enable <= '1';
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when op_shd_setsr => -- set SR instruction
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output.s3.register_write_data_select <= sel_immediate;
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output.s3.register_write_number <= sr_num;
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output.s3.register_write_size <= size_byte;
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output.s3.register_write_enable <= '1';
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output.s2.immediate <= signed(input.instruction(7 downto 0));
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when op_shd_reset => -- reset instruction
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-- PC = zero
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output.s2.pc_summand_select <= sel_immediate;
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output.s2.pc_mode_select <= sel_absolute;
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output.s2.pc_condition <= sel_unconditional;
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output.s2.immediate <= (others => '0');
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-- synthesis translate_off
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when "UUUU" =>
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null; -- ignore startup
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-- synthesis translate_on
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when others =>
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-- unknown operation, throw hardfault
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output.hardfault <= '1';
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-- synthesis translate_off
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assert false report "unknown shadow operation not implemented" severity error;
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-- synthesis translate_on
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end case;
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end process decode;
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end architecture RTL;
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