81 lines
1.9 KiB
VHDL
81 lines
1.9 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use IEEE.math_real.all;
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use ieee.std_logic_arith.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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entity wb_stestrd is
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generic(
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memaddr : generic_addr_type := 0;
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addrmask : generic_mask_type := 16#3fffff#;
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wbidx: integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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slvi : in wb_slv_in_type;
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slvo : out wb_slv_out_type;
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test_rddat : in std_logic_vector(31 downto 0)
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);
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end entity wb_stestrd;
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architecture RTL of wb_stestrd is
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type STATE_TYPE IS (IDLE, RDREQ);
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signal state: STATE_TYPE;
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signal wbslvo : wb_slv_out_type;-- := wbs_out_none;
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begin
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nxts: process(clk, rst)
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begin
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if rst = '1' then
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state <= IDLE;
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elsif(rising_edge(clk)) then
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if slvi.cyc='1' and slvi.stb='1' and slvi.we = '0' then -- need to check cyc ?
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state <= RDREQ;
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else
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state <= IDLE;
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end if;
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end if;
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end process;
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--**************************************
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ocl: process(state)
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begin
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--wbslvo.wbcfg <= wb_membar(memaddr, addrmask);
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--wbslvo.wbidx <= wbidx;
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----if (state=RDREQ and slvi.we = '0' and slvi.stb='1') then
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if (state=RDREQ) then
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wbslvo.dat <= test_rddat; -- test_data
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wbslvo.ack <= '1';
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--wbslvo.tagn <= ;
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--wbslvo.stall<= ;
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--wbslvo.err <= ;
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--wbslvo.rty <= ;
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--wbslvo.wbcfg <= wb_membar(memaddr, addrmask);
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--wbslvo.wbidx <= wbidx;
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else
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wbslvo <= wbs_out_none;
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end if;
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end process;
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--slvo <= wbslvo;
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slvo.dat <= wbslvo.dat;
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slvo.ack <= wbslvo.ack;
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-- slvo.tagn <= wbslvo.tagn;
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-- slvo.stall <= wbslvo.stall;
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-- slvo.err <= wbslvo.err;
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-- slvo.rty <= wbslvo.rty;
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-- wbcfg and wbidx should be assigned directly otw will be delay
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slvo.wbcfg <= wb_membar(memaddr, addrmask);
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end architecture RTL;
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